TCA9539-Q1 [TI]

具有中断输出、复位和配置寄存器的汽车类 16 位 1.65 至 3.6V I2C/SMBus I/O 扩展器;


型号：	TCA9539-Q1
厂家：	TEXAS INSTRUMENTS
描述：	具有中断输出、复位和配置寄存器的汽车类 16 位 1.65 至 3.6V I2C/SMBus I/O 扩展器
文件：	总41页 (文件大小：1680K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TCA9539-Q1

ZHCSEZ2D –JANUARY 2014 –REVISED OCTOBER 2021

具有中断输出、复位引脚和配置寄存器的TCA9539-Q1 汽车类低压16 位I²C 和

SMBus 低功耗I/O 扩展器

1 特性

3 说明

• AEC-Q100（等级1）：符合汽车应用要求

• 提供功能安全

TCA9539-Q1 是一款 24 引脚器件，可为两线双向 I²C

总线（或 SMBus 协议）提供 16 位通用并行输入和输

出 (I/O) 扩展。该器件的工作电源电压 (V_CC) 范围为

1.65V 至 3.6V，并且支持 100kHz（I²C 标准模式）和

400kHz（I²C 快速模式）两种时钟频率。当开关、传

感器、按钮、LED、风扇以及其他相似器件需要额外的

I/O 时，I/O 扩展器（如 TCA9539-Q1）可提供简单解

决方案。

– 可帮助进行功能安全系统设计的文档

• I²C 至并行端口扩展器

• 开漏电路低电平有效中断输出

• 低电平有效复位输入

• 5V 耐压输入和输出端口

• 兼容大多数微控制器

• 400kHz 快速I²C 总线

• 极性反转寄存器

• 内部上电复位

• 加电时无干扰

• 通过两个硬件地址引脚寻址，以便使用多达4 个器

件

• 锁存输出，用于直接驱动LED

• 闩锁性能超过100mA，符合JESD 78 II 类规范的

要求

TCA9539-Q1 包括一项功能：当输入端口状态发生变

化时，在 INT 引脚上生成中断。硬件可选地址引脚 A0

和 A1 最多允许四个 TCA9539-Q1 器件位于同一 I²C

总线上。也可以通过下电上电生成上电复位，将此器件

复位为默认状态。此外，TCA9539-Q1 还具有一个硬

件RESET 引脚，可用于将器件复位为默认状态。

TCA9539-Q1 I²C I/O 扩展器符合汽车类应用的要求。

器件信息

封装类型⁽¹⁾

• ESD 保护性能超过JESD 22 规范要求

封装尺寸（标称值）

器件型号

– 2000V 人体放电模型(A114-A)

– 1000V 带电器件模型(C101)

TCA9539-Q1

TSSOP (24)

7.80mm × 4.40mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 汽车信息娱乐系统、高级驾驶辅助系统(ADAS)、

汽车车身电子装置、混合动力汽车(HEV)、电动车

(EV) 和动力总成

• 工业自动化、工厂自动化、楼宇自动化、测试与测

量、电子销售点终端(EPOS)

• I²C GPIO 扩展

空白

V_CC

Peripheral Devices

SDA

SCL

INT

P00

P01

I²C or SMBus Controller

(e.g. Processor)

/RESET,

ENABLE, or

control inputs

/INT or status

outputs

RESET

TCA9539-Q1

LEDs

P17

GND

简化版方框图

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS254

TCA9539-Q1

ZHCSEZ2D –JANUARY 2014 –REVISED OCTOBER 2021

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Table of Contents

8.2 Functional Block Diagram.........................................16

8.3 Feature Description...................................................17

8.4 Device Functional Modes..........................................18

8.5 Programming............................................................ 18

8.6 Register Maps...........................................................20

9 Power Supply Recommendations................................29

9.1 Power-On Reset Requirements................................29

10 Layout...........................................................................31

10.1 Layout Guidelines................................................... 31

10.2 Layout Example...................................................... 32

11 Device and Documentation Support..........................33

11.1 Documentation Support.......................................... 33

11.2 接收文档更新通知................................................... 33

11.3 支持资源..................................................................33

11.4 Trademarks............................................................. 33

11.5 Electrostatic Discharge Caution..............................33

11.6 术语表..................................................................... 33

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................3

6 Specifications.................................................................. 4

6.1 Absolute Maximum Ratings........................................ 4

6.2 ESD Ratings............................................................... 4

6.3 Recommended Operating Conditions.........................4

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics.............................................5

6.6 I²C Interface Timing Requirements.............................6

6.7 RESET Timing Requirements.....................................7

6.8 Switching Characteristics............................................7

6.9 Typical Characteristics................................................8

7 Parameter Measurement Information.......................... 11

8 Detailed Description......................................................15

8.1 Overview...................................................................15

4 Revision History

Changes from Revision C (December 2018) to Revision D (October 2021)

Page

• 添加了特性：提供功能安全................................................................................................................................1

• 将提到的旧术语实例全局更改为控制器和目标。................................................................................................ 1

• Corrected the pin number for pins A0, SCL, SDA, and VCC in the TCA9539-Q1 Layout ...............................32

Changes from Revision B (April 2016) to Revision C (December 2018)

Page

• Changed the appearance of the PW pinout image ............................................................................................3

• Removed (5 V) from the V_CClabel in 图9-1 ....................................................................................................25

Changes from Revision A (September 2015) to Revision B (April 2016)

Page

• 将器件状态从产品预发布更改为量产数据.........................................................................................................1

Changes from Revision * (January 2014) to Revision A (September 2015)

Page

• 添加了“ESD 等级”表、“特性说明”部分、“器件功能模式”、“应用和实施”部分、“电源相关建议”部

分、“布局”部分、“器件和文档支持”部分以及“机械、封装和可订购信息”部分.......................................1

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5 Pin Configuration and Functions

INT

SDA

SCL

RESET

P00

P01

P17

P16

P15

P14

P13

P12

P11

P10

P02

P03

P04

P05

P06

P07

GND

Not to scale

图5-1. PW Package, 24-Pin TSSOP, Top View

表5-1. Pin Functions

I/O

DESCRIPTION

NO.

NAME

INT

Interrupt open-drain output. Connect to V_CCthrough a pull-up resistor

Address input. Connect directly to V_CCor ground

RESET

P00

P01

P02

P03

P04

P05

P06

P07

GND

P10

P11

Active-low reset input. Connect to V_CCthrough a pull-up resistor if no active connection is used

P-port input-output. Push-pull design structure. At power-on, P00 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P01 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P02 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P03 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P04 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P05 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P06 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P07 is configured as an input

Ground

I/O

—

I/O

P-port input-output. Push-pull design structure. At power-on, P10 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P11 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P12 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P13 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P14 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P15 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P16 is configured as an input

P-port input-output. Push-pull design structure. At power-on, P17 is configured as an input

Address input. Connect directly to V_CCor ground

P12

P13

P14

P15

P16

P17

SCL

SDA

V_CC

Serial clock bus. Connect to V_CCthrough a pull-up resistor

I/O

Serial data bus. Connect to V_CCthrough a pull-up resistor

Supply voltage

—

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

MIN

–0.5

MAX

3.6

UNIT

V_CC

V_I

Supply voltage

Input voltage ⁽²⁾

V_O

I_IK

Output voltage ⁽²⁾

Input clamp current

V_I< 0

–20

±20

I_OK

I_IOK

I_OL

I_OH

Output clamp current

V_O< 0

Input-output clamp current

Continuous output low current

Continuous output high current

Continuous current through GND

Continuous current through V_CC

Maximum junction temperature

Storage temperature

V_O< 0 or V_O> V_CC

V_O= 0 to V_CC

–50

–250

160

I_CC

T_j(MAX)

T_stg

135

°C

150

–65

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply

functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If

used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully

functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) The input negative voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

VALUE

±2000

±1000

UNIT

Human-body model (HBM), per AEC Q100-002⁽¹⁾

Charged-device model (CDM), per AEC Q100-011

V_(ESD)

Electrostatic discharge

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

V_CC

Supply voltage

1.65

–0.5

3.6

5.5

3.6

5.5

SCL, SDA, A0, A1, RESET, INT ⁽¹⁾

V_I/O

I/O ports voltage

For P00–P07, P10–P17 configured as outputs

For P00–P07, P10–P17 configured as inputs⁽¹⁾

SCL, SDA, A0, A1, RESET, P07–P00, P10–P17

P00–P07, P10–P17

–0.5

V_IH

V_IL

I_OH

High-level input voltage

Low-level input voltage

High-level output current

0.7 × V_CC

0.3 × V_CC

–10

T_j≤65°C

T_j= 85°C

(2)

I_OL

Low-level output current

P00–P07, P10–P17

T_j= 105°C

T_j= 125°C

T_j= 135°C

4.5

3.5

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6.3 Recommended Operating Conditions (continued)

over operating free-air temperature range (unless otherwise noted)

MIN

MAX UNIT

T_j≤85°C

T_j= 105°C

T_j= 125°C

T_j= 135°C

1.8

(2)

I_OL

Low-level output current

INT, SDA

1.5

T_A

Operating free-air temperature

125

°C

–40

(1) For voltages applied above V_CC, an increase in I_CCresults.

(2) The values shown apply to specific junction temperatures. See the 节9.2.1.1 section on how to calculate the junction temperature.

6.4 Thermal Information

TCA9539-Q1

THERMAL METRIC ⁽¹⁾

PW (TSSOP)

24 PINS

108.8

UNIT

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

62.8

Junction-to-top characterization parameter

Junction-to-board characterization parameter

11.1

62.3

ψ_JB

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report, SPRA953.

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN

TYP ⁽¹⁾MAX UNIT

V_IK

Input diode clamp voltage

1.65 V to 3.6 V

I_I= –18 mA

–1.2

Power-on reset voltage, V_CC

rising

V_PORR

V_I= V_CCor GND

1.65 V to 3.6 V

1.2

1.5

Power-on reset voltage, V_CC

falling

V_PORF

0.75

1.65 V

2.3 V

3 V

1.2

1.8

2.6

3.3

I_OH= –8 mA

3.6 V

1.65 V

2.3 V

3 V

P-port high-level output voltage

V_OH

(2)

1.7

2.5

3.2

I_OH= –10 mA

3.6 V

SDA

V_OL= 0.4 V

V_OL= 0.5 V

V_OL= 0.7 V

V_OL= 0.4 V

I_OL

P port ⁽³⁾

1.65 V to 3.6 V

µA

INT

SCL, SDA

A0, A1, RESET

P port

±1

I_I

V_I= V_CCor GND

1.65 V to 3.6 V

I_IH

I_IL

V_I= V_CC

1.65 V to 3.6 V

µA

P port

V_I= GND

–1

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6.5 Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

3.6 V

MIN

TYP ⁽¹⁾MAX UNIT

V_I= V_CCor GND, I_O= 0,

I/O = inputs, f_SCL= 400 kHz, no load

Operating mode

2.7 V

1.95 V

3.6 V

1.1

I_CC

V_I= V_CC

2.7 V

4.5 µA

3.5

1.95 V

3.6 V

0.4

1.1

I_O= 0, I/O = inputs,

f_SCL= 0 kHz, no load

Standby mode

V_I= GND

2.7 V

9.5

6.5

1.95 V

1.65 V to 3.6 V

0.4

C_i

SCL

V_I= V_CCor GND

V_IO= V_CCor GND

9.5

SDA

P port

C_io

1.65 V to 3.6 V

3.7

(1) All typical values are at nominal supply voltage (1.8 V, 2.5 V, or 3.3 V, V_CC) and T_A= 25°C.

(2) Each I/O must be externally limited to the maximum allowed I_OL, and each octal (P07–P00 and P17–P10) must be limited to a

maximum current of 100 mA, for a device total of 200 mA at T_j≤85°C. See the 节6.3 table for more information.

(3) The total current sourced by all I/Os must be limited to 160 mA (80 mA for P07–P00 and 80 mA for P17–P10) for T_j≤85°C. See the

节6.3 table for more information.

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)

MIN

MAX

UNIT

I²C BUS—STANDARD MODE

f_scl

I²C clock frequency

100

kHz

µs

t_sch

t_scl

I²C clock high time

I²C clock low time

4.7

t_sp

I²C spike time

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

250

1000

300

t_icf

I²C input fall time

t_ocf

t_buf

t_sts

I²C output fall time

10 pF to 400 pF bus

300

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

Valid data time

4.7

t_sth

t_sps

t_vd(data)

SCL low to SDA output valid

3.45

400

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

µs

MIN

MAX

UNIT

I²C BUS—FAST MODE

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

0.6

1.3

400

kHz

µs

I²C clock high time

I²C clock low time

I²C spike time

µs

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MIN

100

MAX

UNIT

t_sds

t_sdh

t_icr

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

300

20 × (V_CC

t_icf

I²C input fall time

I²C output fall time

5.5 V)

20 × (V_CC

t_ocf

10 pF to 400 pF bus

300

5.5 V)

t_buf

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

1.3

µs

t_sts

0.6

t_sth

0.6

t_sps

0.6

t_vd(data)

Valid data time

SCL low to SDA output valid

0.9

ACK signal from SCL low to

SDA (out) low

t_vd(ack)

C_b

Valid data time of ACK condition

I²C bus capacitive load

µs

400

6.7 RESET Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see 图7-4)

MIN

MAX

UNIT

t_W

Reset pulse duration

t_REC

Reset recovery time

400

550

Time to reset; For V_CC=2.3 V –3.6 V

Time to reset; For V_CC= 1.65 V –2.3 V

t_RESET

6.8 Switching Characteristics

over recommended operating free-air temperature range, C_L≤100 pF (unless otherwise noted) (see 图7-2 and 图7-3)

FROM

(INPUT)

(OUTPUT)

PARAMETER

Interrupt valid time

MIN

MAX

UNIT

t_iv

t_ir

P port

SCL

INT

µs

Interrupt reset delay time

t_pv

Output data valid; For V_CC= 2.3 V –3.6

200

300

SCL

P port

Output data valid; For V_CC= 1.65 V –2.3

t_ps

t_ph

Input data setup time

Input data hold time

P port

SCL

150

µs

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6.9 Typical Characteristics

T_A= 25°C (unless otherwise noted)

1.75

1.5

Vcc = 1.65 V

Vcc = 1.8 V

Vcc = 2.5 V

Vcc = 3.3 V

Vcc = 3.6 V

Vcc = 1.65 V

Vcc = 1.8 V

Vcc = 2.5 V

Vcc = 3.3 V

Vcc = 3.6 V

1.25

0.75

0.5

0.25

-40 -25 -10

20 35 50 65 80 95 110 125

T_A- Temperature (°C)

-40 -25 -10

20 35 50 65 80 95 110 125

T_A- Temperature (°C)

D002

D001

图6-2. Standby Supply Current vs Temperature for Different

Supply Voltage (V_CC

图6-1. Supply Current vs Temperature for Different Supply

Voltage (V_CC

)

-40 °C

25 °C

85 °C

125 °C

-40èC

25èC

85èC

125èC

1.6 1.8

2.2 2.4 2.6 2.8

V_CC- Supply Voltage (V)

3.2 3.4 3.6

0.1

0.2

0.3

0.4

0.5

V_OL- Output Low Voltage (V)

0.6

0.7

D003

D004

图6-3. Supply Current vs Supply Voltage for Different

图6-4. I/O Sink Current vs Output Low Voltage for Different

Temperature (T_A)

Temperature (T_A) for V_CC= 1.65 V

-40èC

25èC

85èC

125èC

85èC

125èC

0.1

0.2

V_OL- Output Low Voltage (V)

0.3

0.4

0.5

0.6

0.7

0.1

0.2

V_OL- Output Low Voltage (V)

0.3

0.4

0.5

0.6

0.7

D005

D006

图6-5. I/O Sink Current vs Output Low Voltage for Different

图6-6. I/O Sink Current vs Output Low Voltage for Different

Temperature (T_A) for V_CC= 1.8 V

Temperature (T_A) for V_CC= 2.5 V

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6.9 Typical Characteristics (continued)

T_A= 25°C (unless otherwise noted)

300

250

200

150

100

1.8 V, 1 mA

1.8 V, 10 mA

3.3 V, 1mA

3.3 V, 10 mA

-40èC

25èC

85èC

125èC

-40 -25 -10

20 35 50 65 80 95 110 125

T_A- Temperature (°C)

0.1

0.2 0.5

V_OL- Output Low Voltage (V)

0.3

0.4

0.6

0.7

D010

D007

图6-8. I/O Low Voltage vs Temperature for Different V_CCand I_OL

图6-7. I/O Sink Current vs Output Low Voltage for Different

Temperature (T_A) for V_CC= 3.3 V

-40èC

25èC

85èC

-40èC

25èC

85èC

125èC

0.1

0.2

V_CC-V_OH- Output High Voltage (V)

0.3

0.4

0.5

0.6

0.7

0.1

0.2

V_CC-V_OH- Output High Voltage (V)

0.3

0.4

0.5

0.6

0.7

D011

D012

图6-9. I/O Source Current vs Output High Voltage for Different 图6-10. I/O Source Current vs Output High Voltage for Different

Temperature (T_A) for V_CC= 1.65 V

Temperature (T_A) for V_CC= 1.8 V

-40èC

25èC

-40èC

25èC

85èC

125èC

0.1

0.2

V_CC-V_OH- Output High Voltage (V)

0.3

0.4

0.5

0.6

0.7

0.1

0.2

V_CC-V_OH- Output High Voltage (V)

0.3

0.4

0.5

0.6

0.7

D013

D014

图6-11. I/O Source Current vs Output High Voltage for Different 图6-12. I/O Source Current vs Output High Voltage for Different

Temperature (T_A) for V_CC= 2.5 V Temperature (T_A) for V_CC= 3.3 V

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6.9 Typical Characteristics (continued)

T_A= 25°C (unless otherwise noted)

400

12.5

1.65 V, 10 mA

2.5 V, 10 mA

3.6 V, 10 mA

1.65 V

1.8 V

1.95 V

2.5 V

2.7 V

3.3 V

3.6 V

350

300

250

200

150

100

7.5

2.5

-40

-20

Temperature (C)

100

120

-40 -25 -10

20 35 50 65 80 95 110 125

T_A- Temperature (°C)

D001

D018

图6-14. ΔI_CCvs Temperature for Different V_CC(V_I= V_CC–0.6

图6-13. V_CC–V_OHVoltage vs Temperature for Different V_CC

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7 Parameter Measurement Information

= 1 kΩ

SDA

DUT

= 50 pF

(see Note A)

SDA Load Configuration

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Address

Bit 0

Data

Stop

Address

Bit 6

ACK

(A)

Bit 07

(MSB)

Bit 10 Condition

(LSB)

Bit 1

(LSB)

(P)

scl

sch

0.7 × V

0.3 × V

SCL

SDA

icr

sts

vd(ack)

icf

buf

vd(data)

0.7 × V

0.3 × V

icf

icr

sdh

sps

sth

sds

Repeat

Start

Stop

Condition

Start or

Repeat

Start

Condition

Voltage Waveforms

BYTE

DESCRIPTION

I C address

2, 3

P-port data

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. All parameters and waveforms are not applicable to all devices.

图7-1. I²C Interface Load Circuit and Voltage Waveforms

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= 4.7 kΩ

INT

DUT

= 100 pF

(see Note A)

Interrupt Load Configuration

SCL

SDA

Data From Port

Target Address

Data From Port

Data 4

Data 1

A1 A0

R/W

Start

Condition

NACK From

Controller

ACK From

Target

ACK From

Controller

Stop

Condition

Read From

Port

Data Into

Port

Data 2

Data 3

Data 4

Data 5

INT

0.7 × V

0.3 × V

0.7 × V

0.3 × V

SCL

INT

R/W

0.7 × V

0.3 × V

0.7 × V

0.3 × V

Data Into

Port (P_n)

INT

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 Hz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. All parameters and waveforms are not applicable to all devices.

图7-2. Interrupt Load Circuit and Voltage Waveforms

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A. C_Lincludes probe and jig capacitance.

B. t_pvis measured from 0.7 × V_CCon SCL to 50% I/O (P_n) output.

C. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

D. The outputs are measured one at a time, with one transition per measurement.

E. All parameters and waveforms are not applicable to all devices.

图7-3. P-Port Load Circuit and Voltage Waveforms

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500

= 1 kΩ

DUT

2 × V

SDA

DUT

= 50 pF

(see Note 1)

500 Ω

= 50 pF

(see Note 1)

SDA Load Configuration

P-Port Load Configuration

Start

SCL

ACK or Read Cycle

SDA

0.3

RESET

REC

(see Note 4)

-V

A. C_Lincludes probe and jig capacitance.

B. All inputs are supplied by generators having the following characteristics: PRR ≤10 MHz, Z_O= 50 Ω, t_r/t_f≤30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

D. I/Os are configured as inputs.

E. All parameters and waveforms are not applicable to all devices.

图7-4. Reset Load Circuits and Voltage Waveforms

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8 Detailed Description

8.1 Overview

The TCA9539-Q1 is a 16-bit I/O expander for the two-line bidirectional bus (I²C) designed for 1.65 V to 3.6 V,

V_CCoperation. It provides general-purpose remote I/O expansion for most microcontroller families via the I²C

interface, serial clock (SCL) and serial data (SDA).

The TCA9539-Q1 consists of two 8-bit Configuration (input or output selection), Input Port, Output Port, and

Polarity Inversion (active-high or active-low operation) registers. At power-on, the I/Os are configured as inputs.

The system controller can enable the I/Os as either inputs or outputs by writing to the configuration register bits.

The data for each input or output is kept in the corresponding Input or output register. The polarity of the Input

Port register can be inverted with the Polarity Inversion register. All registers can be read by the system

controller.

The system controller can reset the TCA9539-Q1 in the event of a time-out or other improper operation by

asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the

I²C-SMBus state machine. Asserting RESET causes the same reset-initialization to occur without depowering

the part.

The TCA9539-Q1 open-drain interrupt ( INT) output is activated when any input state differs from its

corresponding Input Port register state and is used to indicate to the system controller that an input state has

changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the

remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via

the I²C bus. Thus, the TCA9539-Q1 can remain a simple target device.

The TCA9539-Q1 is similar to the TCA9555, except for the removal of the internal I/O pull-up resistor, which

greatly reduces power consumption when the I/Os are held low, replacement of A2 with RESET, and a different

address range. The TCA9539-Q1 is similar to the PCA9539 with lower voltage support (down to V_CC= 1.65 V),

and also improved power-on reset circuitry for different application scenarios.

Two hardware pins (A0 and A1) are used to program and vary the fixed I²C address and allow up to four devices

to share the same I²C bus or SMBus.

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8.2 Functional Block Diagram

TCA9539-Q1

Interrupt

Logic

INT

LP Filter

P07-P00

P17-P10

SCL

SDA

I C Bus

Input

Filter

Shift

I/O

16 Bits

Control

Port

Write Pulse

Read Pulse

RESET

Power-On

Reset

GND

Pin numbers shown are for PW package.

All I/Os are set to inputs at reset.

图8-1. Logic Diagram (Positive Logic)

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Data From

Output Port

Shift Register

Configuration

Data From

Shift Register

CLK

Write Configuration

Pulse

CLK

I/O Pin

Write Pulse

Output Port

Input Port

GND

Input Port

CLK

Read Pulse

To INT

Data From

Polarity

Shift Register

CLK

Write Polarity

Pulse

Polarity Inversion

At power-on reset, all registers return to default values.

图8-2. Simplified Schematic of P-Port I/Os

8.3 Feature Description

8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The

input voltage may be raised above V_CCto a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In

this case, there are low-impedance paths between the I/O pin and either V_CCor GND. The external voltage

applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 RESET Input

A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA9539-Q1 registers and

I²C-SMBus state machine are held in their default states until RESET is once again high. This input requires a

pull-up resistor to V_CC, if no active connection is used.

8.3.3 Interrupt ( INT) Output

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the

signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original

setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the

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acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before

the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short)

because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and

is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output

cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the

state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read

independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.

INT has an open-drain structure and requires a pull-up resistor to V_CC

8.4 Device Functional Modes

8.4.1 Power-On Reset

When power (from 0 V) is applied to V_CC, an internal power-on reset holds the TCA9539-Q1 in a reset condition

until V_CChas reached V_PORR. At that point, the reset condition is released and the TCA9539-Q1 registers and

I²C-SMBus state machine initialize to their default states. After that, V_CCmust be lowered to V_PORFand then

back up to the operating voltage for a power-reset cycle. See 图8-3.

8.5 Programming

8.5.1 I²C Interface

The TCA9539-Q1 has a standard bidirectional I²C interface that is controlled by a controller device in order to be

configured or read the status of this device. Each target on the I²C bus has a specific device address to

differentiate between other target devices that are on the same I²C bus. Many target devices require

configuration upon startup to set the behavior of the device. This is typically done when the controller accesses

internal register maps of the target, which have unique register addresses. A device can have one or multiple

registers where data is stored, written, or read. For more information see Understanding the I²C Bus, SLVA704.

The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines

must be connected to V_CCthrough a pull-up resistor. The size of the pull-up resistor is determined by the amount

of capacitance on the I²C lines. For further details, see I²C Pull-up Resistor Calculation, SLVA689. Data transfer

may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a

STOP condition. See 表8-1.

图8-3 and 图8-4 show the general procedure for a controller to access a target device:

1. If a controller wants to send data to a target:

• Controller-transmitter sends a START condition and addresses the target-receiver.

• Controller-transmitter sends data to target-receiver.

• Controller-transmitter terminates the transfer with a STOP condition.

2. If a controller wants to receive or read data from a target:

• Controller-receiver sends a START condition and addresses the target-transmitter.

• Controller-receiver sends the requested register to read to target-transmitter.

• Controller-receiver receives data from the target-transmitter.

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• Controller-receiver terminates the transfer with a STOP condition.

SCL

SDA

Data Transfer

START

Condition

STOP

Condition

图8-3. Definition of Start and Stop Conditions

SDA line stable while SCL line is high

SCL

ACK

SDA

MSB

Bit

LSB

ACK

Byte: 1010 1010 ( 0xAAh )

图8-4. Bit Transfer

表8-1 shows the interface definition.

表8-1. Interface Definition

BIT

BYTE

7 (MSB)

0 (LSB)

I²C target address

P0x I/O data bus

P1x I/O data bus

R/ W

P00

P10

P07

P17

P06

P16

P05

P15

P04

P14

P03

P13

P02

P12

P01

P11

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8.6 Register Maps

8.6.1 Device Address

图8-5 shows the address byte of the TCA9539-Q1.

R/W

Target Address

A1 A0

Fixed

Programmable

图8-5. TCA9539-Q1 Address

表8-2 shows the address reference of the TCA9539-Q1.

表8-2. Address Reference

INPUTS

I²C BUS TARGET ADDRESS

116 (decimal), 74 (hexadecimal)

117 (decimal), 75 (hexadecimal)

118 (decimal), 76 (hexadecimal)

119 (decimal), 77 (hexadecimal)

The last bit of the target address defines the operation (read or write) to be performed. A high (1) selects a read

operation, while a low (0) selects a write operation.

8.6.2 Control Register And Command Byte

Following the successful acknowledgment of the address byte, the bus controller sends a command byte shown

in 表 8-3 that is stored in the control register in the TCA9539-Q1. Three bits of this data byte state the operation

(read or write) and the internal register (input, output, Polarity Inversion or Configuration) that is affected. This

When a command byte has been sent, the register pair that was addressed continues to be accessed by reads

until a new command byte has been sent. 图8-6 shows the control register bits.

B2 B1 B0

图8-6. Control Register Bits

表8-3. Command Byte

CONTROL REGISTER BITS

COMMAND

BYTE (HEX)

POWER-UP

DEFAULT

PROTOCOL

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Input Port 0

Input Port 1

Read byte

xxxx xxxx

1111 1111

0000 0000

1111 1111

Read byte

Output Port 0

Read-write byte

Output Port 1

Polarity Inversion Port 0

Polarity Inversion Port 1

Configuration Port 0

Configuration Port 1

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8.6.3 Register Descriptions

The Input Port registers (registers 0 and 1) shown in 表 8-4 reflect the incoming logic levels of the pins,

regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on

read operation. Writes to these registers have no effect. The default value, X, is determined by the externally

applied logic level.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the

Input Port register is accessed next.

表8-4. Registers 0 And 1 (Input Port Registers)

Bit

I0.7

I0.6

I0.5

I0.4

I0.3

I0.2

I0.1

I0.0

Default

Bit

I1.7

I1.6

I1.5

I1.4

I1.3

I1.2

I1.1

I1.0

Default

The Output Port registers (registers 2 and 3) shown in 表 8-5 show the outgoing logic levels of the pins defined

as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In

turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual

pin value.

表8-5. Registers 2 And 3 (Output Port Registers)

Bit

O0.7

O0.6

O0.5

O0.4

O0.3

O0.2

O0.1

O0.0

Default

Bit

O1.7

O1.6

O1.5

O1.4

O1.3

O1.2

O1.1

O1.0

Default

The Polarity Inversion registers (registers 4 and 5) shown in 表 8-6 allow Polarity Inversion of pins defined as

inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin's

polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin's original

polarity is retained.

表8-6. Registers 4 And 5 (Polarity Inversion Registers)

Bit

N0.7

N0.6

N0.5

N0.4

N0.3

N0.2

N0.1

N0.0

Default

Bit

N1.7

N1.6

N1.5

N1.4

N1.3

N1.2

N1.1

N1.0

Default

The Configuration registers (registers 6 and 7) shown in 表 8-7 configure the directions of the I/O pins. If a bit in

this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If

a bit in this register is cleared to 0, the corresponding port pin is enabled as an output.

表8-7. Registers 6 And 7 (Configuration Registers)

Bit

C0.7

C0.6

C0.5

C0.4

C0.3

C0.2

C0.1

C0.0

Default

Bit

C1.7

C1.6

C1.5

C1.4

C1.3

C1.2

C1.1

C1.0

Default

8.6.3.1 Bus Transactions

Data is exchanged between the controller and the TCA9539-Q1 through write and read commands, and this is

accomplished by reading from or writing to registers in the target device.

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Registers are locations in the memory of the target which contain information, whether it be the configuration

information or some sampled data to send back to the controller. The controller must write information to these

registers in order to instruct the target device to perform a task.

8.6.3.1.1 Writes

To write on the I²C bus, the controller sends a START condition on the bus with the address of the target, as well

as the last bit (the R/ W bit) set to 0, which signifies a write. After the target sends the acknowledge bit, the

controller then sends the register address of the register to which it wishes to write. The target acknowledges

again, letting the controller know it is ready. After this, the controller starts sending the register data to the target

until the controller has sent all the data necessary (which is sometimes only a single byte), and the controller

terminates the transmission with a STOP condition.

See the 节8.6.2 section to see list of the TCA9539-Q1s internal registers and a description of each one.

图8-7 shows an example of writing a single byte to a target register.

Controller controls SDA line

Target controls SDA line

Write to one register in a device

Data Byte to Register N (8 bits)

Device (Target) Address (7 bits)

START

R/W=0

ACK

STOP

图8-7. Write to Register

图8-9 shows the Write to the Polarity Inversion Register.

Controller controls SDA line

Target controls SDA line

Data Byte to Register 0x01 (8 bits)

Device (Target) Address (7 bits)

START

R/W=0

ACK

STOP

图8-8. Write to the Polarity Inversion Register

图8-9 shows the Write to Output Port Registers

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SCL

Command Byte

Data to Port 0

Data to Port 1

Data 1

Target Address

SDA

0.7

0.0

1.0

A1 A0

1.7

Data 0

R/W

Acknowledge

From Target

Acknowledge

From Target

Start Condition

Acknowledge

From Target

Write to Port

Data Out from Port 0

Data Valid

Data Out from Port 1

图8-9. Write to Output Port Registers

8.6.3.1.2 Reads

Reading from a target is very similar to writing, but requires some additional steps. In order to read from a target,

the controller must first instruct the target which register it wishes to read from. This is done by the controller

starting off the transmission in a similar fashion as the write, by sending the address with the R/ W bit equal to 0

(signifying a write), followed by the register address it wishes to read from. When the target acknowledges this

set to 1 (signifying a read). This time, the target acknowledges the read request, and the controller releases the

SDA bus but continues supplying the clock to the target. During this part of the transaction, the controller

becomes the controller-receiver, and the target becomes the target-transmitter.

The controller continues to send out the clock pulses, but releases the SDA line so that the target can transmit

data. At the end of every byte of data, the controller sends an ACK to the target, letting the target know that it is

ready for more data. When the controller has received the number of bytes it is expecting, it sends a NACK,

signaling to the target to halt communications and release the bus. The controller follows this up with a STOP

condition.

If a read is requested by the controller after a POR without first setting the command byte via a write, the device

NACKs until a command byte-register address is set as described above.

See the 节8.6.2 section to see list of the TCA9539-Q1s internal registers and a description of each one.

图8-10 shows an example of reading a single byte from a target register.

Controller controls SDA line

Target controls SDA line

Read from one register in a device

Device (Target) Address (7 bits)

Data Byte from Register N (8 bits)

R/W=1

START

ACK

Repeated START

ACK

NACK

STOP

R/W=0

图8-10. Read from Register

When a restart occurs after a single write request to a register, the requested register is used for the read

request. Note that when reading multiple bytes of data. Data is clocked into the register on the rising edge of the

ACK clock pulse before data is sent. The internal register value is also changed to the other register of the pair

on the rising edge of the ACK clock pulse before data is sent. After the first byte is read, additional bytes may be

read, but the data now reflect the information in the other register in the pair. For example, if Input Port 1 is read,

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the next byte read is Input Port 0. If a restart occurs during a read, the data is lost because the internal register

already has been changed to the next register in the pair.

There is no limitation on the number of data bytes received in one read transmission, but when the final byte is

received, the bus controller must not acknowledge the data. 图 8-11 and 图 8-12 show two different scenarios of

Read Input Port Register.

SCL

I0.x

I1.x

I0.x

I1.x

SDA

A1 A0

Acknowledge

R/W

Acknowledge

From Target

No Acknowledge

From Controller

Read From Port 0

Data Into Port 0

Read From Port 1

Data Into Port 1

INT

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is

valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual

data transfer from the P port (see the 节8.6.3.1.2 section for these details).

图8-11. Read Input Port Register, Scenario 1

<br/>

SCL

10.x

11.x

10.x

11.x

A1 A0

SDA

Acknowledge

From Controller

Acknowledge

From Controller

Acknowledge

From Target

Acknowledge

From Controller

R/W

No Acknowledge

From Controller

Read From Port 0

Data Into Port 0

Data 00

Data 01

Data 02

Data 03

Read From Port 1

Data

Data 10

Data

Data Into Port 1

INT

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is

valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

This figure eliminates the command byte transfer, a restart, and target address call between the initial target address call and actual

data transfer from the P port (see the 节8.6.3.1.2 section for these details).

图8-12. Read Input Port Register, Scenario 2

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Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes. Customers should validate and test their design

implementation to confirm system functionality.

9.1 Application Information

Applications of the TCA9539-Q1 has this device connected as a target to an I²C controller (processor), and the

I²C bus may contain any number of other target devices. The TCA9539-Q1 is typically in a remote location from

the controller, placed close to the GPIOs to which the controller needs to monitor or control.

IO Expanders such as the TCA9539-Q1 are typically used for controlling LEDs (for feedback or status lights),

controlling enable or reset signals of other devices, and even reading the outputs of other devices or buttons.

9.2 Typical Application

图9-1 shows an application in which the TCA9539-Q1 can be used.

Subsystem 1

(e.g.,Temperature

Sensor)

INT

Subsystem 2

(e.g., Counter)

100 kΩ

2 kΩ

10 kΩ 10 kΩ 10 kΩ 10 kΩ

100 kΩ 100 kΩ

RESET

P00

SCL

SDA

INT

SCL

P01

Controller

GND

SDA

P02

P03

INT

ENABLE

RESET

P04

P05

TCA9539-Q1

Controlled Switch

(e.g., CBT Device)

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

ALARM

Keypad

Subsystem 3

(e.g., Alarm)

GND

Device address is configured as 1110100 for this example.

P00, P02, and P03 are configured as outputs.

P01 and P04 to P17 are configured as inputs.

Pin numbers shown are for the PW package.

图9-1. Application Schematic

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9.2.1 Design Requirements

9.2.1.1 Calculating Junction Temperature and Power Dissipation

When designing with the TCA9539-Q1, it is important that the 节 6.3 not be violated. Many of the parameters of

this device are rated based on junction temperature, so junction temperature must be calculated in order to verify

that safe operation of the device is met. The basic equation for junction temperature is shown in 方程式1.

T_j= T_A+ q ´ P

(

)

(1)

θ_JAis the standard junction to ambient thermal resistance measurement of the package, as seen in 节6.4 table.

P_dis the total power dissipation of the device, and the approximation is shown in 方程式2.

P » I_{CC_STATIC}´ V_CC

(

P_{d_PORT _L}

P_{d_PORT _H}

)

(2)

方程式 2 is the approximation of power dissipation in the device. The equation is the static power plus the

summation of power dissipated by each port (with a different equation based on if the port is outputting high, or

outputting low. If the port is set as an input, then power dissipation is the input leakage of the pin multiplied by

the voltage on the pin). Note that this ignores power dissipation in the INT and SDA pins, assuming these

transients to be small. They can easily be included in the power dissipation calculation by using 方程式 3 to

calculate the power dissipation in INT or SDA while they are pulling low, and this gives maximum power

dissipation.

P_{d_PORT _L}= I ´ V_OL

(

)

(3)

方程式 3 shows the power dissipation for a single port which is set to output low. The power dissipated by the

port is the V_OLof the port multiplied by the current it is sinking.

P_{d_PORT _H}= I

(

´ V - V_OH

(

)

(4)

方程式 4 shows the power dissipation for a single port which is set to output high. The power dissipated by the

port is the current sourced by the port multiplied by the voltage drop across the device (difference between V_CC

and the output voltage).

9.2.1.2 Minimizing I_CCWhen I/Os Control LEDs

When an I/O is used to control an LED, normally it is connected to V_CCthrough a resistor (see 图 9-1). Because

the LED acts as a diode, when the LED is off, the I/O V_INis about 1.2 V less than V_CC. The ΔI_CCparameter in

the 节 6.5 table show how I_CCincreases as V_INbecomes lower than V_CC. For battery-powered applications, it is

essential that the voltage of I/O pins is greater than or equal to V_CC, when the LED is off, to minimize current

consumption.

图 9-2 shows a high-value resistor in parallel with the LED. 图 9-3 shows V_CCless than the LED supply voltage

by at least 1.2 V. Both of these methods maintain the I/O V_CCat or above V_CCand prevent additional supply-

current consumption when the LED is off.

Take care to make sure that the recommended maximum I_OLthrough the ports not be violated based upon

junction temperature. See the 节6.3 for more information.

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LED

100 kΩ

图9-2. High-Value Resistor In Parallel With LED

3.3 V

5 V

LED

图9-3. Device Supplied By Lower Voltage

9.2.2 Detailed Design Procedure

The pull-up resistors, R_P, for the SCL and SDA lines need to be selected appropriately and take into

consideration the total capacitance of all targets on the I²C bus. The minimum pull-up resistance is a function of

_CC, V_OL,(max), and I_OLas shown in 方程式5.

V_CC- V_OL(max)

R_p(min)

I_OL

(5)

The maximum pull-up resistance is a function of the maximum rise time, t_r(300 ns for fast-mode operation,

f_SCL= 400 kHz) and bus capacitance, C_bas shown in 方程式6.

t_r

R_p(max)

0.8473´C_b

(6)

The maximum bus capacitance for an I²C bus must not exceed 400 pF for standard-mode or fast-mode

operation. The bus capacitance can be approximated by adding the capacitance of the TCA9539-Q1, C_ifor SCL

or C_iofor SDA, the capacitance of wires, connections, traces, and the capacitance of additional targets on the

bus.

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9.2.3 Application Curves

1.8

1.6

1.4

1.2

Standard-mode

Fast-mode

0.8

0.6

0.4

0.2

V_CC> 2V

V_CC<= 2

0.5

1.5

2.5 3

V_CC(V)

3.5

4.5

5.5

100 150 200 250 300 350 400 450

C_b(pF)

D009

D008

Standard-mode

Fast-mode

V_OL= 0.2 × V_CC, I_OL= 2 mA when V_CC≤2 V

(f_SCL= 100 kHz, t_r= 1 µs)

(f_SCL= 400 kHz, t_r= 300 ns)

V_OL= 0.4 V, I_OL= 3 mA when V_CC> 2 V

图9-4. Maximum Pull-Up resistance (R_p(max)) vs

图9-5. Minimum Pull-Up Resistance (R_p(min)) vs

Pull-Up Reference Voltage (V_CC

Bus Capacitance (C_b)

)

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9 Power Supply Recommendations

9.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9539-Q1 can be reset to its default conditions by using the power-

on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

The voltage waveform for a power-on reset is shown in 图9-1.

Ramp-Down

Ramp-Up

CC_TRR

drops below V_PORF– 50 mV

Time

Time to Re-Ramp

CC_FT

CC_RT

图9-1. V_CCis Lowered Below the POR Threshold, then Ramped Back Up to V_CC

表9-1 specifies the performance of the power-on reset feature for TCA9539-Q1.

表9-1. Recommended Supply Sequencing And Ramp Rates ⁽¹⁾

PARAMETER

MIN TYP

MAX UNIT

V_{CC_FT}

V_{CC_RT}

Fall rate

0.1

See 图9-1

Rise rate

Time to re-ramp (when V_CCdrops to V_{POR_MIN}–50 mV or

when V_CCdrops to GND)

V_{CC_TRR}

V_{CC_GH}

V_{CC_MV}

See 图9-1

See 图9-2

μs

The level (referenced to V_CC) that V_CCcan glitch down to, but

not cause a functional disruption when V_{CC_GW}

1.2

The minimum voltage that V_CCcan glitch down to without

causing a reset (V_{CC_GH}must not be violated)

1.5

See 图9-2

V_{CC_GW}

V_PORF

V_PORR

Glitch width that does not cause a functional disruption

Voltage trip point of POR on falling V_CC

μs

0.75

Voltage trip point of POR on rising V_CC

1.2

1.5

(1) T_A= –40°C to +125°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. 图 9-2 and 表 9-1 provide more

information on how to measure these specifications.

CC_GH

CC_MV

Time

CC_GW

图9-2. Glitch Width, Glitch Height, and Minimum Glitch Voltage

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V_PORis critical to the power-on reset. V_{POR R}is the voltage level at which the reset condition is released and all

the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers

based on the V_CCbeing lowered to or from 0. 图9-3 and 表9-1 provide more details on this specification.

V_CC

V_PORR

V_PORF

Time

POR

Time

图9-3. V_POR

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10 Layout

10.1 Layout Guidelines

For printed circuit board (PCB) layout of the TCA9539-Q1, common PCB layout practices must be followed but

additional concerns related to high-speed data transfer such as matched impedances and differential pairs are

not a concern for I²C signal speeds.

In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from

each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher

amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors

are commonly used to control the voltage on the V_CCpin, using a larger capacitor to provide additional power in

the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These

capacitors must be placed as close to the TCA9539-Q1 as possible. These best practices are shown in 图10-1.

For the layout example provided in 图 10-1, it would be possible to fabricate a PCB with only 2 layers by using

the top layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND).

However, a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is

common to route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and

dedicate the other internal layer to a power plane. In a board layout using planes or split planes for power and

ground, vias are placed directly next to the surface mount component pad which must attach to V_CCor GND and

the via is connected electrically to the internal layer or the other side of the board. Vias are also used when a

signal trace needs to be routed to the opposite side of the board, but this technique is not demonstrated in 图

10-1.

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10.2 Layout Example

LEGEND

Partial view of plane

(inner layer)

Via to power plane

Via to GND plane

By-pass/de-coupling

capacitors

图10-1. TCA9539-Q1 Layout

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Understanding the I2C Bus, SLVA704

• I2C Pull-up Resistor Calculation, SLVA689

• Introduction to Logic, SLVA700

• Maximum Clock Frequency of I2C Bus Using Repeaters, SLVA695

• I2C Bus Pull-Up Resistor Calculation, SLVA689

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCA9539QPWRQ1

ACTIVE

TSSOP

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 125

TCA539Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TCA9539-Q1 :

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

31-Aug-2021

Catalog : TCA9539

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCA9539QPWRQ1

TSSOP

2000

330.0

16.4

6.95

8.3

1.6

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 24

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

TCA9539QPWRQ1

2000

Pack Materials-Page 2

PACKAGE OUTLINE

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

22X 0.65

7.15

7.9

7.7

NOTE 3

0.30

24X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

0.25

GAGE PLANE

0.15

0.05

(0.15) TYP

SEE DETAIL A

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220208/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

24X (1.5)

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220208/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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EXAMPLE STENCIL DESIGN

PW0024A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

24X (1.5)

SYMM

(R0.05) TYP

24X (0.45)

22X (0.65)

SYMM

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220208/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

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TCA9539-Q1 [TI]

相关型号：

TCA9539PWR

TCA9539QPWRQ1

TCA9539RGER

TCA9539RTWR

TCA9539_15

TCA9543A

TCA9543ADR

TCA9543APWR

TCA9544A

TCA9544APWR

TCA9545A

TCA9545APWR