TCA9545APWR [TI]

具有中断、复位和电压转换功能的 4 通道、1.65V 至 5.5V I2C/SMBus 开关 | PW | 20 | -40 to 85;


型号：	TCA9545APWR
厂家：	TEXAS INSTRUMENTS
描述：	具有中断、复位和电压转换功能的 4 通道、1.65V 至 5.5V I2C/SMBus 开关 \| PW \| 20 \| -40 to 85 开关光电二极管接口集成电路
文件：	总31页 (文件大小：845K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

TCA9545A 低压 4 通道 I²C 和系统管理总线 (SMbus) 开关，具有中断逻辑

电路和复位功能

1 特性

2 应用

•

4 选 1 双向转换开关

•

服务器

与 I²C 总线和 SMBus 兼容

四个低电平有效中断输入

低电平有效中断输出

路由器（电信交换设备）

工厂自动化

具有 I²C 从器件地址冲突（例如多个完全一样的温

度传感器）的产品

低电平有效复位输入

两个地址终端，允许在 I²C 总线上支持多达四个器

件

3 说明

TCA9545A 是一款通过 I²C 总线控制的四路双向转换

开关。串行时钟/串行数据 (SCL/SDA) 上行对分散到四

个下行对，或者通道。根据可编程控制寄存器的内容，

可选择任一单独 SCn/SDn 通道或者通道组合。提供四

个中断输入 (INT3-INT0)，每个中断输入针对一个下行

对。一个中断 (INT) 输出可作为四个中断输入的与

(AND) 操作。

•

通过 I²C 总线进行通道选择，可任意组合

上电时所有开关通道取消选定

低 R_ON开关

支持在 1.8V、2.5V、3.3V 和 5V 总线间进行电压

电平转换

•

上电时无干扰

支持热插入

低待机电流

一个低电平有效 (RESET) 输入使得 TCA9545A 能够

在其中一个下行 I²C 总线长时间处于低电平状态时恢

复。将 RESET 下拉为低电平会使 I²C 状态机复位，并

且使所有通道取消选中，这一功能与内部加电复位功能

的作用一样。

工作电源电压范围为

1.65V 至 5.5V

•

5.5V 耐压输入

0 至 400kHz 时钟频率

闩锁性能超过 JESD 78 所规定的 100mA

ESD 保护性能超出 JESD 22 标准

在开关上建有导通栅极，这样的话，VCC 端子可被用

于限制 TCA9545A 传递的最大高压。这允许在每个对

上使用不同的总线电压，以便 1.8V，2.5V 或 3.3V 部

件可以在没有任何额外保护的情况下与 5V 部件通信。

对于每个通道，外部上拉电阻器将总线电压上拉至所需

的电压水平。所有 I/O 引脚为 5.5V 耐压。

–

4000V 人体放电模型 (A114-A)

1500V 充电器件模型 (C101)

器件信息

订货编号

封装

封装尺寸

薄型小外形尺寸封装

(02)

TCA9545APWR

6.5mm x 4.4mm

简化的应用示意图

Channel 0

VCC

SD0

SC0

INT0

SDA

SCL

INT

Slaves A₀, A₁...A_N

I2C or SMBus

Master

Channel 1

SD1

SC1

INT1

RESET

(e.g. µProcessor)

Slaves B₀, B₁...B_N

TCA9545A

Channel 2

Channel 3

SD2

SC2

INT2

Slaves C₀, C₁...C_N

Slaves D₀, D₁...D_N

SD3

GND

SC3

INT3

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS204

TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

www.ti.com.cn

8.3 Feature Description................................................. 12

8.4 Device Functional Modes........................................ 12

8.5 Programming........................................................... 12

8.6 Control Register ...................................................... 15

Application and Implementation ........................ 17

9.1 Application Information............................................ 17

9.2 Typical Application .................................................. 17

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 4

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions ...................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 I²C Interface Timing Requirements........................... 6

6.7 Switching Characteristics.......................................... 7

6.8 Interrupt and Reset Timing Requirements................ 7

6.9 Typical Characteristics.............................................. 8

Parameter Measurement Information .................. 9

Detailed Description ............................................ 11

8.1 Overview ................................................................. 11

8.2 Functional Block Diagram ....................................... 11

10 Power Supply Recommendations ..................... 20

10.1 Power-On Reset Requirements ........................... 20

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................. 22

11.2 Layout Example .................................................... 22

12 器件和文档支持 ..................................................... 23

12.1 接收文档更新通知 ................................................. 23

12.2 支持资源................................................................ 23

12.3 商标....................................................................... 23

12.4 静电放电警告......................................................... 23

12.5 Glossary................................................................ 23

13 机械、封装和可订购信息....................................... 23

4 修订历史记录

Changes from Revision C (July 2019) to Revision D

Page

•

Changed V_CC= 3.3 V to V_CC= 2.5 V in Figure 16................................................................................................................ 17

Changes from Revision B (March 2014) to Revision C

Page

•

Moved T_stgto the Absolute Maximum Ratings table............................................................................................................... 4

Changed the Handling Ratings table To: ESD Ratings table................................................................................................. 4

Changed the last row of column B1 From: X To: 0 in Table 1 ............................................................................................ 16

Changes from Revision A (March 2014) to Revision B

Page

•

更新了图形中的引脚名称。..................................................................................................................................................... 1

Changes from Original (January 2014) to Revision A

Page

•

将“预览”文档更新为完整版。 .................................................................................................................................................. 1

TCA9545A

www.ti.com.cn

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

5 Pin Configuration and Functions

PW package

20-Pin TSSOP

Top View

VCC

SDA

SCL

INT

RESET

INT0

SD0

SC3

SD3

INT3

SC2

SD2

INT2

SC0

INT1

SD1

SC1

GND

Not to scale

Pin Functions

DESCRIPTION

NO.

NAME

Address input 0. Connect directly to V_CCor ground.

Address input 1. Connect directly to V_CCor ground.

Active-low reset input. Connect to V_CCor V_DPUM⁽¹⁾through a pull-up resistor if not

used.

RESET

INT0

SD0

SC0

INT1

SD1

SC1

GND

INT2

SD2

SC2

INT3

SD3

SC3

INT

Active-low interrupt input 0. Connect to V_DPU0⁽¹⁾through a pull-up resistor.

Serial data 0. Connect to V_DPU0⁽¹⁾through a pul-up resistor.

(1)

Serial clock 0. Connect to V_DPU0through a pull-up resistor.

Active-low interrupt input 1. Connect to V_DPU1⁽¹⁾through a pull-up resistor.

Serial data 1. Connect to V_DPU1⁽¹⁾through a pull-up resistor.

Serial clock 1. Connect to V_DPU1⁽¹⁾through a pull-up resistor.

Ground

Active-low interrupt input 2. Connect to V_DPU2⁽¹⁾through a pull-up resistor.

Serial data 2. Connect to V_DPU2⁽¹⁾through a pull-up resistor.

Serial clock 2. Connect to V_DPU2⁽¹⁾through a pull-up resistor.

Active-low interrupt input 3. Connect to V_DPU3⁽¹⁾through a pull-up resistor.

Serial data 3. Connect to V_DPU3⁽¹⁾through a pull-up resistor.

Serial clock 3. Connect to V_DPU3⁽¹⁾through a pull-up resistor.

Active-low interrupt output. Connect to V_DPUM⁽¹⁾through a pull-up resistor.

Serial clock line. Connect to V_DPUM⁽¹⁾through a pull-up resistor.

Serial data line. Connect to V_DPUM⁽¹⁾through a pull-up resistor.

Supply power

SCL

SDA

VCC

(1) V_DPUXis the pull-up reference voltage for the associated data line. V_DPUMis the master I²C master reference voltage and V_DPU0–V_DPU3

are the slave channel reference voltages.

TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

UNIT

V_CC

V_I

Supply voltage range

Input voltage range⁽²⁾

I_I

Input current

±20

±25

±100

400

°C

I_O

Output current

Continuous current through V_CC

Continuous current through GND

Total power dissipation

Operating free-air temperature range

Storage temperature range

P_tot

T_A

–40

–65

T_stg

150

°C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

6.2 ESD Ratings

PARAMETER

DEFINITION

MIN MAX UNIT

Human Body Model (HBM), ESD Stress Voltage⁽²⁾

Charged Device Model (CDM) ESD Stress Voltage⁽³⁾All Terminals

All Terminals

4000

1500

(1)

V_ESD

(1) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by assembly line electrostatic discharges into

the device.

(2) Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500-V HBM allows safe

manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance.

(3) Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250-V CDM allows safe

manufacturing with a standard ESD control process. Terminals listed as 250 V may actually have higher performance.

6.3 Recommended Operating Conditions⁽¹⁾

MIN

1.65

MAX UNIT

V_CC

V_IH

Supply voltage

5.5

SCL, SDA

0.7 × V_CC

–0.5

High-level input voltage

A1, A0, INT3–INT0, RESET

SCL, SDA

V_CC+ 0.5

0.3 × V_CC

V_IL

T_A

Low-level input voltage

A1, A0, INT3–INT0, RESET

–0.5

Operating free-air temperature

–40

°C

(1) All unused inputs of the device must be held at V_CCor GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

TCA9545A

THERMAL METRIC⁽¹⁾

20 TERMINALS

115.3

UNIT

θ_JA

Junction-to-ambient thermal resistance

θ_JCtop

θ_JB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

48.7

66.4

°C/W

ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

6.5

ψ_JB

65.8

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TCA9545A

www.ti.com.cn

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CC

MIN TYP⁽¹⁾

MAX UNIT

Power-on reset voltage, VCC

rising

V_PORR

V_PORF

No load, V_I= V_CCor GND⁽²⁾

1.2

1.5

Power-on reset voltage, VCC

falling⁽³⁾

No load,V_I= V_CCor GND⁽²⁾

0.8

5 V

4.5 V to 5.5 V

3.3 V

3.6

2.6

1.6

1.0

0.5

4.5

2.8

1.8

1.9

1.4

0.8

3 V to 3.6 V

2.5 V

V_pass

Switch output voltage

V_SWin= V_CC

I_SWout= –100 μA

2.3 V to 2.7 V

1.8 V

1.65 V to 1.95 V

1.65 V to 5.5 V

1.1

I_OH

INT

V_O= V_CC

μA

V_OL= 0.4 V

V_OL= 0.6 V

V_OL= 0.4 V

SDA

I_OL

1.65 V to 5.5 V

INT

SCL, SDA

SC3–SC0, SD3–SD0

A1, A0

±1

I_I

V_I= V_CCor GND⁽²⁾

1.65 V to 5.5 V

μA

INT3–INT0

RESET

5.5 V

3.6 V

2.7 V

1.65 V

5.5 V

3.6 V

2.7 V

1.65 V

5.5 V

3.6 V

2.7 V

1.65 V

5.5 V

3.6 V

2.7 V

1.65 V

V_I= V_CCor GND⁽²⁾

I_O= 0

t_r,max= 300 ns

f_SCL= 400 kHz

Operating mode

V_I= V_CCor GND⁽²⁾

I_O= 0

t_r,max= 1 µs

f_SCL= 100 kHz

I_CC

μA

1.6

1.0

0.7

0.4

1.6

1.0

0.7

0.4

1.3

1.1

0.55

Low inputs

V_I= GND⁽²⁾

I_O= 0

Standby mode

1.3

1.1

0.55

High inputs

V_I= V_CC

I_O= 0

One INT3–INT0 input at 0.6 V,

Other inputs at V_CCor GND⁽²⁾

INT3–INT0

SCL, SDA

One INT3–INT0 input at V_CC– 0.6 V,

Other inputs at V_CCor GND⁽²⁾

Supply-current

change

ΔI_CC

1.65 V to 5.5 V

μA

SCL or SDA input at 0.6 V,

Other inputs at V_CCor GND⁽²⁾

SCL or SDA input at V_CC– 0.6 V,

Other inputs at V_CCor GND⁽²⁾

(1) All typical values are at nominal supply voltage (V_CC= 1.8 V, 2.5 V, 3.3 V, or 5 V), T_A= 25°C.

(2) RESET = V_CC(held high) when all other input voltages, V_I= GND

(3) The power-on reset circuit resets the I²C bus logic with V_CC< V_PORF

TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

www.ti.com.cn

Electrical Characteristics (continued)

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER

A1, A0

TEST CONDITIONS

V_CC

MIN TYP⁽¹⁾

MAX UNIT

4.5

C_i

INT3–INT0

V_I= V_CCor GND⁽²⁾

1.65 V to 5.5 V

5.5

RESET

SCL, SDA

V_I= V_CCor

GND⁽²⁾

(4)

C_io(OFF)

Switch OFF

I_O= 15 mA

I_O= 10 mA

1.65 V to 5.5 V

SC3–SC0, SD3–SD0

4.5 V to 5.5 V

3 V to 3.6 V

V_O= 0.4 V

R_ON

Switch on-state resistance

Ω

2.3 V to 2.7 V

1.65 V to 1.95 V

(4) C_io(ON)depends on the device capacitance and load that is downstream from the device.

6.6 I²C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5)

STANDARD MODE

I²C BUS

FAST MODE

I²C BUS

UNIT

MIN

MAX

MIN

MAX

f_scl

t_sch

t_scl

t_sp

I²C clock frequency

I²C clock high time

I²C clock low time

I²C spike time

I²C serial-data setup time

I²C serial-data hold time

I²C input rise time

I²C input fall time

100

400

kHz

μs

0.6

1.3

4.7

t_sds

t_sdh

t_icr

250

0⁽¹⁾

100

0⁽¹⁾

(2)

1000

300

20 + 0.1C_b

300

(2)

t_icf

20 + 0.1C_b

t_ocf

t_buf

t_sts

t_sth

t_sps

I²C output fall time

10-pF to 400-pF bus

300

I²C bus free time between stop and start

I²C start or repeated start condition setup

I²C start or repeated start condition hold

I²C stop condition setup

4.7

1.3

0.6

SCL low to SDA output low

valid

t_vdL(Data)Valid-data time (high to low)⁽³⁾

t_vdH(Data)Valid-data time (low to high)⁽³⁾

μs

SCL low to SDA output high

valid

0.6

ACK signal from SCL low

to SDA output low

t_vd(ack)

C_b

Valid-data time of ACK condition

I²C bus capacitive load

μs

400

(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to as the V_IHmin of the SCL signal), in order

to bridge the undefined region of the falling edge of SCL.

(2) C_b= total bus capacitance of one bus line in pF

(3) Data taken using a 1-kΩ pullup resistor and 50-pF load (see Figure 5)

TCA9545A

www.ti.com.cn

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

6.7 Switching Characteristics

over recommended operating free-air temperature range, C_L≤ 100 pF (unless otherwise noted) (see Figure 7)

FROM

(INPUT)

(OUTPUT)

PARAMETER

MIN

MAX

UNIT

R_ON= 20 Ω, C_L= 15 pF

R_ON= 20 Ω, C_L= 50 pF

0.3

(1)

t_pd

Propagation delay time

SDA or SCL

SDn or SCn

t_iv

t_ir

Interrupt valid time⁽²⁾

Interrupt reset delay time⁽²⁾

INTn

INT

μs

(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capacitance, when driven by an ideal voltage source (zero output impedance).

(2) Data taken using a 4.7-kΩ pullup resistor and 100-pF load (see Figure 7)

6.8 Interrupt and Reset Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7)

PARAMETER

Low-level pulse duration rejection of INTn inputs

High-level pulse duration rejection of INTn inputs

Pulse duration, RESET low

MIN

MAX UNIT

t_PWRL

t_PWRH

t_WL

μs

0.5

(1)

t_rst

RESET time (SDA clear)

500

t_REC(STA)

Recovery time from RESET to start

(1) t_rstis the propagation delay measured from the time the RESET terminal is first asserted low to the time the SDA terminal is asserted

high, signaling a stop condition. It must be a minimum of t_WL

TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

www.ti.com.cn

6.9 Typical Characteristics

800

1.8

1.6

1.4

1.2

V_CC= 5.5V

V_CC= 3.3V

V_CC= 1.65V

700

600

500

400

300

200

100

0.8

0.6

0.4

0.2

25ºC (Room Temperature)

85ºC

-40ºC

I_OL(mA)

1.5

2.5

3.5

V_CC(V)

4.5

5.5

D003

D004

Figure 1. SDA Output Low Voltage (V_OL) vs Load Current

(I_OL) at Three V_CCLevels

Figure 2. Standby Current (I_CC) vs Supply Voltage (V_CC) at

Three Temperature Points

25ºC (Room Temperature)

85ºC

-40º

5.8

5.6

5.4

5.2

4.8

4.6

4.4

4.2

25ºC (Room Temperature)

85ºC

-40ºC

0.5

1.5

2.5

V_CC(V)

3.5

4.5

5.5

0.5

1.5

2.5

V_CC(V)

3.5

4.5

5.5

D006

D001

Figure 3. Slave channel (SCn/SDn) capacitance (C_io(OFF)) vs.

Supply Voltage (V_CC) at Three Temperature Points

Figure 4. ON-Resistance (R_ON) vs Supply Voltage (V_CC) at

Three Temperatures

TCA9545A

www.ti.com.cn

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

7 Parameter Measurement Information

= 1 kΩ

SDn, SCn

DUT

= 50 pF

(See Note A)

I C PORT LOAD CONFIGURATION

Two Bytes for Complete

Device Programming

Stop

Condition Condition

(P) (S)

Start

Address

Bit 7

(MSB)

R/W

Bit 0

(LSB)

Data

Bit 7

(MSB)

Data

Bit 0

(LSB)

Stop

Condition

(P)

ACK

(A)

Address

Bit 6

Address

Bit 1

ACK

(A)

BYTE

DESCRIPTION

I C address + R/W

Control register data

scl

sch

0.7 × V

0.3 × V

SCL

SDA

vd(ACK)

or t

icr

sts

vdL

icf

buf

vdH

0.7 × V

0.3 × V

icf

icr

sdh

sps

sth

Repeat

sds

Stop

Condition

Start

Condition

Start or Repeat

Start Condition

VOLTAGE WAVEFORMS

A. C_Lincludes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω,

t_r/t_f= 30 ns.

C. The outputs are measured one at a time, with one transition per measurement.

Figure 5. I²C Interface Load Circuit, Byte Descriptions, and Voltage Waveforms

TCA9545A

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

www.ti.com.cn

Parameter Measurement Information (continued)

Start

ACK or Read Cycle

SCL

SDA

30%

50%

rst

RESET

REC

Figure 6. Reset Timing

= 4.7 kΩ

INT

DUT

= 100 pF

(See Note A)

INTERRUPT LOAD CONFIGURATION

INTn

0.5 × V

(input)

0.5 × V

(input)

INT

0.5 × V

(output)

VOLTAGE WAVEFORMS (t )

A. C_Lincludes probe and jig capacitance.

B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω,

t_r/t_f= 30 ns.

Figure 7. Interrupt Load Circuit and Voltage Waveforms

TCA9545A

www.ti.com.cn

ZHCSC52D –JANUARY 2014–REVISED NOVEMBER 2019

8 Detailed Description

8.1 Overview

The TCA9545A is a 4-channel, bidirectional translating I²C switch. The master SCL/SDA signal pair is directed to

four channels of slave devices, SC0/SD0-SC3/SD3. Any individual downstream channel can be selected as well

as any combination of the four channels. The TCA9545A also supports interrupt signals in order for the master to

detect an interrupt on the INT output terminal that can result from any of the slave devices connected to the

INT3-INT0 input terminals.

The device offers an active-low RESET input which resets the state machine and allows the TCA9545A to

recover should one of the downstream I²C buses get stuck in a low state. The state machine of the device can

also be reset by cycling the power supply, V_CC, also known as a power-on reset (POR). Both the RESET function

and a POR will cause all channels to be deselected.

The connections of the I²C data path are controlled by the same I²C master device that is switched to

communicate with multiple I²C slaves. After the successful acknowledgment of the slave address (hardware

selectable by A0 and A1 terminals), a single 8-bit control register is written to or read from to determine the

selected channels and state of the interrupts.

The TCA9545A may also be used for voltage translation, allowing the use of different bus voltages on each

SCn/SDn pair such that 1.8-V, 2.5-V, or 3.3-V parts can communicate with 5-V parts. This is achieved by using

external pull-up resistors to pull the bus up to the desired voltage for the master and each slave channel.

8.2 Functional Block Diagram

TCA9545A

SC0

SC1

SC2

SC3

SD0

SD1

SD2

SD3

Switch Control Logic

GND

VCC

Power-on Reset

RESET

SCL

Input Filter

I C Bus Control

SDA

INT0

INT1

INT2

INT3

Output

Filter

INT

Interrupt Logic

TCA9545A

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8.3 Feature Description

The TCA9545A is a 4-channel, bidirectional translating switch for I²C buses that supports Standard-Mode (100

kHz) and Fast-Mode (400 kHz) operation. The TCA9545A features I²C control using a single 8-bit control register

in which the four least significant bits control the enabling and disabling of the 4 switch channels of I²C data flow.

The TCA9545A also supports interrupt signals for each slave channel and this data is held in the four most

significant bits of the control register. Depending on the application, voltage translation of the I²C bus can also be

achieved using the TCA9545A to allow 1.8-V, 2.5-V, or 3.3-V parts to communicate with 5-V parts. Additionally,

in the event that communication on the I²C bus enters a fault state, the TCA9545A can be reset to resume

normal operation using the RESET pin feature or by a power-on reset which results from cycling power to the

device.

8.4 Device Functional Modes

8.4.1 RESET Input

The RESET input can be used to recover the TCA9545A from a bus-fault condition. The registers and the I²C

state machine within this device initialize to their default states if this signal is asserted low for a minimum of t_WL

All channels also are deselected in this case. RESET must be connected to V_CCthrough a pull-up resistor.

8.4.2 Power-On Reset

When power is applied to VCC, an internal power-on reset holds the TCA9545A in a reset condition until V_CChas

reached V_PORR. At this point, the reset condition is released and the TCA9545A registers and I²C state machine

are initialized to their default states, all zeroes, causing all the channels to be deselected. Thereafter, V_CCmust

be lowered below at least V_PORFto reset the device.

8.5 Programming

8.5.1 I²C Interface

The I²C bus is for two-way two-line communication between different ICs or modules. The two lines are a serial

data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up

resistor when connected to the output stages of a device. Data transfer can be initiated only when the bus is not

busy.

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high

period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see Figure 8).

SDA

SCL

Data Line

Stable;

Data Valid

Change

of Data

Allowed

Figure 8. Bit Transfer

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the

clock is high is defined as the start condition (S). A low-to-high transition of the data line while the clock is high is

defined as the stop condition (P) (see Figure 9).

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Programming (continued)

SDA

SCL

Start Condition

Stop Condition

Figure 9. Definition of Start and Stop Conditions

A device generating a message is a transmitter; a device receiving a message is the receiver. The device that

controls the message is the master, and the devices that are controlled by the master are the slaves (see

Figure 10).

SDA

SCL

I C

Multiplexer

Master

Transmitter/

Receiver

Master

Transmitter/

Receiver

Slave

Transmitter/

Receiver

Master

Transmitter

Slave

Receiver

Slave

Figure 10. System Configuration

The number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not

limited. Each byte of eight bits is followed by one acknowledge (ACK) bit. The transmitter must release the SDA

line before the receiver can send an ACK bit.

When a slave receiver is addressed, it must generate an ACK after the reception of each byte. Also, a master

must generate an ACK after the reception of each byte that has been clocked out of the slave transmitter. The

device that acknowledges must pull down the SDA line during the ACK clock pulse so that the SDA line is stable

low during the high pulse of the ACK-related clock period (see Figure 11). Setup and hold times must be taken

into account.

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Programming (continued)

Data Output

by Transmitter

NACK

Data Output

by Receiver

ACK

SCL From

Master

Start

Clock Pulse for ACK

Condition

Figure 11. Acknowledgment on the I²C Bus

A master receiver must signal an end of data to the transmitter by not generating an acknowledge (NACK) after

the last byte has been clocked out of the slave. This is done by the master receiver by holding the SDA line high.

In this event, the transmitter must release the data line to enable the master to generate a stop condition.

Data is transmitted to the TCA9545A control register using the write mode shown in Figure 12.

Slave Address

Control Register

SDA

A1 A0

B3 B2 B1 B0

ACK From Slave

Stop Condition

R/W ACK From Slave

Start Condition

Figure 12. Write Control Register

Data is read from the TCA9545A control register using the read mode shown in Figure 13.

Slave Address

Control Register

SDA

INT3 INT2 INT1INT0 B3 B2 B1 B0

A1 A0

Start Condition

R/W ACK From Slave

NACK From Master

Stop Condition

Figure 13. Read Control Register

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8.6 Control Register

8.6.1 Device Address

Following a start condition, the bus master must output the address of the slave it is accessing. The address of

the TCA9545A is shown in Figure 14. To conserve power, no internal pullup resistors are incorporated on the

hardware-selectable address terminals, and they must be pulled high or low.

Slave Address

R/W

Hardware

Selectable

Fixed

Figure 14. TCA9545A Address

The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,

while a logic 0 selects a write operation.

8.6.2 Control Register Description

Following the successful acknowledgment of the slave address, the bus master sends a byte to the TCA9545A,

which is stored in the control register (see Figure 15). If multiple bytes are received by the TCA9545A, it saves

the last byte received. This register can be written and read via the I²C bus.

Interrupt Bits

(Read Only)

Channel-Selection Bits

(Read/Write)

INT3 INT2 INT1 INT0 B3

Channel 0

Channel 1

Channel 2

Channel 3

INT0

INT1

INT2

INT3

Figure 15. Control Register

8.6.3 Control Register Definition

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see

Table 1). After the TCA9545A has been addressed, the control register is written. The four LSBs of the control

byte are used to determine which channel or channels are to be selected. When a channel is selected, the

channel becomes active after a stop condition has been placed on the I²C bus. This ensures that all SCn/SDn

lines are in a high state when the channel is made active, so that no false conditions are generated at the time of

connection. A stop condition must occur always right after the acknowledge cycle.

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Control Register (continued)

Table 1. Control Register Write (Channel Selection), Control Register Read (Channel Status)⁽¹⁾

INT3

INT2

INT1

INT0

COMMAND

Channel 0 disabled

Channel 0 enabled

Channel 1 disabled

Channel 1 enabled

Channel 2 disabled

Channel 2 enabled

Channel 3 disabled

Channel 3 enabled

No channel selected,

power-up/reset default state

(1) Several channels can be enabled at the same time. For example, B3 = 0, B2 = 1, B1 = 1, B0 = 0 means that channels 0 and 3 are

disabled, and channels 1 are 2 and enabled. Care should be taken not to exceed the maximum bus capacity.

8.6.4 Interrupt Handling

The TCA9545A provides four interrupt inputs (one for each channel) and one open-drain interrupt output (see

Table 2). When an interrupt is generated by any device, it is detected by the TCA9545A and the interrupt output

is driven low. The channel does not need to be active for detection of the interrupt. A bit also is set in the control

Bits 4–7 of the control register correspond to channels 0–3 of the TCA9545A, respectively. Therefore, if an

interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the

control register when a read is accomplished. Likewise, an interrupt on any device connected to channel 0 would

cause bit 4 of the control register to be set on the read. The master then can address the TCA9545A and read

the contents of the control register to determine which channel contains the device generating the interrupt. The

master then can reconfigure the TCA9545A to select this channel and locate the device generating the interrupt

and clear it.

It should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to

ensure that all devices on a channel are interrogated for an interrupt.

The interrupt inputs can be used as general-purpose inputs if the interrupt function is not required.

If unused, interrupt input(s) must be connected to V_CC

Table 2. Control Register Read (Interrupt)⁽¹⁾

INT3

INT2

INT1

INT0

COMMAND

No interrupt on channel 0

Interrupt on channel 0

No interrupt on channel 1

Interrupt on channel 1

No interrupt on channel 2

Interrupt on channel 2

No interrupt on channel 3

Interrupt on channel 3

(1) Several interrupts can be active at the same time. For example, INT3 = 0, INT2 = 1, INT1 = 1, INT0 = 0 means that there is no interrupt

on channels 0 and 3, and there is interrupt on channels 1 and 2.

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9 Application and Implementation

9.1 Application Information

Applications of the TCA9545A will contain an I²C (or SMBus) master device and up to four I²C slave devices.

The downstream channels are ideally used to resolve I²C slave address conflicts. For example, if four identical

digital temperature sensors are needed in the application, one sensor can be connected at each channel: 0, 1, 2,

and 3. When the temperature at a specific location needs to be read, the appropriate channel can be enabled

and all other channels switched off, the data can be retrieved, and the I²C master can move on and read the next

channel.

In an application where the I²C bus will contain many additional slave devices that do not result in I²C slave

address conflicts, these slave devices can be connected to any desired channel to distribute the total bus

capacitance across multiple channels. If multiple switches will be enabled simultaneously, additional design

requirements must be considered (See Design Requirements and Detailed Design Procedure).

9.2 Typical Application

A typical application of the TCA9545A will contain anywhere from 1 to 5 separate data pull-up voltages, V_DPUX

one for the master device (V_DPUM) and one for each of the selectable slave channels (V_DPU0– V_DPU3). In the

event where the master device and all slave devices operate at the same voltage, then the pass voltage, V_pass

V_DPUX. Once the maximum V_passis known, V_cccan be selected easily using Figure 17. In an application where

voltage translation is necessary, additional design requirements must be considered (See Design Requirements).

Figure 16 shows an application in which the TCA9545A can be used.

DPUM

= 1.65 V to 5.5 V

= 2.5 V

DPU0

= 1.65 V to 5.5 V

VCC

SD0

SC0

INT0

SDA

Channel 0

I C/SMBus

Master

SCL

INT

SCL

= 1.65 V to 5.5 V

DPU1

DPU2

DPU3

RESET

SD1

Channel 1

SC1

INT1

= 1.65 V to 5.5 V

TCA9545A

SD2

Channel 2

SC2

INT2

= 1.65 V to 5.5 V

SD3

SC3

INT3

Channel 3

GND

Figure 16. TCA9545A Typical Application Schematic

TCA9545A

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Typical Application (continued)

9.2.1 Design Requirements

The pull-up resistors on the INT3-INT0 terminals in the application schematic are not required in all applications.

If the device generating the interrupt has an open-drain output structure or can be tri-stated, a pull-up resistor is

required. If the device generating the interrupt has a push-pull output structure and cannot be tri-stated, a pull-up

resistor is not required. The interrupt inputs should not be left floating in the application.

The A0 and A1 terminals are hardware selectable to control the slave address of the TCA9545A. These

terminals may be tied directly to GND or V_CCin the application.

If multiple slave channels will be activated simultaneously in the application, then the total I_OLfrom SCL/SDA to

GND on the master side will be the sum of the currents through all pull-up resistors, R_p.

The pass-gate transistors of the TCA9545A are constructed such that the V_CCvoltage can be used to limit the

maximum voltage that is passed from one I²C bus to another.

Figure 17 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using

data specified in the Electrical Characteristics section of this data sheet). In order for the TCA9545A to act as a

voltage translator, the V_passvoltage must be equal to or lower than the lowest bus voltage. For example, if the

main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V_passmust be equal to or below 2.7 V

to effectively clamp the downstream bus voltages. As shown in Figure 17, V_pass(max)is 2.7 V when the TCA9545A

supply voltage is 4 V or lower, so the TCA9545A supply voltage could be set to 3.3 V. Pull-up resistors then can

be used to bring the bus voltages to their appropriate levels (see Figure 16).

9.2.2 Detailed Design Procedure

Once all the slaves are assigned to the appropriate slave channels and bus voltages are identified, the pull-up

resistors, R_p, for each of the buses need to be selected appropriately. The minimum pull-up resistance is a

function of V_DPUX, V_OL,(max), and I_OL

V_DPUX- V_OL(max)

R_p(min)

I_OL

(1)

The maximum pull-up resistance is a function of the maximum rise time, t_r(300 ns for fast-mode operation, f_SCL

400 kHz) and bus capacitance, C_b:

t_r

R_p(max)

0.8473´C_b

(2)

The maximum bus capacitance for an I²C bus must not exceed 400 pF for fast-mode operation. The bus

capacitance can be approximated by adding the capacitance of the TCA9545A, C_io(OFF), the capacitance of

wires/connections/traces, and the capacitance of each individual slave on a given channel. If multiple channels

will be activated simultaneously, each of the slaves on all channels will contribute to total bus capacitance.

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Typical Application (continued)

9.2.3 TCA9545A Application Curves

Standard-mode

Fast-mode

25ºC (Room Temperature)

85ºC

-40ºC

0.5

1.5

2.5 3

V_CC(V)

3.5

4.5

5.5

100 150 200 250 300 350 400 450

C_b(pF)

D007

D008

Space

space_space

Space

space_space

Standard-mode

(f_SCL= 100 kHz, t_r= 1 µs)

Fast-mode

(f_SCL= 400 kHz, t_r= 300 ns)

Figure 17. Pass-Gate Voltage (V_pass) vs Supply Voltage

(V_CC) at Three Temperature Points

Figure 18. Maximum Pull-Up resistance (R_p(max)) vs Bus

Capacitance (C_b)

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

V_DPUX> 2V

V_DPUX<= 2

0.5

1.5

2.5 3

V_DPUX(V)

3.5

4.5

5.5

D009

V_OL= 0.2*V_DPUX, I_OL= 2 mA when V_DPUX≤ 2 V

V_OL= 0.4 V, I_OL= 3 mA when V_DPUX> 2 V

Figure 19. Minimum Pull-Up Resistance (R_p(min)) vs Pull-Up Reference Voltage (V_DPUX

)

TCA9545A

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10 Power Supply Recommendations

The operating power-supply voltage range of the TCA9545A is 1.65 V to 5.5 V applied at the VCC pin. When the

TCA9545A is powered on for the first time or anytime the device needs to be reset by cycling the power supply,

the power-on reset requirements must be followed to ensure the I²C bus logic is initialized properly.

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9545A can be reset to its default conditions by using the power-on

reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This

reset also happens when the device is powered on for the first time in an application.

A power-on reset is shown in Figure 20.

Ramp-Down

Ramp-Up

CC_TRR

drops below V_PORF– 50 mV

Time

Time to Re-Ramp

CC_FT

CC_RT

Figure 20. V_CCis Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 3 specifies the performance of the power-on reset feature for TCA9545A for both types of power-on reset.

Table 3. Recommended Supply Sequencing And Ramp Rates⁽¹⁾

PARAMETER

MIN TYP

MAX UNIT

V_{CC_FT}

V_{CC_RT}

Fall time

See Figure 20

100

Rise time

0.1

Time to re-ramp (when V_CCdrops below V_PORF(min)– 50 mV or

when V_CCdrops to GND)

V_{CC_TRR}

V_{CC_GH}

V_{CC_GW}

See Figure 20

See Figure 21

μs

Level that V_CCcan glitch down to, but not cause a functional

disruption when V_{CC_GW}= 1 μs

1.2

Glitch width that will not cause a functional disruption when

V_{CC_GH}= 0.5 × V_CC

μs

V_PORF

V_PORR

Voltage trip point of POR on falling V_CC

Voltage trip point of POR on rising V_CC

See Figure 22

0.8

1.25

1.5

1.05

(1) All supply sequencing and ramp rate values are measured at T_A= 25°C

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Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width

(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and

device impedance are factors that affect power-on reset performance. Figure 21 and Table 3 provide more

information on how to measure these specifications.

CC_GH

Time

CC_GW

Figure 21. Glitch Width and Glitch Height

V_PORis critical to the power-on reset. V_PORis the voltage level at which the reset condition is released and all the

registers and the I²C/SMBus state machine are initialized to their default states. The value of V_PORdiffers based

on the V_CCbeing lowered to or from 0. Figure 22 and Table 3 provide more details on this specification.

PORR

PORF

Time

POR

Time

Figure 22. V_POR

TCA9545A

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11 Layout

11.1 Layout Guidelines

For PCB layout of the TCA9545A, common PCB layout practices should be followed but additional concerns

related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I²C

signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that

are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon

pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the

VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and

a smaller capacitor to filter out high-frequency ripple.

In an application where voltage translation is not required, all V_DPUXvoltages and V_CCcould be at the same

potential and a single copper plane could connect all of pull-up resistors to the appropriate reference voltage. In

an application where voltage translation is required, V_DPUM, V_DPU0, V_DPU1, V_DPU2, and V_DPU3may all be on the

same layer of the board with split planes to isolate different voltage potentials.

To reduce the total I²C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a

short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper

weight).

11.2 Layout Example

LEGEND

Polygonal

Copper Pour

Partial Power Plane

To I2C Master

VIA to Power Plane

VIA to GND Plane (Inner Layer)

By-pass/De-coupling

capacitors

V_DPUM

GND

V_CC

V_DPU0

VCC

SDA

SCL

INT

V_DPU3

RESET

INT0

SD0

SC0

INT1

SD1

SC1

SC3

SD3

INT3

SC2

SD2

INT2

GND

V_DPU2

GND

V_DPU1

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12 器件和文档支持

12.1 接收文档更新通知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品

信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.2 支持资源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight

from the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do

not necessarily reflect TI's views; see TI's Terms of Use.

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 机械、封装和可订购信息

The following packaging information and addendum reflect the most current data available for the designated

devices. This data is subject to change without notice and revision of this document.

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCA9545APWR

ACTIVE

TSSOP

2000 RoHS & Green

NIPDAU

Level-1-260C-UNLIM

-40 to 85

PW545A

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCA9545APWR

TSSOP

2000

330.0

16.4

6.95

7.0

1.4

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

TSSOP PW 20

SPQ

Length (mm) Width (mm) Height (mm)

356.0 356.0 35.0

TCA9545APWR

2000

Pack Materials-Page 2

PACKAGE OUTLINE

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SEATING

PLANE

6.6

6.2

TYP

0.1 C

PIN 1 INDEX AREA

18X 0.65

5.85

6.6

6.4

NOTE 3

0.30

20X

4.5

4.3

NOTE 4

0.19

1.2 MAX

0.1

C A B

(0.15) TYP

SEE DETAIL A

0.25

GAGE PLANE

0.15

0.05

0.75

0.50

0 -8

DETAIL A

TYPICAL

4220206/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

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EXAMPLE BOARD LAYOUT

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

SYMM

20X (1.5)

(R0.05) TYP

20X (0.45)

SYMM

18X (0.65)

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

METAL UNDER

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

EXPOSED METAL

0.05 MAX

ALL AROUND

0.05 MIN

ALL AROUND

NON-SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

15.000

(PREFERRED)

SOLDER MASK DETAILS

4220206/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

EXAMPLE STENCIL DESIGN

PW0020A

TSSOP - 1.2 mm max height

SMALL OUTLINE PACKAGE

20X (1.5)

SYMM

(R0.05) TYP

20X (0.45)

SYMM

18X (0.65)

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

4220206/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

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