TCA9617B [TI]

具有断电高阻抗的 2 位电平转换 1MHz I2C/SMBus 缓冲器/中继器;


型号：	TCA9617B
厂家：	TEXAS INSTRUMENTS
描述：	具有断电高阻抗的 2 位电平转换 1MHz I2C/SMBus 缓冲器/中继器中继器
文件：	总23页 (文件大小：784K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

TCA9617B 电平转换 FM+ I²C 总线中继器

1 特性

2 应用

•

双通道双向 I²C 缓冲器

•

服务器

•

支持标准模式、快速模式 (400kHz) 和快速模式+

(1MHz) I²C 操作

路由器（电信交换设备）

工业设备

具有多个 I²C 从器件和/或印刷电路板 (PCB) 走线

较长的产品

•

在 A 侧上，运行电源电压范围为 0.8V 至 5.5V

在 B 侧上，运行电源电压范围为 2.2V 至 5.5V

从 0.8V 至 5.5V 和 2.2V 至 5.5V 的电压电平转换

针对 TCA9517 的封装和功能替代产品

高电平有效中继器启用输入

漏极开路 I²C I/O

5.5V 电压容错 I²C 和启用输入支持

3 说明

TCA9617B 是一款专门用于 I²C 总线和 SMBus 系统

的 BiCMOS 双路双向缓冲器。此器件可在混合应用中

提供低电压（低至 0.8V）和较高电压（2.2V 至

5.5V）间的双向电压水平转换（上行转换模式和下行

转换模式）。电平转换期间，这个器件在不损失系统性

能的情况下可扩展 I²C 和相似的总线系统。

无闭锁操作

断电高阻抗 I²C 总线引脚

器件上支持时钟扩展和多主机仲裁

闩锁性能超出 JESD 78 II 类规范要求的 100mA

TCA9617B 缓冲 I²C 总线上的串行数据 (SDA) 和串行

时钟 (SCL) 信号，从而将 550pF 的两条总线连接至一

个 I²C 应用。这款器件也可用于将总线隔离为电压和电

容两部分。

静电放电 (ESD) 保护性能超过 JESD 22 规范的要

求

–

4000V 人体放电模式 (A114-A)

1500V 充电器件模型 (C101)

器件信息⁽¹⁾

器件型号

TCA9617B

封装

VSSOP (8)

封装尺寸（标称值）

3.00mm × 3.00mm

(1) 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品

附录。

简化原理图

VCCA

SCLA

SDAA

VCCB

I²C slave devices

I²C or SMBus

Master

(e.g. Processor)

SCLB

SDAB

TCA9617B

GND

本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确

性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SCPS259

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

8.3 Feature Description................................................. 10

8.4 Device Functional Modes........................................ 11

Application and Implementation ........................ 12

9.1 Application Information............................................ 12

9.2 Typical Application .................................................. 12

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 3

6.1 Absolute Maximum Ratings ..................................... 3

6.2 ESD Ratings.............................................................. 4

6.3 Recommended Operating Conditions....................... 4

6.4 Thermal Information.................................................. 4

6.5 Electrical Characteristics........................................... 5

6.6 Timing Requirements................................................ 6

6.7 Typical Characteristics.............................................. 6

Parameter Measurement Information .................. 7

Detailed Description .............................................. 9

8.1 Overview ................................................................... 9

8.2 Functional Block Diagram ....................................... 10

10 Power Supply Recommendations ..................... 15

11 Layout................................................................... 16

11.1 Layout Guidelines ................................................. 16

11.2 Layout Example .................................................... 16

12 器件和文档支持 ..................................................... 17

12.1 接收文档更新通知 ................................................. 17

12.2 社区资源................................................................ 17

12.3 商标....................................................................... 17

12.4 静电放电警告......................................................... 17

12.5 术语表 ................................................................... 17

13 机械、封装和可订购信息....................................... 17

4 修订历史记录

Changes from Revision A (December 2014) to Revision B

Page

•

Changed the appearance of the DGK pin out image ............................................................................................................ 3

Changed V_CCA< V_CCBTo: V_CCA≤ V_CCBin the Design Requirements list ............................................................................. 12

Changes from Original (December 2014) to Revision A

Page

•

初始完整版。 .......................................................................................................................................................................... 1

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

5 Pin Configuration and Functions

DGK Package

8-Pin VSSOP

Top View

VCCA

SCLA

SDAA

GND

VCCB

SCLB

SDAB

Not to scale

Pin Functions

DESCRIPTION

NAME

VCCA

NO.

A-side supply voltage (0.8 V to 5.5 V)

SCLA

SDAA

GND

I²C SCL line, A side. Connect to V_CCAthrough a pull-up resistor.

I²C SDA line, A side. Connect to V_CCAthrough a pull-up resistor.

Supply ground

Active-high repeater enable input

SDAB

SCLB

VCCB

I²C SDA line, B side. Connect to V_CCBthrough a pull-up resistor.

I²C SCL line, B side. Connect to V_CCBthrough a pull-up resistor.

B-side and device supply voltage (2.2 V to 5.5 V)

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

over operating free-air temperature range (unless otherwise noted)

MIN

–0.5

MAX

UNIT

V_CCB

V_CCA

V_I

Supply voltage range

Enable input voltage range⁽²⁾

I²C bus voltage range⁽²⁾

Input clamp current

V_I/O

I_IK

V_I< 0

–50

±50

±100

150

I_OK

Output clamp current

V_O< 0

Continuous output current

Continuous current through V_CCor GND

Storage temperature range

°C

I_O

T_stg

–65

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

±4000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-

C101⁽²⁾

±1500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with

less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

0.8

MAX

V_CCB

5.5

UNIT

V_CCA

V_CCB

I_OLA

I_OLB

T_A

Supply voltage, A-side bus

Supply voltage, B-side bus

Low-level output current

Operating free-air temperature

2.2

°C

0.1

–40

6.4 Thermal Information

TCA9617B

DGK

THERMAL METRIC⁽¹⁾

UNIT

8 PINS

171.8

61.2

R_θJA

R_θJC(top)

R_θJB

ψ_JT

Junction-to-ambient thermal resistance

°C/W

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

93.6

Junction-to-top characterization parameter

Junction-to-board characterization parameter

7.9

ψ_JB

91.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

6.5 Electrical Characteristics

V_CCB= 2.2 V to 5.5 V, GND = 0 V, T_A= –40°C to 85°C (unless otherwise noted)

PARAMETER

TEST CONDITIONS

V_CCB

MIN

TYP

MAX

UNIT

V_IK

Input clamp voltage

I_I= –18 mA

2.2 V to 5.5 V

–1.2

I_OL= 100 µA or 30 mA,

V_ILA= 0 V

SDAB, SCLB

0.48

0.53

0.1

0.58

V_OL

Low-level output voltage

2.2 V to 5.5 V

SDAA, SCLA

I_OL= 30 mA

0.23

5.5

0.7 × V_CCA

0.7 × V_CCB

V_IH

High-level input voltage SDAB, SCLB

5.5

0.3 ×

V_CCA

SDAA, SCLA

V_IL

Low-level input voltage

SDAB, SCLB

2.2 V to 5.5 V

0.4

0.3 ×

V_CCB

Both channels low,

SDAA = SCLA = GND and

I_OLB=100 µA, or

I_CCA

Quiescent supply current for V_CCA

µA

SDAA = SCLA = open and

SDAB = SCLB = GND

Both Channels high,

SDAA = SCLA = V_CCA

B-side pulled up to V_CCBwith

pull-up resistors

+4.5

+5.7

I_CCB

Quiescent supply current

5.5 V

Both channels low,

SDAA = SCLA = GND,

I_OLB= 100 µA

+8.1

V_I= V_CCB

–1

–10

–1

+10

V_I= 0.2 V, EN = 0

V_I= V_CCB– 0.2 V

V_I= 5.5 V,V_CCA= 0 V

V_I= V_CCA

2.2 V to 5.5 V

0 V

SDAB, SCLB

–10

–1

+10

I_I

Input leakage current

μA

V_I= 0.2 V, EN = 0

V_I= V_CCA– 0.2 V

V_I= 5.5 V, V_CCA= 0 V

V_I= V_CCB

2.2 V to 5.5 V

0 V

–10

–1

+10

SDAA, SCLA

–10

–1

+10

V_I= 0.2 V

–25

C_I

Input capacitance

V_I= 3 V or 0 V

3.3 V

0 V

SCLA, SDAA

V_I= 3 V or 0 V

C_I/O

Input/output capacitance

3.3 V

0 V

SCLB, SDAB

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

6.6 Timing Requirements

V_CCA= 0.8 V to 5.5 V, V_CCB= 2.2 V to 5.5 V, GND = 0 V, T_A= –40°C to 85°C (unless otherwise noted)^(1)(2)(3)

FROM

(INPUT)

(OUTPUT)

PARAMETER

TEST CONDITIONS

MIN

TYP MAX UNIT

SDAB, SCLB

SDAA, SCLA

t_PLH

Propagation delay

_CCB≤ 3 V

88 137 ns

94 250

SDAA, SCLA

SDAB, SCLB

V_CCB> 3 V

SDAB, SCLB

SDAA, SCLA

SDAB, SCLB

93 144

t_PHL

t_TLH

t_THL

Propagation delay

90 140

B side

Transition

time

(4)

30%

70%

30%

A side

B side

A side

5.40

1.40

100

6.41 13.8

Transition

time

70%

4.71 11.3

t_su,en

Setup time, EN high before Start condition⁽⁵⁾

(1) Times are specified with loads of 240 Ω ±1% and 400 pF ±10% on B-side and 240 Ω ±1% and 200 pF ±10% on A-side. Different load

resistance and capacitance alter the rise time, thereby changing the propagation delay and transition times.

(2) Times are specified with A-side signals pulled up to V_CCAand B-side signals pulled up to V_CCB

(3) Typical values were measured with V_CCA= 0.9 V and V_CCB= 2.5 V at T_A= 25°C, unless otherwise noted.

(4) T_TLHis determined by the pull-up resistance and load capacitance.

(5) EN should change state only when the global bus and the repeater port are in an idle state.

6.7 Typical Characteristics

T_A= 85 C

T_A= 25 C

T_A= -40 C

T_A= 25 C

T_A= -40 C

T_A= 85 C

Port A I_OL(mA)

Port B I_OL(mA)

V_CCA= 0.9 V

V_CCB= 2.2 V

V_CCA= 0.9 V

V_CCB= 2.2 V

图 1. Port A V_OLvs I_OL

图 2. Port B V_OLvs I_OL

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

7 Parameter Measurement Information

V_CCA

V_CCB

R_PUA

R_PUB

VCCA VCCB

DUT

V_IN

V_OUT

Open Drain

Driver

C_LA

C_LB

图 3. Test Circuit for Open-Drain Output from A to B

V_CCA

V_CCB

R_PUA

R_PUB

VCCA VCCB

DUT

V_OUT

V_IN

Open Drain

Driver

1 M

C_LA

C_LB

A. V_CCA= 0.9 V

B. V_CCB= 2.5 V

C. R_PUA= R_PUB= 240 Ω on the A-side and the B-side

D. C_LA= 200 pF on A-side and C_LB= 400 pF on B-side (includes probe and jig capacitance)

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z_O= 50 Ω, slew rate

≥ 1 V/ns

F. The outputs are measured one at a time, with one transition per measurement.

图 4. Test Circuit for Open-Drain Output from B to A

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

Parameter Measurement Information (接下页)

t_PHL,AB

t_THL,B

0.7 * V_CC

0.3 * V_CC

V_OLB

V_ILA

A-side

B-side

t_PLH,AB

t_TLH,B

0.7 * V_CC

0.3 * V_CC

V_OLB

V_ILA

图 5. Propagation Delay And Transition Times (A to B)

t_PHL,BAt_THL,A

0.7 * V_CC

0.3 * V_CC

A-side

B-side

t_PLH,BA

t_TLH,A

0.7 * V_CC

0.3 * V_CC

0.4 V

图 6. Propagation Delay And Transition Times (B to A)

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

8 Detailed Description

8.1 Overview

The TCA9617B is a BiCMOS dual bidirectional buffer intended for I²C bus and SMBus systems. As with the

standard I²C system, pull-up resistors are required to provide the logic high levels on the buffered bus. The

TCA9617B has standard open-drain configuration of the I²C bus. The size of these pull-up resistors depends on

the system, but each side of the repeater must have a pull-up resistor. The device is designed to work with

Standard mode, Fast mode and Fast Mode+ I²C devices. The SCL and SDA lines shall be at high-impedance

when either one of the supplies is powered off.

The TCA9617B B-side drivers operate from 2.2 V to 5.5 V. The output low level for this internal buffer is

approximately 0.5 V, but the input voltage must be below V_ILwhen the output is externally driven low. The

higher-voltage low signal is called a buffered low. When the B-side I/O is driven low internally, the low is not

recognized as a low by the input. This feature prevents a lockup condition from occurring when the input low

condition is released. This type of design on the B side prevents it from being used in series with another

TCA9617B B-side or other buffers that incorporate a static or dynamic offset voltage. This is because these

devices do not recognize buffered low signals as a valid low and do not propagate it as a buffered low again.

The TCA9617B A-side drivers operate from 0.8 V to 5.5 V and do not have the buffered low feature (or the static

offset voltage). This means that a low signal on the B side translates to a nearly 0-V low on the A side, which

accommodates smaller voltage swings of low-voltage logic. The output pull-down on the A side drives a hard low,

and the input level is set to 0.3 V_CCAto accommodate the need for a lower low level in systems where the low-

voltage-side supply voltage is as low as 0.8 V.

The A side of two or more TCA9617Bs can be connected together to allow a star topology, with the A side on the

common bus. Also, the A side can be connected directly to any other buffer with static or dynamic offset voltage.

Multiple TCA9617Bs can be connected in series, A side to B side, with no buildup in offset voltage with only

time-of-flight delays to consider.

The TCA9617B includes a power-up circuit that keeps the output drivers turned off until V_CCBis above 2.0 V and

V_CCAis above 0.7 V. V_CCAis only used to provide references for the A-side input comparators and the power-

good-detect circuit. The TCA9617B internal circuitry and all I/Os are powered by the V_CCBpin.

After power up and with the EN high, the A side falling below 0.7 V_CCAturns on the corresponding B-side driver

(either SDA or SCL) and drives the B-side down momentarily to 0 V before settling to approximately 0.5 V. When

the A-side rises above 0.3 V_CCA, the B-side pull-down driver is turned off and the external pull-up resistor pulls

the pin high. If the B side falls first and goes below 0.7 V_CCB, the A-side driver is turned on and drives the A-side

to 0 V. When the B-side rises above 0.45 V, the A-side pull-down driver is turned off and the external pull-up

resistor pulls the pin high.

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

8.2 Functional Block Diagram

CCA

CCB

SDAA

SDAB

SCLA

SCLB

CCB

Pullup

Resistor

GND

8.3 Feature Description

8.3.1 Bidirectional Level Translation

The TCA9617B can provide bidirectional voltage level translation (up-translation and down-translation) between

low voltages (down to 0.8 V) and higher voltages (2.2 V to 5.5 V) in mixed-mode applications.

8.3.2 Low to High Transition Characteristics

图 8 depicts the offset voltage on the B side of the device. As shown in 图 8 the slave releases and the B-side

rises, and it will rise to 0.5 V and stay there until the A-side rises above 0.3 V_CCA. This effect can cause the low

level signal to have a "pedestal." Once the voltage on the A-side crosses 0.3 V_CCA, the B-side will continue to

rise to V_CCB

Due to nature of the B-side pedestal and the static offset voltage, there will be a slight overshoot as the B-side

rises from being externally driven low to the 0.5 V offset. The TCA9617B is designed to control this behavior

provided the system is designed with rise times greater than 20 ns. Therefore, care should be taken to limit the

pull-up strength when devices with rise time accelerators are present on the B side. Excessive overshoot on the

B-side pedestal may cause devices with rise time accelerators to trip prematurely if the overshoot is more than

accelerator thresholds. Since the A-side does not have a static offset low voltage, no pedestal is seen on the A-

side as shown in 图 7.

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

Feature Description (接下页)

8.3.3 High to Low Transition Characteristics

When the A side of the bus is driven to 0.7 V_CCA, the B side driver will turn on. This will drive the B-side to 0 V for

a short period (see 图 8) and then the B-side will rise to the static offset voltage of 0.5 V (V_OLof TCA9617B).

This effect, called an inverted pedestal, allows the B-side to drive to logic low much faster than driving to the

static offset. Driving to the static offset voltage requires that the fall time be slowed to prevent ringing.

9^thClock Pulse – Acknowledge

SCL

SDA

图 7. Bus A (0.8 V to 5.5 V Bus) Waveform

9 Clock Pulse – Acknowledge

Inverted Pedestal

SCL

Pedestal

SDA

GND

V_OLof TCA9617B

V_OLof Slave

图 8. Bus B (2.2 V to 5.5 V Bus) Waveform

8.4 Device Functional Modes

The TCA9617B has an active-high enable (EN) input with an internal pull-up to V_CCB, which allows the user to

select when the repeater is active. This can be used to isolate a badly behaved slave on power-up reset. It

should never change state during an I²C operation, because disabling during a bus operation may hang the bus,

and enabling part way through the bus cycles could confuse the I²C parts being enabled. The EN input should

change state only when the global bus and repeater port are in the idle state to prevent system failures.

表 1. Function Table

INPUT

FUNCTION

Outputs disabled

SDAA = SDAB

SCLA = SCLB

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

9 Application and Implementation

9.1 Application Information

A typical application is shown in 图 9. In this example, the system master is running on a 0.9-V I²C bus, and the

slave is connected to a 2.5-V bus. Both buses are running at 400 kHz. Decoupling capacitors are required but

are not shown in 图 14 for simplicity.

The TCA9617B is 5-V tolerant so no additional circuits are required to translate between 0.8-V to 5.5-V bus

voltages and 2.7-V to 5.5-V bus voltages.

When the A side of the TCA9617B is pulled low by a driver on the I²C bus, a comparator detects the falling edge

when it goes below 0.7 V_CCAand cause the internal driver on the B side to turn on. The B-side will first pull down

to 0 V and then settle to 0.5 V. When the B side of the TCA9617B falls below 0.45 V, the TCA9617B will detect

the falling edge, turn on the internal driver on the A side and pull the A-side pin down to ground.

On the B-side bus of the TCA9617B, the clock and data lines will have a positive offset from ground equal to the

V_OLof the TCA9617B. After the eighth clock pulse, the data line is pulled to the V_OLof the slave device, which is

close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the

driver of the TCA9617B for a short delay (approximately 0.5 V), while the A-side bus rises above 0.3 V_CCAand

then continues high.

Although the TCA9617 has a single application, the device can exist in multiple configurations. 图 9 shows the

standard configuration for the TCA9617. Multiple TCA9617s can be connected either in star configuration (图 12)

or in series configuration (图 13). The design requirements , detailed design procedure, and application curves in

Standard Application are valid for all three configurations.

9.2 Typical Application

9.2.1 Standard Application

0.9 V

2.5 V

240

820

VCCA

VCCB

SDAA

SCLA

SDAB

SCLB

Master

1 MHz

TCA9617B

Slave

1 MHz

BUS A

BUS B

图 9. Bidirectional Voltage Level Translator

9.2.1.1 Design Requirements

For the level-translating application, the following should be true:

•

V_CCA= 0.8 V to 5.5 V

V_CCB= 2.2 V to 5.5 V

V_CCA≤ V_CCB

I_OL> I_O

TCA9617B

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ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

Typical Application (接下页)

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Pullup Resistor Sizing

For the TCA9617B to function correctly, all devices on the B-side must be able to pull the B-side below the

voltage input low contention level (0.45 V). This means that the V_OLof any device on the B-side must be below

0.4 V to ensure proper operation.

The V_OLof a device can be adjusted by changing the I_OLthrough the device which is set by the pull-up resistor

value. The pull-up resistor on the B-side must be carefully selected to ensure that logic levels will be transferred

correctly to the A-side.

The B-side pull-up resistor sizing must also ensure that the rise time is greater than 20 ns. Shorter rise times will

increase the pedestal overshoot shown in point 2 of 图 10.

9.2.1.3 Application Curves

图 10. B-side Pedestal

图 11. B-side Inverted Pedestal

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

Typical Application (接下页)

9.2.2 Star Application

Multiple TCA9617B A sides can be connected in a star configuration, allowing all nodes to communicate with

each other.

V_CCA

V_CCB

240

820

VCCA VCCB

SDAA SDAB

SCLA SCLB

TCA9617B

Slave

1 MHz

Master

1 MHz

820

VCCA VCCB

SDAA

SCLA

SDAB

SCLB

TCA9617B

Slave

1 MHz

BUS B

820

VCCA VCCB

SDAA

SCLA

SDAB

SCLB

TCA9617B

Slave

1 MHz

图 12. Typical Star Application

9.2.2.1 Design Requirements

Refer to Design Requirements.

9.2.2.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

9.2.2.3 Application Curves

Refer to Application Curves.

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

Typical Application (接下页)

9.2.3 Series Application

Multiple TCA9617Bs can be connected in series as long as the A side is connected to the B side. I²C bus slave

devices can be connected to any of the bus segments. The number of devices that can be connected in series is

limited by repeater delay/time-of-flight considerations on the maximum bus speed requirements.

V_CCA

V_CCB

240

820

VCCA

SDAA

SCLA

VCCB

SDAB

SCLB

VCCA

SDAA

SCLA

VCCB

SDAB

SCLB

VCCA

SDAA

SCLA

VCCB

SDAB

SCLB

SDA

SCL

Master

1 MHz

TCA9617B

Slave

1 MHz

图 13. Typical Series Application

9.2.3.1 Design Requirements

Refer to Design Requirements.

9.2.3.2 Detailed Design Procedure

Refer to Detailed Design Procedure.

9.2.3.3 Application Curves

Refer to Application Curves.

10 Power Supply Recommendations

For VCCA, an 0.8-V to 5.5-V power supply is required. For VCCB, a 2.2-V to 5.5-V power supply is required.

Standard decoupling capacitors are recommended. These capacitors typically range from 0.1 µF to 1 µF, but the

ideal capacitance depends on the amount of noise from the power supply.

TCA9617B

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

www.ti.com.cn

11 Layout

11.1 Layout Guidelines

The recommended decoupling capacitors should be placed as close to the VCCA and VCCB pins of the

TCA9617B as possible.

11.2 Layout Example

Polygonal Copper Pour

VIA to GND Plane

Decoupling capacitors

VCCA

SCLA

VCCB

SCLB

SDAB

TCA9617B

SDAA

GND

图 14. Layout Schematic

TCA9617B

www.ti.com.cn

ZHCSD69B –DECEMBER 2014–REVISED DECEMBER 2018

12 器件和文档支持

12.1 接收文档更新通知

要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查阅已修订文档中包含的修订历史记录。

12.2 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.3 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.4 静电放电警告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损

伤。

12.5 术语表

SLYZ022 — TI 术语表。

这份术语表列出并解释术语、缩写和定义。

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且

不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。

PACKAGE OPTION ADDENDUM

www.ti.com

29-Sep-2022

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCA9617BDGKR

ACTIVE

VSSOP

DGK

2500 RoHS & Green

NIPDAUAG | SN

Level-1-260C-UNLIM

-40 to 85

ZBOK

Samples

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCA9617BDGKR

VSSOP

DGK

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Mar-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

VSSOP DGK

SPQ

Length (mm) Width (mm) Height (mm)

364.0 364.0 27.0

TCA9617BDGKR

2500

Pack Materials-Page 2

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

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保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

TCA9617B [TI]

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TCA9617BDGKR

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