TCAN1043HGDQ1 [TI]
具有 CAN FD 和唤醒输入的故障保护 CAN 收发器 | D | 14 | -55 to 125;
| 型号： | TCAN1043HGDQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 CAN FD 和唤醒输入的故障保护 CAN 收发器 | D | 14 | -55 to 125 |
| 文件： | 总52页 (文件大小：2117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN1043-Q1, TCAN1043H-Q1
TCAN1043HG-Q1, TCAN1043G-Q1
ZHCSH19E –NOVEMBER 2017 –REVISED MARCH 2021
TCAN1043xx-Q1 具有CAN FD 和唤醒功能的低功耗故障保护CAN 收发器
– 信息娱乐系统
– 仪表组
– 车身电子装置与照明
1 特性
• AEC Q100 标准：符合汽车应用要求
– 温度等级1：-55°C 至125°C，TA
– 器件HBM 分级等级：±16kV
– 器件CDM 分级等级：±1500V
• 提供功能安全
3 说明
TCAN1043xx-Q1 满足 ISO 11898–2 (2016) 高速控制
器局域网(CAN) 规范的物理层要求，提供CAN 总线和
CAN 协议控制器之间的接口。这些器件支持传统 CAN
和 CAN FD 协议，具有最高 2Mbps 的数据速率。器件
编号以“G”结尾的器件专为数据速率高达 5Mbps 的
CAN FD 应用而设计。TCAN1043xx-Q1 可以（通过
INH 输出引脚）选择性地启用节点上可能存在的各种电
源，从而在整个系统级别减少电池电流消耗。这使得在
超低电流睡眠状态中，功率传送到除 TCAN1043xx-Q1
以外的所有系统组件，而 TCAN1043xx-Q1 则仍然处
于低功耗状态，并对CAN 总线进行监控。
– 可帮助进行功能安全系统设计的文档
• 符合ISO 11898-2 (2016) 的要求
• 所有器件均支持经典CAN 和2Mbps CAN FD（灵
活数据速率），而“G”选项支持5Mbps
– 具有较短的对称传播延迟时间和快速循环次数，
可增加时序裕量
– 在有负载CAN 网络中实现更快的数据速率
• VIO 电平转换支持2.8V 至5.5V 的电压范围
• 工作模式
– 正常模式
– 具有INH 输出以及本地和远程唤醒请求功能的
待机模式
– 具有INH 输出以及本地和远程唤醒请求的低功
耗睡眠模式
器件信息
封装(1)
SOIC (14)
VSON (14)
封装尺寸（标称值）
8.95mm x 3.91mm
4.50mm x 3.00mm
器件型号
TCAN1043xx-Q1
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 未供电时具有理想无源行为
– 总线和逻辑终端为高阻抗（运行总线或应用上无
负载）
VCC
3
VIO
5
VSUP
10
NC
11
VCC
– 支持热插拔：在总线和RXD 输出上可实现上电/
断电无干扰运行
• 符合或超出EMC 标准要求
VIO
VCC
TRANSMIT
DOMINANT
TIME OUT
1
TXD
VSUP
13
12
7
9
INH
VSUP
– 符合IEC 62228-3 –2007 标准
– 符合SAE J2962-2 标准
• 保护特性
WAKE
WAKE
LDO
8
nFAULT
14
CONTROL and MODE
LOGIC
nSTB
EN
– 总线终端的IEC ESD 保护：±8kV
– 总线故障保护：±58V（非H 型号）和±70V（H
型号）
6
Sleep Receiver
WUP
Detect
UNDER
VOLTAGE
OVER
TEMP
– 电源终端欠压保护
– 驱动器显性超时(TXD DTO)：数据速率低至
9.2kbps
Normal Receiver
RECEIVE
DOMINANT
TIME OUT
4
MUX
RXD
2
GND
– 热关断保护(TSD)
Copyright © 2016, Texas Instruments Incorporated
• 接收器共模输入电压：±30V
• 典型循环延迟：110ns
功能模块图
• 结温范围为–55°C 至150°C
• 采用SOIC (14) 封装和无引线VSON (14) 封装
(4.5mm x 3.0mm)，具有改进的自动光学检查(AOI)
功能
2 应用
• 12V 或24V 系统应用
• 汽车和运输
– 高级驾驶辅助系统(ADAS)
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEV0
TCAN1043-Q1, TCAN1043H-Q1
TCAN1043HG-Q1, TCAN1043G-Q1
ZHCSH19E –NOVEMBER 2017 –REVISED MARCH 2021
www.ti.com.cn
Table of Contents
9.1 Overview...................................................................18
9.2 Functional Block Diagram.........................................18
9.3 Feature Description...................................................19
9.4 Device Functional Modes..........................................24
10 Application Information Disclaimer...........................34
10.1 Application Information........................................... 34
10.2 Typical Application.................................................. 34
11 Power Supply Recommendations..............................37
12 Layout...........................................................................38
12.1 Layout..................................................................... 38
12.2 Layout Example...................................................... 39
13 Device and Documentation Support..........................40
13.1 Related Links.......................................................... 40
13.2 Receiving Notification of Documentation Updates..40
13.3 Community Resources............................................40
13.4 Trademarks.............................................................40
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 ESD Ratings IEC Specification...................................6
7.4 Recommended Operating Conditions.........................6
7.5 Thermal Information....................................................6
7.6 Dissipation Ratings..................................................... 7
7.7 Electrical Characteristics.............................................7
7.8 Switching Characteristics..........................................10
7.9 Typical Characteristics..............................................12
8 Parameter Measurement Information..........................13
9 Detailed Description......................................................18
Information.................................................................... 40
4 Revision History
Changes from Revision D (July 2019) to Revision E (January 2021)
Page
• 向特性列表添加了“功能安全”........................................................................................................................ 1
Changes from Revision C (October 2018) to Revision D (July 2019)
Page
• Changed the second sentence in the CAN Bus Dominant Fault section..........................................................21
• Changed the D0014A mechanical pages ........................................................................................................ 40
Changes from Revision B (May 2018) to Revision C (October 2018)
Page
• Updated ICC dominant with bus fault ..................................................................................................................7
• Added footnote for IIH and IIL ............................................................................................................................. 7
• Changed the Under-Voltage callout in 图9-4 .................................................................................................. 24
• Added sentence: "This minimizes the current flowing into the WAKE pin..." to the last paragraph in Local
Wake Up (LWU) via WAKE Input Terminal ......................................................................................................29
Changes from Revision A (December 2017) to Revision B (May 2018)
Page
• Updated note 1 to: AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/
JEDEC JS-01 specification.................................................................................................................................5
• Added Note 2 To ESD Specification Table..........................................................................................................6
• Updated IEC 61000-4-2 Unpowered Contact Dicharge to ±15kV ..................................................................... 6
• Changed Max tWK_FILTER to 1.8µs.....................................................................................................................10
Changes from Revision * (November 2017) to Revision A (December 2017)
Page
• 将状态从预告信息更改为生产数据....................................................................................................................1
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5 Description (continued)
When a wake-up pattern is detected on the bus or when a local wake-up is requested via the WAKE input, the
TCAN1043xx-Q1 will initiate node start-up by driving INH high. The TCAN1043xx-Q1 includes internal logic level
translation via the VIO terminal to allow for interfacing directly to 3.3 V or 5 V controllers. The device includes
many protection and diagnostic features including CAN bus line short-circuit detection and battery connection
detection. The TCAN1043xx-Q1 meets the ESD and EMC requirements of IEC 62228-3 and J2962-2 without the
need for additional protection components.
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Device Comparison Table
DEVICE NUMBER
TCAN1043-Q1
BUS FAULT PROTECTION
MAXIMUM DATA RATE
±58 V
±70 V
±58 V
±70 V
2 Mbps
2 Mbps
5 Mbps
5 Mbps
TCAN1043H-Q1
TCAN1043G-Q1
TCAN1043HG-Q1
6 Pin Configuration and Functions
TXD
1
2
3
4
5
6
7
14
13
12
11
10
9
nSTB
CANH
CANL
NC
TXD
1
2
3
4
5
6
7
14
13
12
11
10
9
nSTB
CANH
CANL
NC
GND
GND
V
CC
V
ꢀ
ꢀ
CC
Thermal
Pad
RXD
RXD
VSUP
WAKE
nFAULT
V
IO
V
V
ꢀ
EN
IO
SUP
INH
8
EN
WAKE
INH
8
nFAULT
Not to scale
图6-2. DMT Package, 14 Pin (VSON), Top View
图6-1. D Package, 14 Pin (SOIC), Top View
表6-1. Pin Functions
PINS
TYPE
DESCRIPTION
NAME
TXD
NO
1
Digital Input
GND
CAN transmit data input (low for dominant and high for recessive bus states)
GND
VCC
2
Ground connection
3
Supply
5-V CAN bus supply voltage
RXD
VIO
4
Digital Output
Supply
CAN receive data output (low for dominant and high for recessive bus states), tri-state
I/O supply voltage
5
EN
6
Digital Input
Enable input for mode control, integrated pull down
INH
7
High Voltage Output Can be used to control system voltage regulators
nFAULT
WAKE
VSUP
NC
8
Digital Output
High Voltage Input
Supply
Fault output, inverted logic
9
Wake input terminal, high voltage input
Reverse-blocked battery supply input
No connect (not internally connected)
Low-level CAN bus input/output line
High-level CAN bus input/output line
Standby input for mode control, integrated pull down
10
11
12
13
14
—
CANL
CANH
nSTB
Bus I/O
Bus I/O
Digital Input
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7 Specifications
7.1 Absolute Maximum Ratings
See (1) (2)
MIN
–0.3
–0.3
–0.3
–0.3
–58
–70
–58
–70
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
58
70
7
UNIT
V
Battery supply (reverse-blocked) voltage range –standard versions
VSUP
V
Battery supply (reverse blocked) voltage range –H versions
5-V bus supply voltage
VCC
VIO
V
I/O level shifting voltage
7
V
CAN bus I/O voltage range (CANH, CANL)
CAN bus I/O voltage range (CANH, CANL)
Devices without the "H" suffix
58
70
58
70
7
V
VBUS
Devices with the "H" suffix
Devices without the "H" suffix
Devices with the "H" suffix
V
V
Max differential voltage between CANH and
CANL
V(DIFF)
V
V(Logic_Input)
Logic input terminal voltage range
Logic output terminal voltage range
INH output pin voltage range
INH output pin voltage range
WAKE input pin voltage range
WAKE input pin voltage range
Logic output current
V
V(Logic_Output)
7
V
Devices without the "H" suffix
H versions
V
58 and VO ≤VSUP + 0.3
VINH
V
70 and VO ≤VSUP + 0.3
Devices without the "H" suffix
H versions
V
58 and VI ≤VSUP + 0.3
V(WAKE)
V
70 and VI ≤VSUP + 0.3
IO(LOGIC)
IO(INH)
RXD, and nFAULT
8
4
mA
mA
INH output current
Wake current if due to ground shifts V(WAKE) ≤V(GND) –0.3 V, thus the current into
WAKE must be limited via an external serial resistor
IO(WAKE)
TJ
3
mA
°C
Operating virtual junction temperature range
150
–55
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
7.2 ESD Ratings
VALUE
±4000
±6000
±16000
±1500
±500
UNIT
V
VSUP, INH(1)
Human body model (HBM), per AEC Q100-002
All pins, except VSUP, INH(1)
CAN bus terminals (CANH, CANL)(2)
All terminals(3)
V
V
V(ESD)
Electrostatic discharge
Charged device model (CDM) - SOIC
Charged device model (CDM) - DMT
Machine model (MM)
V
All terminals(3)
V
Corner terminals(3)
All terminals(4)
±750
V
±200
V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Test method based upon AEC-Q100-002, CAN bus terminals stressed with respect to each other and to GND.
(3) Tested in accordance to AEC-Q100-011.
(4) Tested in accordance to JEDEC Standard 22, Test Method A115A.
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VALUE UNIT
7.3 ESD Ratings IEC Specification
ISO 10605 per SAE J2962-2:
Powered Air Discharge(2)
±15000
±8000
V
V
V
V
ISO 10605 per SAE J2962-2:
Powered Contact Discharge(2)
CAN bus terminals (CANH, CANL)
to GND
System level electrostatic discharge
(ESD)
IEC 61000-4-2 (150 pF, 330 Ω):
Unpowered contact discharge
±15000
±6000
IEC 61000-4-2 (150 pF, 330 Ω)
Unpowered contact discharge
VSUP and WAKE
V(ESD)
Pulse 1
Pulse 2
Pulse 3a
Pulse 3b
V
V
V
V
–100
+75
ISO 7637-2
CAN bus terminals (CANH, CANL)
to GND, VSUP, WAKE
Transients according to GIFT - ICT
CAN EMC test specification(1)
–150
+100
Direct coupling capacitor "slow
transient pulse" with 100-nF
coupling capacitor - powered
CAN bus terminals (CANH, CANL)
to GND, VSUP, WAKE
ISO 7637-3 Transients
±85
V
(1) ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different
system level configurations will lead to different results.
(2) Verified by external test facility on SOIC package
7.4 Recommended Operating Conditions
MIN NOM MAX UNIT
Battery supply (reverse-blocked) voltage range - standard version
Battery supply (reverse-blocked) voltage range - H version
5V Supply Voltage
4.5
4.5
4.5
2.8
–2
45
60
V
V
VSUP
VCC
5.5
5.5
V
VIO
I/O supply voltage
V
IOH(LOGIC)
IOL(LOGIC)
IO(INH)
TA
mA
mA
mA
°C
Logic terminal high level output current –RXD and nFAULT
Logic terminal low level output current –RXD and nFAULT
INH output current
2
1
Operational free-air temperature
125
–55
7.5 Thermal Information
TCAN1043x-Q1
THERMAL METRIC(1)
D (SOIC)
14 PINS
78
DMT (VSON)
14 PINS
33.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
33.6
30.5
34.7
10.8
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
5.7
0.4
ΨJT
34.3
10.7
ΨJB
RθJC(bot)
n/a
1.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.6 Dissipation Ratings
PARAMETER
POWER
UNIT
TEST CONDITIONS
DISSIPATION
VSUP = 14 V, VCC = 5 V, VIO = 5 V, TJ = 27°C, RL = 60 Ω,
nSTB = 5 V, EN = 5 V, CL_RXD = 15 pF. Typical CAN
operating conditions at 500 kbps with 25% transmission
(dominant) rate.
58
mW
mW
PD
Average power dissipation
VSUP = 14 V, VCC = 5.5 V, VIO = 5.5 V, TJ = 150°C, RL = 50
Ω, nSTB = 5.5 V, EN = 5.5 V, CL_RXD = 15 pF. Typical high
load CAN operating conditions at 1 Mbps with 50%
transmission (dominant) rate and loaded network.
126
TTSD
Thermal shutdown temperature
Thermal shutdown hysteresis
170
10
°C
°C
TTSD_HYS
7.7 Electrical Characteristics
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
SUPPLY CHARACTERISTICS
Normal, Silent, Go-to-Sleep
40
15
70
45
µA
µA
Standby mode, VCC > 4.5 V, VIO > 2.8 V,
VINH = V(WAKE) = VSUP
Supply current
VSUP
Standby mode
Sleep mode
ISUP
Sleep mode, VCC = VIO = VINH = 0 V
V(WAKE) = VSUP
15
30
70
µA
mA
mA
mA
mA
mA
See 图8-2. TXD = 0 V, RL = 60 Ω, CL
=
=
open. Typical bus load.
Dominant
See 图8-2. TXD = 0 V, RL = 50 Ω, CL
open. High bus load.
80
Supply current
Normal mode
VCC
See 图8-2. TXD = 0 V, CANH = -25 V, RL
open, CL = open
=
Dominant with bus fault
Recessive
110
5
ICC
See 图8-2. TXD = VIO, RL = 50 Ω, CL
open, RCM = open
=
=
See 图8-2. TXD = VIO, RL = 50 Ω, CL
open
Supply current Silent and Go-to-Sleep mode
2.5
Supply current Standby mode
Sleep mode
5
5
See 图8-2. EN = L, NSTB = L
µA
µA
See 图8-2. EN = H or L, NSTB = L
RXD floating, TXD = 0 V (dominant) nSTB =
VIO, EN = VIO
Normal mode
450
5
µA
µA
µA
V
IIO
I/O supply current
Normal, Silent or Go-to-
Sleep mode
RXD floating, TXD = VIO recessive
NSTB = L
Sleep mode
5
UVSUP
Undervoltage detection on VSUP for protected mode
Hysteresis voltage on UVSUP
3.0
4.2
VHYS(UVSUP)
50
4.1
3.9
200
mV
V
Rising undervoltage detection on VCC for protected mode
Falling undervoltage detection on VCC for protected mode
Hysteresis voltage on UVVCC
4.4
UVVCC
3.5
1.3
V
VHYS(UVVCC)
UVVIO
mV
V
Undervoltage detection on VIO for protected mode
Hysteresis voltage on UVIO
2.75
VHYS(UVIO)
80
mV
Driver Electrical Characteristics
CANH
CANL
2.75
0.5
4.5
V
V
Bus output voltage
dominant - normal
mode
See 图8-2 and 图9-3, TXD = 0 V, Normal
VO(D)
mode, 50 ≤RL ≤65 Ω, CL = open, RCM
=
2.25
open
See 图8-2 and 图9-3, TXD = VCC, VIO
=
Bus output voltage
recessive
VCC, Normal or Silent(2), RL = open, RCM
open
=
VO(R)
CANH and CANL
2
0.5 × VCC
3
V
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MAX UNIT
7.7 Electrical Characteristics (continued)
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
See 图8-2 and 图9-3, TXD = 0 V, Normal
mode, 50 Ω ≤RL ≤65 Ω, CL = open, RCM
= open
1.5
3
V
See 图8-2 and 图9-3, TXD = 0 V, Normal
mode, 45 Ω ≤RL ≤50 Ω, CL = open, RCM
= open
1.4
1.5
1.4
3
5
V
V
V
Differential output
voltage dominant
VOD(D)
CANH - CANL
See 图8-2 and 图9-3, TXD = 0 V, Normal
mode, RL = 2240 Ω, CL = open, RCM = open
See 图8-2 and 图9-3, TXD = 0 V, Normal
mode, 45 Ω ≤RL ≤70 Ω, CL = open, RCM
= open
3.3
See 图8-2 and 图9-3, TXD = VCC, Normal
or Silent mode(2), RL = 60 Ω, CL = open,
RCM = open
12
50
mV
mV
–120
–50
Differential output
voltage recessive
VOD(R)
CANH - CANL
See 图8-2 and 图9-3, TXD = VCC, Normal
or Silent mode(2), RL = open, CL = open,
RCM = open
Driver symmetry, dominant or recessive
VSYM = (VO(CANH) + VO(CANL))/VCC
See 图8-2 and 图10-4, Normal mode, CL
=
VSYM
0.9
–400
–100
1.1 V / V
open, RCM = open, TXD = 1MHz(3)
Driver symmetry, dominant
VSYM(DC) = VCC - VO(CANH) - VO(CANL)
See 图8-2 and 图9-3, Normal or Silent
mode, RL = 60 Ω, CL = open, RCM = open
VSYM_DC
400
mV
mA
mA
See 图8-10 and 图9-3, VCANH = -5 V, CANL
= open, TXD = 0 V
Short circuit steady-state output current
dominant
IOS(DOM)
See 图8-10 and 图9-3, VCANL = 40 V,
CANH = open, TXD = 0 V
100
5
See 图8-10 and 图9-3
–27 V ≤VBUS ≤32 V, VBUS = CANH =
CANL, TXD = VIO
Short circuit steady-state output current
recessive
IOS(REC)
mA
–5
CANH
0
0
0
0.1
0.1
0.2
V
V
V
–0.1
–0.1
–0.2
Bus output voltage
Standby mode
STB = VCC or VIO, RL = open,
RCM = open
VO(STB)
CANL
CANH - CANL
Receiver Electrical Characteristics
Common mode range
VCM
-30
30
V
See 图8-3 and 表9-5
Normal and Silent modes
500
400
-3
900
1000
0.5
mV
mV
V
See 图8-3 and 表9-5, VCM ≤±20 V
See 图8-3 and 表9-5, VCM ≤±30 V
Input threshold voltage
Normal and Silent modes
VIT
VREC
VDOM
Receiver recessive voltage
Receiver dominant voltage
See 图8-3 and 表9-5
Normal or Silent mode, VCM = ±20V
0.9
8
V
Hysteresis voltage for input threshold
Normal and Silent modes
VHYS
120
mV
mV
V
See 图8-3 and 表9-5
Input threshold
Sleep mode
VIT(Sleep)
VREC(Sleep)
VDOM(Sleep)
VCM
400
-3
1150
0.4
8
Receiver recessive voltage
Sleep mode
See 图8-3 and 表9-5; VCM = ±12
Receiver dominant voltage
Sleep mode
1.15
-12
V
Common mode range
Standby, Go-to-Sleep and Sleep modes
12
V
See 图8-3 and 表9-5
CANH = CANL = 5 V, VCC = GND, VIO
GND, VSUP = 0 V
=
IIOFF(LKG)
Power-off (unpowered) bus input leakage current
4.8
µA
CI
Input capacitance to ground (CANH or CANL)
Differential input capacitance (CANH or CANL)
Differential input resistance
24
12
30
15
80
40
pF
pF
kΩ
kΩ
(4)
TXD = VCC, VIO = VCC
CID
RID
RIN
30
15
TXD = VCC = VIO = 5 V, Normal mode; -30
≤VCM ≤+30V
Input resistance (CANH or CANL)
Input resistance matching:
[1 –RIN(CANH) / RIN(CANL)] × 100%
RIN(M)
V(CANH) = V(CANL) = 5V
2%
–2%
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7.7 Electrical Characteristics (continued)
Over recommended operating conditions with TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Valid differential load impedance range for bus
fault circuitry
RCBF
RCM = RL, CL = open
45
70
Ω
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
VIH
VIL
High level input voltage
0.7 VIO
V
Low level input voltage
0.3 VIO
V
IIH
High level input leakage current
Low level input leakage current
Unpowered leakage current
Input capacitance
TXD = VCC = VIO = 5.5 V
0
1
–2.5
1
µA
µA
µA
pF
–2.5
–100
–1
IIL
TXD = 0 V, VCC = VIO = 5.5 V
TXD = 5.5 V, VCC = VIO = 0 V
VIN = 0.4 x sin(2 x πx 2 x 106 x t) + 2.5 V
ILKG(OFF)
CI
0
5
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
VOH
VOL
High level output voltage
Low level output voltage
0.8 VIO
0.8 VIO
0.7 VIO
V
V
See 图8-3, IO = –2 mA.
See 图8-3, IO = –2 mA.
0.2 VIO
0.2 VIO
nFAULT TERMINAL (FAULT AND STATUS OUTPUT)
VOH
VOL
High level output voltage
Low level output voltage
V
V
See 图8-1, IO = –2 mA.
See 图8-1 IO = 2 mA.
nSTB TERMINAL (STANDBY MODE INPUT)
VIH
High level input voltage
V
VIL
Low level input voltage
0.3 VIO
V
IIH
High level input leakage current
Low level input leakage current
Unpowered leakage current
nSTB = VCC = VIO = 5.5 V
0.5
–1
–1
10
1
µA
µA
µA
IIL
nSTB = 0 V, VCC = VIO = 5.5 V
nSTB = 5.5 V, VCC = 0V, VIO = 0 V
ILKG(OFF)
0
1
EN TERMINAL (ENABLE MODE INPUT)
VIH
High level input voltage
0.7 VIO
V
VIL
Low level input voltage
0.3 VIO
V
IIH
High level input leakage current
Low level input leakage current
Unpowered leakage current
EN = VCC = VIO = 5.5 V
0.5
–1
–1
10
1
µA
µA
µA
IIL
EN = 0 V, VCC = VIO = 5.5 V
EN = 5.5 V, VCC = 0V, VIO = 0 V
ILKG(OFF)
0
1
INH TERMINAL (INHIBIT OUTPUT)
High level voltage drop INH with respect to VSUP
Leakage current
0.5
1
5
V
ΔVH
IINH = –0.5 mA
ILKG(INH)
INH = 0 V, Sleep Mode
-5
µA
Wake TERMINAL (WAKE INPUT)
VIH
VIL
High level input voltage
Low level input voltage
Standby and Sleep Mode
Standby and Sleep Mode
VSUP - 1.9
V
V
VSUP
-
3.5
IIH
IIL
High level input current(5)
Low level input current(5)
µA
µA
WAKE = VSUP –1 V
–25
–15
WAKE = 1 V
15
25
(1) All typical values are at 25°C and supply voltages of VCC = 5 V, VIO = 3.3 V, and RL = 60 Ω. Unless otherwise noted.
(2) The recessive bus voltage will be the same if the device is in Normal mode with the nSTB and EN terminals high or if the device is in
Silent mode with the nSTB terminal high and EN terminal low.
(3) The bus output voltage symmetry, VSYM, is measured using RTERM / 2 = 30 Ω and CSPLIT = 4.7 nF as shown in 图10-4
(4) Specified by design and verified during product validation using the ISO 11898-2 method.
(5) To minimize system level current consumption, the WAKE pin will automatically configure itself based on the applied voltage to have
either an internal pull-up or pull-down current source. A high level input results in an internal pull-up and a low level input results in an
internal pull-down. For more information, refer to Section 10.4.6.2
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7.8 Switching Characteristics
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
UNI
T
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
DRIVER SWITCHING CHARACTERISTICS
tpHR
tpLD
tsk(p)
tR
Propagation delay time, high TXD to driver recessive
50
40
10
45
45
ns
ns
ns
ns
ns
Propagation delay time, low TXD to driver dominant
Pulse skew (|tpHR - tpLD|)
See 图8-2, Normal mode. RL
= 60 Ω, CL = 100 pF, RCM
=
open
Differential output signal rise time
Differential output signal fall time
tF
See 图8-9, RL = 60 Ω, CL =
open
tTXD_DTO
Dominant time out
1.2
3.8 ms
RECEIVER SWITCHING CHARACTERISTICS
tpRH Propagation delay time, bus recessive input to high RXD
50
50
ns
ns
Propagation delay time, bus dominant input to RXD low
output
tpDL
See 图8-3
CL(RXD) = 15 pF
tR
tF
Output signal rise time (RXD)
Output signal fall time (RXD)
8
8
ns
ns
See Figure 17, RL = 60 Ω, CL
tBUS_DOM
tCBF
Dominant time out
1.3
1.9
3.8 ms
µs
= open
45 Ω ≤RCM ≤70 Ω, CL =
open
Bus fault detection time
Wake Terminal (Wake input)
See 图8-12 and 图8-13
Time required for LWU from a
high to low or low to high on
WAKE
tWAKE_HT
WAKE hold time
5
50 µs
Device Switching Characteristics
Total loop delay, driver input (TXD) to receiver output (RXD),
tPROP(LOOP1)
100 160 ns
110 175 ns
See 图8-5, Normal mode, RL
recessive to dominant
= 60 Ω, CL = 100 pF, CL(RXD)
=
Total loop delay, driver input (TXD) to receiver output (RXD),
dominant to recessive
15 pF
tPROP(LOOP2)
See 图8-4 and 图8-5, Mode
change time for leaving Sleep
mode to entering normal and
silent mode after VCC and VIO
have crossed UV thresholds
tMODE1
Mode change time
Mode change time
20 µs
Mode changes between
Normal, Silent and Standby
modes, and Sleep to Standby
mode transition
tMODE2
10 µs
Time for device to return to
normal operation from UVVCC
or UVVIO under voltage event
tUV_RE-ENABLE Re-enable time after under voltage event
200 µs
tPower_Up
Power up time on VSUP
250
µs
See 图8-11
See 图9-5
Bus time to meet filtered bus requirements for wake up
request
tWK_FILTER
0.5
1.8 µs
tWK_TIMEOUT
tUV
Bus Wake-up timeout value
0.5
159
5
2
ms
See 图9-5
Undervoltage filter time for VIO and VCC
Minimum hold time for transition to sleep mode
340 ms
50 µs
VIO ≤UVVIO or VCC < UVVCC
EN = H and nSTB = L
tGo_To_Sleep
FD Timing Parameters
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7.8 Switching Characteristics (continued)
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
UNI
T
PARAMETER
TEST CONDITIONS
MIN TYP(1) MAX
Bit time on CAN bus output pins with tBIT(TXD) = 500 ns, all
devices
435
155
400
530 ns
210 ns
550 ns
tBIT(BUS)
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns, G
device variants only
Normal mode, RL = 60 Ω, CL
= 100 pF,
CL(RXD) = 15 pF,
Bit time on RXD output pins with tBIT(TXD) = 500 ns, all
devices
tBIT(RXD)
Bit time on RXD output pins with tBIT(TXD) = 200 ns, G device
variants only
ΔtREC = tBIT(RXD) - tBIT(BUS)
120
-65
-45
220 ns
40 ns
15 ns
Receiver timing symmetry with tBIT(TXD) = 500 ns, all devices
ΔtREC
Receiver timing symmetry with tBIT(TXD) = 200 ns, G device
variants only
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7.9 Typical Characteristics
3
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0.5
0
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
-55
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
D002
D001
VIO = 5 V
STB = 0 V
RCM = Open
VCC = 5 V
CL = Open
VIO = 3.3 V
RL = 60 Ω
RL = 60 Ω
CL = Open
Temp = 25°C
RCM = Open
STB = 0 V
图7-2. VOD(D) over VCC
图7-1. VOD(D) over Temperature
1.48
150
125
100
75
1.47
1.46
1.45
1.44
1.43
1.42
1.41
50
25
0
-55
-55
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
D003
D004
VCC = 5 V
CL = Open
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
RCM = Open
STB = 0 V
CL = 100 pF
CL_RXD = 15 pF
STB = 0 V
图7-3. ICC Recessive over Temperature
图7-4. Total Loop Delay over Temperature
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8 Parameter Measurement Information
CANH
RL
TXD
CL
CANL
Copyright © 2016, Texas Instruments Incorporated
图8-1. Supply Test Circuit
RCM
CANH
RL
VCC
0V
50%
tpLD
0.9V
50%
tpHR
TXD
TXD
CL
VOD
VCM
VO(CANH)
90%
10%
CANL
RCM
VO(CANL)
VOD
0.5V
tR
tF
Copyright © 2016, Texas Instruments Incorporated
图8-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
VO
CL_RXD
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
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图8-3. Receiver Test Circuit and Measurement
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CANH
CANL
V
IH
TXD
0V
R
C
L
L
EN
50%
EN
0V
V
I
t
MODE1
RXD
V
OH
V
C
L_RXD
O
RXD
50%
V
OL
Copyright © 2017, Texas Instruments Incorporated
图8-4. tMODE1 Test Circuit and Measurement, Silent Mode to Normal Mode
CANH
V
IH
TXD
TXD
EN
R
C
L
V
I
L
0V
CANL
V
I
200 ns
EN
50%
RXD
0V
tMODE2
V
OH
V
C
L_RXD
O
RXD
50%
V
OL
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图8-5. tMODE2 Test Circuit and Measurement, Normal Mode to Silent Mode
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CANH
VCC
TXD
VI
CL
RL
50%
TXD
CANL
0V
tPROP(LOOP2)
tPROP(LOOP1)
RXD
VOH
VO
CL_RXD
50%
RXD
VOL
Copyright © 2016, Texas Instruments Incorporated
图8-6. tPROP(LOOP) Test Circuit and Measurement
RCM
CANH
VCC
TXD
VCM
VI
CL
RL
50%
TXD
CANL RCM
0V
tPROP(LOOP2)
tPROP(LOOP1)
RXD
VOH
VO
CL_RXD
50%
RXD
VOL
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图8-7. tPROP(LOOP) Test Circuit and Measurement with CM Range
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CANH
VI
TXD
70%
VI
CL
RL
TXD
30%
30%
0V
CANL
tBIT
5 x tBIT
RXD
VOH
70%
RXD
VO
CL_RXD
30%
VOL
tREC_SYM
Copyright © 2016, Texas Instruments Incorporated
图8-8. Loop Delay Symmetry Test Circuit and Measurement
CANH
VIH
TXD
TXD
0V
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Copyright © 2016, Texas Instruments Incorporated
图8-9. TXD Dominant Timeout Test Circuit and Measurement
200 ꢀs
IOS
CANH
CANL
TXD
VBUS
0V
IOS
VBUS
VBUS
or
0V
VBUS
VBUS
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图8-10. Driver Short-Circuit Current Test and Measurement
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VSUP
4.5V
VSUP
CVSUP
INH
VSUP
0V
VO
tPower_Up
TCAN1043
INH = H
VSUP -1V
INH
Copyright © 2016, Texas Instruments Incorporated
图8-11. tPower_Up Timing Measurement
VSUP
VSUP
VWAKE
VSUP - 2
VWAKE
VSUP - 3
VSUP
INH
0V
CVSUP
OR
tWAKE_HT
TCAN1043
tWAKE_HT
VWAKE_IN
INH = H
INH = H
INH
INH
VSUP -1V
VSUP -1V
Copyright © 2016, Texas Instruments Incorporated
图8-12. tWAKE_HT While Monitoring INH Output
VSUP
VSUP
VWAKE
VWAKE
VSUP - 2
VSUP - 3
VSUP
RXD
0V
CVSUP
OR
tWAKE_HT
tWAKE_HT
TCAN1043
VWAKE_IN
INH = H
50%
INH = H
50%
RXD
RXD
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图8-13. tWAKE_HT While Monitoring RXD Output
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9 Detailed Description
9.1 Overview
The TCAN1043xx-Q1 meets or exceeds the specifications of the ISO 11898-2 (2016) High Speed CAN
(Controller Area Network) physical layer standard. The device has been certified to the requirements of
ISO11898-2/5 according to the GIFT/ICT High Speed CAN test specification.
This device provides CAN transceiver differential transmit capability to the bus and differential receive capability
from the bus. The device includes many protection features providing device and CAN bus robustness. All of the
devices are available to support CAN and CAN FD (Flexible Data Rate) up to 2 Mbps while the G version of the
device support CAN and CAN FD data rates up to 5 Mbps.
9.2 Functional Block Diagram
VCC
VIO
VSUP
NC
3
5
10
11
VCC
VIO
VCC
TRANSMIT
DOMINANT
TIME OUT
1
TXD
VSUP
13
12
7
9
INH
VSUP
WAKE
WAKE
LDO
8
nFAULT
14
CONTROL and MODE
LOGIC
nSTB
EN
6
Sleep Receiver
WUP
Detect
UNDER
VOLTAGE
OVER
TEMP
Normal Receiver
RECEIVE
DOMINANT
TIME OUT
4
MUX
RXD
2
GND
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9.3 Feature Description
9.3.1 Internal and External Indicator Flags (nFAULT and RXD)
The following device status indicator flags are implemented to allow for the MCU to determine the status of the
device and the system. In addition to faults, the nFAULT terminal also signals wake up requests and a “cold”
power-up sequence on the VSUP battery terminal so the system can do any diagnostics or cold booting sequence
necessary. The RXD terminal indicates wake up request and the faults are multiplexed (ORed) to the nFAULT
output.
表9-1. Device Status Indicator Flags
EVENT
FLAG NAME
CAUSE
INDICATORS(1)
FLAG IS CLEARED
COMMENT
Power up on VSUP and
any return of VSUP after
it has been below
UVVSUP
nFAULT = L upon
entering Silent mode
from Standby, Go-to-
Sleep, or Sleep mode
After transition to normal
mode
Power-up
PWRON
Wake up request may
After transition to normal only be set from standby,
Wake up event on CAN nFAULT = RXD = L after
bus, state transition on
WAKE pin, or initial
power up
wake up in standby
mode, go-to-sleep mode,
and sleep mode
Wake-up Request
WAKERQ(2)
WAKESR
mode, or either a UVVCC
or UVVIO event
Go-to-sleep, or sleep
mode. Resets timers for
UVVCC or UVVIO
Available upon entering
After four recessive to
dominant edges on TXD
in normal mode,leaving
normal mode, or either a
UVVCC or UVVIO event
Wake up event on CAN normal mode(4) , nFAULT
bus, state transition on
Wake-up Source
Recognition(3)
= L indicates wake from
WAKE pin, initial power WAKE terminal, nFAULT
A LWU source flag is set
on intial power up
up
= H indicates wake from
CAN bus
VCC returns, or Wake-up
request occurs
UVVCC
UVVIO
Under voltage VCC
Under voltage VIO
Not externally indicated
Not externally indicated
VIO returns, or Wake-up
request occurs
Under voltage
VSUP undervoltage event
triggers the PWRON and
WAKERQ flags upon
return of VSUP
UVVSUP
CBF
Under voltage VSUP
Not externally indicated
VSUP returns
CANH shorted to GND,
VCC, VSUP or CANL
shorted to GND, VCC
VSUP
Failure must persist for
four consecutive
dominant to recessive
transistions
nFAULT = L in Normal
mode only(5)
Upon leaving Normal
mode
CAN Bus Failures
,
TXD Dominant Time Out,
dominant (low) signal for
t ≥tTXD_DTO
CAN driver remains
disabled until the
TXDDTO is cleared
TXDDTO
TXDRXD
RXD = L and TXD = H,
or upon transitioning into
Normal, Standby, Go-to-
Sleep, or Sleep modes
TXD and RXD pins are
shorted together for t ≥
tTXD_DTO
CAN driver remains
disabled until the
TXDRXD is cleared
CAN bus dominant fault,
when dominant bus
signal received for t ≥
tBUS_DOM
RXD = H, or upon
transitioning into Normal,
Standby, Go-to-Sleep, or
Sleep modes
nFAULT = L upon
entering Silent mode
from Normal mode
Local Faults
CANDOM
TSD
Driver remains enabled
TJ drops below tTSD and
either RXD = L and TXD
= H, or upon transitioning
into Normal, Standby,
Go-to-Sleep, or Sleep
modes
Thermal Shutdown,
junction temperature ≥
TTSD
CAN driver remains
disabled until the TSD is
cleared
(1) VIO and VSUP are present
(2) Transitions to Go-to-sleep mode is blocked until WAKERQ flag is cleared
(3) Wake-up source recognition reflects the first wake up source. If additional wake-up events occur the source still indicates the original
wake up source
(4) Indicator is only available in normal mode until the flag is cleared
(5) CAN Bus failure flag is indicated after four recessive to dominant edges on TXD
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9.3.2 Power-Up Flag (PWRON)
This is an internal and external flag that is set and controls the power up state of the device. The device powers
on to standby mode with the PWRON flag set after VSUP has cleared the under voltage lock out for VSUP
UVVSUP
,
9.3.3 Wake-Up Request Flag (WAKERQ)
This is an internal and external flag that can be set in standby, go-to-sleep, or sleep mode. This flag is set when
either a valid local wake up (LWU) request occurs, or a valid remote wake request occurs, or on power up on
VSUP. The setting of this flag clears tUV timer for the UVVCC or UVVIO. This flag is cleared upon entering normal
mode or during a under voltage event on VCC or VIO.
9.3.4 Wake-Up Source Recognition Flag (WAKESR)
This flag is an internal and external flag that is set high or low after a valid local wake up (LWU) request occurs,
or a valid remote wake request occurs. This flag is only available in Normal mode before four recessive to
dominant transitions occur on TXD. If the nFAULT pin is high after entering normal mode, this indicates that a
remote wake request was received. If the nFAULT output is low after entering Normal mode, this indicates that a
local wake up event occurred. Upon power up on VSUP, or after and under voltage event on VSUP, the local wake
up request is indicated on nFAULT.
9.3.5 Undervoltage Fault Flags
The TCAN1043xx-Q1 device comes with undervoltage detection circuits on all three supply terminals: VSUP
VCC, and VIO. These flags are internal flags and are not indicated on the nFAULT terminal.
,
9.3.5.1 Undervoltage on VCC Fault
This internal flag is set when the voltage on VCC drops below the undervoltage detection voltage threshold,
UVVCC, for longer than the undervoltage filter time, tUV
.
9.3.5.2 Undervoltage on VIO Fault
This internal flag is set when the voltage on VIO drops below the undervoltage detection voltage threshold,
UVVIO, for longer than the undervoltage filter time, tUV
.
9.3.5.3 Undervoltage on VSUP Fault
This internal flag is set when the voltage on VSUP drops below the undervoltage detection voltage threshold,
UVVSUP. While this flag is not externally indicated, the PWRON and WAKERQ flags are set once the VSUP
supply returns
9.3.6 CAN Bus Failure Fault Flag
The TCAN1043xx-Q1 devices are able to detect the following six faults that can occur on the CANH and CANL
bus terminals. These faults are only detected in Normal mode and are only indicated via the nFAULT terminal
while in Normal mode.
1. CANH bus pin shorted VSUP
2. CANH bus pin shorted VCC
3. CANH bus pin shorted GND
4. CANL bus pin shorted VSUP
5. CANL bus pin shorted VCC
6. CANL bus pin shorted GND
These failures are detected while transmitting a dominant signal on the CAN bus. If one of these fault conditions
persists for four consecutive dominant bit transmissions, the nFAULT indicates a CAN bus failure flag in Normal
mode by driving the nFAULT pin low. The CAN bus driver remains active.
The bus fault failure circuitry is able to detect bus faults for a range of differential resistance loads (RCBF) and for
any time greater than tCBF_MIN
.
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9.3.7 Local Faults
Local faults are detected in both Normal mode and Silent mode, but are only indicated via the nFAULT pin when
transitioned form Normal mode to Silent mode. All other mode transitions clear the local fault flag indicators.
9.3.7.1 TXD Dominant Timeout (TXD DTO)
During Normal mode, the only mode where the CAN driver is active, the TXD DTO circuit prevents the local
node from blocking network communication in event of a hardware or software failure where TXD is held
dominant longer than the time out period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If
no rising edge is seen before the time out constant of the circuit, tTXD_DTO, expires, the CAN driver is disabled.
This keeps the bus free for communication between other nodes on the network. The CAN driver is re-activated
when a recessive signal is seen on the TXD terminal, thus clearing the dominant time out. The receiver and RXD
terminal reflects what is on the CAN bus and the bus terminals is biased to recessive level during a TXD DTO.
This fault is indicated via the TXDDTO flag shown on the nFAULT terminal.
TXD fault stuck dominant: example PCB
failure or bad software
Fault is repaired & transmission
capability restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be —stuck dominant“ blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
Normal CAN
communication
communication after the time tTXD_DTO
.
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus node(s)
Communication from
repaired node
RXD
(receiver)
Communication from
other bus node(s)
Communication from
repaired local node
Communication from
local node
图9-1. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible
transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed
immediately by an error frame. The minimum transmitted data rate may be calculated by: Minimum
Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps.
9.3.7.2 TXD Shorted to RXD Fault
The TXDRXD flag is set if the device detects that the TXD and RXD lines have been shorted together for t
≥tTXD_DTO. This fault is then indicated via the nFAULT terminal. The CAN driver is disabled until the TXDRXD
fault is cleared.
This fault is only indicated in Normal mode and Silent mode.
9.3.7.3 CAN Bus Dominant Fault
The CAN bus dominant fault detects if the CAN bus is stuck in a permanent dominant (low) state. This fault is
detected when the device detects a dominant on the bus for time ≥tBUS_DOM. This fault is then indicated via the
CANDOM flag shown on the nFAULT terminal.
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This fault is only indicated on the nFAULT pin in Silent mode. This fault can also be seen on the RXD pin as a
dominant pulse for a time ≥tBUS_DOM
.
9.3.7.4 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shut down threshold, the device turns off the CAN
driver circuits thus blocking the TXD to the bus transmission path. The shutdown condition is cleared when the
junction temperature of the device drops below the thermal shutdown temperature of the device. If the fault
condition that caused the thermal shutdown is still present, the temperature may rise again causing the device to
reenter thermal shut down. Prolonged operation with thermal shutdown conditions may affect device reliability.
The thermal shutdown circuit includes hysteresis to avoid oscillation of the driver output. This fault is indicated
via the TSD flag shown on the nFAULT terminal.
9.3.7.5 RXD Recessive Fault
The RXD recessive fault detects if the RXD terminal is stuck (clamped) in a permanent recessive state. This fault
is detected when the device transmits four dominant bits to the bus via TXD but the RXD output does not follow.
This fault is then indicated via the RXDREC flag shown on the nFAULT terminal.
9.3.7.6 Undervoltage Lockout (UVLO)
The supply terminals have under voltage detection which puts the device in protected mode if one of the supply
rails drop below the threshold voltage. This protects the bus and system during an under voltage event on either
VSUP, VCC or VIO supply terminals. These faults are internal fault flags and are not indicated via the nFAULT
terminal.
During an undervoltage event on VCC or VIO the device goes into protected mode and the driver is disabled.
After the UV timer expires, the device transitions into sleep mode and the INH pin goes into a high impedance
state. In the event of a UV on VIO where the mode pins are no longer driven, the device transitions into standby
mode (due to internal fail safe biasing on the NSTB and EN pins) until the UV timer expires and the device
transitions into sleep mode.
The VCC and VIO undervoltage detection circuits share the same timer. Therefore, if an undervoltage on one
supply occurs and the timers starts, and then during the undervoltage the other supply has an undervoltage
event before the first supply recovers the timer does not reset.
Once an under voltage condition is cleared and the supplies have returned to valid levels the device typically
needs 200 µs to transition to normal operation.
9.3.7.7 Unpowered Device
The device is designed to be an "ideal passive" or “no load” to the CAN bus if it is unpowered. The bus
terminals (CANH, CANL) have extremely low leakage currents when the device is un-powered so they do not
load down the bus. This is critical if some nodes of the network are unpowered while the rest of the of network
remains in operation.
Logic terminals also have extremely low leakage currents when the device is un-powered so they do not load
down other circuits which may remain powered.
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9.3.7.8 Floating Terminals
These devices have internal pull ups on critical terminals to place the device into known states if the terminals
float. See 表9-2 for details on terminal bias conditions.
表9-2. Terminal Failsafe Biasing
TERMINAL
PULL UP or PULL DOWN
COMMENT
Weakly biases TXD toward recessive to prevent bus blockage or
TXD DTO triggering
TXD
Pull up
Weakly biases nSTB terminal towards low power Standby mode to
prevent excessive system power
nSTB
EN
Pull down
Pull down
Weakly biases EN terminal towards low power mode to prevent
excessive system power
Note
The internal bias should not be relied on by design, especially in noisy environments but should be
considered a fall back protection. Special care needs to be taken when the device is used with MCUs
using open drain outputs. TXD is weakly internally pulled up. The TXD pull up strength and CAN bit
timing require special consideration when this device is used with an open drain TXD output on the
microprocessor CAN controller. An adequate external pull up resistor must be used to ensure that the
TXD output of the microprocessor maintains adequate bit timing input to the CAN transceiver.
9.3.7.9 CAN Bus Short Circuit Current Limiting
The TCAN1043xx-Q1 has several protection features that limit the short circuit current when a CAN bus line is
shorted. These include CAN driver current limiting (dominant and recessive). The device has TXD dominant time
out which prevents permanently having the higher short circuit current of dominant state in case of a system
fault. During CAN communication the bus switches between dominant and recessive states, thus the short circuit
current may be viewed either as the current during each bus state or as a DC average current. For system
current and power considerations in the termination resistors and common mode choke ratings, the average
short circuit current should typically be used. The percentage dominant is limited by the TXD dominant time out
and CAN protocol which has forced state changes and recessive bits such as bit stuffing, control fields, and
interframe space. These ensure there is a minimum recessive amount of time on the bus even if the data field
contains a high percentage of dominant bits.
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short
circuit currents. The average short circuit current may be calculated with 方程式1.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
(1)
Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
Note
The short circuit current and possible fault cases of the network should be taken into consideration
when sizing the power ratings of the termination resistance and other network components.
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9.4 Device Functional Modes
The device has four main operating modes: Normal mode, Standby mode, Silent mode and Sleep mode, and
one transitional mode called Go-to-Sleep mode. Operating mode selection is made via the nSTB and EN input
terminals in conjunction with supply conditions and wake events.
表9-3. Operating Modes
WAKERQ
Flag
VCC and VIO
VSUP
EN
nSTB
Mode
Driver
Receiver
RXD
Bus Bias
INH
> UVVCC & >
UVVIO
> UVVSUP
H
H
X
Normal
Enabled
Enabled
Mirrors Bus
State
VCC/2
ON
> UVVCC & >
UVVIO
> UVVSUP
> UVVSUP
L
H
L
X
Silent
Disabled
(OFF)
Enabled
Mirrors Bus
State
VCC/2
ON
> UVVCC & >
UVVIO
H
Cleared
Go-to-Sleep(1)
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
Weak pull to
GND
ON(2)
(no VIO
)
Cleared
Sleep(3)
Standby
Standby
Sleep
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
(no VIO
Weak pull to
GND
OFF
ON
)
Set
X
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
LOW signals
wake up
Weak pull to
GND
> UVVCC & >
UVVIO
> UVVSUP
> UVVSUP
< UVVSUP
L
X
X
L
X
X
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
LOW signals
wake up
Weak pull to
GND
ON
< UVVCC
<UVVIO
&
X
Disabled
(OFF)
Low Power
Bus Monitor
Enabled (ON)
High or High Z
Weak pull to
GND
OFF (High Z)
OFF (High Z)
(no VIO
)
X
X
Protected
Disabled
(OFF)
Disabled
(OFF)
High Z
High Z
(1) Go-to-sleep: Transitional mode for EN = H, nSTB = L until tgo_to_sleep timer has expired
(2) The INH pin transitions to high Z (off) after tgo_to_sleep timer has expired
(3) Mode change from Go-to-Sleep mode to sleep mode once tgo_to_sleep timer has expired
9.4.1 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See 图9-2 and 图9-3.
In the recessive bus state the bus is biased to a common mode of approximately VCC/2 (2.5 V) via the high
resistance internal input resistors of the receiver of each node on the bus. Recessive is equivalent to a logic high
and is typically a differential voltage on the bus of approximately 0 V.
The dominant bus state is when the bus is driven differentially by one or more drivers. Current flows through the
termination resistors and generates a differential voltage on the bus. Dominant is equivalent to a logic low and is
a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state
overwrites the recessive state.
During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential
voltage of the bus is greater than the differential voltage of a single driver.
The host microprocessor of the CAN node uses the TXD terminal to drive the bus and receives data from the
bus on the RXD terminal.
The TCAN1043xx-Q1 transceivers has a third bus state in low power standby mode where the bus terminals are
weakly biased to ground via the high resistance internal resistors of the receiver. See 图9-2 and 图9-3.
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图9-2. Bus States (Physical Bit Representation)
CANH
VCC/2
GND
A
B
Bias
Unit
RXD
CANL
A. Normal and Silent Modes
B. Sleep and Standby Modes
图9-3. Bias Unit (Recessive Common Mode Bias) and Receiver
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Power
Off
Power On
Start Up
Standby Mode
EN = L,
NSTB = L
Normal Mode
EN: L
NSTB: L
CAN: weak ground
EN = H,
NSTB = H
EN: H
NSTB: H
EN = L,
NSTB = H
EN = L,
CAN: Bi-directional
NSTB = H
INH: H
Wake Sources: CAN, WAKE
INH: H
Silent Mode
EN: L
NSTB: H
CAN: Silent (Receive only)
INH: H
EN = H,
NSTB = H
EN = L or WAKERQ set)
and NSTB = L
EN = H,
NSTB = H
EN = H,
NSTB = L and
WAKERQ Cleared
NSTB = H, EN = L
VCC and VIO supplied
EN = L,
NSTB = H
EN = H,
NSTB = L
EN = H,
NSTB = L and
WAKERQ Cleared
Wake-up Event:
CAN bus
or
WAKE Pin
EN = L,
t < tGO-TO-SLEEP
Go-to-Sleep Mode
EN: H
NSTB: L
Sleep Mode
CAN: weak ground
Wake Sources: CAN, WAKE
INH: H
EN: X*
NSTB: L
CAN: weak ground
EN = H,
t > tGO-TO-SLEEP
NSTB = H, EN = H
VCC and VIO supplied
Wake Sources: CAN, WAKE
INH: floating
VCC < VCC,UV and / or
VIO < VIO,UV for t > tUV
Under-Voltage
On VCC or VIO
*The enable pin can be in a logical high or low state while in sleep mode but since it has an internal pull-down, the lowest possible
power consumption occurs when the pin is left either floating or pulled low externally.
图9-4. State Diagram
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9.4.2 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH
and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD
Entering Normal mode clears both the WAKERQ and PWRON flags.
9.4.3 Silent Mode
Silent mode is commonly referred to as listen only and receive only mode. In this mode, the CAN driver is
disabled but the receiver is fully operational and CAN communication is unidirectional into the device. The
receiver is translating the differential signal from CANH and CANL to a digital output on the RXD terminal.
In Silent mode, the PWRON, and Local Failure Flags can be polled.
9.4.4 Standby Mode
Standby mode is a low power mode where the driver and receiver are disabled, reducing current consumption.
However, this is not the lowest power mode of the device since the INH terminal is on, allowing the rest of the
system to resume normal operation.
During standby mode, a wake up request (WAKERQ) is indicated by the RXD terminal being low. The wake up
source is identified via the nFAULT pin after the device is returned to normal mode.
9.4.5 Go-to-Sleep Mode
Go-to-Sleep mode is the transitional mode of the device from any state to sleep. In this state the driver and
receiver are disabled, reducing the current consumption. However, the INH terminal is on allowing the rest of the
system to resume normal operation. If the device is held in this state for time ≥ tgo_to_sleep the device transitions
to sleep mode and the INH is turned off (high Z).
Entering Go-to-Sleep Mode from standby mode is gated if the WAKERQ flag is set. Once this flag is cleared the
transition is no longer gated.
9.4.6 Sleep Mode with Remote Wake and Local Wake Up Requests
Sleep mode is the lowest power mode of the device. The CAN driver and main receiver are turned off and bi-
directional CAN communication is not possible.
The low power receiver with bus monitor and WAKE circuits are supplied via the VSUP supply terminal. The low
power receiver is able to monitor the bus for any activity that validates the wake up pattern (WUP) requirements,
and the WAKE monitoring circuit monitors for state changes on the WAKE terminal for a local wake up (LWU)
event. The VCC and VIO supplies may be turned off or be controlled via the INH output for additional system level
current savings.
The valid wake up sources in sleep mode are:
• Remote wake request: CAN bus activity that validates the WUP requirements
• Local wake up (LWU) request: state change on WAKE terminal
Additionally, EN and nSTB can be used to change modes if both VCC and VIO are powered.
If a bus wake up pattern (WUP) or local wake up (LWU) event occurs, the internal WAKERQ flag is set and the
device transitions to standby mode which in turn sets the INH output high. The wake up source recognition flag
(WAKESR) is set either high or low to identify which wake event occurred. This flag can be polled via the
nFAULT pin after the device is returned to normal mode and only until there have been four recessive to
dominant transitions on the TXD pin.
The wake source (WAKESR) flag has two states:
• Low: This indicates that the wake up source was via the WAKE pin.
• High: This indicates that a remote wake request via the CAN bus occurred.
If both a local wake and a remote wake request occur, the device indicates whichever event was completed first.
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The device transitions into sleep mode if at any time either or both the VCC or VIO supplies have an under
voltage condition that lasts longer than timer tUV. If VIO remains active in sleep mode, it is recommended to drive
the EN pin low once the device has transitioned into sleep mode to reduce the current consumption due to the
internal pull-down on the EN terminal.
9.4.6.1 Remote Wake Request via Wake Up Pattern (WUP)
The TCAN1043xx-Q1 use the multiple filtered dominant wake up pattern (WUP) from ISO 11898-2 (2016) to
qualify bus activity. The WUP is active for both sleep and standby modes and results in the RXD terminal being
driven low after a valid pattern is received.
The WUP consists of a filtered dominant pulse, followed by a filtered recessive pulse, and finally by a second
filtered dominant pulse. The first filtered dominant initiates the WUP, and the bus monitor then waits on a filtered
recessive; other bus traffic does not reset the bus monitor. Once a filtered recessive is received the bus monitor
is waiting for a filtered dominant and again, other bus traffic does not reset the bus monitor. Immediately upon
reception of the second filtered dominant the bus monitor recognizes the WUP and transition to standby mode,
drives the INH output high and sets the RXD terminal low (if VIO is present) to signal the wake up request.
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than the
tWK_FILTER time. Due to variability in tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP and a wake request may be
generated. Bus state times greater than tWK_FILTER(MAX) will always be detected as part of a WUP and thus a
wake request will always be generated. See 图9-5 for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and wake request prevents noise and bus stuck dominant
faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request.
If the device is switched to normal mode or an under voltage event occurs on either the VCC or VIO supplies, the
wake request is lost.
ISO 11898-2 (2016) has two sets of times for a short and long wake up filter times. The tWK_FILTER timing for the
TCAN1043xx-Q1 devices have been picked to be within the min and max values of both filter ranges. This timing
has been chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the
filter in either bus state.
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Wake
Request
Wake Up Pattern (WUP) received in t < tWK_timeout
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
Mode
Sleep or Standby Mode
Standby Mode
INH
*
RXD
The RXD pin is only driven once VIO is present.
图9-5. Wake Up Pattern (WUP)
For an additional layer of robustness and to prevent false wake-ups, these devices implement a timeout feature.
For a remote wake up event to successfully occur, the entire WUP must be received within the timeout value t <
tWK_timeout (see 图 9-5). If not, the internal logic is reset and the part remains in its current state without waking
up. The full pattern must then be retransmitted, conforming to the constraints mentioned in this section and
shown in figure 图9-5.
9.4.6.2 Local Wake Up (LWU) via WAKE Input Terminal
The WAKE terminal is a high voltage input terminal which can be used for local wake up (LWU) requests via a
voltage transition. The terminal triggers a local wake up (LWU) event on either a low-to-high, or a high-to-low
transition since it has a bi-directional input threshold (falling or rising edge).
This terminal may be used with a switch to VSUP or to ground. If the terminal is unused it should be pulled to
ground or VSUP to avoid unwanted parasitic wake up events.
VSUP
WAKE
RSERIES
Filter
VTH
GND
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图9-6. TCAN1043xx-Q1 WAKE Circuit Example
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图 9-6 shows two possible configurations for the WAKE terminal, the low-side and high side switch
configurations. The objective of the series resistor, RSERIES, is to protect the WAKE pin of the transceiver from
over current conditions that may occur in the event of a ground shift or ground loss. The minimum value of
RSERIES can be calculated using the maximum supply voltage, VSUPMAX and the maximum allowable current of
the WAKE pin, IIO(WAKE). RSERIES is calculated using:
RSERIES = VSUPMAX / IIO(WAKE)
(2)
If the battery voltage never exceeds 58 V DC, then the RSERIES value is approximately 20 kΩ.
The RBIAS resistor is used to set the static voltage level of the WAKE pin when the switch is not in use. When the
switch is in use in a high-side switch configuration, the RBIAS resistor in combination with the RSERIES resistor
sets the WAKE pin voltage appropriately above the VIH threshold. The maximum value of RBIAS can be
calculated using the maximum supply voltage, VSUPMAX, the maximum WAKE threshold voltage VIH, the
maximum WAKE input current IIH and the series resistor value RSERIES. RBIAS is calculated using:
RBIAS < ((VSUP - VIH) / IIH) - RSERIES
(3)
If the battery voltage never exceed 58 V DC, then the RBIAS resistor value must be less than 60 kΩ.
For lower current consumption, the low-side switch configuration is the ideal architecture.
The LWU circuitry is active in 节9.4.6, 节9.4.4 and 节9.4.5. If a valid LWU event occurs the device transitions to
standby mode. The LWU circuitry is not active in Normal mode or Silent mode.
To minimize system level current consumption, the internal bias voltages of the terminal follows the state on the
terminal with a delay of tWAKE(min). A constant high level on WAKE has an internal pull-up to VSUP and a constant
low level on WAKE has an internal pull-down to GND. This minimizes the current flowing into the WAKE pin
under these steady-state conditions so that it does not need to be factored into calculations of the total draw
from VSUP
.
Wake
Threshold
Not Crossed
t ≤ tWAKEHT
No Wake
UP
t ≥ tWAKEHT
Wake UP
Wake
INH
Local Wake Request
*
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
图9-7. Local Wake Up –Rising Edge
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Wake
Threshold
Not Crossed
t ≤ tWAKEHT
No Wake
UP
t ≥ tWAKEHT
Wake UP
Wake
INH
Local Wake Request
*
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
图9-8. Local Wake Up –Falling Edge
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9.4.7 Driver and Receiver Function Tables
表9-4. Driver Function Table
BUS OUTPUTS(2)
DEVICE MODE TXD INPUTS(1)
DRIVEN BUS STATE(3)
CANH CANL
L
Normal
H
Z
Z
Z
Z
Z
L
Z
Z
Z
Z
Z
Dominant
H or Open
Common Mode Biased to VCC/2
Common Mode Biased to VCC/2
Common Mode Biased to GND
Common Mode Biased to GND
Common Mode Biased to GND
Silent
Standby
Go-to-Sleep
Sleep
X
X
X
X
(1) H = high level, L = low level, X = irrelevant.
(2) H = high level, L = low level, Z = high Z receiver bias.
(3) For Bus state and bias see Figure 3 and Figure 4.
表9-5. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD TERMINAL(1)
VID = VCANH –VCANL
Dominant
L
VID ≥0.9 V
Indeterminat
e
0.5 V < VID < 0.9 V
Indeterminate
Normal
Recessive
Open
H
H
VID ≤0.5 V
Open (VID ≈0 V)
VID ≥1.15 V
Dominant
H
Indeterminat
e
VID ≤0.4 V
L if either remote or
local wake events have
occurred
Standby
0.5 V < VID < 1.15 V
Open (VID ≈0 V)
VID ≥1.15 V
Recessive
Open
H
Dominant
L if either remote or
local wake events have
occurred andVIO is
present.
Tri-State if VIO or VSUP
are not present
Indeterminat
e
0.4 V , VIO < 1.15 V
Sleep and Go-to-
Sleep (WUP Monitor)
Recessive
Open
VID ≤0.4 V
Open (VID ≈0 V)
(1) H = high level, L = low level
9.4.8 Digital Inputs and Outputs
All devices have a VIO supply that is used to set the digital input thresholds and digital output levels. The input
thresholds are ratio metric to the VIO supply using CMOS input levels, making them scalable for µPs with digital
IOs from 2.8 V to 5 V. The high level output voltages for the RXD and nFAULT output pins are driven to VIO level
for logic high output.
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9.4.9 INH (Inhibit) Output
The inhibit output terminal is used to control system power management devices allowing for extremely low
system current consumption in sleep mode. This terminal can be used to enable and disable local power
supplies. The pin has two states: driven high and high impedance (High Z).
When high (on), the terminal shows VSUP minus a diode voltage drop. In the high impedance state, the output is
left floating. The INH pin is high for normal, silent, Go-to-Sleep, and standby modes. It is low when in sleep
mode.
Note
This terminal should be considered a “high voltage logic” terminal, not a power output thus should
be used to drive the EN terminal of the system’s power management device and not used as a
switch for the power management supply itself. This terminal is not reverse battery protected and thus
should not be connected outside the system module.
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10 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
The TCAN1043xx-Q1 transceivers are typically used in applications with a host microprocessor or FPGA that
includes the data link layer portion of the CAN protocol. These types of applications usually also include power
management technology that allows for power to be gated to the application via an enable (EN) or inhibit (INH)
pin. A single 5-V regulator can be used to drive both VCC and VIO as shown in 图 10-1, or independent 5-V and
3.3-V regulators can be used to drive VCC and VIO separately as shown in 图10-2. The bus termination is shown
for illustrative purposes.
10.2 Typical Application
VBATTERY
3.3 kꢀ
100 nF
33 kꢀ
EN
VSUP
INH
100 nF
5 V
Vreg
WAKE
CANH
10
7
VOUT
5
9
VIO
TCAN1043
VIN
VIO
nSTB
EN
13
TPSxxx
Port a
14
6
Port b
Port c
MCU
nFAULT
8
NC
11
12
TMS570
RXD
TXD
RXD
TXD
4
1
CANL
3
2
VCC
GND
100 nF
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图10-1. Typical CAN Bus Application Using TCAN1043xx-Q1 with 5 V µC
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VBATTERY
3.3 kꢀ
100 nF
EN
VSUP
33 kꢀ
INH
100 nF
3.3 V
Vreg
WAKE
CANH
7
10
VOUT
5
9
VIO
TCAN1043
VIN
VIO
nSTB
EN
13
TPSxxx
Port a
14
6
Port b
Port c
MCU
nFAULT
8
NC
11
12
TMS570
RXD
TXD
RXD
TXD
4
1
CANL
5 V
Vreg
3
2
VIN
EN
TPSxxx
VCC
GND
VOUT
100 nF
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图10-2. Typical CAN Bus Application Using TCAN1043xx-Q1 with 3.3 V µC
10.2.1 Design Requirements
10.2.1.1 Bus Loading, Length and Number of Nodes
A typical CAN application can have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1043xx-Q1
family.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In ISO 11898-2 the driver differential output is specified
with a bus load that can range fro 50 Ω to 65 Ω where the differential output must be greater than 1.5 V. The
TCAN1043xx-Q1 family is specified to meet the 1.5-V requirement down to 50 Ω and is specified to meet 1.4-V
differential output at 45Ω bus load. The differential input resistance of the TCAN1043xx-Q1 is a minimum of 30
kΩ. If 100 TCAN1043xx-Q1 transceivers are in parallel on a bus, this is equivalent to a 300-Ωdifferential load in
parallel with the nominal 60 Ω bus termination which gives a total bus load of 50 Ω. Therefore, the
TCAN1043xx-Q1 family theoretically supports over 100 transceivers on a single bus segment. However for CAN
network design margin must be given for signal loss across the system and cabling, parasitic loadings, timing,
network imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is much
lower. Bus length may also be extended beyond 40 meters by careful system design and data rate tradeoffs. For
example, CANopen network design guidelines allow the network to be up to 1 km with changes in the
termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
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10.2.2 Detailed Design Procedures
10.2.2.1 CAN Termination
The ISO11898-2 standard specifies the interconnect to be a single twisted pair cable (shielded or unshielded)
with 120 Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be
used to terminate both ends of the cable to prevent signal reflections. Unterminated drop-lines (stubs)
connecting nodes to the bus should be kept as short as possible to minimize signal reflections. The termination
may be in a node but is generally not recommended, especially if the node may be removed from the bus.
Termination must be carefully placed so that it is not removed from the bus. System level CAN implementations
such as CANopen allow for different termination and cabling concepts for example to add cable length.
Node n
(with termination)
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN Controller
CAN
CAN
CAN
Controller
Controller
Controller
TCAN1043HG-Q1
TCAN1043HG-Q1
TCAN1043HG-Q1
TCAN1043HG-Q1
RTERM
RTERM
图10-3. Typical CAN Bus Application
Termination may be a single 120-Ωresistor at the ends of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired then “split termination” may be
used, see 图 10-4. Split termination improves the electromagnetic emissions behavior of the network by
eliminating fluctuations in the bus common mode voltage levels at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM/2
CANL
CANL
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图10-4. CAN Bus Termination Concepts
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10.2.3 Application Curves
50
40
30
20
10
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
D005
VCC = 4.5 V to 5.5 V
CL = Open
VIO = 3.3 V
Temp = 25°C
RL = 60 Ω
STB = 0 V
图10-5. ICC Dominant Current over VCC Supply Voltage
11 Power Supply Recommendations
The TCAN1043xx-Q1 device is designed to operate with a main VCC input voltage supply range between 4.5 V
and 5.5 V. The device also has an IO level shifting supply input, VIO , designed for a range between 2.8 V and
5.5 V. To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a
100 nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance
and inductance of the PCB power planes.
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12 Layout
12.1 Layout
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
12.1.1 Layout Guidelines
• Place the protection and filtering circuitry close to the bus connector to prevent transients, ESD and noise
from propagating onto the board. In this layout example a transient voltage suppression (TVS) device, D1,
has been shown as added protection. The production solution can be either bi-directional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C6 and C8. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the TCAN1043xx-Q1 transceiver and the connector.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
• Use supply (VCC) and ground planes to provide low inductance as high-frequency current will follow the path
of least impedance and not the path of least resistance.
• Use at least two vias for supply (VCC, VIO, VSUP) and ground connections of bypass capacitors and protection
devices to minimize trace and via inductance.
• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C4 on the VCC supply net, C5 on the VIO supply net and C9 on the VSUP supply net.
• Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C7. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination. See the application section for information on power ratings needed
for the termination resistor(s).
• To limit current of digital lines, series resistors may be used as in R2, R3 and R5 but are not required.
• Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,
this is mandatory to ensure the bit timing into the device is met.
• Terminal 9: SW1 is oriented in a low-side configuration which is used to implement a local WAKE event. The
series resistor R10 is needed for protection against over current conditions as it limits the current into the
WAKE pin when the ECU has lost its ground connection. The pull-up resistor R9 is required to provide
sufficient current during stimulation of a WAKE event. See the application section for more information on
calculating both the R9 and R10 values.
• Terminal 14: Is shown assuming the mode terminal, nSTB, is used. If the device is only be used in normal
mode, R5 is not needed and R4 could be used for the pull-up resistor to VIO
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12.2 Layout Example
R1
R2
VIO
CAN Controller
VIO
R4
R5
TCAN1043HG-Q1
1
2
3
4
5
6
7
14
13
12
11
10
9
CAN Controller
TXD
GND
VCC
nSTB
R6
R7
CANH
CANL
NC
C7
VCC
R3
RXD
VIO
CAN Controller
VBAT
VIO
R8
VSUP
SW1
LOCAL
WAKE
R10
EN
WAKE
nFAULT
CAN Controller
Regulator EN
GND
8
CAN Controller
INH
图12-1. TCAN1043xx-Q1 Layout Example
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13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表13-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TCAN1043-Q1
TCAN1043H-Q1
TCAN1043HG-Q1
TCAN1043G-Q1
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
13.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.3 Community Resources
13.4 Trademarks
所有商标均为其各自所有者的财产。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DMT0014A
VSON - 0.9 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.05)
S
C
A
L
E
3
0
.
0
0
0
SECTION A-A
TYPICAL
C
0.9 MAX
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
A
A
2X
15
SYMM
3.9
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
14X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
4223033/B 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
( 0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4223033/B 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1
TCAN1043-Q1, TCAN1043H-Q1
TCAN1043HG-Q1, TCAN1043G-Q1
ZHCSH19E –NOVEMBER 2017 –REVISED MARCH 2021
www.ti.com.cn
EXAMPLE STENCIL DESIGN
DMT0014A
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
7
8
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4223033/B 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
Copyright © 2021 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN1043DMTRQ1
TCAN1043DMTTQ1
TCAN1043DQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
SOIC
SOIC
VSON
VSON
SOIC
SOIC
VSON
VSON
SOIC
SOIC
VSON
VSON
SOIC
SOIC
DMT
DMT
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
3000 RoHS & Green
NIPDAU | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
1043
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
Samples
250
50
RoHS & Green
RoHS & Green
NIPDAU | SN
NIPDAU
TCAN1043DRQ1
D
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
TCAN1043GDMTRQ1
TCAN1043GDMTTQ1
TCAN1043GDQ1
DMT
DMT
D
NIPDAU | SN
NIPDAU | SN
NIPDAU
250
50
RoHS & Green
RoHS & Green
TCAN1043GDRQ1
TCAN1043HDMTRQ1
TCAN1043HDMTTQ1
TCAN1043HDQ1
D
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
DMT
DMT
D
NIPDAU | SN
NIPDAU | SN
NIPDAU
250
50
RoHS & Green
RoHS & Green
TCAN1043HDRQ1
TCAN1043HGDMTRQ1
TCAN1043HGDMTTQ1
TCAN1043HGDQ1
TCAN1043HGDRQ1
D
2500 RoHS & Green
3000 RoHS & Green
NIPDAU
DMT
DMT
D
NIPDAU | SN
NIPDAU | SN
NIPDAU
250
50
RoHS & Green
RoHS & Green
D
2500 RoHS & Green
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1043DMTRQ1
TCAN1043DMTTQ1
TCAN1043DRQ1
VSON
VSON
SOIC
VSON
VSON
SOIC
VSON
VSON
SOIC
VSON
VSON
SOIC
SOIC
DMT
DMT
D
14
14
14
14
14
14
14
14
14
14
14
14
14
3000
250
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
12.4
12.4
16.4
16.4
3.3
3.3
6.5
3.3
3.3
6.5
3.3
3.3
6.5
3.3
3.3
6.5
6.5
4.8
4.8
9.0
4.8
4.8
9.0
4.8
4.8
9.0
4.8
4.8
9.0
9.0
1.2
1.2
2.1
1.2
1.2
2.1
1.2
1.2
2.1
1.2
1.2
2.1
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
12.0
12.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
2500
3000
250
TCAN1043GDMTRQ1
TCAN1043GDMTTQ1
TCAN1043GDRQ1
DMT
DMT
D
2500
3000
250
TCAN1043HDMTRQ1
TCAN1043HDMTTQ1
TCAN1043HDRQ1
DMT
DMT
D
2500
3000
250
TCAN1043HGDMTRQ1
TCAN1043HGDMTTQ1
TCAN1043HGDRQ1
TCAN1043HGDRQ1
DMT
DMT
D
2500
2500
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN1043DMTRQ1
TCAN1043DMTTQ1
TCAN1043DRQ1
VSON
VSON
SOIC
VSON
VSON
SOIC
VSON
VSON
SOIC
VSON
VSON
SOIC
SOIC
DMT
DMT
D
14
14
14
14
14
14
14
14
14
14
14
14
14
3000
250
367.0
210.0
340.5
367.0
210.0
340.5
210.0
210.0
340.5
367.0
210.0
356.0
340.5
367.0
185.0
336.1
367.0
185.0
336.1
185.0
185.0
336.1
367.0
185.0
356.0
336.1
35.0
35.0
32.0
35.0
35.0
32.0
35.0
35.0
32.0
35.0
35.0
35.0
32.0
2500
3000
250
TCAN1043GDMTRQ1
TCAN1043GDMTTQ1
TCAN1043GDRQ1
DMT
DMT
D
2500
3000
250
TCAN1043HDMTRQ1
TCAN1043HDMTTQ1
TCAN1043HDRQ1
DMT
DMT
D
2500
3000
250
TCAN1043HGDMTRQ1
TCAN1043HGDMTTQ1
TCAN1043HGDRQ1
TCAN1043HGDRQ1
DMT
DMT
D
2500
2500
D
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TCAN1043DQ1
TCAN1043GDQ1
TCAN1043HDQ1
TCAN1043HGDQ1
D
D
D
D
SOIC
SOIC
SOIC
SOIC
14
14
14
14
50
50
50
50
507
507
507
507
8
8
8
8
3940
3940
3940
3940
4.32
4.32
4.32
4.32
Pack Materials-Page 3
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不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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Copyright © 2023，德州仪器 (TI) 公司
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