TCAN1051HVDRBRQ1 [TI]
具有灵活数据速率的汽车类故障保护 CAN 收发器 | DRB | 8 | -55 to 125;
| 型号： | TCAN1051HVDRBRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有灵活数据速率的汽车类故障保护 CAN 收发器 | DRB | 8 | -55 to 125 |
| 文件： | 总47页 (文件大小：1836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
TCAN1051-Q1 具有CAN FD 和故障保护功能的汽车类CAN 收发器
5Mbps 的数据速率，器件型号包含“V”后缀的器件配
有提供 I/O 电平的辅助电源输入，用于设置输入引脚阈
值和 RXD 输出电平。该系列器件具有静音模式，通常
也称作仅侦听模式。此外，所有器件都提供多种保护特
性来提高器件和网络的耐用性。
1 特性
• AEC Q100 标准：符合汽车应用要求
– 温度等级1：-40°C 至125°C，TA
– HBM 分级等级：±16kV
– CDM 分级等级：±1500V
• 符合ISO 11898-2:2016 和
ISO 11898-5:2007 物理层标准
• 提供功能安全型
器件信息
封装(1)
器件型号
封装尺寸
SOIC (8)
VSON (8)
4.90mm × 3.91mm
3.00mm x 3.00mm
TCAN1051x-Q1
– 可帮助进行功能安全系统设计的文档
• “Turbo”CAN：
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
– 所有器件均支持经典CAN 和2Mbps CAN FD
（灵活数据速率），而“G”选项支持5Mbps
– 具有较短的对称传播延迟时间和快速循环次数，
可增加时序裕量
VCC
3
NC or VIO
5
VCC or VIO
– 在有负载CAN 网络中实现更快的数据速率
• EMC 性能：支持SAE J2962-2 和IEC 62228-3
（最高500kbps）无需共模扼流圈
• I/O 电压范围支持3.3V 和5V MCU
• 未供电时具有理想无源行为
7
6
CANH
CANL
TSD
Dominant
time-out
1
8
TXD
S
– 总线和逻辑引脚处于高阻态（无负载）
– 在总线和RXD 输出上实现上电/断电无干扰运行
• 保护特性
Mode
Select
UVP
– IEC ESD 保护高达±15kV
VCC or VIO
– 总线故障保护：±58V（非H 型号）和±70V（H
型号）
– VCC 和VIO（仅限V 型号）电源终端具有欠压保
护
Logic
Output
4
RXD
2
– 驱动器显性超时(TXD DTO) - 数据速率低至
10kbps
Copyright © 2016, Texas Instruments Incorporated
GND
A. 引脚5 的功能取决于器件；在不含V 后缀的器件上为无连接
(NC) 引脚，在包含V 后缀的器件上为用于I/O 电平转换的VIO
引脚
– 热关断保护(TSD)
• 接收器共模输入电压：±30V
• 典型循环延迟：110ns
• 结温范围为–55°C 至150°C
• 采用SOIC (8) 封装和无引线VSON (8) 封装
(3.0mm x 3.0mm)，具有改进的自动光学检查(AOI)
功能
B. RXD 逻辑输出在不含“V”后缀的器件上驱动为VCC，而在包
含“V”后缀的器件上驱动为VIO。
功能方框图
2 应用
• 汽车和运输
• 所有器件均支持高负载CAN 网络
• 重型机械ISOBUS 应用–
ISO 11783
3 说明
这款 CAN 收发器系列符合 ISO1189-2 (2016) 高速
CAN（控制器局域网络）物理层标准。所有器件均设
计用于数据速率高达 2Mbps（兆位每秒）的 CAN FD
网络。器件型号包含“G”后缀的器件旨在实现高达
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSET0
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
www.ti.com.cn
Table of Contents
8.1 Overview...................................................................18
8.2 Functional Block Diagram.........................................18
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................22
9 Application Information Disclaimer.............................24
9.1 Application Information............................................. 24
9.2 Typical Applications.................................................. 24
10 Power Supply Recommendations..............................28
11 Device and Documentation Support..........................31
11.1 Documentation Support.......................................... 31
11.2 Receiving Notification of Documentation Updates..31
11.3 Support Resources................................................. 31
11.4 Trademarks............................................................. 31
11.5 Electrostatic Discharge Caution..............................31
11.6 Glossary..................................................................31
12 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................5
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings ....................................... 6
6.2 ESD Ratings............................................................... 6
6.3 ESD Ratings, Specifications....................................... 7
6.4 Recommended Operating Conditions.........................8
6.5 Thermal Information....................................................8
6.6 Power Rating.............................................................. 8
6.7 Electrical Characteristics.............................................9
6.8 Switching Characteristics..........................................12
6.9 Typical Characteristics..............................................13
7 Parameter Measurement Information..........................14
8 Detailed Description......................................................18
Information.................................................................... 31
4 Revision History
Changes from Revision C (May 2017) to Revision D (April 2021)
Page
• 添加了特性：EMC 性能：.................................................................................................................................. 1
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 添加了特性“提供功能安全型”........................................................................................................................ 1
• Deleted "Base" from the D and DRB pin images in the Pin Configurations and Functions ...............................5
• Deleted "Product Preview" from the DRB pin images in the Pin Configurations and Functions ........................5
• Added footnote to the GND pin in the Pin Functions table ................................................................................ 5
• Changed ICC Normal Mode Max value From: 180 To 110 in the Electrical Characteristics table....................... 9
• Added SR, Differential output slew rate to the Switching Characteristics table ...............................................12
Changes from Revision B (May 2016) to Revision C (May 2017)
Page
• 向汽车应用特性添加了条目................................................................................................................................1
• 删除了特性“符合2015 年12 月17 日发布的ISO 11898-2 物理层更新草案”.................................................1
• 将特性从“符合发布的ISO 11898-2:2007 和ISO 11898-2:2003 物理层标准”更改为“符合ISO
11898-2:2016 和ISO 11898-5:2007 物理层标准”.............................................................................................1
• 将“特性”从“所有器件均支持2Mbps CAN FD..”更改为“所有器件均支持经典CAN 和2Mbps CAN FD..”
............................................................................................................................................................................1
• 添加了特性“可采用SOIC(8) 封装和无引线VSON(8) 封装...”....................................................................... 1
• 将应用从“重型机械ISO11783”更改为“重型机械ISOBUS 应用–ISO 11783”........................................ 1
• 更改了功能方框图，删除了显性超时功能框....................................................................................................... 1
• Changed "D Package for (HV) and (HGV)" To: "DRB Package for (HV) and (HGV)" ........................................5
• Added Storage temperature range to the Absolute Maximum Ratings table......................................................6
• Changed the ESD Ratings table to show the D(SOIC) and DRB (VSON) values .............................................6
• Changed Human Body Model (HBM) From: ±10000 To: ±16000 in the ESD Ratings table...............................6
• Changed Charged Device Model (CDM) From: ±750 To: ±1500 in the ESD Ratings table................................6
• Changed TBD to values for the DRB (VSON) Package in the ESD Ratings table.............................................6
• Added the Power Rating table ...........................................................................................................................8
• Changed VSYM in the DRIVER ELECTRICAL CHARACTERISTICS table.........................................................9
• Changed VSYM_DC in the DRIVER ELECTRICAL CHARACTERISTICS table................................................... 9
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TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
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• Deleted "VI = 0.4 sin (4E6 πt) + 2.5 V" from the Test Condition of CI in the RECEIVER ELECTRICAL
CHARACTERISTICS table.................................................................................................................................9
• Deleted "VI = 0.4 sin (4E6 πt)" from the Test Condition of CID in the RECEIVER ELECTRICAL
CHARACTERISTICS table.................................................................................................................................9
• Added "-30 V ≤VCM ≤+30" to the Test Condition of RID and RIN in the RECEIVER ELECTRICAL
CHARACTERISTICS table table........................................................................................................................ 9
• Changed the Functional Block Diagram, removed the Dominant time-out box................................................18
• Changed 表8-2, BUS OUTPUT colum.............................................................................................................20
Changes from Revision A (April 2016) to Revision B (May 2016)
Page
• 添加了特性“符合发布的ISO 11898-2:2007 和ISO 11898-2:2003 物理层标准”............................................1
• 将特性从“符合ISO11898-2 (2016) 标准的要求”更改为“符合2015 年12 月17 日发布的ISO 11898-2 物
理层更新草案”...................................................................................................................................................1
• 更改了应用列表..................................................................................................................................................1
• 向器件信息表中添加了VSON (8) 引脚封装.......................................................................................................1
• Added the VSON (8) pin package to the Pin Configuration and Functions ....................................................... 5
• Added V(Diff) to the 节6.1 table ..........................................................................................................................6
• Added the DRB package to the Thermal Information table ............................................................................... 8
Changes from Revision * (March 2016) to Revision A (April 2016)
Page
• 将器件状态从“产品预发布”更改为“量产”....................................................................................................1
• Added the VSON (8) pin package to the Pin Configuration and Functions ....................................................... 5
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Product Folder Links: TCAN1051-Q1 TCAN1051V-Q1 TCAN1051H-Q1 TCAN1051HV-Q1 TCAN1051G-Q1
TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
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Device Comparison Table
DEVICE
NUMBER
5-Mbps FLEXIBLE DATA
RATE
3-V LEVEL SHIFTER
INTEGRATED
BUS FAULT PROTECTION
PIN 8 MODE SELECTION
TCAN1051-Q1 (Base)
TCAN1051G-Q1
TCAN1051GV-Q1
TCAN1051V-Q1
±58 V
±58 V
±58 V
±58 V
±70 V
±70 V
±70 V
±70 V
X
X
X
X
Silent Mode
TCAN1051H-Q1
TCAN1051HG-Q1
TCAN1051HGV-Q1
TCAN1051HV-Q1
X
X
X
X
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TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
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5 Pin Configuration and Functions
S
TXD
GND
VCC
1
2
3
4
8
7
6
5
S
TXD
1
2
3
4
8
7
6
5
GND
VCC
CANH
CANL
NC
CANH
CANL
NC
RXD
RXD
图5-2. DRB Package for (H), (G), and (HG) Devices
8 PIN (VSON) Top View
图5-1. D Package for (H), (G) and (HG) Devices 8
PIN (SOIC) Top View
S
TXD
1
2
3
4
8
7
6
5
S
TXD
GND
VCC
1
2
3
4
8
7
6
5
GND
VCC
CANH
CANL
VIO
CANH
CANL
VIO
RXD
RXD
图5-4. DRB Package for (V), (GV), (HV) and (HGV)
Devices 8 PIN (VSON) Top View
图5-3. D Package for (V), (GV), (HV), and (HGV)
Devices 8 PIN (SOIC) Top View
表5-1. Pin Functions
PINS
TYPE
DESCRIPTION
(V), (GV), (HV),
(HGV)
NAME
(H), (G), (HG)
TXD
GND(1)
VCC
RXD
NC
1
2
3
4
5
1
2
3
4
DIGITAL INPUT
GND
CAN transmit data input (LOW for dominant and HIGH for recessive bus states)
Ground connection
POWER
Transceiver 5-V supply voltage
DIGITAL OUTPUT CAN receive data output (LOW for dominant and HIGH for recessive bus states)
No Connect
—
5
—
POWER
VIO
Transceiver I/O level shifting supply voltage (Devices with "V" suffix only)
Low level CAN bus input/output line
High level CAN bus lnput/output line
Silent Mode control input (active high)
—
6
CANL
CANH
S
6
BUS I/O
7
7
BUS I/O
8
8
DIGITAL INPUT
(1) For DRB (VSON) package options, the thermal pad may be connected to GND in order to optimize the thermal characteristics of the
package.
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TCAN1051GV-Q1 TCAN1051HG-Q1 TCAN1051HGV-Q1
TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
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6 Specifications
over operating free-air temperature range (unless otherwise noted) (1) (2)
6.1 Absolute Maximum Ratings
MIN
–0.3
–0.3
MAX
UNIT
V
VCC
VIO
5-V Bus Supply Voltage Range
I/O Level-Shifting Voltage Range
All Devices
7
7
Devices with the "V" Suffix
V
CAN Bus I/O voltage range (CANH,
CANL)
VBUS
Devices without the "H" Suffix
Devices without the “H”suffix
Devices with the "H" Suffix
58
V
V
V
V
–58
–58
-70
Max differential voltage between
CANH and CANL
V(Diff)
58
CAN Bus I/O voltage range (CANH,
CANL)
VBUS
70
70
Max differential voltage between
CANH and CANL
V(Diff)
Devices with the “H”suffix
–70
–0.3
Logic input terminal voltage range (TXD,
S)
V(Logic_Input)
V
+7 and VI ≤VIO + 0.3
All Devices
V(Logic_Output)
IO(RXD)
TJ
Logic output terminal voltage range (RXD)
RXD (Receiver) output current
V
–0.3
–8
+7 and VI ≤VIO + 0.3
8
mA
°C
°C
150
150
Virtual junction temperature range (see 节6.5)
Storage temperature range (see 节6.5)
–55
–65
TSTG
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated condition for extended periods may affect device reliability.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
TEST CONDITIONS
VALUE
UNIT
D (SOIC) Package
All terminals(1)
±6000
±16000
±1500
±200
Human Body Model (HBM) ESD stress voltage
V
CAN bus terminals (CANH, CANL) to GND(2)
All terminals(3)
Charged Device Model (CDM) ESD stress voltage
Machine Model
V
V
All terminals(4)
DRB (VSON) Package
All terminals(1)
±6000
±16000
±1500
±200
Human Body Model (HBM) ESD stress voltage
V
CAN bus terminals (CANH, CANL) to GND(2)
All terminals(3)
Charged Device Model (CDM) ESD stress voltage
Machine Model
V
V
All terminals(4)
(1) Tested in accordance to JEDEC Standard 22, Test Method A114.
(2) Test method based upon JEDEC Standard 22 Test Method A114, CAN bus is stressed with respect to GND.
(3) Tested in accordance to JEDEC Standard 22, Test Method C101.
(4) Tested in accordance to JEDEC Standard 22, Test Method A115.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
ZHCSGC4D –MARCH 2016 –REVISED APRIL 2021
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6.3 ESD Ratings, Specifications
TEST CONDITIONS
VALUE
UNIT
D (SOIC) Package
SAE J2962-2 per ISO 10605:
Powered Air Discharge
±15000
±8000
±15000
±8000
±4000
CAN bus terminals (CANH,
CANL) to GND
System Level Electro-Static Discharge (ESD)
V
SAE J2962-2 per ISO 10605:
Powered Contact Discharge
IEC 61000-4-2: Unpowered
Contact Discharge
CAN bus terminals (CANH,
CANL) to GND
System Level Electro-Static Discharge (ESD)
System Level Electrical fast transient (EFT)
V
V
IEC 61000-4-2: Powered
Contact Discharge
CAN bus terminals (CANH,
CANL) to GND
IEC 61000-4-4: Criteria A
Pulse 1
Pulse 2
Pulse 3a
Pulse 3b
–100
+75
ISO7637 Transients according to GIFT - ICT
CAN EMC test spec(1)
CAN bus terminals (CANH,
CANL) to GND
V
V
–150
+100
Direct Coupling Capacitor "Slow
Transient Pulse" with100 nF
coupling capacitor - Powered
CAN bus terminals (CANH,
CANL) to GND
ISO7637-3 Transients
±85
DRB (VSON) Package
SAE J2962-2 per ISO 10605:
Powered Air Discharge
±15000
±8000
±14000
±8000
±4000
CAN bus terminals (CANH,
CANL) to GND
System Level Electro-Static Discharge (ESD)
V
SAE J2962-2 per ISO 10605:
Powered Contact Discharge
IEC 61000-4-2: Unpowered
Contact Discharge
CAN bus terminals (CANH,
CANL) to GND
System Level Electro-Static Discharge (ESD)
System Level Electrical fast transient (EFT)
V
V
IEC 61000-4-2: Powered
Contact Discharge
CAN bus terminals (CANH,
CANL) to GND
IEC 61000-4 Criteria A
Pulse 1
Pulse 2
Pulse 3a
Pulse 3b
–100
+75
ISO7637 Transients according to GIFT - ICT
CAN EMC test spec(1)
CAN bus terminals (CANH,
CANL) to GND
V
V
–150
+100
Direct Coupling Capacitor "Slow
Transient Pulse" with100 nF
coupling capacitor - Powered
CAN bus terminals (CANH,
CANL) to GND
ISO7637-3 Transients
±85
(1) ISO7637 is a system level transient test. Results given here are specific to the GIFT-ICT CAN EMC Test specification conditions.
Different system level configurations may lead to different results.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
TCAN1051G-Q1, TCAN1051GV-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1
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MAX UNIT
6.4 Recommended Operating Conditions
MIN
4.5
VCC
5-V Bus Supply Voltage Range
5.5
V
5.5
VIO
I/O Level-Shifting Voltage Range
RXD terminal HIGH level output current
RXD terminal LOW level output current
2.8
IOH(RXD)
IOL(RXD)
–2
mA
2
6.5 Thermal Information
TCAN1051-Q1
DRB (VSON)
8 Pins
Thermal Metric(1)
TEST CONDITIONS
D (SOIC)
8 Pins
105.8
46.8
Unit
RθJA
Junction-to-air thermal resistance
High-K thermal resistance
40.2
°C/W
°C/W
°C/W
°C/W
RθJB
Junction-to-board thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-top characterization parameter
49.7
RθJC(TOP)
ΨJT
48.3
15.7
8.7
0.6
Junction-to-board characterization
parameter
46.2
15.9
°C/W
ΨJB
TTSD
Thermal shutdown temperature
Thermal shutdown hysteresis
170
5
170
5
°C
°C
TTSD_HYS
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Power Rating
PARAMETER
TEST CONDITIONS
POWER DISSIPATION
UNIT
VCC = 5 V, VIO = 5 V (if applicable), TJ = 27°C, RL = 60 Ω, S at 0
V, Input to TXD at 250 kHz, CL_RXD = 15 pF. Typical CAN
operating conditions at 500 kbps with 25% transmission
(dominant) rate.
52
mW
PD
Average power dissipation
VCC = 5.5 V, VIO = 5.5 V (if applicable), TJ = 150°C, RL = 50 Ω, S
at 0 V, Input to TXD at 500 kHz, CL_RXD = 15 pF. Typical high
load CAN operating conditions at 1 Mbps with 50% transmission
(dominant) rate and loaded network.
124
mW
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6.7 Electrical Characteristics
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Supply Characteristics
See 图7-1, TXD = 0 V, RL = 60 Ω, CL
=
=
40
45
70
80
open, RCM = open, S = 0V
Normal mode
(dominant)
See 图7-1, TXD = 0 V, RL = 50 Ω, CL
open, RCM = open, S = 0V
Normal mode (dominant
–bus fault)
See 图7-1, TXD = 0 V, S = 0V, CANH =
-12V, RL = open, CL = open, RCM = open
110
mA
ICC
5-V Supply current
See 图7-1, TXD = VCC, RL = 50 Ω, CL
open, RCM = open,
S = 0V
=
Normal mode
(recessive)
1.5
1.5
2.5
See 图7-1, TXD = VCC, RL = 50 Ω,CL
open, RCM = open,
=
Silent mode
2.5
S = VCC
Normal and Silent
modes
IIO
I/O supply current
RXD Floating, TXD = S = 0 or 5.5 V
90
300
4.4
µA
V
Rising undervoltage detection on VCC for
protected mode
4.2
UVVCC
Falling undervoltage detection on VCC for
protected mode
All devices
3.8
1.3
4.0
4.25
VHYS(UVVCC)
UVVIO
Hysteresis voltage on UVVCC
200
mV
V
Undervoltage detection on VIO for protected
mode
2.75
Devices with the "V" Suffix (I/O level-shifting)
VHYS(UVVIO)
Hysteresis voltage on UVVIO for protected mode
80
mV
S Terminal (Mode Select Input)
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
S = VCC or VIO = 5.5 V
0.7 x VIO
2
VIH
VIL
High-level input voltage
V
0.3 x VIO
Low-level input voltage
0.8
30
2
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
IIL
S = 0 V, VCC = VIO = 5.5 V
0
µA
–2
Ilkg(OFF)
S = 5.5 V, VCC = VIO = 0 V
-1
1
TXD Terminal (CAN Transmit Data Input)
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
Devices with the "V" suffix (I/O level-shifting)
Devices without the "V" suffix (5-V only)
TXD = VCC = VIO = 5.5 V
0.7 x VIO
2
VIH
VIL
High-level input voltage
Low-level input voltage
V
0.3 x VIO
0.8
1
IIH
High-level input leakage current
Low-level input leakage current
Unpowered leakage current
Input capacitance
0
-25
0
–2.5
–100
–1
IIL
TXD = 0 V, VCC = VIO = 5.5 V
µA
pF
–7
Ilkg(OFF)
CI
TXD = 5.5 V, VCC = VIO = 0 V
1
5
VIN = 0.4 * sin(4E6 * π* t) + 2.5 V
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MAX UNIT
6.7 Electrical Characteristics (continued)
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
RXD Terminal (CAN Receive Data Output)
Devices with the "V" suffix (I/O level-
shifting), See 图7-2, IO = –2 mA
0.8 × VIO
4
VOH
High-level output voltage
Devices without the "V" suffix (5-V only),
See 图7-2, IO = –2 mA
4.6
V
Devices with the "V" suffix (I/O level-
shifting), See 图7-2, IO = +2 mA
0.2 x VIO
VOL
Low-level output voltage
Devices without the "V" suffix (5-V only),
0.2
0
0.4
See 图7-2, IO = +2 mA
Ilkg(OFF)
Unpowered leakage current
RXD = 5.5 V, VCC = 0 V, VIO = 0 V
1
µA
–1
Driver Electrical Characteristics
CANH
CANL
2.75
0.5
4.5
Bus output voltage
(dominant
See 图8-2 and 图7-1, TXD = 0 V, S = 0 V,
50 Ω ≤RL ≤65 Ω, CL = open, RCM = open
VO(DOM)
2.25
See 图8-2 and 图7-1, TXD = VCC, VIO
=
Bus output voltage
(recessive)
VCC, S = VCC or 0 V (2), RL = open (no load),
RCM = open
VO(REC)
CANH and CANL
2
0.5 × VCC
3
V
See 图8-2 and 图7-1, TXD = 0 V, S = 0 V,
45 Ω ≤RL < 50 Ω, CL = open, RCM = open
1.4
1.5
3
3
Differential output
VOD(DOM)
See 图8-2 and 图7-1, TXD = 0 V, S = 0 V,
50 Ω ≤RL ≤65 Ω, CL = open, RCM = open
CANH - CANL
voltage (dominant)
See 图8-2 and 图7-1, TXD = 0 V, S = 0 V,
RL = 2240 Ω, CL = open, RCM = open
1.5
5
See 图8-2 and 图7-1, TXD = VCC, S = 0 V,
RL = 60 Ω, CL = open, RCM = open
12
50
–120
–50
Differential output
VOD(REC)
CANH - CANL
mV
voltage (recessive)
See 图8-2 and 图7-1, TXD = VCC, S = 0 V,
RL = open (no load), CL = open, RCM = open
See 图7-1 and 图9-2, S at 0 V, Rterm = 60
Ω, Csplit = 4.7 nF, CL = open,
Transient symmetry (dominant or recessive)
( VO(CANH) + VO(CANL)) / VCC
VSYM
0.9
–0.4
–100
1.1
0.4
V/V
V
RCM = open, TXD = 250 kHz, 1 MHz
DC Output symmetry (dominant or recessive)
See 图7-1 and 图8-2, S = 0 V,
RL = 60 Ω, CL = open, RCM = open
VSYM_DC
(VCC –VO(CANH) –VO(CANL)
)
See 图8-2 and 图7-7, 图7-7, S at 0 V,
VCANH = -5 V to 40 V, CANH = open,
TXD = 0 V
Short-circuit steady-state output current,
dominant
IOS(SS_DOM)
mA
mA
See 图8-2 and 图7-7, S at 0 V, VCANL = -5
V to 40 V, CANH = open,
TXD = 0 V
100
5
See 图8-2 and 图7-7, –27 V ≤VBUS ≤32
V, Where VBUS = CANH = CANL, TXD =
Short-circuit steady-state output current,
recessive
IOS(SS_REC)
–5
V
CC, all modes
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6.7 Electrical Characteristics (continued)
Over recommended operating conditions, TA = –55°C to 125°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX UNIT
Receiver Electrical Characteristics
See 图7-2, 表8-5 and 表7-1, S = 0 or VCC
or VIO
VCM
VIT+
VIT–
VIT+
VIT–
Common mode range, normal mode
-30
+30
900
V
Positive-going input threshold voltage, all modes
See 图7-2, 表8-5 and 表7-1, S = 0 or VCC
or VIO, -20 V ≤VCM ≤+20 V
Negative-going input threshold voltage, all
modes
500
400
mV
Positive-going input threshold voltage, all modes
1000
See 图7-2, 表8-5 and 表7-1, S = 0 or VCC
or VIO, -30 V ≤VCM ≤+30 V
Negative-going input threshold voltage, all
modes
See 图7-2, 表8-5 and 表7-1, S = 0 or VCC
or VIO
VHYS
Hysteresis voltage (VIT+ - VIT–
)
120
mV
Ilkg(IOFF)
CI
Power-off (unpowered) bus input leakage current CANH = CANL = 5 V, VCC = VIO = 0 V
4.8
30
15
80
40
µA
pF
pF
kΩ
kΩ
Input capacitance to ground (CANH or CANL)
Differential input capacitance
TXD = VCC, VIO = VCC
TXD = VCC, VIO = VCC
24
12
CID
RID
Differential input resistance
30
15
TXD = VCC = VIO = 5 V, S = 0 V,
-30 V ≤VCM ≤+30 V
RIN
Input resistance (CANH or CANL)
Input resistance matching:
[1 –RIN(CANH) / RIN(CANL)] × 100%
RIN(M)
VCANH = VCANL = 5 V
+2%
–2%
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V, RL = 60 Ω.
(2) For the bus output voltage (recessive) will be the same if the device is in Normal mode with S terminal LOW or if the device is in Silent
mode with the S terminal is HIGH.
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6.8 Switching Characteristics
Over recommended operating conditions with TA = -55°C to 125°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1) MAX UNIT
Device Switching Characteristics
Total loop delay, driver input (TXD) to receiver
output (RXD), recessive to dominant
tPROP(LOOP1)
tPROP(LOOP2)
tMODE
100
110
1
160
175
See 图7-4, S = 0 V,
RL = 60 Ω,
ns
Total loop delay, driver input (TXD) to receiver
output (RXD), dominant to recessive
CL = 100 pF, CL(RXD) = 15 pF
Mode change time, from Normal to Silent or
from Silent to Normal
10 µs
See 图7-3
Driver Switching Characteristics
Propagation delay time, high TXD to driver
tpHR
75
55
recessive (dominant to recessive)
Propagation delay time, low TXD to driver
dominant (recessive to dominant)
See 图7-1, S = 0 V,
RL = 60 Ω,
CL = 100 pF, RCM = open
tpLD
ns
tsk(p)
tR
Pulse skew (|tpHR - tpLD|)
20
45
45
Differential output signal rise time
Differential output signal fall time
tF
Differential output slew rate, dominant-to-
recessive transition
SR
70 V/µs
3.8 ms
See 图7-6, S = 0 V,
RL = 60 Ω, CL = open
tTXD_DTO
Dominant timeout
1.2
Receiver Switching Characteristics
Propagation delay time, bus recessive input to
tpRH
65
50
ns
ns
high output (Dominant to Recessive)
Propagation delay time, bus dominant input to
low output (Recessive to Dominant)
See 图7-2, S = 0 V,
CL(RXD) = 15 pF
tpDL
tR
tF
RXD Output signal rise time
RXD Output signal fall time
10
10
ns
ns
FD Timing Parameters
Bit time on CAN bus output pins with tBIT(TXD)
=
=
435
155
400
120
-65
530
210
500 ns, all devices
tBIT(BUS)
tBIT(RXD)
ΔtREC
Bit time on CAN bus output pins with tBIT(TXD)
200 ns, G device variants only
Bit time on RXD output pins with tBIT(TXD)
500 ns, all devices
=
See 图7-5 , S = 0 V,
RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF,
550
ns
Bit time on RXD output pins with tBIT(TXD)
200 ns, G device variants only
=
220
ΔtREC = tBIT(RXD) - tBIT(BUS)
Receiver timing symmetry with tBIT(TXD) = 500
ns, all devices
40
15
Receiver timing symmetry with tBIT(TXD) = 200
ns, G device variants only
-45
(1) All typical values are at 25°C and supply voltages of VCC = 5 V and VIO = 5 V (if applicable), RL = 60 Ω
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6.9 Typical Characteristics
3
2.5
2
3
2.5
2
1.5
1
1.5
1
0.5
0.5
0
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
-55
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
D002
D001
VIO = 5 V
S = 0 V
VCC = 5 V
CL = Open
VIO = 3.3 V
RL = 60 Ω
RL = 60 Ω
CL = Open
RCM = Open
Temp = 25°C
RCM = Open
S = 0 V
图6-2. VOD(D) over VCC
图6-1. VOD(D) over Temperature
1.48
150
125
100
75
1.47
1.46
1.45
1.44
1.43
1.42
1.41
50
25
0
-55
-55
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
-35
-15
5
25 45
Temperature (°C)
65
85
105 125
D003
D004
VCC = 5 V
CL = Open
VIO = 3.3 V
RL = 60 Ω
VCC = 5 V
VIO = 3.3 V
RL = 60 Ω
RCM = Open
S = 0 V
CL = 100 pF
CL_RXD = 15 pF
S = 0 V
图6-3. ICC Recessive over Temperature
图6-4. Total Loop Delay over Temperature
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7 Parameter Measurement Information
RCM
CANH
VCC
50%
tpLD
0.9V
50%
tpHR
TXD
TXD
0V
RL
CL
VOD
VCM
VO(CANH)
90%
10%
CANL
RCM
VO(CANL)
VOD
0.5V
tR
tF
Copyright © 2016, Texas Instruments Incorporated
图7-1. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
VO
CL_RXD
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
Copyright © 2016, Texas Instruments Incorporated
图7-2. Receiver Test Circuit and Measurement
表7-1. Receiver Differential Input Voltage Threshold Test
INPUT (See Receiver Test Circuit and Measurement
OUTPUT
VCANH
VCANL
-30.5 V
29.5 V
|VID|
1000 mV
1000 mV
900 mV
900 mV
500 mV
500 mV
400 mV
400 mV
X
RXD
-29.5 V
30.5 V
L
L
VOL
-19.55 V
20.45 V
-19.75 V
20.25 V
-29.8 V
30.2 V
-20.45 V
19.55 V
-20.25 V
19.75 V
-30.2 V
29.8 V
L
L
H
H
H
H
H
VOH
Open
Open
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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CANH
VIH
TXD
0V
VI
RL
CL
S
50%
CANL
S
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
Copyright © 2016, Texas Instruments Incorporated
图7-3. tMODE Test Circuit and Measurement
CANH
VIH
TXD
0V
VI
RL
CL
S
50%
CANL
S
0V
tMODE
RXD
VOH
VO
CL_RXD
RXD
50%
VOL
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图7-4. TPROP(LOOP) Test Circuit and Measurement
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VI
70%
TXD
CANH
30%
30%
0V
900mV
VOH
TXD
VI
RL
CL
5 x tBIT
tBIT(TXD)
CANL
tBIT(BUS)
S
0V
VDIFF
RXD
500mV
VO
CL_RXD
70%
RXD
30%
VOL
tBIT(RXD)
图7-5. CAN FD Timing Parameter Measurement
CANH
RL
VIH
TXD
TXD
0V
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
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图7-6. TXD Dominant Timeout Test Circuit and Measurement
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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200 ꢀs
IOS
CANH
CANL
TXD
VBUS
IOS
VBUS
VBUS
0V
or
0V
VBUS
VBUS
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图7-7. Driver Short Circuit Current Test and Measurement
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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8 Detailed Description
8.1 Overview
These CAN transceivers meet the ISO11898-2 (2016) High Speed CAN (Controller Area Network) physical layer
standard. They are designed for data rates in excess of 1 Mbps for CAN FD and enhanced timing margin /
higher data rates in long and highly-loaded networks. These devices provide many protection features to
enhance device and CAN robustness.
8.2 Functional Block Diagram
VCC
3
NC or VIO
5
VCC or VIO
7
6
CANH
CANL
TSD
Dominant
time-out
1
8
TXD
S
Mode
Select
UVP
VCC or VIO
Logic
Output
4
RXD
2
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GND
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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8.3 Feature Description
8.3.1 TXD Dominant Timeout (DTO)
During normal mode (the only mode where the CAN driver is active), the TXD DTO circuit prevents the
transceiver from blocking network communication in the event of a hardware or software failure where TXD is
held dominant longer than the timeout period tTXD_DTO. The DTO circuit timer starts on a falling edge on TXD.
The DTO circuit disables the CAN bus driver if no rising edge is seen before the timeout period expires. This
frees the bus for communication between other nodes on the network. The CAN driver is re-activated when a
recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition. The receiver and RXD
terminal still reflect activity on the CAN bus, and the bus terminals are biased to the recessive level during a TXD
dominant timeout.
TXD fault stuck dominant: example PCB
failure or bad software
Fault is repaired & transmission
capability restored
TXD
(driver)
tTXD_DTO
Driver disabled freeing bus for other nodes
Bus would be —stuck dominant“ blocking communication for the
whole network but TXD DTO prevents this and frees the bus for
Normal CAN
communication
communication after the time tTXD_DTO
.
CAN
Bus
Signal
tTXD_DTO
Communication from
other bus node(s)
Communication from
repaired node
RXD
(receiver)
Communication from
other bus node(s)
Communication from
repaired local node
Communication from
local node
图8-1. Example Timing Diagram for TXD DTO
Note
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible
transmitted data rate of the device. The CAN protocol allows a maximum of eleven successive
dominant bits (on TXD) for the worst case, where five successive dominant bits are followed
immediately by an error frame. This, along with the tTXD_DTO minimum, limits the minimum data rate.
Calculate the minimum transmitted data rate by: Minimum Data Rate = 11 / tTXD_DTO
.
8.3.2 Thermal Shutdown (TSD)
If the junction temperature of the device exceeds the thermal shutdown threshold (TTSD), the device turns off the
CAN driver circuits thus blocking the TXD-to-bus transmission path. The CAN bus terminals are biased to the
recessive level during a thermal shutdown, and the receiver-to-RXD path remains operational. The shutdown
condition is cleared when the junction temperature drops at least the thermal shutdown hysteresis temperature
(TTSD_HYS) below the thermal shutdown temperature (TTSD) of the device.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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8.3.3 Undervoltage Lockout
The supply terminals have undervoltage detection that places the device in protected mode. This protects the
bus during an undervoltage event on either the VCC or VIO supply terminals.
表8-1. Undervoltage Lockout 5 V Only Devices (Devices without the "V" Suffix)
VCC
DEVICE STATE(1)
BUS OUTPUT
RXD
> UVVCC
< UVVCC
Normal
Per TXD
Mirrors Bus(2)
Protected
High Impedance
High Impedance
(1) See the VIT section of the Electrical Characteristics.
(2) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
表8-2. Undervoltage Lockout I/O Level Shifting Devices (Devices with the "V" Suffix)
VCC
VIO
DEVICE STATE
BUS OUTPUT
RXD
> UVVCC
< UVVCC
> UVVCC
< UVVCC
> UVVIO
> UVVIO
< UVVIO
< UVVIO
Normal
Per TXD
Mirrors Bus(1)
High (Recessive)
High Impedance
High Impedance
Protected
Protected
Protected
High Impedance
High Impedance
High Impedance
(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
Note
After an undervoltage condition is cleared and the supplies have returned to valid levels, the device
typically resumes normal operation within 50 µs.
8.3.4 Unpowered Device
The device is designed to be 'ideal passive' or 'no load' to the CAN bus if it is unpowered. The bus terminals
(CANH, CANL) have extremely low leakage currents when the device is unpowered to avoid loading down the
bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains in
operation. The logic terminals also have extremely low leakage currents when the device is unpowered to avoid
loading down other circuits that may remain powered.
8.3.5 Floating Terminals
These devices have internal pull ups on critical terminals to place the device into known states if the terminals
float. The TXD terminal is pulled up to VCC or VIO to force a recessive input level if the terminal floats. The S
terminal is also pulled down to force the device into Normal mode if the terminal floats.
8.3.6 CAN Bus Short Circuit Current Limiting
The device has two protection features that limit the short circuit current when a CAN bus line is short-circuit fault
condition: driver current limiting (both dominant and recessive states) and TXD dominant state time out to
prevent permanent higher short circuit current of the dominant state during a system fault. During CAN
communication the bus switches between dominant and recessive states, thus the short circuit current may be
viewed either as the instantaneous current during each bus state or as an average current of the two states. For
system current (power supply) and power considerations in the termination resistors and common-mode choke
ratings, use the average short circuit current. Determine the ratio of dominant and recessive bits by the data in
the CAN frame plus the following factors of the protocol and PHY that force either recessive or dominant at
certain times:
• Control fields with set bits
• Bit stuffing
• Interframe space
• TXD dominant time out (fault case limiting)
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These ensure a minimum recessive amount of time on the bus even if the data field contains a high percentage
of dominant bits. The short circuit current of the bus depends on the ratio of recessive to dominant bits and their
respective short circuit currents. The average short circuit current may be calculated with the following formula:
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
(1)
Where:
• IOS(AVG) is the average short circuit current
• %Transmit is the percentage the node is transmitting CAN messages
• %Receive is the percentage the node is receiving CAN messages
• %REC_Bits is the percentage of recessive bits in the transmitted CAN messages
• %DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
• IOS(SS)_REC is the recessive steady state short circuit current
• IOS(SS)_DOM is the dominant steady state short circuit current
Note
Consider the short circuit current and possible fault cases of the network when sizing the power
ratings of the termination resistance and other network components.
8.3.7 Digital Inputs and Outputs
8.3.7.1 5-V VCC Only Devices (Devices without the "V" Suffix):
The 5-V VCC only devices are supplied by a single 5-V rail. The digital inputs have TTL input thresholds and are
therefore 5 V and 3.3 V compatible. The RXD outputs on these devices are driven to the VCC rail for logic high
output. Additionally, the TXD pin is internally pulled up to VCC, and the S pin is pulled low to GND. The internal
bias of the mode pins may only place the device into a known state if the terminals float, they may not be
adequate for system-level biasing during transients or noisy enviroments.
Note
TXD pull up strength and CAN bit timing require special consideration when these devices are used
with CAN controllers with an open-drain TXD output. An adequate external pull up resistor must be
used to ensure that the CAN controller output of the micrcontroller maintains adequate bit timing to the
TXD input.
8.3.7.2 5 V VCC with VIO I/O Level Shifting (Devices with the "V" Suffix):
These devices use a 5 V VCC power supply for the CAN driver and high speed receiver blocks. These
transceivers have a second power supply for I/O level-shifting (VIO). This supply is used to set the CMOS input
thresholds of the TXD and S pins and the RXD high level output voltage. Additionally, the TXD pin is internally
pulled up to VIO, and the S pin is pulled low to GND.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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8.4 Device Functional Modes
The device has two main operating modes: Normal mode and Silent mode. Operating mode selection is made
via the S input terminal.
表8-3. Operating Modes
S Terminal
LOW
MODE
DRIVER
RECEIVER
Enabled (ON)
Enabled (ON)
RXD Terminal
Mirrors Bus State(1)
Mirrors Bus State(1)
Normal Mode
Silent Mode
Enabled (ON)
Disabled (OFF)
HIGH
(1) Mirrors bus state: low if CAN bus is dominant, high if CAN bus is recessive.
8.4.1 CAN Bus States
The CAN bus has two states during powered operation of the device: dominant and recessive. A dominant bus
state is when the bus is driven differentially, corresponding to a logic low on the TXD and RXD terminal. A
recessive bus state is when the bus is biased to VCC / 2 via the high-resistance internal input resistors RIN of the
receiver, corresponding to a logic high on the TXD and RXD terminals.
Normal and Silent Mode
4
CANH
3
Vdiff(D)
2
Vdiff(R)
CANL
1
Time, t
Recessive
Logic H
Dominant
Logic L
Recessive
Logic H
图8-2. Bus States (Physical Bit Representation)
8.4.2 Normal Mode
Select the Normal mode of device operation by setting S terminal low. The CAN driver and receiver are fully
operational and CAN communication is bi-directional. The driver translates a digital input on TXD to a differential
output on CANH and CANL. The receiver translates the differential signal from CANH and CANL to a digital
output on RXD.
8.4.3 Silent Mode
Activate Silent mode by setting S terminal high. The CAN driver is disabled, preventing communication from the
TXD pin to the CAN bus. The high speed receiver remains active so that CAN bus communication continues to
be relayed to the RXD output pin.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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8.4.4 Driver and Receiver Function Tables
表8-4. Driver Function Table
INPUTS
OUTPUTS
DEVICE
DRIVEN BUS STATE
S (1)
L or open
H
TXD(1) (2)
CANH(1)
CANL(1)
L
H or Open
X
H
Z
Z
L
Z
Z
Dominant
Recessive
Recessive
All Devices
(1) H = high level, L = low level, X = irrelevant, Z = common mode (recessive) bias to VCC / 2. See CAN Bus States for bus state and
common mode bias information.
(2) Devices have an internal pull up to VCC or VIO on TXD terminal. If the TXD terminal is open, the terminal is pulled high and the
transmitter remain in recessive (non-driven) state.
表8-5. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD TERMINAL(1)
VID = VCANH –VCANL
Dominant
?
L(2)
VID ≥VIT+(MAX)
(2)
VIT-(MIN) < VID < VIT+(MAX)
VID ≤VIT-(MIN)
?
Normal or Silent
Recessive
Open
H(2)
H
Open (VID ≈0 V)
(1) H = high level, L = low level, ? = indeterminate.
(2) See Receiver Electrical Characteristics section for input thresholds.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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9 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the
data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V
microprocessor applications. The bus termination is shown for illustrative purposes.
9.2 Typical Applications
Node n
(with termination)
Node 1
Node 2
Node 3
MCU or DSP
MCU or DSP
MCU or DSP
MCU or DSP
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Controller
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
CAN
Transceiver
RTERM
RTERM
图9-1. Typical CAN Bus Application
9.2.1 Design Requirements
9.2.1.1 Bus Loading, Length and Number of Nodes
The ISO 11898-2 Standard specifies a maximum bus length of 40 m and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A large number of nodes requires transceivers with high input impedance such as the TCAN1051 family of
transceivers.
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2. They have made system-level trade-offs for data rate, cable length, and parasitic loading of the bus.
Examples of some of these specifications are ARINC825, CANopen, DeviceNet and NMEA2000.
The TCAN1051 family is specified to meet the 1.5 V requirement with a 50Ω load, incorporating the worst case
including parallel transceivers. The differential input resistance of the TCAN1051 family is a minimum of 30 kΩ. If
100 TCAN1051 family transceivers are in parallel on a bus, this is equivalent to a 300Ω differential load worst
case. That transceiver load of 300 Ω in parallel with the 60Ω gives an equivalent loading of 50 Ω. Therefore, the
TCAN1051 family theoretically supports up to 100 transceivers on a single bus segment. However, for CAN
network design margin must be given for signal loss across the system and cabling, parasitic loadings, network
imbalances, ground offsets and signal integrity thus a practical maximum number of nodes is typically much
lower. Bus length may also be extended beyond the original ISO 11898 standard of 40 m by careful system
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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design and datarate tradeoffs. For example CANopen network design guidelines allow the network to be up to 1
km with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. In using this flexibility comes the
responsibility of good network design and balancing these tradeoffs.
9.2.2 Detailed Design Procedures
9.2.2.1 CAN Termination
The ISO 11898 standard specifies the interconnect to be a twisted pair cable (shielded or unshielded) with 120-
Ω characteristic impedance (ZO). Resistors equal to the characteristic impedance of the line should be used to
terminate both ends of the cable to prevent signal reflections. Unterminated drop lines (stubs) connecting nodes
to the bus should be kept as short as possible to minimize signal reflections. The termination may be on the
cable or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that
two terminations always exist on the network.
Termination may be a single 120-Ω resistor at the end of the bus, either on the cable or in a terminating node. If
filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used.
(See 图 9-2). Split termination improves the electromagnetic emissions behavior of the network by eliminating
fluctuations in the bus common-mode voltages at the start and end of message transmissions.
Standard Termination
Split Termination
CANH
CANH
RTERM/2
CAN
Transceiver
CAN
Transceiver
RTERM
CSPLIT
RTERM/2
CANL
CANL
Copyright © 2016, Texas Instruments Incorporated
图9-2. CAN Bus Termination Concepts
The TCAN1051 family of transceivers have variants for both 5-V only applications and applications where level
shifting is needed for a 3.3-V micrcontroller.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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图9-3. Typical CAN Bus Application Using 5 V CAN Controller
图9-4. Typical CAN Bus Application Using 3.3 V CAN Controller
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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9.2.3 Application Curves
50
40
30
20
10
0
4.5 4.6 4.7 4.8 4.9
5
VCC (V)
5.1 5.2 5.3 5.4 5.5
D005
VCC = 4.5 V to 5.5 V
CL = Open
VIO = 3.3 V
Temp = 25°C
RL = 60 Ω
S = 0 V
图9-5. ICC Dominant Current over VCC Supply Voltage
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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10 Power Supply Recommendations
These devices are designed to operate from a VCC input supply voltage range between 4.5 V and 5.5 V. Some
devices have an output level shifting supply input, VIO, designed for a range between 3 V and 5.5 V. Both supply
inputs must be well regulated. A bulk capacitance, typically 4.7 μF, should be placed near the CAN transceiver's
main VCC supply output, and in addition a bypass capacitor, typically 0.1 μF, should be placed as close to the
device VCC and VIO supply terminals. This helps to reduce supply voltaeg ripple present on the outputs of the
switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB
power planes and traces.
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Layout
Robust and reliable bus node design often requires the use of external transient protection device in order to
protect against EFT and surge transients that may occur in industrial enviroments. Because ESD and transients
have a wide frequency bandwidth from approximately 3 MHz to 3 GHz, high-frequency layout techniques must
be applied during PCB design. The TCAN1051 family comes with high on-chip IEC ESD protection, but if higher
levels of system level immunity are desired external TVS diodes can be used. TVS diodes and bus filtering
capacitors should be placed as close to the on-board connectors as possible to prevent noisy transient events
from propagating further into the PCB and system.
11.1 Layout Guidelines
• Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and
noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,
D1, has been used for added protection. The production solution can be either bi-directional TVS diode or
varistor with ratings matching the application requirements. This example also shows optional bus filter
capacitors C4 and C5. Additionally (not shown) a series common mode choke (CMC) can be placed on the
CANH and CANL lines between the transceiver U1 and connector J1.
• Design the bus protection components in the direction of the signal path. Do not force the transient current to
divert from the signal path to reach the protection device.
• Use supply (VCC) and ground planes to provide low inductance.
Note
High-frequency currents follows the path of least impedance and not the path of least resistance.
• Use at least two vias for supply (VCC) and ground connections of bypass capacitors and protection devices to
minimize trace and via inductance.
• Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver,
examples are C1, C2 on the VCC supply and C6 and C7 on the VIO supply.
• Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C3. Split
termination provides common mode filtering for the bus. When bus termination is placed on the board instead
of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the
bus thus also removing the termination. See the application section for information on power ratings needed
for the termination resistor(s).
• To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not
required.
• Terminal 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used,
this is mandatory to ensure the bit timing into the device is met.
• Terminal 5: For "V" variants of the TCAN1051 family, bypass capacitors should be placed as close to the pin
as possible (example C6 and C7). For device options without VIO I/O level shifting, this pin is not internally
connected and can be left floating or tied to any existing net, for example a split pin connection.
• Terminal 8: is shown assuming the mode terminal, S, will be used. If the device will only be used in normal
mode, R4 is not needed and R5 could be used for the pull down resistor to GND.
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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11.2 Layout Example
S
VCC or VIO
TXD
GND
R1
R2
1
2
3
4
8
7
6
5
GND
R6
R7
GND
C3
U1
VCC
GND
VIO
RXD
R3
GND
图11-1. Layout Example
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TCAN1051-Q1, TCAN1051V-Q1, TCAN1051H-Q1, TCAN1051HV-Q1
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11 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
11.1 Documentation Support
11.1.1 Related Documentation
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
NIPDAU
SN
TCAN1051DQ1
LIFEBUY
ACTIVE
SOIC
SON
D
8
8
75
RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
TCAN1051DRBRQ1
DRB
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
Samples
Samples
Samples
TCAN1051DRBTQ1
TCAN1051DRQ1
ACTIVE
ACTIVE
SON
DRB
D
8
8
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
SOIC
NIPDAU
TCAN1051GDQ1
LIFEBUY
ACTIVE
SOIC
SON
D
8
8
75
RoHS & Green
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
TCAN1051GDRBRQ1
DRB
3000 RoHS & Green
Samples
Samples
Samples
Samples
Samples
Samples
Samples
TCAN1051GDRBTQ1
TCAN1051GDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SOIC
SOIC
SON
SON
SOIC
DRB
D
8
8
8
8
8
8
250
2500 RoHS & Green
75 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
RoHS & Green
SN
NIPDAU
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1051
1051
TCAN1051GVDQ1
D
1051V
1051V
1051V
1051V
TCAN1051GVDRBRQ1
TCAN1051GVDRBTQ1
TCAN1051GVDRQ1
DRB
DRB
D
SN
NIPDAU
TCAN1051HDQ1
LIFEBUY
ACTIVE
SOIC
SON
D
8
8
75
RoHS & Green
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
TCAN1051HDRBRQ1
DRB
3000 RoHS & Green
Samples
Samples
Samples
TCAN1051HDRBTQ1
TCAN1051HDRQ1
ACTIVE
ACTIVE
SON
DRB
D
8
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
SOIC
2500 RoHS & Green
NIPDAU
TCAN1051HGDQ1
LIFEBUY
ACTIVE
SOIC
SON
D
8
8
75
RoHS & Green
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051
1051
TCAN1051HGDRBRQ1
DRB
3000 RoHS & Green
Samples
Samples
Samples
TCAN1051HGDRBTQ1
TCAN1051HGDRQ1
TCAN1051HGVDQ1
ACTIVE
ACTIVE
LIFEBUY
SON
SOIC
SOIC
DRB
D
8
8
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
1051
1051
1051V
2500 RoHS & Green
NIPDAU
NIPDAU
D
75
RoHS & Green
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN1051HGVDRBRQ1
TCAN1051HGVDRBTQ1
TCAN1051HGVDRQ1
ACTIVE
ACTIVE
ACTIVE
SON
SON
SOIC
DRB
DRB
D
8
8
8
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
1051V
Samples
Samples
Samples
SN
1051V
1051V
NIPDAU
TCAN1051HVDQ1
LIFEBUY
ACTIVE
SOIC
SON
D
8
8
75
RoHS & Green
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
1051V
1051V
TCAN1051HVDRBRQ1
DRB
3000 RoHS & Green
Samples
Samples
Samples
Samples
Samples
Samples
Samples
TCAN1051HVDRBTQ1
TCAN1051HVDRQ1
TCAN1051VDQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SON
SOIC
SOIC
SON
SON
SOIC
DRB
D
8
8
8
8
8
8
250
2500 RoHS & Green
75 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
RoHS & Green
SN
NIPDAU
NIPDAU
SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
1051V
1051V
1051V
1051V
1051V
1051V
D
TCAN1051VDRBRQ1
TCAN1051VDRBTQ1
TCAN1051VDRQ1
DRB
DRB
D
SN
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jun-2023
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TCAN1051H-Q1, TCAN1051HG-Q1, TCAN1051HGV-Q1, TCAN1051HV-Q1 :
Catalog : TCAN1051H, TCAN1051HG, TCAN1051HGV, TCAN1051HV
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1051DRBRQ1
TCAN1051DRBTQ1
TCAN1051DRQ1
SON
SON
SOIC
SON
SON
SOIC
SOIC
SON
SON
SOIC
SON
SON
SOIC
SOIC
SON
SON
DRB
DRB
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
330.0
180.0
330.0
330.0
180.0
330.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
330.0
330.0
180.0
12.4
12.4
12.5
12.4
12.4
12.4
12.5
12.4
12.4
12.5
12.4
12.4
12.4
12.5
12.4
12.4
3.3
3.3
6.4
3.3
3.3
6.4
6.4
3.3
3.3
6.4
3.3
3.3
6.4
6.4
3.3
3.3
3.3
3.3
5.2
3.3
3.3
5.2
5.2
3.3
3.3
5.2
3.3
3.3
5.2
5.2
3.3
3.3
1.0
1.0
2.1
1.0
1.0
2.1
2.1
1.0
1.0
2.1
1.0
1.0
2.1
2.1
1.0
1.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q2
Q2
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q2
Q2
Q1
Q1
Q2
Q2
2500
3000
250
TCAN1051GDRBRQ1
TCAN1051GDRBTQ1
TCAN1051GDRQ1
DRB
DRB
D
2500
2500
3000
250
TCAN1051GDRQ1
D
TCAN1051GVDRBRQ1
TCAN1051GVDRBTQ1
TCAN1051GVDRQ1
TCAN1051HDRBRQ1
TCAN1051HDRBTQ1
TCAN1051HDRQ1
DRB
DRB
D
2500
3000
250
DRB
DRB
D
2500
2500
3000
250
TCAN1051HDRQ1
D
TCAN1051HGDRBRQ1
TCAN1051HGDRBTQ1
DRB
DRB
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN1051HGDRQ1
TCAN1051HGVDRBRQ1
TCAN1051HGVDRBTQ1
TCAN1051HGVDRQ1
TCAN1051HGVDRQ1
TCAN1051HVDRBRQ1
TCAN1051HVDRBTQ1
TCAN1051HVDRQ1
SOIC
SON
SON
SOIC
SOIC
SON
SON
SOIC
SON
SON
SOIC
D
DRB
DRB
D
8
8
8
8
8
8
8
8
8
8
8
2500
3000
250
330.0
330.0
180.0
330.0
330.0
330.0
180.0
330.0
330.0
180.0
330.0
12.5
12.4
12.4
12.4
12.5
12.4
12.4
12.5
12.4
12.4
12.5
6.4
3.3
3.3
6.4
6.4
3.3
3.3
6.4
3.3
3.3
6.4
5.2
3.3
3.3
5.2
5.2
3.3
3.3
5.2
3.3
3.3
5.2
2.1
1.0
1.0
2.1
2.1
1.0
1.0
2.1
1.0
1.0
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
12.0
Q1
Q2
Q2
Q1
Q1
Q2
Q2
Q1
Q2
Q2
Q1
2500
2500
3000
250
D
DRB
DRB
D
2500
3000
250
TCAN1051VDRBRQ1
TCAN1051VDRBTQ1
TCAN1051VDRQ1
DRB
DRB
D
2500
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN1051DRBRQ1
TCAN1051DRBTQ1
TCAN1051DRQ1
SON
SON
SOIC
SON
SON
SOIC
SOIC
SON
SON
SOIC
SON
SON
SOIC
SOIC
SON
SON
SOIC
SON
DRB
DRB
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
3000
250
346.0
200.0
340.5
346.0
200.0
356.0
340.5
346.0
200.0
340.5
346.0
200.0
356.0
340.5
346.0
200.0
340.5
346.0
346.0
183.0
336.1
346.0
183.0
356.0
336.1
346.0
183.0
336.1
346.0
183.0
356.0
336.1
346.0
183.0
336.1
346.0
35.0
25.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
25.0
35.0
25.0
35.0
25.0
35.0
25.0
25.0
35.0
2500
3000
250
TCAN1051GDRBRQ1
TCAN1051GDRBTQ1
TCAN1051GDRQ1
DRB
DRB
D
2500
2500
3000
250
TCAN1051GDRQ1
D
TCAN1051GVDRBRQ1
TCAN1051GVDRBTQ1
TCAN1051GVDRQ1
TCAN1051HDRBRQ1
TCAN1051HDRBTQ1
TCAN1051HDRQ1
DRB
DRB
D
2500
3000
250
DRB
DRB
D
2500
2500
3000
250
TCAN1051HDRQ1
D
TCAN1051HGDRBRQ1
TCAN1051HGDRBTQ1
TCAN1051HGDRQ1
TCAN1051HGVDRBRQ1
DRB
DRB
D
2500
3000
DRB
Pack Materials-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN1051HGVDRBTQ1
TCAN1051HGVDRQ1
TCAN1051HGVDRQ1
TCAN1051HVDRBRQ1
TCAN1051HVDRBTQ1
TCAN1051HVDRQ1
TCAN1051VDRBRQ1
TCAN1051VDRBTQ1
TCAN1051VDRQ1
SON
SOIC
SOIC
SON
SON
SOIC
SON
SON
SOIC
DRB
D
8
8
8
8
8
8
8
8
8
250
2500
2500
3000
250
200.0
356.0
340.5
346.0
200.0
340.5
346.0
200.0
340.5
183.0
356.0
338.1
346.0
183.0
336.1
346.0
183.0
336.1
25.0
35.0
20.6
35.0
25.0
25.0
35.0
25.0
25.0
D
DRB
DRB
D
2500
3000
250
DRB
DRB
D
2500
Pack Materials-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Jun-2023
TUBE
T - Tube
height
L - Tube length
W - Tube
width
B - Alignment groove width
*All dimensions are nominal
Device
Package Name Package Type
Pins
SPQ
L (mm)
W (mm)
T (µm)
B (mm)
TCAN1051DQ1
TCAN1051GDQ1
TCAN1051GVDQ1
TCAN1051HDQ1
TCAN1051HGDQ1
TCAN1051HGVDQ1
TCAN1051HVDQ1
TCAN1051VDQ1
D
D
D
D
D
D
D
D
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
8
8
8
8
8
8
8
8
75
75
75
75
75
75
75
75
507
507
507
507
507
507
507
507
8
8
8
8
8
8
8
8
3940
3940
3940
3940
3940
3940
3940
3940
4.32
4.32
4.32
4.32
4.32
4.32
4.32
4.32
Pack Materials-Page 5
PACKAGE OUTLINE
DRB0008F
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
S
C
A
L
E
3
0
.
A
SECTION A-A
TYPICAL
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
EXPOSED
THERMAL PAD
1.6 0.05
(0.2) TYP
4
5
A
A
2X
1.95
2.4 0.05
8
1
6X 0.65
0.35
0.25
8X
PIN 1 ID
0.5
0.3
0.1
C A B
C
8X
(OPTIONAL)
0.05
4222121/C 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
SYMM
8X (0.6)
1
8
8X (0.3)
(2.4)
(0.95)
6X (0.65)
4
5
(R0.05) TYP
(0.55)
(2.8)
(
0.2) VIA
TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222121/C 10/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRB0008F
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
METAL
TYP
8X (0.6)
8X (0.3)
1
8
(0.635)
SYMM
(1.07)
6X (0.65)
5
4
(R0.05) TYP
(1.47)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
82% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4222121/C 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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