TCAN11625-Q1 [TI]
TCAN1162x-Q1 Automotive CAN FD System Basis Chip with Sleep Mode and LDO Output;型号: | TCAN11625-Q1 |
厂家: | TEXAS INSTRUMENTS |
描述: | TCAN1162x-Q1 Automotive CAN FD System Basis Chip with Sleep Mode and LDO Output |
文件: | 总51页 (文件大小:2840K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
TCAN1162x-Q1 Automotive CAN FD System Basis Chip with Sleep Mode and LDO
Output
1 Features
3 Description
•
AEC Q100 (Grade 1) Qualified for automotive
applications
Meets the requirements of ISO 11898-2:2016
Functional Safety-Capable
– Documentation available to aid in functional
safety system design
Wide input operational voltage range
Integrated LDO for CAN transceiver supply
– 5-V LDO with 100 mA output current capability -
TCAN11625
The TCAN1162x-Q1 are high-speed controller area
network (CAN) system basis chips (SBC) that
meet the physical layer requirements of the ISO
11898-2:2016 high-speed CAN specification. The
TCAN1162x-Q1 supports both classical CAN and
CAN FD networks up to 8 megabits per second
(Mbps).
•
•
•
•
Both the TCAN11623-Q1 and TCAN11625-Q1 support
a wide input supply range and integrates some
form of an LDO output. The TCAN11625-Q1 has a
5-V LDO output (VCCOUT) which supplies the CAN
transceiver voltage internally as well as additional
current externally. The TCAN11623-Q1 has a 3.3-V
LDO output (VLDO3), supplied from the 5-V LDO,
supporting external loads.
– 3.3-V LDO with 70 mA output current capability
- TCAN11623
Classic CAN and CAN FD up to 8 Mbps
VIO level shifting supports: 1.7 V to 5.5 V
Operating modes
•
•
•
– Normal mode
– Standby mode
– Low-power sleep mode
High-voltage INH output for system power control
Local wake-up support via the WAKE pin
Defined behavior when unpowered
– Bus and IO terminals are high impedance (no
load to operating bus or application)
Protection features:
The TCAN1162x-Q1 allows for system-level
reductions in battery current consumption by
selectively enabling the various power supplies that
may be present on a system via the INH output pin.
This allows an ultra-low-current sleep state where
power is gated to all system components except for
the TCAN1162x-Q1, while monitoring the CAN bus.
When a wake-up event is detected, the TCAN1162x-
Q1 initiates system start-up by driving INH high.
•
•
•
•
– ±58-V CAN bus fault tolerant
– Load dump support on VSUP
– IEC ESD protection
– Under-voltage and over-voltage protection
– Thermal shutdown protection
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
TCAN11623-Q1
TCAN11625-Q1
VSON (14)
4.5 mm x 3.00 mm
– TXD dominant state timeout (TXD DTO)
Extra wide junction temperature support
Available in the leadless VSON (14) package
with wettable flank for improved automated optical
inspection (AOI) capability
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
•
EN
3.3V Voltage Regulator
(e.g. TPSxxxx)
VBAT
Motor Driver
2 Applications
0.1ꢀF
0.1ꢀF
10ꢀF
3.3kΩ
33kΩ
VSUP
10
VIO
VLDO5
5
3
•
•
•
•
Advanced driver assistance system (ADAS)
Body electronics and lighting
Automotive infotainment and cluster
Hybrid, electric and powertrain systems
0.1nF
9
7
WAKE
CANH
VIN
13
INH
TCAN11625
nSLP
TS
14
6
CAN FD
Controller
nRST
TXD
11
1
CANL
12
Optional:
Terminating
Node
RXD
4
Optional:
Filtering,
Transient and
ESD
2
GND
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Description (continued).................................................. 3
6 Pin Configurations and Functions (TCAN11625)..........4
7 Pin Configurations and Functions (TCAN11623)..........5
8 Specifications.................................................................. 6
8.1 Absolute Maximum Ratings........................................ 6
8.2 ESD Ratings............................................................... 6
8.3 ESD Ratings IEC Specification...................................6
8.4 Recomended Operating Conditions............................7
8.5 Thermal Information....................................................7
8.6 Power Supply Characteristics.....................................7
8.7 Electrical Characteristics.............................................9
8.8 Switching Characteristics..........................................11
8.9 Typical Characteristics..............................................13
9 Parameter Measurement Information..........................14
10 Detailed Description....................................................18
10.1 Overview.................................................................18
10.2 Functional Block Diagram.......................................18
10.3 Feature Description.................................................20
10.4 Device Functional Modes........................................25
11 Application Information.............................................. 36
11.1 Application Information Disclaimer..........................36
11.2 Typical Application.................................................. 36
11.3 Application Curves.................................................. 38
12 Power Supply Requirements......................................39
13 Layout...........................................................................40
13.1 Layout Guidelines................................................... 40
13.2 Layout Example...................................................... 40
14 Device and Documentation Support..........................42
14.1 Documentation Support.......................................... 42
14.2 Receiving Notification of Documentation Updates..42
14.3 Support Resources................................................. 42
14.4 Trademarks.............................................................42
14.5 Electrostatic Discharge Caution..............................42
14.6 Glossary..................................................................42
15 Mechanical, Packaging, and Orderable
Information.................................................................... 42
4 Revision History
Changes from Revision * (May 2021) to Revision A (November 2021)
Page
•
Changed the document status from Advanced Information to Production data................................................. 1
Copyright © 2021 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
5 Description (continued)
This allows an ultra-low-current sleep state in which power is gated to all system components except for the
TCAN1162x-Q1, which remains in a low-power state while monitoring the CAN bus. When a wake-up event is
detected, the TCAN1162x-Q1 initiates node start-up by driving INH high.
The TCAN1162x-Q1 supports an ultra low-power standby mode where the high-speed transmitter and normal
receiver are switched off and a low-power wake-up receiver enables remote wake-up via the ISO 11898-2:2016
defined wake-up pattern (WUP).
The TCAN1162x-Q1 includes internal logic level translation via the VIO terminal to allow for interfacing directly to
1.8-V, 2.5-V, 3.3-V, or 5-V controllers. The transceiver includes many protection and diagnostic features including
undervoltage detection, over voltage detection, thermal shutdown (TSD), driver dominant timeout (TXD DTO),
and bus fault protection up to ±58-V.
The TCAN1162x-Q1 allows for system-level reductions in battery current consumption by selectively enabling
the various power supplies that may be present on a node via the INH output pin. This allows an ultra-low-
current sleep state in which power is gated to all system components except for the TCAN1162x-Q1, which
remains in a low-power state while monitoring the CAN bus. When a wake-up pattern is detected on the bus or
when a local wake-up is requested via the WAKE input, the TCAN1162x-Q1 initiates node start-up by driving INH
high.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
6 Pin Configurations and Functions (TCAN11625)
TXD
1
2
3
4
5
6
7
14
13
12
11
10
9
nSLP
CANH
CANL
nRST
VSUP
GND
VCCOUT
RXD
VIO
Thermal
Pad
TS
WAKE
NC
INH
8
Not to scale
Figure 6-1. DMT Package, 14 Pin (VSON), Top View
Table 6-1. Pin Functions
PINS
TYPE
DESCRIPTION
NAME
TXD
NO.
1
Digital
GND
CAN transmit data input, integrated pull-up
GND
VCCOUT
RXD
VIO
2
Ground connection
3
Supply
Digital
Supply
Digital
5-V LDO regulated output voltage pin and transceiver supply
CAN receive data output, tri-state when VIO < UVVIO
IO supply voltage
4
5
TS
6
Transceiver status
INH
7
High Voltage Inhibit pin to control system voltage regulators and supplies, high voltage
Internally connected, leave floating or connect to GND
High Voltage Local WAKE input terminal, high voltage
NC
8
—
WAKE
VSUP
nRST
CANL
CANH
nSLP
9
10
11
12
13
14
Supply
Digital
Bus IO
Bus IO
Digital
High voltage supply from the battery
Reset input/output
Low level CAN bus input/output line
High level CAN bus input/output line
Sleep mode control input, integrated pull-down
Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB)
ground plane for thermal relief
Thermal Pad
—
Copyright © 2021 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
7 Pin Configurations and Functions (TCAN11623)
TXD
1
2
3
4
5
6
7
14
13
12
11
10
9
nSLP
GND
CANH
CANL
nRST
VSUP
ꢀ
ꢀ
VFLT
RXD
VIO
Thermal
Pad
TS
WAKE
VLDO3
INH
8
Not to scale
Figure 7-1. DMT Package, 14 Pin (VSON), Top View
Table 7-1. Pin Functions
PINS
TYPE
DESCRIPTION
NAME
TXD
NO.
1
Digital Input
GND
CAN transmit data input, integrated pull-up
Ground connection
GND
VFLT
2
3
Supply
5-V LDO transceiver filter pin. Place a 10 µF capacitor on this pin to ground.
CAN receive data output, tri-state when VIO < UVVIO
IO supply voltage
RXD
VIO
4
Digital Output
Supply
5
TS
6
Digital
Transceiver status
INH
7
High Voltage
Supply
Inhibit pin to control system voltage regulators and supplies, high voltage
3.3-V LDO regulated output voltage pin
Local WAKE input terminal, high voltage
High voltage supply from the battery
Reset input/output
VLDO3
WAKE
VSUP
nRST
CANL
CANH
nSLP
8
9
High Voltage
Supply
10
11
12
13
14
Digital
Bus IO
Low level CAN bus input/output line
Bus IO
High level CAN bus input/output line
Sleep mode control input, integrated pull-down
Digital
Thermal
Pad
Electrically connected to GND, connect the thermal pad to the printed circuit board (PCB) ground
plane for thermal relief
—
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8 Specifications
8.1 Absolute Maximum Ratings
over operating virtual junction temperature range (unless otherwise noted)(1)
MIN
–0.3
-0.3
-0.3
–0.3
–0.3
–58
MAX
UNIT
V
VSUP
Supply voltage range
42
VFLT
Transceiver supply voltage
5 V regulated output
6
V
VCCOUT
VLDO3
6
V
3.3 V regulated output
4.5
V
VIO
IO level shifting voltage range
CAN bus IO voltage range (CANH, CANL)
WAKE input pin voltage range
INH output pin voltage range
Logic input terminal voltage range
Logic output terminal voltage range
Logic output current
6
V
VBUS
58
V
VWAKE
VINH
–18
42 and VI ≤ VSUP + 0.3
V
–0.3
–0.3
–0.3
42 and VO ≤ VSUP + 0.3
V
V(Logic_Input)
V(Logic_Output)
IO(LOGIC)
IO(INH)
6
6
8
6
V
V
mA
mA
INH output current
Wake current if due to ground shifts V(WAKE) ≤ V(GND) – 0.3 V, thus the
current into WAKE must be limited via an external serial resistor
IO(WAKE)
3
mA
TJ
Operating virtual junction temperature range
Storage temperature
–40
-65
150
165
°C
°C
TSTG
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
8.2 ESD Ratings
VALUE
UNIT
HBM classification level 3A for all
pin
±4000
Human body model (HBM), per AEC
Q100-002(1)
HBM classification level 3A for
VSUP, WAKE, INH
±8000
±10000
±750
V(ESD)
Electrostatic discharge
V
HBM classification level 3B for
global pins CANH & CANL
Charged-device model (CDM), per AEC Q100-011
CDM classification level C5 for all pins
(1) AEC-Q100-002 indicates that HBM stresses shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
8.3 ESD Ratings IEC Specification
VALUE
UNIT
CAN bus terminals (CANH & CANL) to
±8000
System level electro-static
discharge (ESD)(1)
IEC 61000-4-2 (150pF, 330Ω)
unpowered contact discharge
GND
VESD
VSUP and WAKE
±8000
–100
75
Pulse 1
V
Pulse 2
ISO 7637 ISO pulse transients(2)
ISO 7637-3 transient(3)
CAN bus terminals (CANH & CANL) to
GND, VSUP and WAKE
VTRAN
Pulse 3a
–150
100
Pulse 3b
DCC slow transient pulse
±30
(1) Tested according to IEC 62228-3 CAN Transceiver, Section 6.4; DIN EN 61000-4-2
(2) Tested according to IEC 62228-3 CAN Transceiver, Section 6.3; standard pulse parameters defined in ISO 7637-2
(3) Tested according to ISO 7637-3; electrical transient transmission by capacitive and inductive coupling via lines other than supply line
Copyright © 2021 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.4 Recomended Operating Conditions
MIN
5.5
1.7
–2
NOM
MAX UNIT
VSUP
Supply voltage range
28
V
VIO
IO supply voltage
5.5
V
IOH(DO)
IOL(DO)
IO(INH)
CVSUP
CVCCOUT
CFLT
Digital output terminal high level output current
Digital output terminal low level output current
INH output current
mA
mA
mA
µF
µF
µF
µF
°C
°C
°C
2
1
VSUP pin capacitance
0.1
VCCOUT pin capacitance TCAN11625
Filter pin capacitance TCAN11623
VLDO3 pin capacitance TCAN11623
Thermal shutdown rising
10
10
CLDO3
TSDR
1
4.7
180
165
15
10
175
TSDF
Thermal shutdown falling
170
THYS
Thermal shutdown hysterisis
8.5 Thermal Information
DMT (VSON)
THERMAL METRIC(1)
UNIT
14 PINS
37.7
37.9
14.2
0.7
RΘJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RΘJC(top)
RΘJB
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ΨJB
14.2
4.9
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
8.6 Power Supply Characteristics
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Supply Voltage and Current
TXD = 0 V, RL = 60 Ω, CL = open
See Figure 9-2
60
70
mA
mA
Supply current
Bus biasing active: dominant
Transceiver only
TXD = 0 V, RL = 50 Ω, CL = open
See Figure 9-2
ISUP
Supply current
Bus biasing active: recessive
Transceiver only
TXD = VIO, RL = 50 Ω, CL = open
See Figure 9-2
3
255
150
50
mA
µA
µA
µA
µA
Supply current TCAN11623
Standby mode
Bus biasing autonomous: inactive
5.5 V < VSUP ≤ 19 V
See Figure 9-2
ISUP(STB)
ISUP(STB)
ISUP(SLP)
ISUP(SLP)
Supply current TCAN11625
Standby mode
Bus bias autonomous: inactive
5.5 V < VSUP ≤ 19 V
See Figure 9-2
Supply current
Sleep mode
Bus bias autonomous: inactive
nSLP = 0 V, 5.5 V < VSUP ≤ 19 V
TA > 85℃
See Figure 9-2
Supply current
Sleep mode
Bus bias autonomous: inactive
nSLP = 0 V, 5.5 V < VSUP ≤ 19 V
TA ≤ 85℃
See Figure 9-2
40
Supply current
5.5 V < VSUP ≤ 28 V
See Figure 9-2
ISUP(BIAS)
UVSUPR
60
µA
V
Bus bias autonomous: active(1)
Under voltage VSUP threshold rising
Ramp Up
4.05
4.42
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.6 Power Supply Characteristics (continued)
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
UVSUPF
IIO
Under voltage VSUP threshold falling
Ramp Down
3.9
4.25
V
IO Supply Current
Normal mode
RXD floating, TXD = 0 V
RXD floating, TXD = VIO
RXD floating, TXD = VIO
nSLP = 0 V
150
12
µA
µA
µA
µA
IO Supply Current - TCAN11625
Normal, or Standby
IIO
IIO
IIO
IO Supply Current - TCAN11623
Normal, or Standby
12.5
IO Supply Current
Sleep mode (TJ ≤ 125℃)
10
UVIOR
Under voltage VIO threshold rising
Under voltage VIO threshold falling
Hysteresis voltage on UVVIO
Ramp Up
1.4
1.25
80
1.65
V
V
UVIOF
Ramp Down
1
VHYS(UVIO)
40
160
mV
VFLT /VLDO3 VCCOUT Characteristics
VFLT
CAN regulator filter pin
VSUP = 5.5 to 28 V
4.9
4.9
5.1
5.1
V
V
VSUP = 5.5 to 18 V
IL = 0 to 100 mA
TXD = VIO
VCCOUT
5 V regulated output
5 V regulated output
VSUP = 5.65 to 18 V
IL = 0 to 175 mA
TXD = VIO
VCCOUT
4.9
4.9
5.1
V
VSUP = 5.65 to 18 V
IL = 0 to 100 mA
TXD = 0 V; VCANH = 0 V
VCCOUT
5 V regulated output
Dropout voltage
5.1
650
3.4
V
mV
V
VCCOUT_DROP
VLDO3
5 V LDO, VSUP – VCCOUT, IL = 125 mA
300
VSUP = 5.5 to 18 V
ILDO = 0 to 70 mA
3.3 V regulated output
3.2
TXD = 0 V; VCANH = 0 V
∆VLDO3(∆VSUP)
∆VCCOUT(∆VSUP)
∆VLDO3(∆VSUPL)
∆VCCOUT(∆VSUPL)
UVFLTR
Line regulation
VSUP = 5.5 to 28 V, ΔVLDO, ILDO = 10 mA
VSUP = 5.5 to 28 V, IL = 10 mA, ΔVCCOUT
ILDO = 1 to 70 mA, VSUP = 14 V, ΔVLDO
IL = 1 to 125 mA, VSUP = 14 V, ΔVCCOUT
Ramp Up
50
50
mV
mV
mV
mV
V
Line regulation
Load regulation
50
Load regulation
50
Under voltage VFLT threshold rising
Under voltage VFLT threshold falling
Under voltage VCCOUT threshold rising
Under voltage VCCOUT threshold falling
Under voltage VLDO3 threshold rising
Under voltage VLDO3 threshold falling
Over voltage VFLT threshold rising
Over voltage VFLT threshold falling
Over voltage VCCOUT threshold rising
Over voltage VCCOUT threshold falling
Over voltage VLDO3 threshold rising
Over voltage VLDO3 threshold falling
Output current limit
4.6
4.45
4.6
4.75
UVFLTF
Ramp Down
4.2
4.2
V
UVVCCOUTR
UVVCCOUTF
UVLDO3R
Ramp Up
4.75
3.1
V
Ramp Down
4.45
2.9
V
Ramp Up
V
UVLDO3F
Ramp Down
2.5
2.75
5.7
V
OVFLTR
Ramp Up
6.15
6.15
3.93
V
OVFLTF
Ramp Down
5.47
5.47
5.65
5.7
V
OVCCOUTR
OVCCOUTF
OVLDO3R
Ramp Up
V
Ramp Down
5.65
3.8
V
Ramp Up
V
OVLDO3F
Ramp Down
3.6
175
90
3.7
V
IL_VCCOUT
IL_LDO3
VCCOUT short to ground
VLDO3 short to ground
275
160
mA
mA
Output current limit
VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100 Hz,
CO = 10 μF
PSRRVCCOUT
PSRRLDO3
Power supply rejection ripple rejection
Power supply rejection ripple rejection
60
37
dB
dB
VRIP = 0.5 VPP, Load = 10 mA, ƒ = 100 Hz,
CO = 4.7 μF
(1) After a valid wake-up the total ISUP current is the sum of ISUP(STB) and ISUP(BIAS) (ISUP = ISUP(STB) + ISUP(BIAS)
)
Copyright © 2021 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.7 Electrical Characteristics
Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
CAN Driver Electrical Characteristics
Dominant output voltage
TEST CONDITIONS
MIN
TYP
MAX UNIT
CANH
CANL
2.75
0.5
2
4.5
2.25
3
V
V
V
TXD = 0 V, 50 ≤ RL ≤ 65 Ω, CL = open, RCM
=
Bus biasing active
VO(D)
open
Dominant output voltage
See Figure 9-2
Bus biasing active
Recessive output voltage
Bus biasing active
TXD = VIO, RL = open (no load), RCM = open
See Figure 9-2
VO(R)
Driver symmetry
nSLP = VIO, RL = 60 Ω, CSPLIT = 4.7 nF, CL =
Bus biasing active
(VO(CANH) + VO(CANL) ) / VCCOUT
(VO(CANH) + VO(CANL) ) / VFLT
Open, RCM = Open, TXD = 250 kHz, 1 Mhz,
2.5 MHz
See Figure 9-2
VSYM
0.9
1.1
V/V
mV
DC Driver symmetry
Bus biasing active
VCCOUT – VO(CANH) – VO(CANL)
VFLT – VO(CANH) – VO(CANL)
nSLP = VIO, RL = 60 Ω, CL = open
See Figure 9-2
VSYM_DC
VOD(DOM)
VOD(REC)
–400
400
Differential output voltage
Bus biasing active
Dominant
nSLP =VIO, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL =
open
See Figure 9-2
CANH - CANL
1.5
1.4
1.5
3
3.3
5
V
V
V
Differential output voltage
Bus biasing active
Dominant
nSLP = VIO, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL
= open
See Figure 9-2
CANH - CANL
CANH - CANL
Differential output voltage
Bus biasing active
Dominant
nSLP = VIO, TXD = 0 V, RL = 2240 Ω, CL
open
See Figure 9-2
=
=
Differential output voltage
Bus biasing active
Bus biasing inactive
Recessive
nSLP = VIO, TXD = VIO, RL = open Ω, CL
CANH - CANL
open
See Figure 9-2
–50
50
mV
nSLP =0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 9-2
CANH
-0.1
-0.1
-0.2
–75
0.1
0.1
0.2
V
V
Pin output voltage
Bus biasing inactive
VO(INACT)
VOD(STB)
IOS(DOM)
IOS(REC)
nSLP =0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 9-2
CANL
nSLP =0 V, TXD = VIO
RL = open (no load), CL = open
See Figure 9-2
Differential output voltage
Bus biasing inactive
CANH - CANL
V
Short-circuit steady-state output current
Bus biasing active
nSLP = VIO, TXD = 0 V
-15 V ≤ V(CANH) ≤ 40 V
See Figure 9-2 and Figure 9-8
mA
mA
mA
Dominant
Short-circuit steady-state output current
Bus biasing active
nSLP = VIO, TXD = 0 V
-15 V ≤ V(CANL) ≤ 40 V
See Figure 9-2 and Figure 9-8
75
3
Dominant
Short-circuit steady-state output current
Bus biasing active
nSLP = VIO, VBUS = CANH = CANL
-27 V ≤ VBUS ≤ 42 V
–3
Recessive
See Figure 9-2 and Figure 9-8
CAN Receiver Electrical Characteristics
Receiver dominant state input voltage range
VIT(DOM)
0.9
-3
8
V
V
Bus biasing active
nSLP = VIO, -12 V ≤ VCM ≤ 12 V
See Figure 9-3 and Table 10-6
Receiver recessive state input voltage range
Bus biasing active
VIT(REC)
0.5
Hysteresis voltage for input threshold
Bus biasing active
nSLP = VIO
See Figure 9-3 and Table 10-6
VHYS
80
-5
140
mV
V
VDIFF(MAX)
VDIFF(DOM)
VDIFF(REC)
VCM
Maximum rating of VDIFF
10
8
Receiver dominant state input voltage range
Bus biasing inactive
1.150
V
nSLP = 0 V, -12 V ≤ VCM ≤ 12 V
See Figure 9-3 and Table 10-6
Receiver recessive state input voltage range
Bus biasing inactive
-3
0.4
12
V
V
nSLP = VIO
See Figure 9-3 and Table 10-6
Common mode range
–12
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.7 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Power-off (unpowered) bus input leakage
current
IOFF(LKG)
CI
VSUP = 0 V, CANH = CANL = 5 V
2.5
20
µA
pF
Input capacitance to ground (CANH or CANL)
TXD = VIO
TXD = VIO
(1)
CID
RID
RIN
Differential input capacitance(1)
Differential input resistance
10
100
50
pF
kΩ
kΩ
50
25
TXD = VIO, nSLP = 5 V
-12 V ≤ VCM ≤ 12 V
Input resistance (CANH or CANL)
Input resistance matching:
[1 – RIN(CANH) / RIN(CANL)] × 100%
RIN(M)
V(CANH) = V(CANL) = 5 V
–1
1
%
TXD Input Characteristics
VIH
High level input voltage
0.7
VIO
VIO
µA
µA
kΩ
µA
pF
VIL
Low level input voltage
High level input leakage current
Low level input leakage current
Pull-up resistance
0.3
1
IIH
TXD = VIO = 5.5 V
–1
–130
40
0
IIL
TXD = 0 V, VIO = 5.5 V
–15
80
1
RPU
ILKG(OFF)
CI
60
0
Unpowered leakage current
Input Capacitance
TXD = 5.5 V, VSUP = VIO = 0 V
–1
VIN = 0.4 x sin(2 × π × 2 × 106 × t) + 2.5 V
5
RXD Output Characteristics
VOH
High level output voltage
IO = –2 mA.
IO = 2 mA.
0.8
VIO
VIO
kΩ
µA
VOL
Low level output voltage
Pull-up resistance
0.2
80
5
RPU
40
-5
60
ILKG(OFF)
Unpowered leakage curret
RXD = 5.5 V, VSUP = VIO = 0 V
nSLP Input Characteristics
VIH
High level input voltage
0.7
VIO
VIO
µA
µA
kΩ
µA
VIL
Low level input voltage
0.3
130
1
IIH
High level input leakage current
Low level input leakage current
Pull-down resistance
nSLP = VIO = 5.5 V
50
–1
40
–1
IIL
nSLP = 0 V, VIO = 5.5 V
RPD
ILKG(OFF)
60
0
80
1
Unpowered leakage current
nSLP = 5.5 V, VIO = 0 V
INH Output Characteristics
High level voltage drop INH with respect to
VSUP
ΔVH
IINH = –6 mA
INH = 0 V
0.5
1
V
ILKG(INH)
Sleep mode leakage current
–0.5
4
0.5
µA
WAKE Input Characteristics
VIH
VIL
High-level input voltage
V
V
Sleep mode
WAKE = 1 V
Low-level input voltage
Low level input leakage current
Input hysteresis
2
3
IIL
µA
mV
VHYS
800
0.8
0.8
1200
nRST Bidirectional Characteristics
VIH
VIL
High level input voltage
VCCOUT
Low level input voltage
0.2 VCCOUT
VLDO3
VIH
VIL
High level input voltage
Low level input voltage
0.2 VLDO3
0.2 VCCOUT
0.2 VLDO3
VOL
VOL
IIH
Low level output voltage (TCAN11625)
Low level output voltage (TCAN11623)
High level input leakage current
Pull-up resistance to VLDO
IO = 2 mA.
IO = 2 mA.
–1
0
1
µA
kΩ
RPU
160
240
320
TS Output Characteristics
VOH High-level output voltage
IO = -2 mA
0.8
VIO
Copyright © 2021 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.7 Electrical Characteristics (continued)
Over recommended operating conditions with TJ = –40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
Low-level output voltage
Unpowered leakage current
TEST CONDITIONS
MIN
TYP
MAX UNIT
VOL
IO = 2 mA
TS = 5.5 V, VIO = 0 V
0.2
1
VIO
µA
ILKG(OFF)
–1
0
(1) Test according to ISO 11898-2:2003
8.8 Switching Characteristics
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
Supply Switching Characteristics
CFLT = 10 µF
CVCCOUT = 10 µF
CLDO3 = 4.7 µF
See Figure 9-9
See Figure 9-10
tPOWER_UP
CAN supply power up time
1.8
4
ms
tUV(SUP)
tUV(FLT)
VSUP filter time (rising and falling)
4
4
25
25
µs
µs
Undervoltage detection delay timeCAN active to CAN autonomous: active or inactive
Time for device to enter sleep
tUV(LDO)
tUVIO
VLDO filter time (rising and falling)
VIO filter time (rising and falling)
state reset state once UVLDO is
reached
30
10
µs
µs
8
12
Device Switching Characteristics
tUVIO(SLP) Undervoltage detection delay time standby mode to sleep mode
tUV(nRST)
200
350
50
1.8
2
ms
µs
µs
ms
s
Undervoltage detection delay time nRST low
Bus time to meet filtered bus requirments for wakeup request
Bus wakeup timeout value
tWK_FILTER
tWK_TIMEOUT
tSILENCE
0.5
0.8
See Figure 10-7
Time out for bus inactivity
0.9
4
1.2
5
tINACTIVE
Hardware timer for failsafe and power up inactivity(1)
3
min
Time from the start of a dominant-recessive-dominant sequence
until Vsym ≥ 0.1
Each phase: 6 μs
See Figure 9-12
tBIAS
250
µs
us
ns
VFLT > UVFLT(R)
VCCOUT > UVVCCOUT(R)
VIO > UVIO(R)
tCAN(ACTIVE)
Time from swtiching to CAN active mode to TS pin transitioning high
25
nSLP = VIO
Total loop delay, driver input (TXD) to receiver output (RXD)
Recessive to dominant
tPROP(LOOP1)
tPROP(LOOP2)
tnSLP(fltr)
100 160
RL = 60 Ω, CL = 100 pF, CL(RXD)
15 pF
See Figure 9-6
=
Total loop delay, driver input (TXD) to receiver output (RXD)
Dominant to recessive
120 175
ns
µs
µs
µs
nSLP pin filter time
Sleep pin filter time
2.5
20
7.5
35
50
Low time required on nSLP to
enter sleep mode
tSLP
Mode change time
tmode_slp_reset
WUP or LWU event to INH asserted high, see
Driver Switching Characteristics
tpHR
tpLD
tsk(p)
tR
Propagation delay time, high TXD to driver recessive
20
15
35
40
10
40
45
70
70
20
ns
ns
ns
ns
ns
Propagation delay time, low TXD to driver dominant
Pulse skew (|tpHR - tpLD|)
RL = 60 Ω, CL = 100 pF, RCM
open
See Figure 9-2
=
Differential output signal rise time
Differential output signal fall time
tF
RL = 60 Ω, CL = open
See Figure 9-7, TXD = 0 V
tTXD_DTO
Dominant timeout
1.2
3.8
ms
Receiver Switching Characteristics
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.8 Switching Characteristics (continued)
Over recomended operating conditions with TJ = -40°C to 150°C, unless otherwise noted. All typical values are taken at
25°C, VSUP = 12 V, VIO = 3.3 V and RL = 60 Ω
PARAMETER
TEST CONDITIONS
MIN
TYP MAX UNIT
tpRH
tpDL
tR
Propagation delay time, bus recessive input to high RXD
Propagation delay time, bus dominant input to RXD low output
Output signal rise time (RXD)
25
80 140
ns
ns
ns
ns
20
50
8
110
CL(RXD) = 15 pF
See Figure 9-3
tF
Output signal fall time (RXD)
5
WAKE Characteristics
tWAKE Time required for INH pin to go high after an local wake event occurs on the WAKE pin
nRST Characteristics
40
µs
tnRST
Minimum low time for reset
Input pulse width
Cold crank
15
20
1
µs
ms
ms
tnRST(cold)
tnRST(warm)
Output pulse width
Output pulse width
27
Warm crank
1.5
CAN FD Timing Characteristics
Bit time on CAN bus output pins with tBIT(TXD)
=
=
=
=
=
=
435
155
80
530
210
140
530
215
140
ns
ns
ns
ns
ns
ns
500 ns
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
Bit time on CAN bus output pins with tBIT(TXD)
200 ns
tBIT(BUS)
VIO > 1.8V
Bit time on CAN bus output pins with tBIT(TXD)
125 ns
Bit time on CAN bus output pins with tBIT(TXD)
500 ns
435
155
80
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
Bit time on CAN bus output pins with tBIT(TXD)
200 ns
tBIT(BUS)
VIO ≤ 1.8V
Bit time on CAN bus output pins with tBIT(TXD)
125 ns
Bit time on RXD output pins with tBIT(TXD) = 500 ns
Bit time on RXD output pins with tBIT(TXD) = 200 ns
Bit time on RXD output pins with tBIT(TXD) = 125 ns
Receiver timing symmetry with tBIT(TXD) = 500 ns
Receiver timing symmetry with tBIT(TXD) = 200 ns
Receiver timing symetry with tBIT(TXD) = 125 ns
400
120
80
550
220
135
40
ns
ns
ns
ns
ns
ns
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
tBIT(RXD)
RL = 60 Ω, CL = 100 pF
CL(RXD) = 15 pF
ΔtREC = tBIT(RXD) - tBIT(BUS)
See Figure 9-6
-65
-45
-40
ΔtREC
15
10
(1) Timer is reset when the CAN bus changes states.
Copyright © 2021 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
8.9 Typical Characteristics
112
108
104
100
96
26
25.5
25
-40 C
30 C
150 C
-40 C
25 C
125 C
150 C
24.5
24
92
23.5
23
88
84
22.5
22
80
4
8
12
16
VSUP (V)
20
24
CLRXD = 15 pF
28
4
8
12
16
VSUP (V)
20
24
28
RL = 60 Ω
CL = 100 pF
RL = 60 Ω
Figure 8-1. tPROP(LOOP1) over VSUP
Figure 8-2. ISUP over VSUP Sleep Mode
3
-40 C
50 C
150 C
2.75
2.5
2.25
2
1.75
1.5
4
6
8
10 12 14 16 18 20 22 24 26 28
VSUP (V)
RL = 60 Ω
Figure 8-3. VOD(DOM) over VSUP
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
9 Parameter Measurement Information
CANH
TXD
RL
CL
CANL
Figure 9-1. ISUP Test Circuit
RCM
CANH
50%
50%
TXD
TXD
RL
CL
VOD
VCM
VCC
VO(CANH)
tpLD
tpHR
90%
10%
0V
CANL
RCM
0.9V
VO(CANL)
VOD
0.5V
tR
tF
Figure 9-2. Driver Test Circuit and Measurement
CANH
1.5V
0.9V
VID
IO
RXD
0.5V
0V
VID
tpDL
tpRH
VOH
VO
CL_RXD
CANL
90%
VO(RXD)
50%
10%
VOL
tF
tR
Figure 9-3. Receiver Test Circuit and Measurement
Copyright © 2021 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
UVLDO5
(see NOTE A)
nRST
VLDO5
(see NOTE A)
tnRST(warm)
Figure 9-5. tnRST Warm Start
nRST
tnRST(cold)
NOTE A: VFLT & UVFLTR for TCAN11623.
Figure 9-4. tnRST Cold Start
TXD
VI
70%
tLOOP2
30%
30%
CANH
0V
TXD
5 x tBIT(TXD)
tBIT(TXD)
VI
RL
CL
CANL
tBIT(Bus)
nSLP
0V
900mV
500mV
RXD
VDIFF
VO
CL_RXD
RXD
VOH
70%
30%
VOL
tBIT(RXD)
Figure 9-6. Transmitter and Receiver Timing Behavior Test Circuit and Measurement
VIH
CANH
TXD
TXD
0V
RL
CL
VOD
VOD(D)
CANL
0.9V
VOD
0.5V
0V
tTXD_DTO
Figure 9-7. TXD Dominant Timeout Test Circuit and Measurement
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
200 ꢀs
IOS
CANH
TXD
VBUS
IOS
CANL
VBUS
VBUS
0V
or
0V
VBUS
VBUS
Figure 9-8. Driver Short-Circuit Current Test and Measurement
VSUP
4.5V
VFLT
CFLT = 10
F
VSUP
0 V
TCAN11623
VSUP
tPOWER_UP
CVSUP
VLDO3
CLDO3 = 4.7
VLDO3
VO
90%
F
0 V
Figure 9-9. TCAN11623 tPOWER_UP Timing Measurement
Copyright © 2021 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
VSUP
4.5V
VCCOUT
CVCCOUT = 10
F
VSUP
0 V
TCAN11625
VSUP
tPOWER_UP
CVSUP
VCCOUT
90%
VO
0 V
Figure 9-10. TCAN11625 tPOWER_UP Timing Measurement
VIH (WAKE Input)
VIL (WAKE Input)
VWAKE
VWAKE
VSUP
INH
0V
CVSUP
OR
tWAKE
TCAN1162x
tWAKE
VWAKE
INH = high
INH = high
VSUP -1V
INH
VSUP -1V
INH
Figure 9-11. tWAKE While Monitoring INH Output
Figure 9-12. Test Signal Definition for Bias Reaction Time Measurement
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10 Detailed Description
10.1 Overview
The TCAN1162x-Q1 are high speed controller area network (CAN) system basis chips (SBC) that meet the
physical layer requirements of the ISO 11898-2:2016 high speed CAN specification. The TCAN1162x-Q1
supports both classical CAN and CAN FD networks up to 8 megabits per second (Mbps).
Both the TCAN11623-Q1 and TCAN11625-Q1 support a wide input supply range and integrates some form of an
LDO output. The TCAN11625-Q1 has a 5-V LDO output (VCCOUT) which supplies the CAN transceiver voltage
internally as well as additional current externally. The TCAN11623-Q1 has a 3.3-V LDO output (VLDO3), supplied
from the 5-V LDO, supporting external loads.
The TCAN1162x-Q1 allows for system-level reductions in battery current consumption by selectively enabling
the various power supplies that may be present on a system via the INH output pin. This allows an ultra-low-
current sleep state where power is gated to all system components except for the TCAN1162x-Q1, while
monitoring the CAN bus. When a wake-up event is detected, the TCAN1162x-Q1 initiates system start-up by
driving INH high.
10.2 Functional Block Diagram
VIO
VSUP
10
VLDO 5V
VCCOUT
3
5
VIO
1
DOMINANT
TIME OUT
TXD
INH
VSUP
13
12
CANH
CANL
7
9
VSUP
Driver
WAKE
nSLP
TS
WAKE
14
6
CONTROL and MODE
LOGIC
OVER
TEMP
VCCOUT
UNDER
VOLTAGE
11
nRST
RXD
High Speed Receiver
Low Power Receiver
VIO
4
Logic Output
MUX
WUP
Detect
2
GND
Figure 10-1. TCAN11625-Q1
Copyright © 2021 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
VIO
VSUP
10
VLDO 5V
VFLT
VLDO3
8
3
5
VIO
1
DOMINANT
TIME OUT
TXD
INH
VSUP
13
CANH
VLDO
3.3V
7
9
VSUP
Driver
WAKE
nSLP
TS
WAKE
12
CANL
14
6
CONTROL and MODE
LOGIC
OVER
TEMP
VLDO3
UNDER
VOLTAGE
11
nRST
RXD
High Speed Receiver
Low Power Receiver
VIO
4
Logic Output
MUX
WUP
Detect
2
GND
Figure 10-2. TCAN11623-Q1
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.3 Feature Description
10.3.1 VSUP Pin
This pin is connected to the battery supply. It provides the supply to the internal regulators that support the digital
core, the CAN transceiver, the output regulator, and the low power CAN receiver.
10.3.2 VCCOUT Pin
An internal LDO provides power for the integrated CAN transceiver and the VCCOUT output pin. The amount
of current that can be delivered externally is dependent upon the CAN transceiver requirements during normal
operation as well as the ambient operating temperature. When a CAN bus fault takes place that requires
additional current from the LDO, the total available current to external load components may be degraded.
During sleep mode the LDO is disabled and no current can be delivered. Once the device leaves sleep mode
and enters other active modes the LDO is enabled for normal operation. This pin requires a 10 μF external
capacitor as close to the pin as possible.
10.3.3 VFLT Pin
An internal LDO provides power for the integrated CAN transceiver. While in sleep mode the LDO is disabled.
Once the device leaves sleep mode and enters other active modes the LDO is enabled for normal operation.
This pin requires a 10 μF external capacitor as close to the pin as possible.
10.3.4 VLDO3 Pin
An internal LDO provides a 3.3 V output for supplying power to external devices. During sleep mode the LDO
is disabled and no current can be delivered. Once the device leaves sleep mode and enters other active modes
the LDO is enabled for normal operation. This pin requires a 4.7 μF external capacitor as close to the pin as
possible.
10.3.5 Digital Inputs and Outputs
The TCAN1162x-Q1 has a VIO supply that is used to set the digital input thresholds. The input thresholds are
ratio metric to the VIO supply using CMOS input levels, making them scalable for CAN controllers with digital IOs
from 1.7 V to 5.5 V. The TXD input is biased to the VIO level to force a recessive input in case the pin floats. The
high level output voltage for the RXD and TS output pins is driven to the VIO level as logic-high outputs.
10.3.5.1 TXD Pin
TXD is a digital signal, referenced to VIO, from a CAN controller to the TCAN1162x-Q1.
10.3.5.2 RXD Pin
RXD is a digital signal, referenced to VIO, from the TCAN1162x-Q1 to a CAN controller. This pin is only driven
once VIO is present.
10.3.5.3 TS Pin
The transceiver status, TS, output pin is used to indicate to the status of the CAN transceiver to the controller.
When the TCAN1162x-Q1 is in normal mode with no TXD DTO fault the TS pin is driven high. The TS pin is
driven low signaling to the controller that the TCAN1162x-Q1 is not ready for normal operation.
The TS output will be driven low if the following conditions exist:
•
•
TXD driven dominant for t ≥ tTXD_DTO
TJ ≥ TSDR
The TS output is tri-stated if the following conditions exist:
VIO < UVVIOF
The TCAN11625 TS output will be driven low if the following conditions exist:
•
•
•
VLDO5 < UVLDO5F
VLDO5 > OVLDO5R
The TCAN11623 TS output will be driven low if the following conditions exist:
Copyright © 2021 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
•
•
•
•
VFLT < UVVFLTF
VLDO3 < UVLDO3F
VLDO3 > OVLDO3R
VFLT > OVVFLTR
10.3.6 Digital Control and Timing
This device is a 14 pin CAN FD transceiver/SBC. Timings are all mixed signal and are covered at the device
electrical specification level including the small amounts of control logic for this device. All device mode control
is done via one digital input, nSTB or nSLP and through the use of timers and fault conditions internal to the
device.
10.3.7 VIO Pin
The VIO pin provides the digital IO voltage to match the controller's IO voltage thus avoiding the requirements for
an ecternal level shifter. The integrated level shifter supports voltages from 1.7 V to 5.5 V providing the widest
range of controller support.
10.3.8 GND
GND is the ground pin and it must be connected to the PCB ground.
10.3.9 INH Pin
The TCAN1162x-Q1 inhibit (INH) output pin can be used to control the enable of system power management
devices allowing for a significant reduction in battery quiescent current consumption while the application is in
sleep mode. The INH pin has two states: driven high and high impedance. When the INH pin is driven high the
terminal shows VSUP minus a diode voltage drop. In the high impedance state the output will be left floating. The
INH pin is high in the normal and standby modes and is low when in sleep mode. A 100 kΩ load can be added to
the INH output to ensure a fast transition time from the driven high state to the low state and to also force the pin
low when left floating.
This terminal should be considered a high-voltage logic terminal, not a power output thus should be used to drive
the EN terminal of the system’s power management device and not used as a switch for the power management
supply itself. This terminal is not reverse battery protected and thus should not be connected outside the system
module.
10.3.10 WAKE Pin
The WAKE pin is a high-voltage reverse-blocked input used for the local wake-up (LWU) function. This function
is explained further in Local Wake-Up (LWU) via WAKE Input Terminal section. The pin is defaulted to bi-
directional edge trigger, meaning a local wake-up (LWU) is recognize on either a rising or falling edge of WAKE
pin transition.
10.3.11 nRST Pin
The nRST is an bidirectional open drain low side driver with an integrated pull-up resistor to VCCOUT
(TCAN11625-Q1) or VLDO3 (TCAN11623-Q1). It can be pulled low by the device when placed in fail-safe mode.
During initial power-up of the device, a sleep mode to reset transition, a fail-safe mode to reset transition, or
an undervoltage event will be recognized as a cold crank reset condition. The nRST pin will be held low for
tnRST(cold) allowing the MCU and peripheral devices to power-up correctly before data transmission begins.
To enter reset mode from normal mode, or standby mode the nRST must be pulled low for a minimum of time
of tnRST. The TCAN1162x-Q1 recognizes this as a warm crank reset condition and holds the nRST pin low for
tnRST(warm)
.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
nRST
CONTROL and MODE
LOGIC
Figure 10-3. nRST Circuit
10.3.12 CAN Bus Pins
These are the CAN high and CAN low, CANH and CANL, differential bus pins. These pins are connected to the
CAN transceiver and the low-voltage wake receiver.
10.3.13 Local Faults
10.3.13.1 TXD Dominant Timeout (TXD DTO)
While the CAN driver is in active mode a TXD DTO circuit prevents the local node from blocking network
communication in event of a hardware or software failure where TXD is held dominant longer than the time out
period tTXD_DTO. The TXD DTO circuit is triggered by a falling edge on TXD. If no rising edge is seen before
the time out constant of the circuit, tTXD_DTO, expires the CAN driver is disabled releasing the bus lines to the
recessive level. This keeps the bus free for communication between other nodes on the network. The CAN driver
is re-activated on the next dominant to recessive transition on the TXD terminal, thus clearing the dominant time
out. The high-speed receiver and RXD terminal will reflect what is on the CAN bus during a TXD DTO fault. The
TS terminal in driven low during a TXD DTO fault.
Fault is repaired & transmission capability
restored
TXD fault stuck dominant: example PCB failure or bad software
tTXD_DTO
TXD (driver)
Driver disabled freeing bus for other nodes
Normal CAN communication
Bus would be —stuck dominant“ blocking communication for the whole network but TXD DTO
prevents this and frees the bus for communication after the time tTXD_DTO
.
CAN Bus Signal
tTXD_DTO
Communication from other bus node(s)
Communication from repaired node
RXD (receiver)
Communication from local node
Communication from other bus node(s)
Communication from repaired local node
Figure 10-4. Timing Diagram for TXD DTO
Copyright © 2021 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
The minimum dominant TXD time allowed by the TXD DTO circuit limits the minimum possible transmitted
data rate of the device. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD)
for the worst case, where five successive dominant bits are followed immediately by an error frame. The
minimum transmitted data rate may be calculated using the minimum tTXD_DTO time and the maximum number of
successive dominant bits (11 bits).
Minimum Data Rate = 11 bits / tTXD_DTO = 11 bits / 1.2 ms = 9.2 kbps
(1)
10.3.13.2 Thermal Shutdown (TSD)
If the junction temperature of the TCAN1162x-Q1 exceeds the thermal shutdown threshold, TJ > TSDR
,
the device transitions into fail-safe mode and disables the transceiver's transmitter and receiver blocking
transmission to and from the CAN bus. The TSD fault condition is cleared when the device junction temperature
falls below the thermal shutdown temperature threshold, TJ < TSDF. If the fault condition that caused the TSD
fault is still present, the temperature may rise again and the device will enter thermal shutdown again. Prolonged
operation with a TSD fault conditions may affect device reliability.
10.3.13.3 Under/Over Voltage Lockout
The supply terminals implement undervoltage and over voltage detection circuitry. If an undervoltage is detected
the TCAN1162x-Q1 transitions into either reset or sleep mode depending on the undervoltage fault. An
undervoltage fault on VIO causes the SBC to transition into sleep mode while an undervoltage fault on the
integrated regulator causes the SBC to transition to reset mode. The SBC will remain in reset mode until the fault
condition on the regulator is cleared.
If the over voltage fault is detected the TCAN1162x-Q1 transitions into fail-safe mode. These mode changes
place the device in a known state which protect the system from unintended behavior. See Table 10-1
Table 10-1. Undervoltage / Over Voltage Lockout
Fault
UVIO
TCAN11625
TCAN11623
Sleep mode
—
Sleep mode
UVCCOUT
UVFLT
Reset mode
—
Reset mode
Reset mode
—
UVLDO3
OVCCOUT
OVFLT
—
Fail-safe mode
—
—
Fail-safe mode
Fail-safe mode
OVLDO3
10.3.13.4 Unpowered Devices
The device is designed to be an ideal passive or no load to the CAN bus if it is unpowered. The CANH and
CANL pins have low leakage currents when the device is un-powered so they present no load to the bus. This is
critical if some nodes of the network are unpowered while the rest of the of network remains in operation.
The logic terminals also have low leakage currents when the device is un-powered so they do not load down
other circuits which may remain powered.
10.3.13.5 Floating Terminals
The TCAN1162x-Q1 has internal pull-ups and pull-downs on critical pins to ensure a known operating behavior if
the pins are left floating.
The TXD pin is pulled up to VIO which forces a recessive level if the pin floats. This internal bias should not be
relied upon by design but rather a fall-safe option. Special care needs to be taken when the devive is used with
a CAN controller that has open drain outputs. The device implements a weak internal pull-up resistor on the TXD
pin. The CAN bit timing for CAN FD data rates will require special consideration and the pull-up strength should
be considered carfully when using open drain outputs. An adequate external pull-up resistor must be used to
ensure that the TXD output of the CAN controller maintains adequate bit timing input to the CAN device.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
The nSLP pin is weakly pulled down which forces the device into the low-power sleep mode if the terminal is left
floating. See Table 10-2.
Table 10-2. Terminal Fail-Safe Biasing
TERMINAL
PULL-UP or PULL-DOWN
COMMENT
Weakly biases TXD toward recessive to prevent bus blockage or
TXD DTO triggering
TXD
Pull-up
Weakly biases the nSLP terminal towards low power sleep mode to
prevent excessive system power
nSLP
Pull-down
10.3.13.6 CAN Bus Short Circuit Current Limiting
The TCAN1162x-Q1 has several protection features that limit the short circuit current during dominant and
recessive when a CAN bus line is shorted. The device has TXD dominant state timeout which prevents
permanently having a higher short circuit current during a dominant state fault.
During CAN communication the bus switches between the dominant and recessive states, thus the short circuit
current may be viewed either as the current during each bus state or as a DC average current. The average
short circuit current should be used when considering system power for the termination resistors and common
mode choke. The percentage dominant is limited by the TXD dominant state timeout and CAN protocol which
has forced state changes and recessive bits such as bit stuffing, control fields, and interframe space. These
ensure that there is a minimum recessive time on the bus even if the data field contains a high percentage of
dominant bits.
The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short
circuit currents. The average short circuit current may be calculated using Equation 2.
IOS(AVG) = %Transmit × [(%REC_Bits × IOS(SS)_REC) + (%DOM_Bits × IOS(SS)_DOM)] + [%Receive × IOS(SS)_REC
]
(2)
Where:
•
•
•
•
•
•
•
IOS(AVG) is the average short circuit current
%Transmit is the percentage the node is transmitting CAN messages
%Receive is the percentage the node is receiving CAN messages
%REC_Bits is the percentage of recessive bits in the transmitted CAN messages
%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages
IOS(SS)_REC is the recessive steady state short circuit current
IOS(SS)_DOM is the dominant steady state short circuit current
The short circuit current and possible fault cases of the network should be taken into consideration when sizing
the power ratings of the termination resistance and other network components.
10.3.13.7 Sleep Wake Error Timer
The sleep wake error (SWE) timer, tINACTIVE, is a timer used to determine if specific external and internal
functions are working. The SWE timer starts when the device enters standby mode and only runs in standby
mode. A mode transistion stops the timer. If the timer times out while the device is in standby mode the RXD pin
will be pulled low to indicate an interrupt. The TCAN1162x-Q1 will transition to sleep mode.
Copyright © 2021 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.4 Device Functional Modes
The TCAN1162x-Q1 has six modes: normal, standby, sleep, reset, fail-safe, and off mode. Operating mode
selection is made via the nSLP input terminal in conjunction with supply conditions, temperature conditions, and
wake events.
VLDO3 < UVLDO3
VSUP < UVSUPF
UVLDO3
Or
Power Off
VSUP > UVSUPR
Reset
UVFLT
nRST = high
TJ < TSDF
&
VFLT < OVFLTF
&
VLDO3 < OVLDO3F
nSLP = high &
VIO > UVIOR
1
TJ > TSDR
Normal Mode3
1
Standby Mode
Fail-safe Mode
VFLT > OVFLTR
nSLP = low or
VIO < UVIOF
1
VLDO3 > OVLDO3R
Wake-up event
nSLP = low for t > tSLP
& nSLP was high at
some point since Reset
mode & VIO > UVIOF
2
t > tINACTIVE
1 From any mode except sleep mode and off
2 From standby mode
Sleep Mode
2
VIO < UVIOF for t > tUV(SLP)
3 Normal mode is confirmed when the TS pin is high
Figure 10-5. TCAN11623 State Machine
Table 10-3. TCAN11623 Mode Overview
BLOCK
NORMAL
On
STANDBY
RESET
SLEEP
Off
FAIL-SAFE
Off
VFLT
VLDO3
On
On
On
On
On
Off
Off
INH
Active
Off
Active
Active
VLDO3
Active
Active
Low
Off
Off
Low Power CAN RX
nRST
Active
Off
Active(1)
VLDO3
VLDO3
(1) In fail-safe mode wake-up events are ignored until all pending faults are cleared
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
Reset event
VSUP < UVSUPF
Power Off
VSUP > UVSUPR
Reset
UVCCOUT
nRST = high
TJ < TSDF
&
VCCOUT < OVCCOUTF
nSLP = high &
VIO > UVIOR
1
TJ > TSDR
Fail-safe Mode
Standby Mode
Normal Mode3
1
VCCOUT > OVCCOUTR
nSLP = low or
VIO < UVIOF
nSLP = low for t > tSLP
& nSLP was high at
some point since reset
mode & VIO > UVIOF
Wake-up event
2
t > tINACTIVE
1 From any mode except sleep mode and off
2 From standby mode
Sleep Mode
2
VIO < UVIOF for t > tUV(SLP)
3 Normal mode is confirmed when the TS pin is high
Figure 10-6. TCAN11625 State Machine
Table 10-4. TCAN11625 Mode Overview
BLOCK
VCCOUT
NORMAL
On
STANDBY
RESET
SLEEP
Off
FAIL-SAFE
On
On
Off
Off
INH
Active
Off
Active
Active
VCCOUT
Active
Active
Low
Off
Low Power CAN RX
nRST
Active
Off
Active(1)
VCCOUT
VCCOUT
(1) In fail-safe mode wake-up events are ignored until all pending faults are cleared.
10.4.1 Operating Mode Description
10.4.1.1 Normal Mode
This is the normal operating mode of the device. The CAN driver and receiver are fully operational and CAN
communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH
and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.
The tINACTIVE timer in not active in normal mode.
10.4.1.2 Standby Mode
Standby mode is a low power mode of the TCAN1162x-Q1 where the CAN transceiver is placed in the CAN
autonomous inactive state by asserting the nSLP pin low. In this mode the TS pin is driven low, the CAN
transmitter and receiver are switched off, the bus pins are biased to ground, and the transceiver cannot send or
receive data. While in standby mode the low power receiver actively monitors the CAN bus for a valid wake-up
pattern. If a valid wake-up pattern is received the CAN bus pins transition to the CAN autonomous active state
where CANH and CANL are internally biased to 2.5 V from the VSUP power rail. The reception of a valid wake-up
pattern generates a wake-up request by the CAN transceiver by latching the RXD output pin low. The WAKE pin
circuitry is active in standby mode and monitors the WAKE pin for either a high-to-low or low-to-high transition.
The INH pin is active in order to supply an enable to the system power supply.
The RXD output pin is asserted low while in standby mode if the a wake event or a fault is detected. Note that a
POR counts as a wake event and will also cause RXD to latch low.
In standby mode a fail-safe timer, tINACTIVE, is enabled. The tINACTIVE timer add an additional layer of protection
by requiring the system controller to configure the TCAN1162x-Q1 to normal mode before it expires. This feature
forces the TCAN1162x-Q1 to transition to its lowest power mode, sleep mode, if the processor does not come up
properly.
Copyright © 2021 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
The TCAN11625 internal regulator, VCCOUT, is active in standby mode.
The TCAN11623 internal regulators, VFLT and VLDO3, are active in standby mode.
Standby mode is not the lowest power mode of the device since the INH terminal and internal regulators are
active. This allows the rest of the system to operate normally.
10.4.1.3 Sleep Mode
Sleep mode is the lowest power mode of the TCAN1162x-Q1 where the CAN transceiver is placed in the CAN
autonomous inactive state by asserting the nSLP pin low for t > tSLP. In sleep mode, the CAN transmitter
and receiver are switched off, the bus pins are biased to ground after tSILENCE expires, and the transceiver
cannot send or receive data. The INH pin is switched off in sleep mode causing any system power elements
controlled by INH to be switched off thus reducing system power consumption. While in sleep mode, the low
power receiver actively monitors the CAN bus for a valid wake-up pattern and the ISUP current is reduced to its
minimum level.
Sleep mode is entered if:
•
•
The nSLP pin is asserted low for t > tSLP, there are no pending wake-up events, and VIO > UVVIOR
VIO < UVVIOR for t > tUV(SLP)
•
SWE timer expires (see Sleep Wake Error Timer)
Sleep mode is exited if:
•
•
•
If a valid wake-up pattern (WUP) is received via the CAN bus pins
A local WAKE (LWU) event
A reset event occurs (goes to reset mode)
10.4.1.3.1 Remote Wake Request via Wake-Up Pattern (WUP)
The TCAN1162x-Q1 implements a low-power wake receiver in the standby and sleep mode that uses the
multiple filtered dominant wake-up pattern (WUP) defined in the ISO11898-2:2016 standard.
The wake-up pattern (WUP) consists of a filtered dominant bus, then a filtered recessive bus time followed by
a second filtered bus time. The first filtered dominant initiates the WUP and the bus monitor is now waiting on
a filtered recessive, other bus traffic do not reset the bus monitor. Once a filtered recessive is received, the bus
monitor is now waiting on a filtered dominant. The other bus traffic do not reset the bus monitor. Immediately
upon receiving of the second filtered dominant, the bus monitor recognizes the WUP and drives the RXD
terminal low, if a valid VIO is present signaling to the controller the wake-up request. If a valid VIO is not present
when the wake-up pattern is received the device drives the RXD output pin low once VIO > UVIOR
.
The WUP consists of:
•
•
•
A filtered dominant bus of at least tWK_FILTER followed by
A filtered recessive bus time of at least tWK_FILTER followed by
A second filtered dominant bus time of at least tWK_FILTER
For a dominant or recessive to be considered “filtered”, the bus must be in that state for more than tWK_FILTER
time. Due to variability in the tWK_FILTER the following scenarios are applicable. Bus state times less than
tWK_FILTER(MIN) are never detected as part of a WUP, and thus no wake request is generated. Bus state times
between tWK_FILTER(MIN) and tWK_FILTER(MAX) may be detected as part of a WUP, and a wake request may be
generated. Bus state times more than tWK_FILTER(MAX) are always detected as part of a WUP, and thus a wake
request is generated. See Figure 10-7 for the timing diagram of the WUP.
The pattern and tWK_FILTER time used for the WUP and wake request prevents noise and bus stuck dominant
faults from causing false wake requests while allowing any CAN or CAN FD message to initiate a wake request.
ISO11898-2:2016 has two sets of times for a short and long wake-up filter times. The tWK_FILTER timing for the
TCAN1162x-Q1 has been picked to be within the min and max values of both filter ranges. This timing has been
chosen such that a single bit time at 500 kbps, or two back to back bit times at 1 Mbps triggers the filter in either
bus state.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
For an additional layer of robustness and to prevent false wake-ups, the device implements the tWK_TIMEOUT
timer. For a remote wake-up event to successfully occur, the entire wake-up pattern must be received within the
timeout value. If a the full wake-up pattern is notreceived before the tWK_TIMEOUT expires, then the internal logic
is reset and the device remains in sleep mode without waking up. The full pattern must then be transmitted again
within the tWK_TIMEOUT window. See Figure 10-7.
Wake-Up Pattern (WUP) received in t < tWK_TIMEOUT
Wake Request
Filtered
Dominant
Filtered
Dominant
Filtered
Recessive
Waiting for
Filtered
Dominant
Waiting for
Filtered
Recessive
Bus
Bus VDiff
WUP Detect
Mode
≥ tWK_FILTER
≥ tWK_FILTER
≥ tWK_FILTER
*
tINH_SLP_STB
Sleep Mode
Standby Mode
*The RXD pin is only driven once VIO is present.
Figure 10-7. Wake-Up Pattern (WUP) From Sleep Mode To Standby Mode
10.4.1.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
The WAKE terminal is a bi-directional high-voltage reverse battery protected input which can be used for local
wake-up (LWU) requests via a voltage transition. A LWU event is triggered on either a low-to-high or high-to-low
transition since it has bi-directional input thresholds. The WAKE pin could be used with a switch to VSUP or to
ground. If the terminal is unused, it should be pulled to VSUP or ground to avoid unwanted parasitic wake-up
events.
Figure 10-8. WAKE Circuit Example
Figure 10-8 shows two possible configurations for the WAKE pin, a low-side and high-side switch configuration.
The objective of the series resistor, RSERIES, is to protect the WAKE input of the device from over current
conditions that may occur in the event of a ground shift or ground loss. The minimum value of RSERIES can be
Copyright © 2021 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
calculated using the maximum supply voltage, VSUPMAX, and the maximum allowable current of the WAKE pin,
IIO(WAKE). RSERIES is calculated using:
RSERIES = VSUPMAX / IIO(WAKE)
(3)
If the battery voltage never exceeds 42 VDC, then the RSERIES value is approximately 10 kΩ.
The RBIAS resistor is used to set the static voltage level of the WAKE input when the switch is not in use. When
the switch is in use in a high-side switch configuration, the RBIAS resistor in combination with the RSERIES resistor
sets the WAKE pin voltage above the VIH threshold. The maximum value of RBIAS can be calculated using
the maximum supply voltage, VSUPMAX, the maximum WAKE threshold voltage VIH, the maximum WAKE input
current IIH and the series resistor value RSERIES. RBIAS is calculated using:
RBIAS < ((VSUPMAX - VIH) / IIH) - RSERIES
(4)
If the battery voltage never exceed 42 VDC, then the RBIAS resistor value must be less than 650-kΩ.
The LWU circuitry is active in sleep modeand fail-safe mode.. If a valid LWU event occurs while the TCAN1162x-
Q1 is in sleep mode the device transitions to reset mode. If a valid LWU event occurs while the TCAN1162x-Q1
is in fail-safe mode the device transitions to reset mode given the other exit criteria from fail-safe mode have
been met. See the CAN Transceiver Modes section.
The WAKE circuitry is switched off normal mode.
WAKE
threshold
not
crossed
t
tWAKE
t ≥ tWAKE
wake-up
no wake-up
Wake
LWU Request
INH
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
Figure 10-9. LWU Request Rising Edge
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
WAKE
threshold
not
t
tWAKE
t ≥ tWAKE
wake-up
no wake-up
crossed
Wake
LWU Request
INH
RXD
Mode
Sleep Mode
Standby Mode
The RXD pin is only driven once VIO is present.
Figure 10-10. LWU Request Falling Edge
10.4.1.4 Reset Mode
Reset mode is a low power mode of the TCAN1162x-Q1 where the nRST pin is asserted low allowing the
controller to power up correctly. In this state the CAN transmitter and receiver are off, the bus pins are biased to
ground, and the transceiver cannot send or receive data.
While in reset mode the low power receiver actively monitors the CAN bus for a valid wake-up pattern. If a valid
wake-up pattern is received the CAN bus pins transition to the CAN autonomous active state where CANH and
CANL are internally biased to 2.5 V from the VSUP power rail. The reception of a valid wake-up pattern generates
a wake-up request by the CAN transceiver that is output to the RXD pin.
The TCAN1162x-Q1 will enter reset mode due to following conditions:
•
•
Power-on
nRST pulled low externally
The TCAN11625 will enter reset mode due to following conditions:
VCCOUT < UVVCCOUT
The TCAN11623 will enter reset mode due to following conditions:
VFLT < UVVFLT
•
•
The TCAN1162x-Q1 will enter reset mode upon clearing any of the following fault conditions and leaving fail-safe
mode:
•
•
TJ < TSDF
Over voltage event
Copyright © 2021 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.4.1.5 Fail-safe Mode
Fail-safe mode is a low power mode in which the TCAN1162x-Q1 is in a protected state. While in fail-safe mode
the internal regulator (VFLT VCCOUT) is off, the INH pin is off, the reset pin is low, and the CAN transmitter and
receiver are off.
Fail-safe mode is entered if:
•
•
•
•
TJ > TSDR
VVCCOUT > OVCCOUTR - TCAN11625
VVFLT > OVFLTR - TCAN11623
VLDO3 > OVLDO3R - TCAN11623
Fail-safe mode is exited if all of the following criteria are met:
•
•
•
•
•
TJ < TSDF
VVCCOUT < OVCCOUTF - TCAN11625
VVFLT < OVFLTF
VLDO3 > OVLDO3F - TCAN11623
A valid wake-up event exists
If the fault condition is not cleared within tINACTIVE then the device will transition into it's lowest power mode,
sleep mode.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.4.2 CAN Transceiver
10.4.2.1 CAN Transceiver Operation
The TCAN1162x-Q1 CAN transverse has three modes of operation; CAN active, CAN autonomous active, and
CAN autonomous inactive.
10.4.2.2 CAN Transceiver Modes
The TCAN1162x-Q1 supports the ISO 11898-2:2016 CAN physical layer standard autonomous bus biasing
scheme. Autonomous bus biasing enables the transceiver to switch between CAN active, CAN autonomous
active, and CAN autonomous inactive which helps to reduce RF emissions.
CAN Active
CAN Transmitter: on
CAN Receiver: on
RXD: Mirrors CAN bus
CANH & CANL: VFLT/2 (~2.5 V)
From any mode
VSUP < UVSUPF
TJ > TSDR
CAN Off
CAN Transmitter: off
CAN Receiver: off
RXD: wake-up/high
CANH & CANL: floating
CAN Autonomous: Inactive
CAN Transmitter: off
CAN Receiver: off
RXD: wake-up/high
CANH & CANL: bias to GND
CAN Autonomous: Active
CAN Transmitter: off
CAN wake-up or (normal & (VFLT < UVFLTR) or (VLDO3
UVLDO3R) or VIO < UVVIOR
<
VSUP > UVSUPR
TJ < TSDF
)
CAN Receiver: off
RXD: low signals wake-up1
CANH & CANL: bias to 2.5 V from VSUP
t > tSILENCE & (fail-safe or standby or sleep)
1 Wake-up inactive in normal mode
Figure 10-11. TCAN11623 CAN Transceiver State Machine
CAN Active
CAN Transmitter: on
CAN Receiver: on
RXD: Mirrors CAN bus
CANH & CANL: VCCOUT/2 (~2.5 V)
From any mode
VSUP < UVSUPF
TJ > TSDR
CAN Off
CAN Transmitter: off
CAN Receiver: off
RXD: wake-up/high
CANH & CANL: floating
CAN Autonomous: Inactive
CAN Autonomous: Active
CAN Transmitter: off
CAN wake-up or (normal & (VCCOUT < UVCCOUTR) or (VIO
UVIOR))
<
CAN Transmitter: off
CAN Receiver: off
RXD: wake-up/high
VSUP > UVSUPR
TJ < TSDF
CAN Receiver: off
RXD: low signals wake-up1
CANH & CANL: bias to 2.5 V from VSUP
t > tSILENCE & (fail-safe or standby or sleep)
CANH & CANL: bias to GND
1 Wake-up inactive in normal mode
Figure 10-12. TCAN11625 CAN Transceiver State Machine
Copyright © 2021 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.4.2.2.1 CAN Off Mode
In CAN off mode the CAN transceiver is switched off and the CAN bus lines are truly floating. In this mode the
device presents no load to the CAN bus while preventing reverse currents from flowing into the device if the
battery or ground connection is lost.
The CAN off state is entered if:
•
•
TJ > TSDR
VSUP < UVSUPF
The CAN transceiver switches between the CAN off state and CAN autonomous inactive mode if:
•
•
VSUP > UVSUPR
TJ < TSDF
10.4.2.2.2 CAN Autonomous: Inactive and Active
When the CAN transceiver is in standby mode or sleep mode the CAN bias circuit is switched off and the
transceiver moves to the autonomous inactive state. In the autonomous inactive state the CAN pins are biased
to GND. When a valid wake-up event occurs the CAN bus is biased to 2.5 V. If the controller does not transition
the TCAN1162x-Q1 into normal mode before the tSILENCE timer expires, then the CAN biasing circuit is again
switched off and the CAN pins are biased to ground.
The CAN transceiver switches to the CAN autonomous mode if any of the following conditions are met:
•
•
The TCAN1162x-Q1 transitions from CAN off mode to CAN autonomous inactive
The TCAN1162x-Q1 transitions from normal mode to standby mode or fail-safe mode or sleep mode and t <
tSILENCE
•
•
t > tSILENCE and the TCAN1162x-Q1 transitions from normal mode to standby mode or fail-safe mode or sleep
mode
The TCAN1162x-Q1 transitions to reset mode
The CAN transceiver switches between the CAN autonomous inactive mode and CAN autonomous active mode
if:
•
•
A valid wake-up event
The TCAN1162x-Q1 transitions to normal mode and no undervoltage faults exist.
The CAN transceiver switches between the CAN autonomous active mode and CAN autonomous inactive mode
if:
•
t > tSILENCE and the TCAN1162x-Q1 transitions to standby mode, sleep mode, or fail-safe mode.
10.4.2.2.3 CAN Active
When the TCAN1162x-Q1 is in normal mode the CAN transceiver is in active mode. The CAN driver and
receiver are fully operational and CAN communication is bi-directional. The CAN bias voltage in CAN active
mode is derived from:
•
•
VCCOUT - TCAN11625
VFLT - TCAN11623
The CAN transceiver switches between the CAN autonomous inactive or active mode and CAN active mode if:
The TCAN1162x-Q1 transitions to normal mode and no undervoltage faults exist.
•
The CAN transceiver blocks its transmitter and receiver after entering CAN active mode if the TXD pin is
asserted low before leaving standby mode. This prevents disruptions to CAN bus in the event that the TXD pin
has a TXD DTO fault.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
10.4.2.3 Driver and Receiver Function Tables
Table 10-5. Driver Function Table
BUS OUTPUTS
DEVICE MODE
TXD INPUTS(1)
DRIVEN BUS STATE(2)
CANH
CANL
Low
High
Low
Dominant
Normal
Biased to VCCOUT/2 (TCAN11625)
VFLT/2 (TCAN11623)
High or Open
High impedance
High impedance
Standby
Sleep
x
x
High impedance
High impedance
High impedance
High impedance
Biased to GND
Biased to GND
(1) x = irrelevant
(2) For bus states and typical bus voltages see Figure 10-13
Table 10-6. Receiver Function Table
CAN DIFFERENTIAL INPUTS
DEVICE MODE
BUS STATE
RXD TERMINAL
VID = VCANH – VCANL
VID ≥ 0.9 V
Dominant
Indeterminate
Recessive
Open
Low
Indeterminate
High
0.5 V < VID < 0.9 V
VID ≤ 0.5 V
Normal
Open (VID ≈ 0 V)
VID ≥ 1.15 V
High
Dominant
Indeterminate
Recessive
Open
0.5 V < VID < 1.15 V
VID ≤ 0.4 V
High
Standby
Low if wake-up event persists
Open (VID ≈ 0 V)
VID ≥ 1.15 V
Dominant
Indeterminate
Recessive
Open
High
0.4 V < VID < 1.15 V
VID ≤ 0.4 V
Low if wake-up event persists and VIO is
present.
Tri-state if VIO or VSUP are not present
Sleep
Open (VID ≈ 0 V)
10.4.2.4 CAN Bus States
The CAN bus has two logical states during operation: recessive and dominant. See Figure 10-13.
A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD
and RXD pins. A recessive bus state occurs when the bus is biased to one half of the CAN transceiver supply
voltage via the high resistance internal input resistors (RIN) of the receiver and corresponds to a logic high on the
TXD and RXD pins.
A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a
dominant bit at the same time during arbitration, and in this case the differential voltage of the CAN bus will be
greater than the differential voltage of a single CAN driver. The TCAN1162x-Q1 CAN transceiver implements
low-power standby and sleep modes which enables a third bus state where the bus pins are biased to ground
via the high resistance internal resistors of the receiver.
Copyright © 2021 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
Standby Mode
Normal Mode
CANH
VDIFF
VDIFF
CANL
Recessive
Dominant
Recessive
Time, t
Figure 10-13. Bus States
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
11 Application Information
11.1 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
11.2 Typical Application
EN
3.3V Voltage Regulator
(e.g. TPSxxxx)
Motor Driver
VBAT
0.1ꢀF
0.1ꢀF
10ꢀF
3.3kΩ
33kΩ
VSUP
10
VIO
VLDO5
5
3
0.1nF
9
7
WAKE
CANH
VIN
13
INH
TCAN11625
nSLP
TS
14
6
CAN FD
Controller
nRST
TXD
11
1
CANL
12
Optional:
Terminating
Node
RXD
4
Optional:
Filtering,
Transient and
ESD
2
GND
Figure 11-1. Typical Application
Copyright © 2021 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
EN
5V Voltage Regulator
(e.g. TPSxxxx)
Sensor or Second
CAN FD Controller
VBAT
10
F
0.1
F
0.1
F
10 F
3.3k
33k
VLDO3
VSUP
10
VIO
VFLT
8
5
3
0.1nF
9
7
WAKE
INH
CANH
VIN
13
TCAN11623
nSLP
TS
14
6
CAN FD
Controller
nRST
TXD
11
1
CANL
12
Optional:
Terminating
Node
RXD
4
Optional:
Filtering,
Transient and
ESD
2
GND
Figure 11-2. Typical Application
11.2.1 Design Requirements
11.2.1.1 Bus Loading, Length and Number of Nodes
A typical CAN application may have a maximum bus length of 40 meters and maximum stub length of 0.3 m.
However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a
bus. A high number of nodes requires a transceiver with high input impedance such as the TCAN1162x-Q1
Many CAN organizations and standards have scaled the use of CAN for applications outside the original ISO
11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic loading
of the bus. Examples of these CAN systems level specifications are ARINC 825, CANopen, DeviceNet, SAE
J2284, SAE J1939, and NMEA 2000.
A CAN network system design is a series of tradeoffs. In the ISO 11898-2:2016 specification the driver
differential output is specified with a bus load that can range from 50 Ω to 65 Ω where the differential output
must be greater than 1.5 V. The TCAN1162x-Q1 is specified to meet the 1.5-V requirement down to 50 Ω
and is specified to meet 1.4-V differential output at 45Ω bus load. The differential input resistance of the
TCAN1162x-Q1 is a minimum of 40 kΩ. If 100 TCAN1162x-Q1 devices are in parallel on a bus, this is equivalent
to a 400-Ω differential load in parallel with the nominal 60 Ω bus termination which gives a total bus load of
approximately 52 Ω. Therefore, the TCAN1162x-Q1 theoretically supports over 100 devices on a single bus
segment. However, for CAN network design margin must be given for signal loss across the system and cabling,
parasitic loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum
number of nodes is often lower. Bus length may also be extended beyond 40 meters by careful system design
and data rate tradeoffs. For example, CANopen network design guidelines allow the network to be up to 1 km
with changes in the termination resistance, cabling, less than 64 nodes and significantly lowered data rate.
This flexibility in CAN network design is one of the key strengths of the various extensions and additional
standards that have been built on the original ISO 11898-2 CAN standard. However, when using this flexibility
the CAN network system designer must take the responsibility of good network design to ensure robust network
operation.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
11.2.2 Detailed Design Procedures
11.2.2.1 CAN Termination
Termination may be a single 120-Ω resistor at the end of the bus on either the cable or in a terminating node.
If filtering and stabilization of the common mode voltage of the bus is desired then split termination may used,
see Figure 11-3. Split termination improves the electromagnetic emissions behavior of the network by filtering
higher-frequency common-mode noise that may be present on the differential signal lines..
Standard Termination
Split Termination
CANH
CANH
RTERM/2
RTERM
TCAN Transceiver
TCAN Transceiver
CSPLIT
RTERM/2
CANL
CANL
Figure 11-3. CAN Bus Termination Concepts
11.3 Application Curves
3
-40 C
50 C
150 C
2.75
2.5
2.25
2
1.75
1.5
4
6
8
10 12 14 16 18 20 22 24 26 28
VSUP (V)
RL = 60 Ω
Figure 11-4. VOD(D) over VSUP
Copyright © 2021 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
12 Power Supply Requirements
The TCAN1162x-Q1 is designed to operate from a VSUP input supply voltage range between 5.5 V and 28 V.
The TCAN1162x-Q1 also has an output level shifting supply input, VIO, designed for a range between 1.7 V and
5.5 V. Input supplies must be well regulated. A bypass capacitance, typically 100 nF, should be placed close
to the device VSUP and VIO supply pins. This helps to reduce supply voltage ripple present on the outputs of
the switched-mode power supplies and also helps to compensate for the resistance and inductance of the PCB
power planes and traces.
The TCAN11625 integrates a 5-V LDO to supply the CAN transceiver as well as additional external loads. The
VCCOUT pin requires a 10 µF capacitance.
The TCAN11623 integrates a 5-V LDO to supply the CAN transceiver and a 3.3-V LDO for additional external
loads. The VFLT pin requires a 10 µF capacitance and the VLDO3 pin typically uses a capacitance value of 4.7uF.
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
13 Layout
13.1 Layout Guidelines
Place the protection and filtering circuitry as close to the bus connector to prevent transients, ESD and noise
from propagating onto the board. The layout example provides information on components around the device
itself. Transient voltage suppression (TVS) device can be added for extra protection. The production solution can
be either bi-directional TVS diode or varistor with ratings matching the application requirements. This example
also shows optional bus filter capacitors.
Design the bus protection components in the direction of the signal path. Do not force the transient current
to divert from the signal path to reach the protection device. Use supply and ground planes to provide low
inductance.
Note
A high-frequency current follows the path of least impedance and not the path of least resistance.
Use at least two vias for supply and ground connections of bypass capacitors and protection devices to minimize
trace and via inductance.
•
•
Bypass and bulk capacitors should be placed as close as possible to the supply terminals of transceiver.
Bus termination: this layout example shows split termination. This is where the termination is split into two
resistors with the center or split tap of the termination connected to ground via capacitor. Split termination
provides common mode filtering for the bus. When bus termination is placed on the board instead of directly
on the bus, additional care must be taken to ensure the terminating node is not removed from the bus thus
also removing the termination.
13.2 Layout Example
CAN Controller
To VIO
RES
RES
CAN Controller
TXD
GND
VFLT
RXD
VIO
nSLP
CANH
CANL
nRST
VSUP
RES
RES
CAP
ESD
Connector
CAN Controller
CAN Controller
To VIO
RES
VBAT
CAN Controller
Regulator EN
TS
WAKE
VLDO3
RES
INH
CAP
CAN Controller
Figure 13-1. TCAN11623 Example Layout
Copyright © 2021 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
CAN Controller
To VIO
RES
RES
CAN Controller
TXD
GND
VCCOUT
RXD
VIO
nSLP
CANH
CANL
nRST
VSUP
RES
RES
CAP
ESD
Connector
CAN Controller
CAN Controller
CAN Controller
RES
To VIO
VBAT
CAN Controller
Regulator EN
TS
WAKE
NC
RES
INH
Figure 13-2. TCAN11625 Example Layout
Copyright © 2021 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
TCAN11623-Q1, TCAN11625-Q1
SLLSF83A – MAY 2021 – REVISED NOVEMBER 2021
www.ti.com
14 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
14.1 Documentation Support
14.1.1 Related Documentation
14.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
14.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
14.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
14.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TCAN11623-Q1 TCAN11625-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TCAN11623DMTRQ1
TCAN11625DMTRQ1
ACTIVE
ACTIVE
VSON
VSON
DMT
DMT
14
14
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 150
-40 to 150
11623
11625
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Dec-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TCAN11623DMTRQ1
TCAN11625DMTRQ1
VSON
VSON
DMT
DMT
14
14
3000
3000
330.0
330.0
12.4
12.4
3.3
3.3
4.8
4.8
1.2
1.2
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TCAN11623DMTRQ1
TCAN11625DMTRQ1
VSON
VSON
DMT
DMT
14
14
3000
3000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DMT 14
3 x 4.5, 0.65 mm pitch
VSON - 0.9 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225088/A
www.ti.com
PACKAGE OUTLINE
DMT0014B
VSON - 1 mm max height
SCALE 3.200
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
4.6
4.4
0.1 MIN
(0.13)
1.0
0.8
SECTION A-A
SCALE 30.000
SECTION A-A
TYPICAL
C
SEATING PLANE
0.08 C
0.05
0.00
1.6 0.1
SYMM
EXPOSED
THERMAL PAD
(0.2) TYP
7
8
(0.19) TYP
A
A
2X
3.9
15
SYMM
4.2 0.1
14
1
12X 0.65
0.35
0.25
14X
0.45
0.35
PIN 1 ID
14X
0.1
C A B
(OPTIONAL)
0.05
C
4225087/B 01/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.6)
14X (0.6)
14X (0.3)
SYMM
1
14
2X
(1.85)
12X (0.65)
SYMM
15
(4.2)
(0.69)
TYP
(
0.2) VIA
TYP
8
7
(R0.05) TYP
(0.55) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4225087/B 01/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DMT0014B
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.47)
15
14X (0.6)
1
14
14X (0.3)
(1.18)
12X (0.65)
SYMM
(1.38)
(R0.05) TYP
METAL
TYP
8
7
SYMM
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 15
77.4% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4225087/B 01/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021, Texas Instruments Incorporated
相关型号:
©2020 ICPDF网 联系我们和版权申明