TCAN4420 [TI]

具有极性控制功能的 CAN 收发器;


型号：	TCAN4420
厂家：	TEXAS INSTRUMENTS
描述：	具有极性控制功能的 CAN 收发器
文件：	总32页 (文件大小：1224K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Support &

Community

Product

Folder

Order

Now

Tools &

Software

Technical

Documents

TCAN4420

ZHCSH93 –DECEMBER 2017

具有极性控制功能的 TCAN4420 CAN 收发器

1 特性

2 应用

•

符合 ISO 11898-2 (2016) 物理层标准要求

通过 SW（开关）引脚进行外部极性控制

•

楼宇自动化

–

楼宇安全网关

–

可用于将极性切换为 CAN 总线的正常（默认）

或反向配置

HVAC 网关和系统控制器

电梯主面板

•

双电源

3 说明

–

5V V_CC引脚用于为 CAN 驱动器和接收器供电

TCAN4420 是一款符合 ISO 11898-2 (2016) 物理层标

准规格要求的高速控制器局域网 (CAN) 收发器。该器

件还支持通过微控制器由 SW 引脚从外部控制 CAN 总

线极性。TCAN4420 包含众多可实现器件和 CAN 网

络可靠性的保护特性。支持 2.8V 至 5V MCU，且包含

可通过 V_IO引脚实现的 I/O 接口。

2.8V 至 5V V_IO引脚用于为 RXD、TXD 和 SW

引脚供电

宽运行范围

–

±46V 总线故障保护

±12V 共模

–40°C 至 125°C 环境温度

•

保护特性

器件信息⁽¹⁾

–

人体放电模型 (HBM) ESD 保护高达 ±12kV

_CC和 V_IO电源欠压保护

器件型号

TCAN4420

封装

封装尺寸（标称值）

SOIC (D) (8)

4.90mm x 3.91mm

TXD 显性超时 (TXD DTO) - 支持低至 9.2kbps

的数据速率

(1) 如需了解所有可用型号，请参阅数据表末尾的可订购产品附

录。

–

热关断保护 (TSD)

•

优化了未上电时的性能

–

总线和逻辑终端处于高阻态（运行总线或应用上

无负载）

–

上电/断电无毛刺脉冲运行

快速循环时间：150ns

功能框图

V_IO

V_CC

V_IO

V_CC

CANH

CANL

V_CC

Dominant

Time Out

DRIVER

TXD

Over

Temp.

Mode and

Control Logic

Polarity

Control

Under

Voltage

V_IO

V_CC

Logic

Output

RXD

GND

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

English Data Sheet: SLLSF19

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

8.2 Functional Block Diagrams ..................................... 14

8.3 Feature Description................................................. 14

8.4 Device Functional Modes........................................ 16

Application and Implementation ........................ 18

9.1 Application Information............................................ 18

9.2 Typical Application ................................................. 18

特性.......................................................................... 1

应用.......................................................................... 1

说明.......................................................................... 1

修订历史记录 ........................................................... 2

Pin Configuration and Functions......................... 3

Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 ESD Ratings ............................................................ 4

6.3 ESD Ratings Specifications ...................................... 4

6.4 Recommended Operating Conditions....................... 5

6.5 Thermal Information.................................................. 5

6.6 Power Supply Characteristics ................................... 6

6.7 AC and DC Electrical Characteristics ....................... 6

6.8 Timing Requirements ............................................... 7

6.9 Typical Characteristics.............................................. 9

Parameter Measurement Information ................ 10

Detailed Description ............................................ 14

8.1 Overview ................................................................. 14

10 Power Supply Recommendations ..................... 21

11 Layout................................................................... 22

11.1 Layout Guidelines ................................................. 22

11.2 Layout Example .................................................... 23

12 器件和文档支持 ..................................................... 24

12.1 器件支持 ............................................................... 24

12.2 接收文档更新通知 ................................................. 24

12.3 社区资源................................................................ 24

12.4 商标....................................................................... 24

12.5 静电放电警告......................................................... 24

12.6 Glossary................................................................ 24

13 机械、封装和可订购信息....................................... 25

4 修订历史记录

注：之前版本的页码可能与当前版本有所不同。

日期

修订版本

说明

2017 年 12 月

初始发行版

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

5 Pin Configuration and Functions

D Package

8-Pin SOIC

Top View

TXD

GND

V_CC

CANH

CANL

V_IO

RXD

Pin Functions

I/O

DESCRIPTION

NAME

TXD

NO.

Logic Input CAN transmit data input (LOW for dominant and HIGH for recessive bus states)

GND

V_CC

Ground

Power

Ground connection

5 V ±10% supply voltage

RXD

V_IO

Logic Output CAN receive data output (LOW for dominant and HIGH for recessive bus states)

Power

Bus I/O

Transceiver I/O level shifting supply voltage

Low level CAN bus input/output line

High level CAN bus input/output line

CANL

CANH

Polarity switch pin. Set to low for normal polarity (default), and high to reverse the polarity of

the CAN pins

Logic Input

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

(2)

MIN

–0.3

–46

MAX

UNIT

V_CC

Supply voltage

V_IO

Supply voltage select for I/O level shifter

CAN Bus I/O voltage (CANH, CANL)

Logic input terminal voltage

RXD output terminal voltage range

RXD output current

V_BUS

V_{Logic_Input}

V_RXD

I_O(RXD)

T_J

–0.3

°C

Operating virtual junction temperature range, packaged units

Ambient temperature

–40

–65

150

125

150

T_A

T_STG

Storage temperature

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

VALUE

UNIT

Human-body model (HBM), per AEC

Q100-002

All pins⁽¹⁾

All pins⁽²⁾

±4000

V_(ESD)

Electrostatic discharge

Charged-device model (CDM), per AEC

Q100-011

±750

(1) Tested in accordance to AEC-Q100-002.

(2) Tested in accordance to AEC-Q100-011.

6.3 ESD Ratings Specifications

VALUE

UNIT

CAN bus terminal

(CANH, CANL)

Electrostatic discharge⁽¹⁾

Human bodt model (HBM)

±12000

IEC 61400-4-2 according to IBEE CAN

EMC test spec⁽²⁾

IEC 61400-4-2 Air Discharge⁽²⁾

V_(ESD)

(4)

CANH and CANL terminals to GND⁽³⁾

±8000

±15000

–100

Pulse 1

Pulse 2

Pulse 3a

ISO7637 Transients according to IBEE

CAN EMC test spec⁽⁵⁾

CAN bus terminals (CANH, CANL)

–150

(1) System level ESD test, results given here were performed at the system level with appropriate external components such TVS diodes.

Different system level configurations may lead to different results.

(2) IEC 61000-4-2 is a system level ESD test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different

system level configurations may lead to different results.

(3) IEC 61000-4-2 is a system level ESD test. Results given here were performed at the system level with appropriate external components

such TVS diodes. Different system level configurations may lead to different results.

(4) Testing performed in accordance with 3rd party IBEE Zwickau test method.

(5) ISO7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different

system level configurations may lead to different results.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

4.5

2.8

–2

NOM

MAX

5.5

UNIT

V_CC

Supply voltage

V_IO

Supply Voltage for I/O Level Shifter

RXD terminal HIGH level output current

RXD terminal LOW level output current

5.5

I_OH(RXD)

I_OL(RXD)

Operational free-air temperature (see Thermal Characteristics

table)

T_A

–40

125

°C

6.5 Thermal Information

TCAN4420

SOIC

8 PINS

114

THERMAL METRIC⁽¹⁾

UNIT

R_θJA

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

R_θJC(top)

R_θJB

48.2

59.2

Ψ_JT

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

9.5

Ψ_JB

58.1

R_θJC(bot)

–

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

6.6 Power Supply Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

See 图 6, TXD = 0 V, R_L= 60 Ω, C_L

open,

Dominant

See 图 6, TXD = 0 V, R_L= 50 Ω, C_L

open,

100

Supply Current Normal

Mode

I_CC

Dominant with

bus Fault

See 图 6, TXD = 0 V, STBx = 0 V, CANH

= –25 V, R_L= open, C_L= open

180

See 图 6, TXD = V_CC, R_L= 60 Ω, C_L

open, R_CM= open, S or STB = 0 V

Recessive

Under voltage detection on V_CCfor protected mode

Hysteresis voltage

3.5

1.3

4.4

UV_VCC

UV_VIO

200

115

268

Under voltage detection on V_IOfor protected mode

2.7

V_CC= V_IO= 5 V, T_J= 25℃, R_L= 60 Ω, Input to TXD at 250

kHz, 25% duty cycle square wave, C_{L_RXD}= 15 pF. Typical

CAN operating conditions at 500 kbps with 25% transmission

(domiant) rate.

Average Power

Dissapation

P_D

V_CC= V_IO= 5.5 V, T_J= 150℃, R_L= 50 Ω. Input to TXD at

500 kHz, 50% duty cycle square wave, C_{L_RXD}= 15 pF.

Typical high load CAN operating conditions at 1 Mbps with

50% transmission (domiant) rate and loaded network.

Thermal Shutdown Temperature

Thermal Shutdown Hysterisis

185

℃

6.7 AC and DC Electrical Characteristics

All typical values are at 25°C and supply voltages of V_CC= 5 V. R_L= 60 Ω over operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Driver Electrical Characteristics

CANH

CANL

2.75

0.5

4.5

Bus output voltage

(dominant)

See 图 8 and 图 9, TXD = 0 V, R_L= 60 Ω,

C_L= open, R_CM= open

V_O(D)

2.25

See 图 6 and 图 9, TXD = V_CC, R_L= open

(no load), R_CM= open

V_O(R)

Bus output voltage (recessive)

0.5 x V_CC

See 图 6 and 图 9, TXD = 0 V, 50 Ω ≤ R_L

≤ 65 Ω, C_L= open, R_CM= open

1.5

4.75 V ≤ V_CC≤ 5.25 V

V_OD(D)

Differential output voltage (dominant)

See 图 6 and 图 9, TXD = 0 V, 50 Ω ≤ R_L

≤ 65 Ω, C_L= open, R_CM= open

1.3

3.2

4.5 V ≤ V_CC≤ 5.5 V

See 图 6 and 图 9, TXD = V_CC, R_L= 60

Ω, C_L= open, R_CM= open

–120

–50

V_OD(R)

Differential output voltage (recessive)

See图 6 and 图 9,TXD = V_CC, R_L= open,

C_L= open, R_CM= open

Output symmetry (dominant or recessive)

See 图 6 and 图 9, R_L= 60 Ω, C_L= open,

R_CM= open

V_SYM

–400

–115

400

(V_CC- V_O(CANH)- V_O(CANL)

)

See 图 6 and 图 12, V_{(CAN_H)}≤ –5 V,

CANL = open, TXD = 0 V

Short-circuit steady-state output current,

Dominant

I_OS(DOM)

See 图 6 and 图 12, V_{(CAN_L)}= 40 V,

CANH = open, TXD = 0 V

115

Short-circuit steady-state output current,

Recessive

See 图 6 and 图 12, –27 V ≤ V_BUS≤ 32 V,

V_BUS= CANH = CANL

I_OS(REC)

–5

Receiver Electrical Characteristics

V_IT

Input threshold voltage

500

–12

900

V_HYS

V_CM

Hysteresis voltage for input threshold

Common Mode Range

See 图 10

120

I_IOFF(LKG)

Power-off (unpowered) bus input leakage CANH = CANL = 5 V, V_CCto GND via 0

current

µA

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

AC and DC Electrical Characteristics (continued)

All typical values are at 25°C and supply voltages of V_CC= 5 V. R_L= 60 Ω over operating free-air temperature range (unless

otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

C_I

Input capacitance to ground (CANH or

CANL)

C_ID

R_ID

Differential input capacitance

Differential input resistance

TXD = V_CC= V_IO

kΩ

Single Ended Input resistance

(CANH or CANL)

R_IN

kΩ

Input resistance matching:

[1 – (R_IN(CANH)/ R_IN(CANL))] × 100 %

R_IN(M)

V_{(CAN_H)}= V_{(CAN_L)}= 5 V

–1%

2.8

V_IOPIN

V_IO

Supply voltage on V_IOpin

Supply current on V_IOpin

5.5

350

RXD pin floating, TXD = 0 V

RXD pin floating, TXD = 5

µA

I_IO

TXD Terminal (CAN Transmit Data Input)

V_IH

V_IL

High-level input voltage

0.7V_IO

Low-level input voltage

0.3V_IO

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

Input Capacitance

V_TXD= V_IO= V_CC= 5.5 V

–2.5

–200

–1

–6

µA

I_IL

V_TXD= 0 V, V_CC= 5.5 V

I_LKG(OFF)

C_I

V_TXD= 5.5 V, V_IO= V_CC= 0 V

V_IN= 0.4 x sin(2 x M x 2 x 10⁶x t) + 2.5

RXD Pin (CAN Receive Data Output)

V_OH

High-level input voltage

Low-level input voltage

Unpowered leakage current

See 图 10, I_O= –2 mA

0.8V_IO

–1

V_OL

See 图 10, I_O= –2 mA

0.2V_IO

I_LKG(OFF)

V_RXD= 5.5 V, V_IO= V_CC= 0 V

µA

SW Pin (Polarity Switch Input)

V_IH

High-level input voltage

0.7V_IO

V_IL

Low-level input voltage

0.3V_IO

I_IH

High-level input leakage current

Low-level input leakage current

Unpowered leakage current

SW = V_IO= V_CC= 5.5 V

SW = 0 V, V_CC= 5.5 V

0.5

–1

µA

I_IL

I_LKG(OFF)

SW = 5.5 V, V_IO= V_CC= 0 V

6.8 Timing Requirements

MIN

NOM

MAX

UNIT

Switching Characteristics

Propagation delay time,

high TXD to Driver Recessive

t_pHR

t_pLD

See 图 9,

Typical Conditions for DS: R_L

60 Ω, C_L= 100 pF, R_CM= open

Propagation delay time,

low TXD to Driver Dominant

t_sk(p)

Pulse skew (|t_pHR- t_pLD|)

t_R

Differential output signal rise time

Differential output signal fall time

Dominant time out⁽¹⁾

t_F

t_{TXD_DTO}

See 图 13, R_L= 60 Ω, C_L= open

1.2

(1) The TXD dominant time out (t_{TXD_DTO}) disables the driver of the transceiver once the TXD has been dominant longer than t_{TXD_DTO}

which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit

dominant again after TXD has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it

limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD) for the worst

case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_{TXD_DTO}minimum, limits the

minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t_{TXD_DTO}= 11 bits / 1.2 ms = 9.2 kbps.

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

Timing Requirements (continued)

MIN

NOM

MAX

UNIT

Propagation delay time, bus recessive input

to high RXD_INT output

t_pRH

t_pDL

See 图 10 C_L(RXD)= 15 pF

Typical Conditions for DS: CANL

= 1.5 V, CANH = 3.5 V

Propagation delay time, bus dominant input

to RXD low output

t_R

t_F

Differential output signal rise time

Differential output signal fall time

Device Switching Characteristics

Total loop delay, driver input (TXD) to

receiver output (RXD), recessive to

dominant⁽²⁾

See 图 10 Typical Conditions: R_L

= 60 Ω, C_L= 100 pF, C_L(RXD)= 15

t_(LOOP1)

t_(LOOP2)

150

Total loop delay, driver input (TXD) to

receiver output (RXD), dominant to

receissive⁽²⁾

See 图 10 Typical Conditions: R_L

= 60 Ω, C_L= 100 pF, C_L(RXD)= 15

Mode change time from normal

configuration to reverse

t_MODE

300

µs

See 图 10. Time for device to

return to normal operation from

UV_VCCand UV_VIOunder voltage

event

t_{UV_RE-ENABLE}

Re-enable time after UV event

(2) Time span from signal edge on TXD input to next signal edge with same polarity on RXD output, the maximum of delay of both signal

edges is to be considered.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

6.9 Typical Characteristics

2.5

V_ODvs T ; SW = 0

V_ODvs T ; SW = 1

1.5

0.5

V_ODvs V_CC: SW = 0

V_ODvs V_CC: SW = 1

-50

100

150

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

SLLS

Temperature (èC)

V_CC(V)

SLLS

V_CC= 5 V

C_L= Open

V_IO= 5 V

R_CM= Open

R_L= 60Ω

SW = 0 / 1

C_L= Open

V_IO= 5 V

R_L= 60Ω

R_CM= Open

Temp = 25°C

图 1. V_OD(D)over Temperature

图 2. V_OD(D)over V_CCSupply Voltage

13.4

13.3

13.2

13.1

100

I_CCRecessive : SW = 0

I_CCRecessive : SW = 1

12.9

12.8

12.7

12.6

SW=0

SW=1

-40

-20

100 120 140

-50

100

150

Temperature (èC)

SLLS

V_CC= 5 V

C_L= Open

V_IO= 5 V

R_L= 60Ω

V_CC= 5 V

C_L= Open

V_IO= 5 V

R_L= 60Ω

SW = 0 / 1

R_CM= Open

SW = 0 / 1

R_CM= Open

图 3. I_CCover Temperature

图 4. Dominant to Recessive T_LOOPover Temperature

SW = 0

SW = 1

-50

Temperature (èC)

100

150

SLLS

V_CC= 5 V

C_L= Open

V_IO= 5 V

R_CM= Open

R_L= 60 Ω

SW = 0 / 1

图 5. Recessive to Dominant T_LOOPvs Temperature

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

7 Parameter Measurement Information

CANH

V_OD(D)

V_OD(R)

CANL

Time, t

Recessive

Logic H

Dominant

Logic L

Recessive

Logic H

图 6. Bus States (Physical Bit Representation)

10 ꢀ

CANH

V_CC/ 2

RXD

10 ꢀ

CANL

图 7. Common Mode Bias Unit and Receiver

CANH

TXD

R_L

C_L

CANL

图 8. Supply Test Circuit

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

Parameter Measurement Information (接下页)

R_CM

CANH

R_L

V_CC

50%

TXD

0 V

C_L

V_OD

V_CM

V_O(CANH)

t_pLD

t_pHR

90%

CANL

R_CM

0.9 V

V_O(CANL)

V_OD

0.5 V

10%

t_R

t_F

图 9. Driver Test Circuit and Measurement

CANH

1.5 V

RXD

I_O

0.9 V

V_ID

0.5 V

0 V

V_OH

V_ID

t_pDL

t_pRH

V_O

C_{L_RXD}

CANL

90%

70%

V_O(RXD)

30%

10%

V_OL

t_F

t_R

图 10. Receiver Test Circuit and Measurement

5 V

CANH

4.4 V

TXD

V_SUP

0 V

C_L

3.8V

t_{UV_RE-ENABLE}

CANL

STB

0 V

70%

Hi Z

RXD V_O

RXD

30%

V_O

C_{L_RXD}

图 11. UV Re-enable Time after UV Event

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

Parameter Measurement Information (接下页)

CANH

V_I

TXD

V_I

t_LOOP

Falling

edge

C_L

R_L

70%

TXD

30%

CANL

STB

0 V

5 x t_BIT(TXD)

t_BIT(TXD)

RXD

t_BIT(Bus)

V_O

C_{L_RXD}

900 mV

V_Diff

500 mV

V_OH

70%

RXD

30%

V_OL

t_LOOP

rising

edge

t_BIT(RXD)

图 12. Transmitter and Receiver Timing Behavior Test Circuit and Measurement

CANH

V_IH

TXD

30%

TXD

R_L

C_L

V_OD

0 V

V_OD(D)

CANL

0.9 V

V_OD

0.5 V

0 V

t_{TXD_DTO}

图 13. TXD_INT Dominant Time Out Test Circuit and Measurement

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

Parameter Measurement Information (接下页)

200 ꢀs

I_OS

CANH

TXD

V_BUS

I_OS

CANL

V_BUS

0 V

V_BUS

图 14. Driver Short-Circuit Current Test and Measurement

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

8 Detailed Description

8.1 Overview

The TCAN4420 is a high-speed CAN transceiver that meets the specifications of the ISO 11898-2 (2016) High

Speed CAN (Controller Are Network) physical layer standards. It includes many protection features providing

device and CAN network robustness. It also allows for the polarity of the CAN pins to be controlled externally by

a micro-controller through the use of the polarity switch pin, SW.

The CAN bus has two logical states during operation: recessive and dominant. See 图 6 and 图 7.

A recessive bus state occurs when the bus is biased to a common mode of V_CC/2 via the receivers bias unit.

Recessive is equivalent to logic high on the TXD pin and is typically a differential voltage on the bus of

approximately 0 V.

A dominant bus state occurs when the bus is driven differentially by one or more drivers. The driver produces a

current which flows through the termination resistors on the bus and generates a differential voltage. Dominant is

equivalent to logic low on the TXD pin and is a differential voltage on the bus greater than the minimum required

threshold for a CAN dominant.

The host microprocessor of the CAN node uses the TXD terminal, pin 1, to drive the bus and receives data from

the bus via the RXD terminal, pin 4. The TCAN4420 integrates level shifting capabilities into the RXD output via

the V_IOpin. This feature eliminates the need for an additional level shifter between the host microprocessor and

the RXD output of the CAN transceiver.

8.2 Functional Block Diagrams

V_IO

V_CC

V_IO

V_CC

CANH

CANL

V_CC

Dominant

Time Out

DRIVER

TXD

Over

Temp.

Mode and

Control Logic

Polarity

Control

Under

Voltage

V_IO

V_CC

Logic

Output

RXD

GND

8.3 Feature Description

8.3.1 TXD Dominant Time Out (DTO)

The TXD DTO circuit prevents the local node from blocking network communication in event of a hardware or

software failure where TXD is held dominant longer than the time out period t_{TXD_DTO}. The DTO circuit timer

starts on a falling edge on TXD. The DTO circuit disables the CAN bus driver if no rising edge is seen before the

timeout period expires. This frees the bus for communication between other nodes on the network. The CAN

driver is re-activated when a recessive signal is seen on the TXD terminal, thus clearing the TXD DTO condition.

The receiver and RXD terminal still reflect activity on the CAN bus, and the bus terminals are biased to the

recessive level during a TXD dominant timeout.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

Feature Description (接下页)

8.3.2 CAN Bus Short Circuit Current Limiting

The TCAN4420 has several protection features that limit the short circuit current when a CAN bus line is shorted.

These include CAN driver current limiting (dominant and recessive). During CAN communication the bus

switches between dominant and recessive states, thus the short circuit current may be viewed either as the

current during each bus state or as a DC average current. For system current and power considerations in the

termination resistors and common mode choke ratings the average short circuit current should be used. The

percentage dominant is limited by the TXD dominant time out and CAN protocol which has forced state changes

and recessive bits such as bit stuffing, control fields, and inter frame space. These ensure there is a minimum

recessive amount of time on the bus even if the data field contains a high percentage of dominant bits.

The short circuit current of the bus depends on the ratio of recessive to dominant bits and their respective short

circuit currents. The average short circuit current may be calculated using 公式 1.

I_OS(AVG)= %Transmit x [(%REC_Bits x I_{OS(SS)_REC}) + (%DOM_Bits x I_{OS(SS)_DOM})] + [%Receive x I_{OS(SS)_REC}

]

(1)

Where:

•

I_OS(AVG)is the average short circuit current

%Transmit is the percentage the node is transmitting CAN messages

%Receive is the percentage the node is receiving CAN messages

%REC_Bits is the percentage of recessive bits in the transmitted CAN messages

%DOM_Bits is the percentage of dominant bits in the transmitted CAN messages,

I_{OS(SS)_REC}is the recessive steady state short circuit current

I_{OS(SS)_DOM}is the dominant steady state short circuit current.

注

The short circuit current and possible fault cases of the network should be taken into

consideration when sizing the power ratings of the termination resistance, other network

components, and the power supply used to generate V_CC

8.3.3 Thermal Shutdown

If the junction temperature of the device exceeds the thermal shut down threshold of 170ºC the device turns off

the CAN driver circuitry thus blocking the TXD to bus transmission path. The shutdown condition is cleared when

the junction temperature of the device drops below the thermal shutdown temperature of the device. If the fault

condition that caused the thermal shutdown is still present, the temperature may rise again and the device enters

thermal shut down again. Prolonged operation with thermal shutdown conditions may affect device reliability. The

thermal shutdown circuit includes hysteresis to avoid oscillation of the driver output.

注

During thermal shutdown the CAN bus driver is turned off thus no transmission is possible

from TXD to the bus. The CAN bus terminals are biased to recessive level during a

thermal shutdown, and the receiver to RXD path remains operational.

8.3.4 Under Voltage Lockout (UVLO) and Unpowered Device

The V_CCand V_IOsupply terminals have under voltage detection circuitry which places the device in a protected

mode if an under voltage fault occurs. This protects the bus during an under voltage event on these terminals. If

V_IOis under voltage the RXD terminal is tri-stated (high impedance) and the device does not pass any signals

from the bus. If V_CCsupply is lost, or has a brown out that triggers the UVLO, the device transitions to a

protected mode. See 表 1.

If V_IOdrops below UV_VIOunder voltage detection, the transceiver switches off and disengage from the bus until

V_IOhas recovered.

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

Feature Description (接下页)

The device is designed to be an "ideal passive" or “no load” to the CAN bus if the device is unpowered. The bus

terminals (CANH, CANL) have extremely low leakage currents when the device is unpowered, so they do not

load the bus. This is critical if some nodes of the network are unpowered while the rest of the of network remains

operational. Logic terminals also have low leakage currents when the device is unpowered, so they do not load

other circuits which may remain powered.

表 1. Under Voltage Lockout Protection

V_CC

V_IO

DEVICE STATE

Normal

BUS

RXD

> UV_VCC

< UV_VCC

> UV_VCC

< UV_VCC

> UV_VIO

< UV_VIO

Per TXD

Mirrors Bus

Protected

High Impedance

High (Recessive)

High Impedance

space

注

Once an under voltage condition is cleared and the V_CCsupply has returned to valid level

the device typically needs t_MODEto transition to normal operation. The host processor

should not attempt to send or receive messages until this transition time has expired.

8.3.4.1 V_IOSupply PIN

A separate V_IOsupply pin is supported on this device. This pin should be connected to the supply voltage of the

microcontroller, see 图 17 and 图 18. This sets the signal levels for TXD, RXD and SW pins to the I/O level of the

microcontroller.

8.4 Device Functional Modes

8.4.1 Polarity Configuration

The device supports two polarity configurations on the CAN pins. For a conventional (normal) CAN connection,

connect SW pin to GND. Allow for a time interval equal to t_MODEafter changing the SW pin, before reading the

bus or the RXD pin. To support a reverse connection of the CAN pins, connect the SW pin to V_IO. This approach

enables compatibility with existing boards that already use this pin (pin 8) to be connected to GND for normal

operation. See 表 2.

表 2. Polarity Configurations

SW Pin

LOW

Device Polarity

Normal

V_OD(TX) or V_ID(RX)

= CANH-CANL

HIGH

Reverse

= CANL-CANH

8.4.2 Normal Polarity Mode

This is the normal configuration of the device. The CAN driver and receiver are fully operational and CAN

communication is bi-directional. The driver is translating a digital input on TXD to a differential output on CANH

and CANL. The receiver is translating the differential signal from CANH and CANL to a digital output on RXD.

Normal Mode is enabled when there is a logic low on the SW pin.

8.4.3 Reverse Polarity Mode

The TCAN4420 supports a reverse polarity configuration when the SW pin is connected to supply. In this

configuration, both the driver and receiver remain fully operational, the key difference being that both V_ODand V_ID

are now defined as the difference between CANL and CANH pins as indicated in 表 2. Also see Table 表 3 and

表 4 for the pin voltage levels in this configuration.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

8.4.4 Driver and Receiver Function

The digital logic input and output levels for these devices are TTL levels with respect to V_IOfor compatibility with

protocol controllers having 2.8 V to 5 V logic or I/O.

表 3 and 表 4 provide the states of the CAN driver and CAN receiver in each mode.

表 3. Driver Function Table

BUS OUTPUTS⁽²⁾

DRIVEN BUS

DEVICE MODE

TXD INPUT⁽¹⁾

STATE⁽³⁾

CANH

CANL

Dominant

Biased Recessive

Dominant

Normal

H or Open

Reverse

H or Open

Biased Recessive

(1) H = high level, L = low level

(2) H = high level, L = low level, Z = high Z receiver bias

(3) For Bus state and bias see 图 7

表 4. Receiver Function Table

CAN DIFFERENTIAL INPUTS

DEVICE MODE

BUS STATE

RXD TERMINAL⁽¹⁾

V_ID= V_CANH– V_CANL

V_ID≥ 0.9 V

Dominant

Undefined

Recessive

Undefined

Normal: V_ID= V_CANH– V_CANL

Reverse: V_ID= V_CANL– V_CANH

0.5 V < V_ID< 0.9 V

V_ID≤ 0.5 V

(1) H = high level, L = low level

8.4.5 Floating Terminals

The TCAN4420 has internal pull ups and pull downs on critical terminals to place the device into known states if

the terminal floats. See 表 5 for details on terminal bias conditions

表 5. Terminal Bias

TERMINAL

PULL UP or PULL DOWN

COMMENT

Weakly biases TXD toward recessive to prevent bus blockage or

TXD DTO triggering

TXD

Pull up

Weakly biases SW terminal towards GND to use the default (normal)

polarity configuration

Pull down

space

注

The internal bias should not be relied upon as only termination, especially in noisy

environments but should be considered a failsafe protection. Special care needs to be

taken when the device is used with MCUs which implement open drain outputs. TXD is

weakly internally pulled up. The TXD pull up strength and CAN bit timing require special

consideration when this device is used with an open drain TXD output on the

microprocessor CAN controller. An adequate external pull up resistor must be used to

ensure that the TXD output of the microprocessor maintains adequate bit timing input to

the CAN transceiver.

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

9 Application and Implementation

注

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

9.1 Application Information

These CAN transceivers are typically used in applications with a host microprocessor or FPGA that includes the

data link layer portion of the CAN protocol. Below are typical application configurations for both 5 V and 3.3 V

microprocessor applications. The bus termination is shown for illustrative purposes.

9.2 Typical Application

图 15. Typical CAN Bus Application

9.2.1 Design Requirements

9.2.1.1 Bus Loading, Length and Number of Nodes

A typical CAN application can have a maximum bus length of 40 meters and maximum stub length of 0.3 m.

However, with careful design, users can have longer cables, longer stub lengths, and many more nodes to a bus.

A high number of nodes require a transceiver with high input impedance such as the TCAN4420 transceiver.

Many CAN organizations and standards have scaled the use of CAN for applications outside the original

ISO11898-2 standard. They made system level trade off decisions for data rate, cable length, and parasitic

loading of the bus. Examples of these CAN systems level specifications are ARINC825, CANopen, DeviceNet,

SAE J2284, SAE J1939, and NMEA 2000.

A CAN network system design is a series of tradeoffs. In ISO 11898-2 the driver differential output is specified

with a 60-Ω bus load where the differential output must be greater than 1.5 V. The TCAN4420 is specified to

meet the 1.5 V requirement across this load and is specified to meet 1.3-V differential output at 50-Ω bus load.

The differential input resistance of this family of transceiver is a minimum of 20 kΩ. If 67 of these transceivers are

in parallel on a bus, this is equivalent to an 300-Ω differential load in parallel with the 60 Ω bus termination which

gives a total bus load of 50 Ω. Therefore, this family theoretically supports over 67 transceivers on a single bus

segment with margin to the 0.9-V minimum differential input voltage requirement at each receiving node.

However, for network design, margin must be given for signal loss across the system and cabling, parasitic

loadings, timing, network imbalances, ground offsets and signal integrity thus a practical maximum number of

nodes is much lower. Bus length may also be extended beyond 40 meters by careful system design and data

rate tradeoffs. For example CANopen network design guidelines allow the network to be up to 1 km with changes

in the termination resistance, cabling, less than 64 nodes on the bus, and significantly lowered data rate.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

Typical Application (接下页)

This flexibility in network design is one of its key strengths allowing for these system level network extensions

and additional standards to build on the typical CAN bus length parameters. However, when using this flexibility

the network system designer must take the responsibility of good network design to ensure robust network

operation.

9.2.2 Detailed Design Procedure

9.2.2.1 CAN Termination

The ISO 11898 standard specifies the interconnect to be a twisted-pair cable (shielded or unshielded) with 120-Ω

characteristic impedance (Z_O). Resistors equal to the characteristic impedance of the line must be used to

terminate both ends of the cable to prevent signal reflections. Unterminated drop lines, stubs, connecting nodes

to the bus must be kept as short as possible to minimize signal reflections. The termination may be on the cable

or in a node, but if nodes may be removed from the bus, the termination must be carefully placed so that it is not

removed from the bus

Termination may be a single 120-Ω resistor at the end of the bus either on the cable or in a terminating node. If

filtering and stabilization of the common mode voltage of the bus is desired, then split termination may be used,

see 图 16. Split termination improves the electromagnetic emissions behavior of the network by eliminating

fluctuations in the bus common-mode voltages.

Split Termination

Standard Termination

CANH

R_TERM/2

CAN

Transceiver

CAN

Transceiver

R_TERM

C_SPLIT

R_TERM/2

CANL

图 16. CAN Bus Termination Concepts

The TCAN4420 transceiver supports both 5-V only applications and applications where level shifting is needed

for a 3.3-V microcontroller. See 图 17 and 图 18 for application examples.

TCAN4420

ZHCSH93 –DECEMBER 2017

Typical Application (接下页)

www.ti.com.cn

5-V Voltage

Regulator

V_OUT

V_IN

(e.g. TPSxxxx)

V_CC

V_IO

V_CC

GPIO1

5-V MCU

CANH

TCAN4420 CAN

Transceiver

RXD

TXD

RXD

TXD

With Polarity

Control

CANL

Optional:

Terminating

Node

GND

Optional:

Filtering,

Transient and ESD

图 17. Typical CAN Bus Application Using TCAN4420 with 5 V µC

3-V Voltage

V_OUT

V_IN

Regulator

(e.g. TPSxxxx)

5-V Voltage

V_OUT

Regulator

V_IN

(e.g. TPSxxxx)

V_CC

V_IO

V_CC

GPIO1

3-V MCU

CANH

TCAN4420 CAN

Transceiver

RXD

TXD

RXD

TXD

With Polarity

Control

CANL

Optional:

Terminating

Node

GND

Optional:

Filtering,

Transient and ESD

图 18. Typical CAN Application Using TCAN4420 with 3.3 V µC

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

Typical Application (接下页)

9.2.3 Application Curves

I_CCDominant vs V_CC: SW = 0

I_CCDominant vs V_CC: SW = 1

4.5 4.6 4.7 4.8 4.9

5.1 5.2 5.3 5.4 5.5

V_CC(V)

SLLS

图 19. I_CCDominant Current over V_CCSupply Voltage

10 Power Supply Recommendations

The TCAN4420 device is designed to operate with a main V_CCinput voltage supply range between 4.5 V and

5.5 V. The device also has an IO level shifting supply input, V_IO, designed for a range between 2.8 V and

5.5 V. To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a

100-nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage

ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance

and inductance of the PCB power planes.

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

11 Layout

Robust and reliable bus node design often requires the use of external transient protection devices in order to

protect against transients that may occur in industrial environments. Since these transients have a wide

frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be

applied during PCB design.

11.1 Layout Guidelines

•

Place the protection and filtering circuitry as close to the bus connector, J1, to prevent transients, ESD and

noise from propagating onto the board. In this layout example a transient voltage suppression (TVS) device,

D1, has been used for added protection. The production solution can be either bi-directional TVS diode or

varistor with ratings matching the application requirements. This example also shows optional bus filter

capacitors C3 and C4. Additionally (not shown) a series common mode choke (CMC) can be placed on the

CANH and CANL lines between the TCAN4420 transceiver and connector J1.

•

Design the bus protection components in the direction of the signal path. Do not force the transient current to

divert from the signal path to reach the protection device.

Use supply (V_CC) and ground planes to provide low inductance.

注

High-frequency currents follows the path of least impedance and not the path of least

resistance.

•

Use at least two vias for supply (V_CC) and ground connections of bypass capacitors and protection devices to

minimize trace and via inductance.

Bypass capacitors should be placed as close as possible to the supply terminals of transceiver, examples are

C1 on the V_CCsupply and C5 on the V_IOsupply.

Bus termination: this layout example shows split termination. This is where the termination is split into two

resistors, R6 and R7, with the center or split tap of the termination connected to ground via capacitor C2. Split

termination provides common mode filtering for the bus. When bus termination is placed on the board instead

of directly on the bus, additional care must be taken to ensure the terminating node is not removed from the

bus thus also removing the termination. See the application section for information on power ratings needed

for the termination resistor(s).

•

To limit current of digital lines, serial resistors may be used. Examples are R2, R3, and R4. These are not

required.

Pin 1: R1 is shown optionally for the TXD input of the device. If an open drain host processor is used, this is

mandatory to ensure the bit timing into the device is met.

Pin 5: A bypass capacitor should be placed as close to the pin as possible (example C5). A voltage must be

applied to the V_IOfor normal operation.

Pin 8: is shows the SW terminal with R4 and R5 as optional resistors. The SW terminal can also be tied to an

IO for soft polarity configuration.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

11.2 Layout Example

图 20. Example Layout

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

12 器件和文档支持

12.1 器件支持

该器件将遵循以下 CAN 标准。本系统规格涵盖了所需的核心内容；但是，应为这些标准提供参考，并指出和探讨

所有分歧之处。本文档应提供所需的全部基本内容。但是，由于详细的 CAN 协议范围不在此物理层（收发器）规

格范围之内，这些额外的资源对全面了解 CAN（包括协议）非常有帮助。

12.1.1 器件命名规则

CAN 收发器物理层标准：

•

ISO11898-2 高速媒介访问单元（原高速 CAN 收发器标准）

具有低功耗模式的 ISO11898-5 高速媒介访问单元（取代了 ISO11898-2 标准规范中的若干电气规格，并增加

了在低功耗模式下通过总线实现原始唤醒功能）。

一致性测试要求：

•

A Comprehensible Guide to Controller Area Network”, Wilfried Voss, Copperhill Media Corporation

"CAN System Engineering: From Theory to Practical Applications”, 2nd Edition, 2013; Dr. Wolfhard Lawrenz,

Springer.

12.2 接收文档更新通知

如需接收文档更新通知，请导航至 TI.com 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产

品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.3 社区资源

下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，

并且不一定反映 TI 的观点；请参阅 TI 的《使用条款》。

TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在

e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。

设计支持

TI 参考设计支持可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

12.4 商标

E2E is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

12.5 静电放电警告

ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可

能会损坏集成电路。

ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可

能会导致器件与其发布的规格不相符。

12.6 Glossary

SLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

13 机械、封装和可订购信息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知和修

订此文档。如欲获取此数据表的浏览器版本，请参阅左侧的导航。

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

PACKAGE OUTLINE

D0008B

SOIC - 1.75 mm max height

SCALE 2.800

SOIC

SEATING PLANE

.228-.244 TYP

[5.80-6.19]

.004 [0.1] C

PIN 1 ID AREA

6X .050

[1.27]

.189-.197

[4.81-5.00]

NOTE 3

.150

[3.81]

8X .012-.020

[0.31-0.51]

.150-.157

[3.81-3.98]

NOTE 4

.069 MAX

[1.75]

.010 [0.25]

C A

.005-.010 TYP

[0.13-0.25]

SEE DETAIL A

.010

[0.25]

.004-.010

[0.11-0.25]

0 - 8

.016-.050

[0.41-1.27]

DETAIL A

TYPICAL

.041

[1.04]

4221445/B 04/2014

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.

Dimensioning and tolerancing per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed .006 [0.15], per side.

4. This dimension does not include interlead flash.

5. Reference JEDEC registration MS-012, variation AA.

www.ti.com

TCAN4420

www.ti.com.cn

ZHCSH93 –DECEMBER 2017

EXAMPLE BOARD LAYOUT

D0008B

SOIC - 1.75 mm max height

SOIC

8X (.055)

[1.4]

8X (.061 )

[1.55]

SEE

DETAILS

SEE

DETAILS

SYMM

8X (.024)

[0.6]

8X (.024)

[0.6]

SYMM

6X (.050 )

[1.27]

6X (.050 )

[1.27]

(.213)

[5.4]

(.217)

[5.5]

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK

OPENING

SOLDER MASK

OPENING

METAL

.0028 MAX

[0.07]

ALL AROUND

.0028 MIN

[0.07]

ALL AROUND

SOLDER MASK

DEFINED

NON SOLDER MASK

DEFINED

SOLDER MASK DETAILS

4221445/B 04/2014

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com

TCAN4420

ZHCSH93 –DECEMBER 2017

www.ti.com.cn

EXAMPLE STENCIL DESIGN

D0008B

SOIC - 1.75 mm max height

SOIC

8X (.061 )

[1.55]

8X (.055)

[1.4]

SYMM

8X (.024)

[0.6]

8X (.024)

[0.6]

SYMM

6X (.050 )

[1.27]

6X (.050 )

[1.27]

(.217)

[5.5]

(.213)

[5.4]

HV / ISOLATION OPTION

.162 [4.1] CLEARANCE / CREEPAGE

IPC-7351 NOMINAL

.150 [3.85] CLEARANCE / CREEPAGE

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.127 MM] THICK STENCIL

SCALE:6X

4221445/B 04/2014

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

www.ti.com

PACKAGE OPTION ADDENDUM

www.ti.com

10-Dec-2020

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

TCAN4420DR

ACTIVE

SOIC

2500 RoHS & Green

NIPDAU

Level-2-260C-1 YEAR

-40 to 125

4420

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TCAN4420DR

SOIC

2500

330.0

15.4

6.4

5.2

2.1

8.0

12.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

4-Jan-2018

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC

SPQ

Length (mm) Width (mm) Height (mm)

336.6 336.6 41.3

TCAN4420DR

2500

Pack Materials-Page 2

重要声明和免责声明

TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资

源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示

担保。

所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、

验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用

所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权

许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。

TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约

束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE

邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122

TCAN4420 [TI]

相关型号：

TCAN4420DR

TCAN4550

TCAN4550-Q1

TCAN4550RGYR

TCAN4550RGYRQ1

TCAN4550RGYT

TCAN4550RGYTQ1

TCAN4551-Q1

TCAN4551RGYRQ1

TCAQ22340HDH

TCAW-T10-N05

TCB100