TDA2EG-17 [TI]
适用于 ADAS 应用且具有图形和视频加速功能的 SoC 处理器（17mm 封装）;
| 型号： | TDA2EG-17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 适用于 ADAS 应用且具有图形和视频加速功能的 SoC 处理器（17mm 封装） |
| 文件： | 总400页 (文件大小：5005K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
适用于高级驾驶员辅助系统 (ADAS)
的 TDA2Ex SoC 17mm 封装（CBD 封装）
1 器件概述
1.1 特性
1
• 专为 ADAS 应用设计的 架构
• 支持视频、图像和图形处理
– 全高清视频（1920 × 1080p，60fps）
– 多个视频输入和视频输出
• Arm® Cortex®-A15 微处理器子系统
• 32 位 MPU 看门狗计时器
• 六个高速集成电路间 (I2C) 端口
• 10 个可配置 UART/IrDA/CIR 模块
• 4 个多通道串行外设接口 (McSPI)
• 四路 SPI 接口 (QSPI)
• C66x 浮点超长指令字 (VLIW) 数字信号处理器
• 8 个多通道音频串行端口 (McASP) 模块
• 超高速 USB 3.0 双角色设备
• 高速 USB 2.0 双角色设备
(DSP)
– 目标代码与 C67x 和 C64x+ 完全兼容
– 每周期最多 32 次 16 x 16 位定点乘法
• 高达 512KB 的片上 L3 RAM
• 3 级 (L3) 和 4 级 (L4) 互连
• DDR3/DDR3L 存储器接口 (EMIF) 模块
– 最高支持 DDR-1333 (667MHz)
– 高达 2GB 的单芯片选择
• Arm® Cortex®-M4 双核图像处理单元 (IPU)
• IVA-HD 子系统
• 显示子系统
– 带有 DMA 引擎和多达三条管线的显示控制器
– HDMI™编码器：兼容 HDMI 1.4a 和 DVI 1.0
• 单核 PowerVR®SGX544 3D GPU
• 2D 图形加速器 (BB2D) 子系统
– Vivante®GC320 内核
• 高速 USB 2.0 On-The-Go
• 四个多媒体卡/安全数字/安全数字输入输出接口
( MMC™/ SD®/SDIO)
• 带有两个 5Gbps 通道的 PCI Express®具有集成型
PHY 的 3.0 端口
– 1 个与第 2 代兼容的双通道端口
– 或 2 个与第 2 代兼容的单通道端口
• 双控制器局域网 (DCAN) 模块
– CAN 2.0B 协议
• MIPI®CSI-2 摄像头串行接口
• 多达 186 个通用 I/O (GPIO) 引脚
• 器件安全 特性
– 硬件加密加速器和 DMA
– 防火墙
– JTAG 锁定
• 视频处理引擎 (VPE)
– 安全密钥
– 安全 ROM 和引导
– 客户可编程的秘钥
• 一个视频输入端口 (VIP) 模块
– 支持多达 4 个复用输入端口
• 通用存储器控制器 (GPMC)
• 电源、复位和时钟管理
• 片上调试，采用 CTool 技术
• 28nm CMOS 技术
• 增强型直接存储器存取 (EDMA) 控制器
• 2 端口千兆以太网 (GMAC)
– 最多 2 个外部端口，1 个内部端口
• 16 个 32 位通用计时器
• 17mm × 17mm，0.65mm 间距，538 引脚 BGA
(CBD)
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SPRS969
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
1.2 应用
•
低压差分信令 (LVDS) 或以太网环视系统
•
传感器融合 – 视觉、雷达、超声波和激光雷达传感
器
–
–
–
–
–
–
3D 环视
–
–
物体数据融合
原始数据融合
车后物体检测
泊车辅助
行人检测
车道跟踪
行车记录
1.3 说明
TI 的全新 TDA2Ex 片上系统 (SoC) 是经过高度优化的可扩展系列器件，专为满足领先的高级驾驶辅助系统
(ADAS) 的要求而设计。TDA2Ex 系列集最佳的性能、低功耗和 ADAS 视觉分析处理功能于一体，可广泛应
用于当今汽车领域中的 ADAS 应用 以推动实现更自主的无碰撞驾驶体验。
TDA2Ex SoC 通过广泛的 ADAS 支持复杂的嵌入视觉技术 应用 ，包括泊车辅助、环视以及传感器融合系
统。
TDA2Ex SoC 采用异类可扩展架构，包含 TI 的定点和浮点 TMS320C66x 数字信号处理器 (DSP) 生成内
核、Arm Cortex-A15 MPCore™ 和双 Cortex-M4 处理器的组合。它集成有视频加速器，可用于解码以太网
AVB 网络中的多个视频流，并与用于渲染虚拟视图的图形加速器相结合，可以实现 3D 观影体验。TDA2Ex
SoC 还集成了诸多外设，包括支持以太网或 LVDS 环视系统的多摄像头接口（并行和串行，包括 CSI-2）、
显示屏和千兆位以太网 AVB。
此外，TI 提供了一整套针对 Arm 和 DSP 的开发工具，其中包括 C 语言编译器、用于简化编程和调度的
DSP 汇编优化器、可查看源代码执行情况的调试界面等。
每个器件都具有加密加速特性。高安全性 (HS) 器件上还提供支持的所有其他安全 特性，包括安全引导支
持、调试安全性和可信执行环境支持。有关 HS 器件的更多信息，请联系您的 TI 代表。
TDA2Ex ADAS 处理器符合 AEC-Q100 标准。
器件信息
封装
器件编号
封装尺寸
TDA2EG-17
FCBGA (538)
17.0mm × 17.0mm
2
器件概述
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
1.4 功能方框图
图 1-1 是器件的功能方框图。
TDA2Ex
CAL
CSI2
MPU
IVA HD
(1x Arm
Cortex–A15)
1080p Video
Co-Processor
IPU 1
(Dual Cortex–M4)
Display Subsystem
GPU
Secure Boot
Debug
(1x SGX544 3D)
IPU 2
(Dual Cortex–M4)
LCD2
Security
TEE
1xGFX / 3xVID
LCD3
Blend / Scale
DSP
BB2D
(HS devices)
HDMI 1.4a
(C66x Co-Processor)
(GC320 2D)
EDMA
JTAG
MMU x2
VIP x1
VPE
High-Speed Interconnect
System
Connectivity
Spinlock
Mailbox x13
GPIO x8
Timers x16
WDT
SDMA
1x USB 3.0
Dual Mode FS/HS/SS
w/ PHY
PCIe SS x2
GMAC AVB
PWM SS x3
2x USB 2.0
Dual Mode FS/HS
1x PHY, 1x ULPI
Program/Data Storage
Serial Interfaces
GPMC / ELM
(NAND/NOR/
Async)
EMIF
1x 32-bit
DDR3/DDR3L
QSPI
McASP x8
I2C x6
UART x10
McSPI x4
DCAN x2
512-KB
RAM
256-KB ROM
OCMC
MMC / SD x4
DMM
intro-001
Copyright © 2016, Texas Instruments Incorporated
图 1-1. TDA2Ex 框图
版权 © 2016–2018, Texas Instruments Incorporated
器件概述
3
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
内容
1
器件概述.................................................... 1
1.1 特性 ................................................... 1
1.2 应用 ................................................... 2
1.3 说明 ................................................... 2
1.4 功能方框图 ........................................... 3
修订历史记录............................................... 5
Device Comparison ..................................... 6
3.1 Device Comparison Table............................ 6
3.2 Related Products ..................................... 7
Terminal Configuration and Functions.............. 8
4.1 Pin Diagram .......................................... 8
4.2 Pin Attributes ......................................... 8
4.3 Signal Descriptions.................................. 56
4.4 Pin Multiplexing ..................................... 88
4.5 Connections for Unused Pins...................... 101
Specifications ......................................... 102
5.1 Absolute Maximum Ratings........................ 103
5.2 ESD Ratings ....................................... 104
5.3 Power on Hour (POH) Limits ...................... 104
5.4 Recommended Operating Conditions ............. 104
5.5 Operating Performance Points..................... 107
5.6 Power Consumption Summary .................... 126
5.7 Electrical Characteristics........................... 126
6.4 DSP Subsystem ................................... 287
6.5 IVA ................................................. 291
6.6 IPU ................................................. 291
6.7 GPU................................................ 292
6.8 BB2D............................................... 294
6.9 Memory Subsystem................................ 296
6.10 Interprocessor Communication .................... 299
6.11 Interrupt Controller................................. 300
6.12 EDMA .............................................. 301
6.13 Peripherals ......................................... 302
6.14 On-chip Debug..................................... 319
Applications, Implementation, and Layout ...... 322
7.1 Introduction ........................................ 322
7.2 Power Optimizations ............................... 323
7.3 Core Power Domains .............................. 334
7.4 Single-Ended Interfaces ........................... 345
7.5 Differential Interfaces .............................. 347
7.6 Clock Routing Guidelines .......................... 366
2
3
4
7
5
7.7
DDR3 Board Design and Layout Guidelines....... 366
8
Device and Documentation Support.............. 390
8.1 Device Nomenclature .............................. 390
8.2 Tools and Software ................................ 392
8.3 Documentation Support............................ 392
5.8
VPP Specifications for One-Time Programmable
(OTP) eFuses ...................................... 133
Thermal Resistance Characteristics for CBD
8.4
Receiving Notification of Documentation Updates. 393
8.5 Community Resources............................. 393
8.6 商标 ................................................ 393
8.7 静电放电警告....................................... 393
8.8 出口管制提示....................................... 393
8.9 术语表.............................................. 393
5.9
Package............................................ 134
5.10 Timing Requirements and Switching
Characteristics ..................................... 136
6
Detailed Description.................................. 282
6.1 Description ......................................... 282
6.2 Functional Block Diagram ......................... 282
6.3 MPU................................................ 284
9
Mechanical Packaging and Orderable
Information............................................. 394
9.1 Mechanical Data ................................... 394
4
内容
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
2 修订历史记录
Changes from May 4, 2018 to July 15, 2018 (from D Revision (May 2018) to E Revision)
Page
•
•
•
删除了部分安全引导支持信息 ....................................................................................................... 1
Updated porz, resetn and rstoutn signal descriptions in 表 4-23, PRCM Signal Descriptions ............................ 84
Updated vpp supply voltage range for normal operation in 表 5-13, Recommended Operating Conditions for
OTP eFuse Programming ........................................................................................................ 133
Updated Figure 5-5, Power-Up Sequencing ................................................................................... 138
Updated system clock names in Section 5.10.4, Clock Specifications .................................................... 145
Updated phase polarity in all QSPI timing figures............................................................................. 216
Updated note for cosmetic marks on package................................................................................. 391
•
•
•
•
版权 © 2016–2018, Texas Instruments Incorporated
修订历史记录
5
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
3 Device Comparison
3.1 Device Comparison Table
表 3-1 shows a comparison between devices, highlighting the differences.
表 3-1. Device Comparison
FEATURES
Device
TDA2EGx
Features
CTRL_WKUP_STD_FUSE_DIE_ID_2 [31:24] Base PN register bitfield value(2)
20 (0x14)
Processors/Accelerators
Speed Grades
H, D
Yes
Yes
Yes
No
Arm Single Cortex-A15 Microprocessor (MPU) Subsystem
C66x VLIW DSP
MPU core 0
DSP1
BB2D
VOUT1
VOUT2
VOUT3
HDMI
IPU1
BitBLT 2D Hardware Acceleration Engine (BB2D)
Display Subsystem
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Dual Arm Cortex-M4 Image Processing Unit (IPU)
IPU2(1)
Image Video Accelarator (IVA)
IVA
SGX544 Single-Core 3D Graphics Processing Unit (GPU)
GPU
Video Input Port (VIP)
VIP1
vin1a
vin1b
vin2a
vin2b
Video Processing Engine (VPE)
Program/Data Storage
VPE
On-Chip Shared Memory (RAM)
General-Purpose Memory Controller (GPMC)
OCMC_RAM1
GPMC
512KB
Yes
DDR3/DDR3L Memory Controller
EMIF1
up to 2GB
No
SECDED/ECC
DMM
Dynamic Memory Manager (DMM)
Peripherals
Yes
Controller Area Network (DCAN) Interface
DCAN1
Yes
DCAN2
Yes
Enhanced DMA (EDMA)
EDMA
Yes
System DMA (DMA_SYSTEM)
Ethernet Subsystem (Ethernet SS)
DMA_SYSTEM
GMAC_SW[0]
GMAC_SW[1]
GPIO
Yes
MII, RMII, or RGMII
MII, RMII, or RGMII
General-Purpose I/O (GPIO)
Inter-Integrated Circuit Interface (I2C)
System Mailbox Module
Up to 186
I2C
6
MAILBOX
CSI2_0
13
1 CLK + 2 Data
No
Camera Adaptation Layer (CAL) Camera Serial Interface 2 (CSI2)
CSI2_1
6
Device Comparison
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 3-1. Device Comparison (continued)
FEATURES
Device
TDA2EGx
Multichannel Audio Serial Port (McASP)
McASP1
McASP2
McASP3
McASP4
McASP5
McASP6
McASP7
McASP8
16 serializers
16 serializers
4 serializers
4 serializers
4 serializers
4 serializers
4 serializers
2 serializers
1x UHSI 4b
1x eMMC™ 8b
1x SDIO 8b
1x SDIO 4b
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface
(MMC/SD/SDIO)
MMC1
MMC2
MMC3
MMC4
PCI Express 3.0 Port with Integrated PHY
PCIe_SS1
Up to two lanes (second lane
shared with PCIe_SS2 and USB1)
PCIe_SS2
Single lane (shared with PCIe_SS1
and USB1)
Serial Advanced Technology Attachment (SATA)
Real-Time Clock Subsystem (RTCSS)
Multichannel Serial Peripheral Interface (McSPI)
Quad SPI (QSPI)
SATA
No
No
RTCSS
McSPI
4
QSPI
Yes
Yes
16
Spinlock Module
SPINLOCK
TIMERS GP
WD TIMER
PWMSS1
PWMSS2
PWMSS3
UART
Timers, General-Purpose
Timer, Watchdog
Yes
Yes
Yes
Yes
10
Pulse-Width Modulation Subsystem (PWMSS)
Universal Asynchronous Receiver/Transmitter (UART)
Universal Serial Bus (USB3.0)
USB1 (Super- Speed, Dual-
Role- Device [DRD])
Yes
Universal Serial Bus (USB2.0)
USB2 (High- Speed, Dual-
Role- Device [DRD], with
embedded HS PHY)
Yes
USB3 (High- Speed,
OTG2.0, with ULPI)
Yes
No
USB4 (High- Speed,
OTG2.0, with ULPI)
(1) IPU2 subsystem is dedicated to IVA support and is not available for other processing.
(2) For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the TDA2Ex Technical Reference
Manual.
3.2 Related Products
Automotive Processors
TDAx ADAS SoCs TI's TDAx Driver Assistance System-on-Chip (SoC) family offers scalable and open
solutions and a common hardware and software architecture for Advanced Driver Assistance
Systems (ADAS) applications including camera-based front (mono and stereo), rear,
surround view and night vision systems, and mid- and long-range radar and sensor fusion
systems.
Companion Products for TDA2 Review products that are frequently purchased or used in conjunction
with this product.
版权 © 2016–2018, Texas Instruments Incorporated
Device Comparison
7
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
4 Terminal Configuration and Functions
4.1 Pin Diagram
图 4-1 shows the ball locations for the 538 plastic ball grid array (PBGA) package and isused in
conjunction with 表 4-1 through 表 4-26 to locate signal names and ball grid numbers.
图 4-1. CBD S-PBGA-N538 Package (Bottom View)
注
The following bottom balls are not pinned out: AE4 / AE7 / AE10 / AE13 / AD5 / AD8 / AD11
/ AD14 / AC7 / AC9 / AC12 / AC14 / AC17 / AB3 / AB4 / AB5 / AB13 / AB14 / AB17 / AB20 /
AB21 / AB22 / AA14 / AA17 / AA22 / Y22 / W3 / W4 / W5 / W6 / V6 / V21 / V22 / V23 / R3 /
R4 / R5 / R6 / R21 / R22 / R23 / P6 / M3 / M4 / M5 / M6 / M21 / M22 / M23 / J3 / J4 / J5 / J6
/ J21 / J22 / J23 / F4 / F5 / F9 / F12 / F15 / F18 / F21 / F22 / E3 / E4 / E5 / E6 / E9 / E12 /
E15 / E18 / E21 / E22 / E23 / D4 / D5 / D9 / D12 / D15 / D18 / D21 / D22 / C9 / C12 / C15 /
C18.
These balls do not exist on the package.
4.2 Pin Attributes
表 4-1 describes the terminal characteristics and the signals multiplexed on each ball. The following list
describes the table column headers:
1. BALL NUMBER:This column lists ball numbers on the bottom side associated with each signal on the
bottom.
2. BALL NAME: This column lists mechanical name from package device (name is taken from muxmode
0).
3. SIGNAL NAME:This column lists names of signals multiplexed on each ball (also notice that the name
of the ball is the signal name in muxmode 0).
注
表 4-1 does not take into account the subsystem multiplexing signals. Subsystem
multiplexing signals are described in 节 4.3, Signal Descriptions.
注
In driver off mode, the buffer is configured in high-impedance.
8
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
注
In some cases 表 4-1 may present more than one signal name per muxmode for the same
ball. First signal in the list is the dominant function as selected via CTRL_CORE_PAD_*
register.
All other signals are virtual functions that present alternate multiplexing options. This virtual
functions are controlled via CTRL_CORE_ALT_SELECT_MUX or
CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
4. MUXMODE: Multiplexing mode number:
a. MUXMODE 0 is the primary mode; this means that when MUXMODE=0 is set, the function
mapped on the pin corresponds to the name of the pin. The primary muxmode is not necessarily
the default muxmode.
注
The default mode is the mode at the release of the reset; also see the RESET REL.
MUXMODE column.
b. MUXMODE 1 through 15 are possible muxmodes for alternate functions. On each pin, some
muxmodes are effectively used for alternate functions, while some muxmodes are not used. Only
MUXMODE values which correspond to defined functions should be used.
c. An empty box means Not Applicable.
5. TYPE: Signal type and direction:
–
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or Output
D = Open drain
DS = Differential Signaling
A = Analog
PWR = Power
GND = Ground
CAP = LDO Capacitor
6. BALL RESET STATE: The state of the terminal at power-on reset:
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
7. BALL RESET REL. STATE: The state of the terminal at the deactivation of the rstoutn signal (also
mapped to the PRCM SYS_WARM_OUT_RST signal)
–
–
–
–
–
–
–
drive 0 (OFF): The buffer drives VOL (pulldown or pullup resistor not activated)
drive clk (OFF): The buffer drives a toggling clock (pulldown or pullup resistor not activated)
drive 1 (OFF): The buffer drives VOH (pulldown or pullup resistor not activated)
OFF: High-impedance
PD: High-impedance with an active pulldown resistor
PU: High-impedance with an active pullup resistor
An empty box means Not Applicable
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
9
TDA2E-17
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www.ti.com.cn
注
For more information on the CORE_PWRON_RET_RST reset signal and its reset sources,
see the Power, Reset, and Clock Management / PRCM Reset Management Functional
Description section of the Device TRM.
8. BALL RESET REL. MUXMODE: This muxmode is automatically configured at the release of the
rstoutn signal (also mapped to the PRCM SYS_WARM_OUT_RST signal).
An empty box means Not Applicable.
9. IO VOLTAGE VALUE: This column describes the IO voltage value (the corresponding power supply).
An empty box means Not Applicable.
10. POWER: The voltage supply that powers the terminal IO buffers.
An empty box means Not Applicable.
11. HYS: Indicates if the input buffer is with hysteresis:
–
–
–
Yes: With hysteresis
No: Without hysteresis
An empty box: Not Applicable
注
For more information, see the hysteresis values in 节 5.7, Electrical Characteristics.
12. BUFFER TYPE: Drive strength of the associated output buffer.
An empty box means Not Applicable.
注
For programmable buffer strength:
–
–
The default value is given in 表 4-1.
A note describes all possible values according to the selected muxmode.
13. PULLUP / PULLDOWN TYPE: Denotes the presence of an internal pullup or pulldown resistor.
Pullup and pulldown resistors can be enabled or disabled via software.
–
–
–
–
–
–
PU: Internal pullup
PD: Internal pulldown
PU/PD: Internal pullup and pulldown
PUx/PDy: Programmable internal pullup and pulldown
PDy: Programmable internal pulldown
An empty box means No pull
14. DSIS: The deselected input state (DSIS) indicates the state driven on the peripheral input (logic "0" or
logic "1") when the peripheral pin function is not selected by any of the PINCNTLx registers.
–
–
–
0: Logic 0 driven on the peripheral's input signal port.
1: Logic 1 driven on the peripheral's input signal port.
blank: Pin state driven on the peripheral's input signal port.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected
results. This can be easily prevented with the proper software configuration (Hi-Z mode is not
an input signal).
注
When a pad is set into a multiplexing mode which is not defined by pin multiplexing, that
pad’s behavior is undefined. This should be avoided.
10
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
注
Some of the EMIF1 signals have an additional state change at the release of porz. The state
that the signals change to at the release of porz is as follows:
drive 0 (OFF) for: ddr1_ck, ddr1_odt[0], ddr1_rst.
drive 1 (OFF) for: ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_nck, ddr1_ba[2:0], ddr1_a[15:0],
ddr1_csn[0], ddr1_cke, ddr1_dqm[3:0]
注
Dual rank support is not available on this device, but signal names are retained for
consistency with the TDA2xx family of devices
.
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
11
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F8
cap_vbbldo_dsp
cap_vbbldo_dsp
CAP
T7
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
csi2_0_dx0
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
I
G14
F17
U20
K7
G19
L7
V7
G12
G18
AC1
0
1.8
Yes
LVCMOS
CSI2
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
AD1
AE2
AB2
AC2
AD2
H23
csi2_0_dx1
csi2_0_dx2
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
dcan1_rx
csi2_0_dx1
csi2_0_dx2
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
0
0
0
0
0
I
I
I
I
I
1.8
Yes
Yes
Yes
Yes
Yes
Yes
LVCMOS
CSI2
1.8
LVCMOS
CSI2
1.8
LVCMOS
CSI2
1.8
LVCMOS
CSI2
1.8
LVCMOS
CSI2
dcan1_rx
uart8_txd
mmc2_sdwp
hdmi1_cec
gpio1_15
Driver off
dcan1_tx
uart8_rxd
mmc2_sdcd
hdmi1_hpd
gpio1_14
Driver off
ddr1_a0
0
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Dual Voltage PU/PD
LVCMOS
1
0
2
3
6
IO
IO
I
14
15
0
H22
dcan1_tx
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
2
3
I
6
IO
IO
I
14
15
0
AC18
AE19
ddr1_a0
ddr1_a1
O
PD
PD
drive 1 (OFF)
drive 1 (OFF)
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
No
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
ddr1_a1
0
O
LVCMOS
DDR
12
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
BALL NUMBER [1]
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AD19
AB19
AD20
AE20
AA18
AA20
Y21
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a2
0
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
IO
IO
PD
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 0 (OFF)
drive 1 (OFF)
drive 1 (OFF)
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_casn
ddr1_ck
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PU
PU
PU
PU
PD
PU
PU
PD
PD
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
AC20
AA21
AC21
AC22
AC15
AB15
AC16
AE16
AA16
AB16
AD16
AD21
AB18
AC19
AA23
AC24
LVCMOS
DDR
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
ddr1_a14
ddr1_a15
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_casn
ddr1_ck
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
ddr1_cke
ddr1_csn0
ddr1_d0
ddr1_cke
ddr1_csn0
ddr1_d0
ddr1_d1
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
ddr1_d1
PD
LVCMOS
DDR
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
13
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AB24
AD24
AB23
AC23
AD23
AE24
AA24
W25
Y23
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d2
0
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
ddr1_d3
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
ddr1_d4
LVCMOS
DDR
ddr1_d5
LVCMOS
DDR
ddr1_d6
LVCMOS
DDR
ddr1_d7
LVCMOS
DDR
ddr1_d8
LVCMOS
DDR
ddr1_d9
LVCMOS
DDR
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
LVCMOS
DDR
AD25
AC25
AB25
AA25
W24
W23
U25
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
LVCMOS
DDR
U24
LVCMOS
DDR
W21
T22
LVCMOS
DDR
LVCMOS
DDR
U22
LVCMOS
DDR
U23
LVCMOS
DDR
T21
LVCMOS
DDR
T23
LVCMOS
DDR
14
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
BALL NUMBER [1]
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
T25
ddr1_d25
ddr1_d25
0
IO
IO
IO
IO
IO
IO
IO
O
PD
PD
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
1.35/1.5
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
vdds_ddr1
No
LVCMOS
DDR
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
PUx/PDy
T24
ddr1_d26
ddr1_d26
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PD
PD
PD
PD
PD
PD
PU
PU
PU
PU
PD
PD
PD
PD
PU
PU
PU
PU
PU
PD
PU
PD
PD
No
No
No
No
No
No
No
No
No
No
LVCMOS
DDR
P21
ddr1_d27
ddr1_d27
PD
LVCMOS
DDR
N21
P22
ddr1_d28
ddr1_d28
PD
LVCMOS
DDR
ddr1_d29
ddr1_d29
PD
LVCMOS
DDR
P23
ddr1_d30
ddr1_d30
PD
LVCMOS
DDR
P24
ddr1_d31
ddr1_d31
PD
LVCMOS
DDR
AE23
W22
U21
P25
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_nck
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
ddr1_dqs1
ddr1_dqs2
ddr1_dqs3
ddr1_dqsn0
ddr1_dqsn1
ddr1_dqsn2
ddr1_dqsn3
ddr1_nck
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
drive 1 (OFF)
PD
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
AD22
Y24
IO
IO
IO
IO
IO
IO
IO
IO
O
LVCMOS
DDR
PD
LVCMOS
DDR
V24
PD
LVCMOS
DDR
R24
AE22
Y25
PD
LVCMOS
DDR
PU
LVCMOS
DDR
PU
LVCMOS
DDR
V25
PU
LVCMOS
DDR
R25
AE21
AD18
AD17
AE17
PU
LVCMOS
DDR
drive 1 (OFF)
drive 0 (OFF)
drive 1 (OFF)
drive 0 (OFF)
No
No
No
No
LVCMOS
DDR
ddr1_odt0
ddr1_rasn
ddr1_rst
ddr1_odt0
ddr1_rasn
ddr1_rst
O
LVCMOS
DDR
O
LVCMOS
DDR
O
LVCMOS
DDR
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
15
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
Y20
ddr1_vref0
ddr1_vref0
0
PWR
OFF
drive 1 (OFF)
drive 1 (OFF)
PU
1.35/1.5
1.35/1.5
1.8/3.3
vdds_ddr1
vdds_ddr1
vddshv3
No
LVCMOS
DDR
AE18
C21
ddr1_wen
emu0
ddr1_wen
0
O
PU
PU
No
LVCMOS
DDR
PUx/PDy
emu0
0
IO
IO
IO
IO
O
0
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_30
emu1
14
0
C22
emu1
PU
PU
0
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_31
emu2
14
2
E14
F14
F13
Y5
emu2
PD
PD
PD
PU
PD
PD
PD
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv7
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
emu3
emu3
emu4
2
2
O
O
Dual Voltage PU/PD
LVCMOS
emu4
Dual Voltage PU/PD
LVCMOS
gpio6_10
gpio6_10
mdio_mclk
i2c3_sda
0
IO
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
1
1
0
2
usb3_ulpi_d7
vin2b_hsync1
vin1a_clk0
ehrpwm2A
gpio6_10
Driver off
3
4
9
I
0
10
14
15
0
O
IO
I
Y6
gpio6_11
gpio6_11
mdio_d
IO
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
0
i2c3_scl
2
usb3_ulpi_d6
vin2b_vsync1
vin1a_de0
ehrpwm2B
gpio6_11
Driver off
3
4
9
I
0
10
14
15
0
O
IO
I
H21
gpio6_14
gpio6_14
mcasp1_axr8
dcan2_tx
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
1
1
2
uart10_rxd
i2c3_sda
3
9
IO
IO
IO
I
timer1
10
14
15
gpio6_14
Driver off
16
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
K22
gpio6_15
gpio6_15
0
IO
IO
IO
O
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp1_axr9
dcan2_rx
uart10_txd
i2c3_scl
1
0
1
2
3
9
1
timer2
10
14
15
0
gpio6_15
Driver off
gpio6_16
mcasp1_axr10
clkout1
K23
gpio6_16
IO
IO
O
IO
IO
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
9
timer3
10
14
15
0
gpio6_16
Driver off
gpmc_a0
vin1a_d16
vout3_d16
vin1b_d0
i2c4_scl
M1
gpmc_a0
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
6
0
1
1
7
IO
I
uart5_rxd
8
gpio7_3
14
IO
gpmc_a26
gpmc_a16
Driver off
gpmc_a1
vin1a_d17
vout3_d17
vin1b_d1
i2c4_sda
uart5_txd
gpio7_4
15
0
I
M2
gpmc_a1
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
6
0
1
7
IO
O
IO
I
8
14
15
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
17
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
L2
gpmc_a2
gpmc_a2
0
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
vin1a_d18
vout3_d18
vin1b_d2
uart7_rxd
uart5_ctsn
gpio7_5
2
0
3
O
I
6
0
1
1
7
I
8
I
14
15
0
IO
I
Driver off
gpmc_a3
qspi1_cs2
vin1a_d19
vout3_d19
vin1b_d3
uart7_txd
uart5_rtsn
gpio7_6
L1
K3
K2
gpmc_a3
gpmc_a4
gpmc_a5
O
O
I
PD
PD
PD
PD
15
1.8/3.3
vddshv10
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
3
O
I
6
0
7
O
O
IO
I
8
14
15
0
Driver off
gpmc_a4
qspi1_cs3
vin1a_d20
vout3_d20
vin1b_d4
i2c5_scl
O
O
I
PD
15
1.8/3.3
vddshv10
Dual Voltage PU/PD
LVCMOS
1
1
0
2
3
O
I
6
0
1
1
7
IO
I
uart6_rxd
gpio1_26
Driver off
gpmc_a5
vin1a_d21
vout3_d21
vin1b_d5
i2c5_sda
uart6_txd
gpio1_27
Driver off
8
14
15
0
IO
I
O
I
PD
15
1.8/3.3
vddshv10
Dual Voltage PU/PD
LVCMOS
2
0
3
O
I
6
0
1
7
IO
O
IO
I
8
14
15
18
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
J1
gpmc_a6
gpmc_a6
0
O
I
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
vin1a_d22
vout3_d22
vin1b_d6
2
0
3
O
I
6
0
1
1
uart8_rxd
uart6_ctsn
gpio1_28
Driver off
7
I
8
I
14
15
0
IO
I
K1
K4
H1
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_a7
vin1a_d23
vout3_d23
vin1b_d7
O
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
2
0
0
3
O
I
6
uart8_txd
uart6_rtsn
gpio1_29
Driver off
7
O
O
IO
I
8
14
15
0
gpmc_a8
vin1a_hsync0
vout3_hsync
vin1b_hsync1
timer12
O
I
Dual Voltage PU/PD
LVCMOS
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_sclk
gpio1_30
Driver off
8
14
15
0
gpmc_a9
vin1a_vsync0
vout3_vsync
vin1b_vsync1
timer11
O
I
Dual Voltage PU/PD
LVCMOS
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_d1
8
gpio1_31
Driver off
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
19
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
J2
gpmc_a10
gpmc_a10
0
O
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
vin1a_de0
vout3_de
vin1b_clk1
timer10
2
0
0
0
3
O
I
6
7
IO
IO
IO
I
spi4_d0
8
gpio2_0
14
15
0
Driver off
gpmc_a11
vin1a_fld0
vout3_fld
vin1b_de1
timer9
L3
gpmc_a11
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
2
0
0
1
3
O
I
6
7
IO
IO
IO
I
spi4_cs0
gpio2_1
8
14
15
0
Driver off
gpmc_a12
gpmc_a0
vin1b_fld1
timer8
G1
gpmc_a12
O
O
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
5
6
0
7
IO
IO
I
spi4_cs1
dma_evt1
gpio2_2
8
1
0
9
14
15
0
IO
I
Driver off
gpmc_a13
qspi1_rtclk
timer7
H3
gpmc_a13
O
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
0
7
IO
IO
I
spi4_cs2
dma_evt2
gpio2_3
8
1
0
9
14
15
0
IO
I
Driver off
gpmc_a14
qspi1_d3
timer6
H4
gpmc_a14
O
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
7
spi4_cs3
gpio2_4
8
14
15
Driver off
20
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
K6
gpmc_a15
gpmc_a15
0
O
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
qspi1_d2
timer5
1
0
7
gpio2_5
14
15
0
Driver off
gpmc_a16
qspi1_d0
gpio2_6
K5
G2
F2
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
O
IO
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv11
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
14
15
0
Driver off
gpmc_a17
qspi1_d1
gpio2_7
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
14
15
0
Driver off
gpmc_a18
qspi1_sclk
gpio2_8
O
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
14
15
0
Driver off
gpmc_a19
mmc2_dat4
gpmc_a13
vin2b_d0
gpio2_9
A4(9)
E7(9)
D6(9)
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
14
15
0
IO
I
Driver off
gpmc_a20
mmc2_dat5
gpmc_a14
vin2b_d1
gpio2_10
Driver off
gpmc_a21
mmc2_dat6
gpmc_a15
vin2b_d2
gpio2_11
Driver off
gpmc_a20
O
IO
O
I
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
14
15
0
IO
I
gpmc_a21
O
IO
O
I
PD
PD
15
1.8/3.3
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
14
15
IO
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
21
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
C5(9)
gpmc_a22
gpmc_a22
0
O
IO
O
I
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv11
vddshv11
vddshv11
vddshv11
vddshv11
vddshv11
Yes
Dual Voltage PU/PD
LVCMOS
mmc2_dat7
gpmc_a16
vin2b_d3
1
1
0
2
6
gpio2_12
Driver off
14
15
0
IO
I
B5
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a23
mmc2_clk
gpmc_a17
vin2b_d4
O
IO
O
I
PD
PD
PD
PD
PD
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
gpio2_13
Driver off
14
15
0
IO
I
D7(9)
C6(9)
A5(9)
B6(9)
gpmc_a24
mmc2_dat0
gpmc_a18
vin2b_d5
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
gpio2_14
Driver off
14
15
0
IO
I
gpmc_a25
mmc2_dat1
gpmc_a19
vin2b_d6
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
gpio2_15
Driver off
14
15
0
IO
I
gpmc_a26
mmc2_dat2
gpmc_a20
vin2b_d7
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
0
2
6
gpio2_16
Driver off
14
15
0
IO
I
gpmc_a27
mmc2_dat3
gpmc_a21
vin2b_hsync1
gpio2_17
Driver off
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
2
6
14
15
IO
I
22
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
F1
gpmc_ad0
gpmc_ad0
0
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
vin1a_d0
vout3_d0
gpio1_6
2
3
O
IO
I
14
15
0
sysboot0
gpmc_ad1
vin1a_d1
vout3_d1
gpio1_7
E2
E1
C1
D1
D2
B1
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
Yes
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot1
gpmc_ad2
vin1a_d2
vout3_d2
gpio1_8
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot2
gpmc_ad3
vin1a_d3
vout3_d3
gpio1_9
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
sysboot3
gpmc_ad4
vin1a_d4
vout3_d4
gpio1_10
sysboot4
gpmc_ad5
vin1a_d5
vout3_d5
gpio1_11
sysboot5
gpmc_ad6
vin1a_d6
vout3_d6
gpio1_12
sysboot6
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
23
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B2
gpmc_ad7
gpmc_ad7
0
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
15
15
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
vin1a_d7
vout3_d7
gpio1_13
sysboot7
2
3
O
IO
I
14
15
0
C2
D3
A2
B3
C3
C4
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad8
vin1a_d8
vout3_d8
gpio7_18
sysboot8
IO
I
OFF
OFF
OFF
OFF
OFF
OFF
Yes
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
gpmc_ad9
vin1a_d9
vout3_d9
gpio7_19
sysboot9
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
gpmc_ad10
vin1a_d10
vout3_d10
gpio7_28
sysboot10
gpmc_ad11
vin1a_d11
vout3_d11
gpio7_29
sysboot11
gpmc_ad12
vin1a_d12
vout3_d12
gpio1_18
sysboot12
gpmc_ad13
vin1a_d13
vout3_d13
gpio1_19
sysboot13
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
24
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A3
gpmc_ad14
gpmc_ad14
0
IO
I
OFF
OFF
OFF
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv10
vddshv10
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
0
vin1a_d14
vout3_d14
gpio1_20
sysboot14
gpmc_ad15
vin1a_d15
vout3_d15
gpio1_21
sysboot15
gpmc_advn_ale
gpmc_cs6
clkout2
2
3
O
IO
I
14
15
0
B4
H5
gpmc_ad15
IO
I
OFF
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
O
IO
I
14
15
0
gpmc_advn_ale
O
O
O
I
PU
Dual Voltage PU/PD
LVCMOS
1
2
gpmc_wait1
gpmc_a2
gpmc_a23
timer3
3
1
5
O
O
IO
IO
I
6
7
i2c3_sda
8
1
0
dma_evt2
9
gpio2_23
14
IO
gpmc_a19
Driver off
gpmc_ben0
gpmc_cs4
vin2b_de1
timer2
15
0
I
H2
gpmc_ben0
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
6
7
IO
I
dma_evt3
9
0
gpio2_26
14
IO
gpmc_a21
Driver off
15
I
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
25
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
H6
gpmc_ben1
gpmc_ben1
0
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
gpmc_cs5
vin2b_clk1
gpmc_a3
vin2b_fld1
timer1
1
4
5
O
I
6
7
IO
I
dma_evt4
9
0
gpio2_27
14
IO
gpmc_a22
Driver off
gpmc_clk
gpmc_cs7
clkout1
15
0
I
L4
gpmc_clk
IO
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
2
gpmc_wait1
vin2b_clk1
timer4
3
6
I
7
IO
IO
I
i2c3_scl
8
1
0
dma_evt1
9
gpio2_22
14
IO
gpmc_a20
Driver off
15
0
I
F3
A6
gpmc_cs0
gpmc_cs1
gpmc_cs0
gpio2_19
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv11
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
gpmc_cs1
mmc2_cmd
gpmc_a22
vin2b_vsync1
gpio2_18
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
2
6
14
15
0
IO
I
Driver off
G4
gpmc_cs2
gpmc_cs2
qspi1_cs0
O
IO
IO
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
1
1
gpio2_20
gpmc_a23
gpmc_a13
14
Driver off
15
I
26
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
G3
gpmc_cs3
gpmc_cs3
0
O
O
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
qspi1_cs1
vin1a_clk0
vout3_clk
gpmc_a1
1
1
0
2
3
O
O
IO
5
gpio2_21
gpmc_a24
gpmc_a14
14
Driver off
15
0
I
G5
F6
gpmc_oen_ren
gpmc_wait0
gpmc_oen_ren
gpio2_24
O
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv10
vddshv10
Yes
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
gpmc_wait0
I
Dual Voltage PU/PD
LVCMOS
1
gpio2_28
gpmc_a25
gpmc_a15
14
IO
Driver off
15
0
I
G6
gpmc_wen
gpmc_wen
gpio2_25
O
IO
I
PU
PU
15
1.8/3.3
vddshv10
Yes
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
AE9
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
hdmi1_clockx
hdmi1_clocky
hdmi1_data0x
hdmi1_data0y
hdmi1_data1x
hdmi1_data1y
hdmi1_data2x
hdmi1_data2y
i2c1_scl
O
O
O
O
O
O
O
O
IO
I
1.8
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vdda_hdmi
vddshv3
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
HDMIPHY
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
Pdy
AD10
AE11
AD12
AE12
AD13
AE14
AD15
G22
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8
0
1.8/3.3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS I2C
Driver off
15
0
G23
G21
i2c1_sda
i2c2_scl
i2c1_sda
IO
I
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Dual Voltage PU/PD
LVCMOS I2C
Driver off
15
0
i2c2_scl
IO
IO
I
15
15
Dual Voltage PU/PD
LVCMOS I2C
1
1
hdmi1_ddc_sda
Driver off
1
15
0
F23
AB9
i2c2_sda
ljcb_clkn
i2c2_sda
IO
IO
I
1.8/3.3
1.8
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS I2C
hdmi1_ddc_scl
Driver off
1
15
0
ljcb_clkn
IO
vdda_pcie
LJCB
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
27
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AC8
D16
ljcb_clkp
ljcb_clkp
0
IO
IO
IO
IO
IO
I
1.8
vdda_pcie
vddshv3
LJCB
mcasp1_aclkr
mcasp1_aclkx
mcasp1_axr0
mcasp1_aclkr
mcasp7_axr2
i2c4_sda
0
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
10
14
15
0
gpio5_0
Driver off
C16
D14
mcasp1_aclkx
vin1a_fld0
i2c3_sda
IO
I
PD
PD
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
7
10
14
15
0
IO
IO
I
gpio7_31
Driver off
mcasp1_axr0
uart6_rxd
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
0
1
3
vin1a_vsync0
i2c5_sda
7
I
10
14
15
0
IO
IO
I
gpio5_2
Driver off
B14
mcasp1_axr1
mcasp1_axr1
uart6_txd
IO
O
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
3
vin1a_hsync0
i2c5_scl
7
0
1
10
14
15
0
IO
IO
I
gpio5_3
Driver off
C14
B15
A15
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr2
mcasp6_axr2
uart6_ctsn
gpio5_4
IO
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
3
14
15
0
IO
I
Driver off
mcasp1_axr3
mcasp6_axr3
uart6_rtsn
gpio5_5
IO
IO
O
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
3
14
15
0
Driver off
mcasp1_axr4
mcasp4_axr2
gpio5_6
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
Driver off
28
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A14
mcasp1_axr5
mcasp1_axr5
0
IO
IO
IO
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp4_axr3
gpio5_7
1
14
15
0
Driver off
A17
A16
mcasp1_axr6
mcasp1_axr7
mcasp1_axr6
mcasp5_axr2
gpio5_8
IO
IO
IO
I
PD
PD
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
0
Driver off
mcasp1_axr7
mcasp5_axr3
timer4
IO
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
10
14
15
0
gpio5_9
Driver off
A18
B17
B16
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr8
mcasp6_axr0
spi3_sclk
IO
IO
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
0
1
3
vin1a_d15
timer5
7
10
14
15
0
IO
IO
I
gpio5_10
Driver off
mcasp1_axr9
mcasp6_axr1
spi3_d1
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
0
0
1
3
vin1a_d14
timer6
7
10
14
15
0
IO
IO
I
gpio5_11
Driver off
mcasp1_axr10
mcasp6_aclkx
mcasp6_aclkr
spi3_d0
IO
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
2
3
0
0
vin1a_d13
timer7
7
10
14
15
IO
IO
I
gpio5_12
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
29
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B18
mcasp1_axr11
mcasp1_axr11
0
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp6_fsx
mcasp6_fsr
spi3_cs0
1
2
3
1
0
vin1a_d12
timer8
7
10
14
15
0
IO
IO
I
gpio4_17
Driver off
A19
mcasp1_axr12
mcasp1_axr12
mcasp7_axr0
spi3_cs1
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
0
1
3
vin1a_d11
timer9
7
10
14
15
0
IO
IO
I
gpio4_18
Driver off
E17
mcasp1_axr13
mcasp1_axr13
mcasp7_axr1
vin1a_d10
timer10
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
7
10
14
15
0
IO
IO
I
gpio6_4
Driver off
E16
mcasp1_axr14
mcasp1_axr14
mcasp7_aclkx
mcasp7_aclkr
vin1a_d9
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
7
0
timer11
10
14
15
0
IO
IO
I
gpio6_5
Driver off
F16
mcasp1_axr15
mcasp1_axr15
mcasp7_fsx
mcasp7_fsr
vin1a_d8
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
7
0
timer12
10
14
15
IO
IO
I
gpio6_6
Driver off
30
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D17
mcasp1_fsr
mcasp1_fsr
0
IO
IO
IO
IO
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
mcasp7_axr3
i2c4_scl
1
10
14
15
0
gpio5_1
Driver off
C17
E19
mcasp1_fsx
mcasp1_fsx
vin1a_de0
i2c3_scl
IO
I
PD
PD
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
7
10
14
15
0
IO
IO
I
gpio7_30
Driver off
mcasp2_aclkx
mcasp2_aclkx
vin1a_d7
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
7
Driver off
15
0
I
A20
B19
A21
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr0
Driver off
IO
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
15
0
mcasp2_axr1
Driver off
IO
I
Dual Voltage PU/PD
LVCMOS
15
0
mcasp2_axr2
mcasp3_axr2
vin1a_d5
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
0
1
7
gpio6_8
14
15
0
IO
I
Driver off
B21
mcasp2_axr3
mcasp2_axr3
mcasp3_axr3
vin1a_d4
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
7
gpio6_9
14
15
0
IO
I
Driver off
B20
C19
mcasp2_axr4
mcasp2_axr5
mcasp2_axr4
mcasp8_axr0
gpio1_4
IO
IO
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
0
Driver off
mcasp2_axr5
mcasp8_axr1
gpio6_7
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
14
15
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
31
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D20
mcasp2_axr6
mcasp2_axr6
0
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
mcasp8_aclkx
mcasp8_aclkr
gpio2_29
1
2
14
15
0
Driver off
C20
mcasp2_axr7
mcasp2_axr7
mcasp8_fsx
mcasp8_fsr
gpio1_5
IO
IO
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
2
14
15
0
Driver off
D19
A22
mcasp2_fsx
mcasp2_fsx
vin1a_d6
IO
I
PD
PD
PD
PD
15
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
7
Driver off
15
0
I
mcasp3_aclkx
mcasp3_aclkx
mcasp3_aclkr
mcasp2_axr12
uart7_rxd
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
2
0
1
0
3
vin1a_d3
7
I
gpio5_13
14
15
0
IO
I
Driver off
B22
mcasp3_axr0
mcasp3_axr0
mcasp2_axr14
uart7_ctsn
uart5_rxd
IO
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
0
2
3
4
I
vin1a_d1
7
I
Driver off
15
0
I
B23
mcasp3_axr1
mcasp3_axr1
mcasp2_axr15
uart7_rtsn
uart5_txd
IO
IO
O
O
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
3
4
vin1a_d0
7
0
Driver off
15
I
32
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A23
mcasp3_fsx
mcasp3_fsx
0
IO
IO
IO
O
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
mcasp3_fsr
mcasp2_axr13
uart7_txd
vin1a_d2
1
2
3
7
gpio5_14
14
15
0
IO
I
Driver off
C23
A24
D23
B25
AC3
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsx
mcasp4_aclkx
mcasp4_aclkr
spi3_sclk
IO
IO
IO
I
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
vddshv7
Yes
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
2
0
1
1
uart8_rxd
i2c4_sda
3
4
IO
I
Driver off
15
0
mcasp4_axr0
spi3_d0
IO
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
1
2
uart8_ctsn
uart4_rxd
i2c6_scl
3
4
I
14
15
0
IO
I
Driver off
mcasp4_axr1
spi3_cs0
IO
IO
O
O
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
2
uart8_rtsn
uart4_txd
i2c6_sda
3
4
14
15
0
Driver off
mcasp4_fsx
mcasp4_fsr
spi3_d1
IO
IO
IO
O
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
0
1
2
uart8_txd
i2c4_scl
3
4
Driver off
15
0
mcasp5_aclkx
mcasp5_aclkx
mcasp5_aclkr
spi4_sclk
IO
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
2
0
1
1
uart9_rxd
i2c5_sda
3
4
IO
I
Driver off
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
33
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AA5
mcasp5_axr0
mcasp5_axr0
0
IO
IO
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
0
0
1
1
spi4_d0
2
uart9_ctsn
uart3_rxd
Driver off
mcasp5_axr1
spi4_cs0
uart9_rtsn
uart3_txd
Driver off
mcasp5_fsx
mcasp5_fsr
spi4_d1
3
4
I
15
0
I
AC4
mcasp5_axr1
mcasp5_fsx
IO
IO
O
O
I
PD
PD
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
2
3
4
15
0
U6
IO
IO
IO
O
IO
I
Dual Voltage PU/PD
LVCMOS
0
0
1
1
2
uart9_txd
i2c5_scl
3
4
Driver off
mdio_d
15
0
L6
mdio_d
IO
I
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
0
0
uart3_ctsn
mii0_txer
vin2a_d0
vin1b_d0
gpio5_16
Driver off
mdio_mclk
uart3_rtsn
mii0_col
1
3
O
I
4
5
I
14
15
0
IO
I
L5
mdio_mclk
O
O
I
PU
PU
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
1
3
vin2a_clk0
vin1b_clk1
gpio5_15
Driver off
mmc1_clk
gpio6_21
Driver off
mmc1_cmd
gpio6_22
Driver off
4
I
5
I
14
15
0
IO
I
U3
V4
mmc1_clk
IO
IO
I
PU
PU
PU
PU
15
15
1.8/3.3
1.8/3.3
vddshv8
vddshv8
Yes
Yes
SDIO2KV183 Pux/PDy
3
1
1
14
15
0
mmc1_cmd
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
34
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
V3
mmc1_dat0
mmc1_dat0
0
IO
IO
I
PU
PU
PU
PU
PU
PU
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv8
vddshv8
vddshv8
vddshv8
vddshv8
Yes
SDIO2KV183 Pux/PDy
3
1
1
1
1
gpio6_23
14
15
0
Driver off
V2
W1
V1
U5
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_dat1
gpio6_24
IO
IO
I
PU
PU
PU
PU
Yes
Yes
Yes
Yes
SDIO2KV183 Pux/PDy
3
14
15
0
Driver off
mmc1_dat2
gpio6_25
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
Driver off
mmc1_dat3
gpio6_26
IO
IO
I
SDIO2KV183 Pux/PDy
3
14
15
0
Driver off
mmc1_sdcd
uart6_rxd
I
Dual Voltage PU/PD
LVCMOS
1
1
1
3
I
i2c4_sda
4
IO
IO
I
gpio6_27
14
15
0
Driver off
V5
Y2
mmc1_sdwp
mmc1_sdwp
uart6_txd
I
PD
PU
PD
PU
15
15
1.8/3.3
1.8/3.3
vddshv8
vddshv7
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
3
O
IO
IO
I
i2c4_scl
4
gpio6_28
14
15
0
Driver off
mmc3_clk
mmc3_clk
usb3_ulpi_d5
vin2b_d7
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
3
4
vin1a_d7
9
I
ehrpwm2_tripzone_input
gpio6_29
10
14
15
0
IO
IO
I
Driver off
Y1
mmc3_cmd
mmc3_cmd
spi3_sclk
IO
IO
IO
I
PU
PU
15
1.8/3.3
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
0
1
usb3_ulpi_d4
vin2b_d6
3
4
vin1a_d6
9
I
eCAP2_in_PWM2_out
gpio6_30
10
14
15
IO
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
35
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
Y4
mmc3_dat0
mmc3_dat0
0
IO
IO
I
PU
PU
PU
PU
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
vddshv7
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
0
0
0
0
spi3_d1
1
uart5_rxd
usb3_ulpi_d3
vin2b_d5
2
3
IO
I
4
vin1a_d5
9
I
eQEP3A_in
gpio6_31
10
14
15
0
I
IO
I
Driver off
AA2
AA3
W2
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat1
spi3_d0
IO
IO
O
IO
I
PU
PU
PU
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
uart5_txd
usb3_ulpi_d2
vin2b_d4
2
3
0
0
0
0
4
vin1a_d4
9
I
eQEP3B_in
gpio7_0
10
14
15
0
I
IO
I
Driver off
mmc3_dat2
spi3_cs0
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
1
1
0
0
0
0
1
uart5_ctsn
usb3_ulpi_d1
vin2b_d3
2
3
IO
I
4
vin1a_d3
9
I
eQEP3_index
gpio7_1
10
14
15
0
IO
IO
I
Driver off
mmc3_dat3
spi3_cs1
IO
IO
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
1
1
uart5_rtsn
usb3_ulpi_d0
vin2b_d2
2
3
0
0
0
0
4
vin1a_d2
9
I
eQEP3_strobe
gpio7_2
10
14
15
IO
IO
I
Driver off
36
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
Y3
mmc3_dat4
mmc3_dat4
0
IO
IO
I
PU
PU
PU
PU
PU
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv7
vddshv7
vddshv7
vddshv7
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
0
0
0
spi4_sclk
1
uart10_rxd
usb3_ulpi_nxt
vin2b_d1
2
3
I
4
I
vin1a_d1
9
I
ehrpwm3A
gpio1_22
10
14
15
0
O
IO
I
Driver off
AA1
AA4
AB1
L24
mmc3_dat5
mmc3_dat6
mmc3_dat7
nmin_dsp
mmc3_dat5
spi4_d1
IO
IO
O
I
PU
PU
PU
PD
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
0
1
uart10_txd
usb3_ulpi_dir
vin2b_d0
2
3
0
0
0
4
I
vin1a_d0
9
I
ehrpwm3B
gpio1_23
10
14
15
0
O
IO
I
Driver off
mmc3_dat6
spi4_d0
IO
IO
I
Dual Voltage PU/PD
LVCMOS
1
0
1
1
uart10_ctsn
usb3_ulpi_stp
vin2b_de1
vin1a_hsync0
ehrpwm3_tripzone_input
gpio1_24
2
3
O
I
4
9
I
0
0
10
14
15
0
IO
IO
I
Driver off
mmc3_dat7
spi4_cs0
IO
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
1
1
uart10_rtsn
usb3_ulpi_clk
vin2b_clk1
vin1a_vsync0
eCAP3_in_PWM3_out
gpio1_25
2
3
0
4
I
9
I
0
0
10
14
15
0
IO
IO
I
Driver off
nmin_dsp
I
Dual Voltage PU/PD
LVCMOS
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
37
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AE6
AD7
AE8
AD9
F19
K24
pcie_rxn0
pcie_rxn0
0
I
OFF
OFF
OFF
1.8
vdda_pcie
vdda_pcie
vdda_pcie
vdda_pcie
vddshv3
SERDES
SERDES
SERDES
SERDES
IHHV1833
pcie_rxp0
pcie_txn0
pcie_txp0
porz
pcie_rxp0
pcie_txn0
pcie_txp0
porz
0
0
0
0
0
I
OFF
1.8
O
O
I
1.8
1.8
1.8/3.3
1.8/3.3
Yes
PU/PD
resetn
resetn
I
PU
PD
PU
PD
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
N2
P2
N4
N3
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxc
rmii1_txen
mii0_txclk
vin2a_d5
0
I
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv9
vddshv9
vddshv9
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
2
O
I
3
0
0
0
0
4
I
vin1b_d5
5
I
usb3_ulpi_d2
gpio5_26
6
IO
IO
I
14
15
0
Driver off
rgmii0_rxctl
rmii1_txd1
mii0_txd3
vin2a_d6
I
PD
PD
PD
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
2
O
O
I
3
4
0
0
0
vin1b_d6
5
I
usb3_ulpi_d3
gpio5_27
6
IO
IO
I
14
15
0
Driver off
rgmii0_rxd0
rmii0_txd0
mii0_txd0
vin2a_fld0
vin1b_fld1
usb3_ulpi_d7
gpio5_31
I
Dual Voltage PU/PD
LVCMOS
0
1
O
O
I
3
4
5
I
0
0
6
IO
IO
I
14
15
0
Driver off
rgmii0_rxd1
rmii0_txd1
mii0_txd1
vin2a_d9
I
Dual Voltage PU/PD
LVCMOS
0
1
O
O
I
3
4
0
0
usb3_ulpi_d6
gpio5_30
6
IO
IO
I
14
15
Driver off
38
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P1
rgmii0_rxd2
rgmii0_rxd2
0
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
rmii0_txen
mii0_txen
vin2a_d8
usb3_ulpi_d5
gpio5_29
Driver off
rgmii0_rxd3
rmii1_txd0
mii0_txd2
vin2a_d7
vin1b_d7
usb3_ulpi_d4
gpio5_28
Driver off
rgmii0_txc
uart3_ctsn
rmii1_rxd1
mii0_rxd3
vin2a_d3
vin1b_d3
usb3_ulpi_clk
spi3_d0
1
O
O
I
3
4
0
0
6
IO
IO
I
14
15
0
N1
rgmii0_rxd3
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
2
O
O
I
3
4
0
0
0
5
I
6
IO
IO
I
14
15
0
T4
rgmii0_txc
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
1
0
0
0
0
0
0
1
2
I
3
I
4
I
5
I
6
I
7
IO
IO
IO
I
spi4_cs2
8
gpio5_20
Driver off
rgmii0_txctl
uart3_rtsn
rmii1_rxd0
mii0_rxd2
vin2a_d4
vin1b_d4
usb3_ulpi_stp
spi3_cs0
14
15
0
T5
rgmii0_txctl
O
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
2
0
0
0
0
3
I
4
I
5
I
6
O
IO
IO
IO
I
7
1
1
spi4_cs3
8
gpio5_21
Driver off
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
39
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
R1
rgmii0_txd0
rgmii0_txd0
0
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
rmii0_rxd0
mii0_rxd0
vin2a_d10
usb3_ulpi_d1
spi4_cs0
1
0
0
0
0
1
3
I
4
I
6
IO
IO
O
IO
I
7
uart4_rtsn
gpio5_25
8
14
15
0
Driver off
R2
rgmii0_txd1
rgmii0_txd1
rmii0_rxd1
mii0_rxd1
vin2a_vsync0
vin1b_vsync1
usb3_ulpi_d0
spi4_d0
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
3
I
4
I
5
I
0
0
0
1
6
IO
IO
IO
IO
I
7
uart4_ctsn
gpio5_24
8
14
15
0
Driver off
P3
rgmii0_txd2
rgmii0_txd2
rmii0_rxer
mii0_rxer
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
1
0
0
3
I
vin2a_hsync0
vin1b_hsync1
usb3_ulpi_nxt
spi4_d1
4
I
5
I
0
0
0
6
I
7
IO
O
IO
I
uart4_txd
8
gpio5_23
14
15
Driver off
40
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
P4
rgmii0_txd3
rgmii0_txd3
0
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
rmii0_crs
1
0
0
mii0_crs
3
I
vin2a_de0
vin1b_de1
usb3_ulpi_dir
spi4_sclk
4
I
5
I
0
0
0
1
6
I
7
IO
I
uart4_rxd
gpio5_22
8
14
15
0
IO
I
Driver off
P5
RMII_MHZ_50_CLK
RMII_MHZ_50_CLK
vin2a_d11
gpio5_17
IO
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
0
0
4
14
15
0
IO
I
Driver off
E20
K25
rstoutn
rtck
rstoutn
O
PD
PU
PD
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
rtck
0
O
IO
IO
IO
I
OFF
0
Dual Voltage PU/PD
LVCMOS
gpio8_29
spi1_cs0
gpio7_10
Driver off
spi1_cs1
spi2_cs1
gpio7_11
Driver off
spi1_cs2
uart4_rxd
mmc3_sdcd
spi2_cs2
dcan2_tx
mdio_mclk
hdmi1_hpd
gpio7_12
Driver off
14
0
B24
C25
spi1_cs0
spi1_cs1
PU
PU
PU
PU
15
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
14
15
0
IO
IO
IO
I
15
15
Dual Voltage PU/PD
LVCMOS
1
1
3
14
15
0
E24
spi1_cs2
IO
I
PU
PU
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
1
1
1
1
2
I
3
IO
IO
O
IO
IO
I
4
5
6
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
41
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E25
spi1_cs3
spi1_cs3
0
IO
O
I
PU
PU
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
1
uart4_txd
mmc3_sdwp
spi2_cs3
dcan2_rx
mdio_d
1
2
0
1
1
1
3
IO
IO
IO
IO
IO
I
4
5
hdmi1_cec
gpio7_13
Driver off
spi1_d0
6
14
15
0
D25
D24
C24
F24
spi1_d0
spi1_d1
IO
IO
I
PD
PD
PD
PU
PD
PD
PD
PU
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
1
gpio7_9
14
15
0
Driver off
spi1_d1
IO
IO
I
Dual Voltage PU/PD
LVCMOS
gpio7_8
14
15
0
Driver off
spi1_sclk
gpio7_7
spi1_sclk
spi2_cs0
IO
IO
I
Dual Voltage PU/PD
LVCMOS
14
15
0
Driver off
spi2_cs0
uart3_rtsn
uart5_txd
gpio7_17
Driver off
spi2_d0
IO
O
O
IO
I
Dual Voltage PU/PD
LVCMOS
1
2
14
15
0
G24
spi2_d0
IO
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
0
1
1
uart3_ctsn
uart5_rxd
gpio7_16
Driver off
spi2_d1
1
2
I
14
15
0
IO
I
F25
G25
K21
spi2_d1
spi2_sclk
tclk
IO
O
IO
I
PD
PD
PU
PD
PD
PU
15
15
0
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv3
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
uart3_txd
gpio7_15
Driver off
spi2_sclk
uart3_rxd
gpio7_14
Driver off
tclk
1
14
15
0
IO
I
Dual Voltage PU/PD
LVCMOS
0
1
1
14
15
0
IO
I
I
IQ1833
PU/PD
42
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
L23
J20
tdi
tdi
0
I
PU
PU
PU
0
1.8/3.3
1.8/3.3
vddshv3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_27
tdo
14
0
I
tdo
O
IO
I
PU
0
0
Yes
Dual Voltage PU/PD
LVCMOS
gpio8_28
tms
14
0
L21
L22
L20
tms
PU
PD
PU
PU
PD
PU
1.8/3.3
1.8/3.3
1.8/3.3
vddshv3
vddshv3
vddshv4
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
trstn
trstn
0
I
Dual Voltage PU/PD
LVCMOS
uart1_ctsn
uart1_ctsn
uart9_rxd
mmc4_clk
gpio7_24
Driver off
uart1_rtsn
uart9_txd
mmc4_cmd
gpio7_25
Driver off
uart1_rxd
mmc4_sdcd
gpio7_22
Driver off
uart1_txd
mmc4_sdwp
gpio7_23
Driver off
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
0
I
15
15
Dual Voltage PU/PD
LVCMOS
1
1
1
2
I
3
IO
IO
I
14
15
0
M24
uart1_rtsn
O
O
IO
IO
I
PU
PU
1.8/3.3
vddshv4
Yes
Dual Voltage PU/PD
LVCMOS
2
3
1
14
15
0
L25
M25
N22
uart1_rxd
uart1_txd
uart2_ctsn
I
PU
PU
PU
PU
PU
PU
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv4
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
3
I
14
15
0
IO
I
O
I
Dual Voltage PU/PD
LVCMOS
3
0
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
1
1
1
1
2
I
3
IO
I
4
5
O
IO
I
14
15
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
43
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
N24
uart2_rtsn
uart2_rtsn
0
O
O
O
IO
O
I
PU
PU
PU
PU
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv4
vddshv4
vddshv4
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
uart3_txd
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
gpio1_17
Driver off
uart2_rxd
uart3_ctsn
uart3_rctx
mmc4_dat0
uart2_rxd
uart1_dcdn
gpio7_26
Driver off
uart2_txd
uart3_rtsn
uart3_sd
1
2
3
1
1
4
5
14
15
0
IO
I
N23
N25
N5
uart2_rxd
uart2_txd
uart3_rxd
I
PU
PU
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
1
1
1
I
2
O
IO
I
3
1
1
1
4
5
I
14
15
0
IO
I
O
O
O
IO
O
I
Dual Voltage PU/PD
LVCMOS
1
2
mmc4_dat1
uart2_txd
uart1_dsrn
gpio7_27
Driver off
uart3_rxd
rmii1_crs
mii0_rxdv
vin2a_d1
vin1b_d1
spi3_sclk
gpio5_18
Driver off
3
1
0
4
5
14
15
0
IO
I
I
Dual Voltage PU/PD
LVCMOS
1
0
0
0
0
0
2
I
3
I
4
I
5
I
7
IO
IO
I
14
15
44
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
N6
uart3_txd
uart3_txd
0
O
I
PD
PD
15
1.8/3.3
vddshv9
Yes
Dual Voltage PU/PD
LVCMOS
rmii1_rxer
mii0_rxclk
vin2a_d2
vin1b_d2
spi3_d1
2
0
0
0
0
0
1
3
I
4
I
5
I
7
IO
IO
IO
I
spi4_cs1
gpio5_19
Driver off
usb1_dm
8
14
15
0
AB7
AC6
AD3
usb1_dm
IO
OFF
OFF
PD
OFF
OFF
PD
3.3
vdda33v_usb
1
USBPHY
USBPHY
usb1_dp
usb1_dp
0
IO
3.3
vdda33v_usb
1
usb1_drvvbus
usb1_drvvbus
timer16
0
O
IO
IO
I
15
1.8/3.3
vdda33v_usb Yes
2
Dual Voltage PU/PD
LVCMOS
7
gpio6_12
Driver off
usb2_dm
14
15
0
AC5
AB6
AA6
usb2_dm
IO
3.3
vdda33v_usb No
2
USBPHY
USBPHY
usb2_dp
usb2_dp
0
IO
3.3
vdda33v_usb No
2
usb2_drvvbus
usb2_drvvbus
timer15
0
O
IO
IO
I
PD
PD
15
1.8/3.3
vdda33v_usb Yes
2
Dual Voltage PU/PD
LVCMOS
7
gpio6_13
Driver off
usb_rxn0
pcie_rxn1
usb_rxp0
pcie_rxp1
usb_txn0
pcie_txn1
usb_txp0
pcie_txp1
14
15
0
AE5
AD6
AE3
AD4
usb_rxn0
usb_rxp0
usb_txn0
usb_txp0
I
OFF
OFF
OFF
OFF
1.8
1.8
1.8
1.8
vdda_usb1
vdda_usb1
vdda_usb1
vdda_usb1
SERDES
SERDES
SERDES
SERDES
1
I
0
I
1
I
0
O
O
O
O
1
0
1
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
45
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
J15, J16, J18, K12, vdd
K18, L12, L17, M11,
M13, M15, M17,
vdd
PWR
N11, N13, N15, N18,
P10, P12, P14, P16,
P18, R10, R12, R14,
R16, R17, T11, T13,
T15, T17, T9, U11,
U13, U15, U18, U9,
V10, V12, V14, V16,
V18, W10, W12,
W14, W16
vpp(10)
F20
vpp
PWR
AA10
Y10
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
L9
T6
R20
vdda_ddr
vdda_ddr
N10
vdda_debug
vdda_dsp_iva
vdda_gpu
vdda_debug
vdda_dsp_iva
vdda_gpu
K10, L10
N9
W15, Y15
K16, L16
W13, Y13
W11, Y11
M10
vdda_hdmi
vdda_mpu_abe
vdda_osc
vdda_hdmi
vdda_mpu_abe
vdda_osc
vdda_pcie
vdda_pcie
vdda_per
vdda_per
W8
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdda_usb1
vdda_usb2
vdda_usb3
vdda_video
vdds18v
Y8
Y9
K14, L14
G11, H20, W7, Y18 vdds18v
AA19, P20, Y19
G10, G9
vdds18v_ddr1
vddshv1
vdds18v_ddr1
vddshv1
G15, G17, H15, H17, vddshv3
J19, K19
vddshv3
M19, N19
U7, U8
vddshv4
vddshv7
vddshv8
vddshv9
vddshv10
vddshv11
vddshv4
vddshv7
vddshv8
vddshv9
vddshv10
vddshv11
PWR
PWR
PWR
PWR
PWR
PWR
N8, P8
M7, N7
J7, J8, K8
F7, G7, H7
46
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
BALL NUMBER [1]
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
T19, T20, V20, W17, vdds_ddr1
W18, W20
vdds_ddr1
PWR
P7, R7
vdds_mlbp
vdds_mlbp
vdd_dsp
PWR
PWR
H11, H13, H9, J11, vdd_dsp
J13, J9
D8
vin2a_clk0
vin2a_clk0
vout2_fld
emu5
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
eQEP1A_in
10
14
0
0
gpio3_28
gpmc_a27
gpmc_a17
IO
Driver off
15
0
I
C8
vin2a_d0
vin2a_d0
I
PD
PD
PD
PD
15
1.8/3.3
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
vout2_d23
emu10
4
O
O
I
5
uart9_ctsn
spi4_d0
7
1
0
8
IO
O
IO
I
ehrpwm1B
gpio4_1
10
14
15
0
Driver off
B9
vin2a_d1
vin2a_d1
I
PD
15
1.8/3.3
vddshv1
Dual Voltage PU/PD
LVCMOS
0
vout2_d22
emu11
4
O
O
O
IO
IO
IO
I
5
uart9_rtsn
spi4_cs0
7
8
1
0
ehrpwm1_tripzone_input
gpio4_2
10
14
15
0
Driver off
A7
vin2a_d2
vin2a_d2
I
PD
15
1.8/3.3
vddshv1
Dual Voltage PU/PD
LVCMOS
0
vout2_d21
emu12
4
O
O
I
5
uart10_rxd
eCAP1_in_PWM1_out
gpio4_3
8
1
0
10
14
15
IO
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
47
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
A9
vin2a_d3
vin2a_d3
0
I
PD
PD
PD
PD
PD
PD
15
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
vout2_d20
emu13
4
O
O
O
I
5
uart10_txd
ehrpwm1_synci
gpio4_4
8
10
14
15
0
0
0
1
IO
I
Driver off
vin2a_d4
vout2_d19
emu14
A8
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
I
PD
PD
PD
PD
Yes
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
uart10_ctsn
ehrpwm1_synco
gpio4_5
8
10
14
15
0
O
IO
I
Driver off
vin2a_d5
vout2_d18
emu15
A11
F10
A10
I
Dual Voltage PU/PD
LVCMOS
0
4
O
O
O
I
5
uart10_rtsn
eQEP2A_in
gpio4_6
8
10
14
15
0
0
0
IO
I
Driver off
vin2a_d6
vout2_d17
emu16
I
Dual Voltage PU/PD
LVCMOS
4
O
O
I
5
mii1_rxd1
eQEP2B_in
gpio4_7
8
0
0
10
14
15
0
I
IO
I
Driver off
vin2a_d7
vout2_d16
emu17
I
Dual Voltage PU/PD
LVCMOS
0
4
O
O
I
5
mii1_rxd2
eQEP2_index
gpio4_8
8
0
0
10
14
15
IO
IO
I
Driver off
48
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B10
vin2a_d8
vin2a_d8
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
vout2_d15
emu18
4
O
O
I
5
mii1_rxd3
eQEP2_strobe
8
0
0
10
14
IO
IO
gpio4_9
gpmc_a26
Driver off
vin2a_d9
vout2_d14
emu19
15
0
I
E10
vin2a_d9
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
4
O
O
I
5
mii1_rxd0
ehrpwm2A
8
10
14
O
IO
gpio4_10
gpmc_a25
Driver off
15
0
I
D10
C10
B11
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d10
mdio_mclk
vout2_d13
ehrpwm2B
I
PD
PD
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
1
3
O
O
O
IO
4
10
14
gpio4_11
gpmc_a24
Driver off
15
0
I
vin2a_d11
I
Dual Voltage PU/PD
LVCMOS
0
1
mdio_d
3
IO
O
IO
IO
vout2_d12
4
ehrpwm2_tripzone_input
10
14
0
gpio4_12
gpmc_a23
Driver off
15
0
I
vin2a_d12
rgmii1_txc
I
Dual Voltage PU/PD
LVCMOS
0
3
O
O
I
vout2_d11
mii1_rxclk
4
8
0
0
eCAP2_in_PWM2_out
gpio4_13
10
14
15
IO
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
49
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D11
vin2a_d13
vin2a_d13
0
I
PD
PD
PD
PD
PD
15
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
rgmii1_txctl
vout2_d10
mii1_rxdv
eQEP3A_in
gpio4_14
3
O
O
I
4
8
0
0
10
14
15
0
I
IO
I
Driver off
C11
B12
A12
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d14
rgmii1_txd3
vout2_d9
I
PD
PD
PD
Yes
Yes
Yes
Dual Voltage PU/PD
LVCMOS
0
3
O
O
I
4
mii1_txclk
eQEP3B_in
gpio4_15
8
0
0
10
14
15
0
I
IO
I
Driver off
vin2a_d15
rgmii1_txd2
vout2_d8
I
Dual Voltage PU/PD
LVCMOS
0
0
3
O
O
O
IO
IO
I
4
mii1_txd0
eQEP3_index
gpio4_16
8
10
14
15
0
Driver off
vin2a_d16
vin2b_d7
I
Dual Voltage PU/PD
LVCMOS
0
0
2
I
rgmii1_txd1
vout2_d7
3
O
O
O
IO
IO
I
4
mii1_txd1
eQEP3_strobe
gpio4_24
8
10
14
15
0
0
Driver off
A13
vin2a_d17
vin2a_d17
vin2b_d6
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
2
I
rgmii1_txd0
vout2_d6
3
O
O
O
O
IO
I
4
mii1_txd2
ehrpwm3A
gpio4_25
8
10
14
15
Driver off
50
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
E11
vin2a_d18
vin2a_d18
0
I
PD
PD
PD
PD
15
15
15
1.8/3.3
1.8/3.3
1.8/3.3
vddshv1
vddshv1
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
vin2b_d5
2
I
rgmii1_rxc
vout2_d5
3
I
4
O
O
O
IO
I
mii1_txd3
ehrpwm3B
gpio4_26
8
10
14
15
0
Driver off
F11
vin2a_d19
vin2a_d19
vin2b_d4
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxctl
vout2_d4
3
I
4
O
O
IO
IO
I
mii1_txer
8
0
0
ehrpwm3_tripzone_input
gpio4_27
10
14
15
0
Driver off
B13
vin2a_d20
vin2a_d20
vin2b_d3
I
PD
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd3
vout2_d3
3
I
4
O
I
mii1_rxer
8
0
0
eCAP3_in_PWM3_out
gpio4_28
10
14
15
0
IO
IO
I
Driver off
E13
vin2a_d21
vin2a_d21
vin2b_d2
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd2
vout2_d2
3
I
4
O
I
mii1_col
8
0
gpio4_29
14
15
0
IO
I
Driver off
C13
vin2a_d22
vin2a_d22
vin2b_d1
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
2
I
rgmii1_rxd1
vout2_d1
3
I
4
O
I
mii1_crs
8
0
gpio4_30
14
15
IO
I
Driver off
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
51
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
D13
vin2a_d23
vin2a_d23
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
0
0
0
vin2b_d0
rgmii1_rxd0
vout2_d0
mii1_txen
gpio4_31
Driver off
vin2a_de0
vin2a_fld0
vin2b_fld1
vin2b_de1
vout2_de
emu6
2
I
3
I
4
O
O
IO
I
8
14
15
0
B7
vin2a_de0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
1
I
2
I
3
I
4
O
O
I
5
eQEP1B_in
gpio3_29
Driver off
vin2a_fld0
vin2b_clk1
vout2_clk
emu7
10
14
15
0
0
IO
I
C7
vin2a_fld0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
2
I
4
O
O
IO
IO
5
eQEP1_index
10
14
0
gpio3_30
gpmc_a27
gpmc_a18
Driver off
15
0
I
E8
vin2a_hsync0
vin2a_hsync0
vin2b_hsync1
vout2_hsync
emu8
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
3
I
4
O
O
I
5
uart9_rxd
7
1
0
0
spi4_sclk
8
IO
IO
IO
eQEP1_strobe
10
14
gpio3_31
gpmc_a27
Driver off
15
I
52
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
B8
vin2a_vsync0
vin2a_vsync0
0
I
PD
PD
15
1.8/3.3
vddshv1
Yes
Dual Voltage PU/PD
LVCMOS
vin2b_vsync1
vout2_vsync
emu9
3
I
4
O
O
O
IO
O
IO
I
5
uart9_txd
spi4_d1
7
8
0
ehrpwm1A
gpio4_0
10
14
15
Driver off
vss
A1, A25, AA13,
vss
GND
AA15, AA7, AA8,
AA9, AB8, AC13,
AE1, AE15, AE25,
G13, G16, G8, H10,
H12, H14, H16, H18,
H19, H8, J10, J12,
J14, J17, K11, K13,
K15, K17, K9, L11,
L13, L15, L18, L8,
M12, M14, M16,
M18, M20, M8, M9,
N12, N14, N16, N17,
N20, P11, P13, P15,
P17, P19, P9, R11,
R13, R15, R18, R19,
R8, R9, T10, T12,
T14, T16, T18, T8,
U10, U12, U14, U16,
U17, U19, V11, V13,
V15, V17, V19, V8,
V9, W19, W9, Y14,
Y16, Y17, Y7
AA12
AB11
AC10
vssa_osc0
vssa_osc1
Wakeup0
vssa_osc0
vssa_osc1
dcan1_rx
GND
GND
1
I
I
15
15
1.8/3.3
1.8/3.3
vdda33v_usb Yes
1
IHHV1833
IHHV1833
PU/PD
PU/PD
1
gpio1_0
sys_nirq2
14
Driver off
sys_nirq1
15
1
I
I
I
AB10
Wakeup3
vdda33v_usb Yes
1
gpio1_3
14
dcan2_rx
Driver off
xi_osc0
15
0
I
I
Y12
xi_osc0
xi_osc1
xo_osc0
1.8
1.8
1.8
vdda_osc
vdda_osc
vdda_osc
No
No
No
LVCMOS
Analog
AC11
AB12
xi_osc1
xo_osc0
0
0
I
LVCMOS
Analog
O
LVCMOS
Analog
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
53
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-1. Pin Attributes(1) (continued)
BALL
RESET REL.
MUXMODE
[8]
BALL
RESET
STATE [6]
BALL
RESET REL.
STATE [7]
I/O
PULL
UP/DOWN
TYPE [13]
MUXMODE
[4]
BUFFER
TYPE [12]
BALL NUMBER [1]
BALL NAME [2]
SIGNAL NAME [3]
TYPE [5]
VOLTAGE POWER [10]
VALUE [9]
HYS [11]
DSIS [14]
AA11
J25
xo_osc1
xref_clk0
xo_osc1
0
A
1.8
1.8/3.3
vdda_osc
vddshv3
No
Yes
LVCMOS
Analog
xref_clk0
0
I
PD
PD
15
Dual Voltage PU/PD
LVCMOS
mcasp2_axr8
mcasp1_axr4
mcasp1_ahclkx
mcasp5_ahclkx
vin1a_d0
1
IO
IO
O
O
I
0
0
2
3
4
7
0
clkout2
9
O
IO
IO
I
timer13
10
14
15
0
gpio6_17
Driver off
J24
xref_clk1
xref_clk1
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr9
mcasp1_axr5
mcasp2_ahclkx
mcasp6_ahclkx
vin1a_clk0
timer14
1
IO
IO
O
O
I
0
0
2
3
4
7
0
10
14
15
0
IO
IO
I
gpio6_18
Driver off
H24
xref_clk2
xref_clk2
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr10
mcasp1_axr6
mcasp3_ahclkx
mcasp7_ahclkx
timer15
1
IO
IO
O
O
IO
IO
I
0
0
2
3
4
10
14
15
0
gpio6_19
Driver off
H25
xref_clk3
xref_clk3
I
PD
PD
15
1.8/3.3
vddshv3
Yes
Dual Voltage PU/PD
LVCMOS
mcasp2_axr11
mcasp1_axr7
mcasp4_ahclkx
mcasp8_ahclkx
clkout3
1
IO
IO
O
O
O
IO
IO
I
0
0
2
3
4
9
timer16
10
14
15
gpio6_20
Driver off
54
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
(1) NA in this table stands for Not Applicable.
(2) For more information on recommended operating conditions, see Section 5.4, Recommended Operating Conditions.
(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.
(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40 Ω. For more information on DS[1:0] register configuration, see the
Device TRM.
(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).
(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.
For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.
(7) This function will not be supported on some pin-compatible roadmap devices. Pin compatibility can be maintained in the future by not using these GPIO signals.
(8) In PUx / PDy, x and y = 60 to 200 μA.
The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.
(9) The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in the section Sysboot Configuration of the Device
TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external
pull-downs should be implemented to keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
(10) This signal is valid only for High-Security devices. For more details, see 节 5.8 VPP Specification for One-Time Programmable (OTP) eFUSEs. For General Purpose devices do not
connect any signal, test point, or board trace to this signal.
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
55
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
4.3 Signal Descriptions
Many signals are available on multiple pins, according to the software configuration of the pin multiplexing options.
1. SIGNAL NAME: The name of the signal passing through the pin.
注
The subsystem multiplexing signals are not described in 表 4-1 and 表 4-27.
2. DESCRIPTION: Description of the signal
3. TYPE: Signal direction and type:
–
–
–
–
–
–
–
–
I = Input
O = Output
IO = Input or output
D = Open Drain
DS = Differential
A = Analog
PWR = Power
GND = Ground
4. BALL: Associated ball(s) bottom
注
For more information, see the Control Module / Control Module Register Manual section of the device TRM.
4.3.1 VIP
注
For more information, see the Video Input Port (VIP) section of the device TRM.
表 4-2. VIP Signal Descriptions
SIGNAL NAME
Video Input 1
vin1a_clk0
DESCRIPTION
TYPE
BALL
Video Input 1 Port A Clock input.Input clock for 8-bit 16-bit or 24-bit Port A video capture. Input data is sampled on
the CLK0 edge.
I
G3, J24, Y5
vin1a_d0
vin1a_d1
Video Input 1 Port A Data input
Video Input 1 Port A Data input
I
I
AA1, B23, F1, J25
B22, E2, Y3
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表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
A23, E1, W2
A22, AA3, C1
AA2, B21, D1
A21, D2, Y4
B1, D19, Y1
B2, E19, Y2
C2, F16
D3, E16
A2, E17
A19, B3
B18, C3
B16, C4
A3, B17
A18, B4
M1
vin1a_d2
vin1a_d3
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Data input
Video Input 1 Port A Field ID input
Video Input 1 Port A Field ID input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_de0
vin1a_fld0
vin1a_hsync0
vin1a_vsync0
vin1b_clk1
vin1b_d0
M2
L2
L1
K3
K2
J1
K1
C17, J2, Y6
C16, L3
AA4, B14, K4
AB1, D14, H1
J2, L5
Video Input 1 Port A Horizontal Sync input
Video Input 1 Port A Vertical Sync input
Video Input 1 Port B Clock input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Data input
L6, M1
vin1b_d1
M2, N5
L2, N6
vin1b_d2
vin1b_d3
L1, T4
vin1b_d4
K3, T5
vin1b_d5
K2, N2
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表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
vin1b_d6
DESCRIPTION
TYPE
BALL
Video Input 1 Port B Data input
Video Input 1 Port B Data input
Video Input 1 Port B Field ID input
Video Input 1 Port B Field ID input
I
I
I
I
I
I
J1, P2
K1, N1
L3, P4
G1, N4
K4, P3
H1, R2
vin1b_d7
vin1b_de1
vin1b_fld1
vin1b_hsync1
vin1b_vsync1
Video Input 1 Port B Horizontal Sync input
Video Input 1 Port B Vertical Sync input
Video Input 2
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
Video Input 2 Port A Clock input.
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Data input
Video Input 2 Port A Field ID input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
D8, L5
C8, L6
B9, N5
A7, N6
A9, T4
A8, T5
A11, N2
F10, P2
A10, N1
B10, P1
E10, N3
D10, R1
C10, P5
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
B7, P4
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表 4-2. VIP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
B7, C7, N4
E8, P3
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2b_clk1
vin2b_d0
Video Input 2 Port A Field ID input
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Video Input 2 Port A Horizontal Sync input
Video Input 2 Port A Vertical Sync input
Video Input 2 Port B Clock input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Data input
Video Input 2 Port B Field ID input
Video Input 2 Port B Field ID input
Video Input 2 Port B Horizontal Sync input
Video Input 2 Port B Vertical Sync input
B8, R2
AB1, C7, L4, H6
AA1, D13, A4
C13, Y3, E7
E13, W2, D6
AA3, B13, C5
AA2, F11, B5
E11, Y4, D7
A13, Y1, C6
A12, Y2, A5
AA4, B7, H2
B7, H6
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
vin2b_d7
vin2b_de1
vin2b_fld1
vin2b_hsync1
vin2b_vsync1
E8, Y5, B6
B8, Y6, A6
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4.3.2 DSS
表 4-3. DSS Signal Descriptions
SIGNAL NAME
DPI Video Output 2
vout2_clk
DESCRIPTION
TYPE
BALL
Video Output 2 Clock output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
Video Output 2 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
C7
D13
C13
E13
B13
F11
E11
A13
A12
B12
C11
D11
B11
C10
D10
E10
B10
A10
F10
A11
A8
vout2_d0
vout2_d1
vout2_d2
vout2_d3
vout2_d4
vout2_d5
vout2_d6
vout2_d7
vout2_d8
vout2_d9
vout2_d10
vout2_d11
vout2_d12
vout2_d13
vout2_d14
vout2_d15
vout2_d16
vout2_d17
vout2_d18
vout2_d19
vout2_d20
vout2_d21
vout2_d22
vout2_d23
vout2_de
A9
A7
B9
C8
Video Output 2 Data Enable output
B7
vout2_fld
Video Output 2 Field ID output. This signal is not used for embedded sync modes.
D8
vout2_hsync
Video Output 2 Horizontal Sync output. This signal is not used for embedded sync
modes.
E8
vout2_vsync
DPI Video Output 3
vout3_clk
Video Output 2 Vertical Sync output. This signal is not used for embedded sync modes.
O
B8
Video Output 3 Clock output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
Video Output 3 Data output
O
O
O
O
O
O
O
O
O
O
O
O
O
G3
F1
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
vout3_d0
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_d10
vout3_d11
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表 4-3. DSS Signal Descriptions (continued)
SIGNAL NAME
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d16
vout3_d17
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vout3_de
DESCRIPTION
TYPE
O
BALL
C3
C4
A3
B4
M1
M2
L2
Video Output 3 Data output
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
L1
Video Output 3 Data output
O
K3
K2
J1
Video Output 3 Data output
O
Video Output 3 Data output
O
Video Output 3 Data output
O
K1
J2
Video Output 3 Data Enable output
Video Output 3 Field ID output. This signal is not used for embedded sync modes.
O
vout3_fld
O
L3
vout3_hsync
Video Output 3 Horizontal Sync output. This signal is not used for embedded sync
modes.
O
K4
vout3_vsync
Video Output 3 Vertical Sync output. This signal is not used for embedded sync modes.
O
H1
4.3.3 HDMI
注
For more information, see the Display Subsystem / Display Subsystem Overview of the
device TRM.
表 4-4. HDMI Signal Descriptions
SIGNAL NAME
hdmi1_cec
DESCRIPTION
TYPE
IOD
BALL
E25, H23
E24, H22
F23
HDMI consumer electronic control
hdmi1_hpd
HDMI display hot plug detect
IO
hdmi1_ddc_scl
hdmi1_ddc_sda
hdmi1_clockx
hdmi1_clocky
hdmi1_data2x
hdmi1_data2y
hdmi1_data1x
hdmi1_data1y
hdmi1_data0x
hdmi1_data0y
HDMI display data channel clock
IOD
HDMI display data channel data
IOD
G21
HDMI clock differential positive or negative
HDMI clock differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 2 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 1 differential positive or negative
HDMI data 0 differential positive or negative
HDMI data 0 differential positive or negative
ODS
ODS
ODS
ODS
ODS
ODS
ODS
ODS
AE9
AD10
AE14
AD15
AE12
AD13
AE11
AD12
4.3.4 CSI2
注
For more information, see the CAL Subsystem / CAL Subsystem Overview of the device
TRM.
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表 4-5. CSI 2 Signal Descriptions
SIGNAL NAME
csi2_0_dx0
csi2_0_dy0
csi2_0_dx1
csi2_0_dy1
csi2_0_dx2
csi2_0_dy2
DESCRIPTION
TYPE
BALL
AC1
AB2
AD1
AC2
AE2
AD2
Serial data/clock input - line 0 (position 1)
Serial data/clock input - line 0 (position 1)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 1 (position 2)
Serial data/clock input - line 2 (position 3)
Serial data/clock input - line 2 (position 3)
I
I
I
I
I
I
4.3.5 EMIF
注
For more information, see the Memory Subsystem / EMIF Controller section of the device
TRM.
注
The index number 1 which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-6, EMIF
Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM
memories.
表 4-6. EMIF Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
BALL
AC19
AB18
AD21
AE21
AD18
AD16
AD17
AE18
AE17
AE16
AA16
AB16
AC18
AE19
AD19
AB19
AD20
AE20
AA18
AA20
Y21
ddr1_csn0
ddr1_cke
ddr1_ck
EMIF1 Chip Select 0
EMIF1 Clock Enable
EMIF1 Clock
ddr1_nck
ddr1_odt0
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_rst
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
ddr1_a1
ddr1_a2
ddr1_a3
ddr1_a4
ddr1_a5
ddr1_a6
ddr1_a7
ddr1_a8
ddr1_a9
ddr1_a10
ddr1_a11
ddr1_a12
ddr1_a13
EMIF1 Negative Clock
EMIF1 On-Die Termination for Chip Select 0
EMIF1 Column Address Strobe
EMIF1 Row Address Strobe
EMIF1 Write Enable
EMIF1 Reset output (DDR3-SDRAM only)
EMIF1 Bank Address
EMIF1 Bank Address
EMIF1 Bank Address
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
AC20
AA21
AC21
AC22
AC15
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Address Bus
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表 4-6. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
O
BALL
AB15
AC16
AA23
AC24
AB24
AD24
AB23
AC23
AD23
AE24
AA24
W25
Y23
ddr1_a14
ddr1_a15
ddr1_d0
EMIF1 Address Bus
EMIF1 Address Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Bus
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
EMIF1 Data Mask
O
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
ddr1_d1
ddr1_d2
ddr1_d3
ddr1_d4
ddr1_d5
ddr1_d6
ddr1_d7
ddr1_d8
ddr1_d9
ddr1_d10
ddr1_d11
ddr1_d12
ddr1_d13
ddr1_d14
ddr1_d15
ddr1_d16
ddr1_d17
ddr1_d18
ddr1_d19
ddr1_d20
ddr1_d21
ddr1_d22
ddr1_d23
ddr1_d24
ddr1_d25
ddr1_d26
ddr1_d27
ddr1_d28
ddr1_d29
ddr1_d30
ddr1_d31
ddr1_dqm0
ddr1_dqm1
ddr1_dqm2
ddr1_dqm3
ddr1_dqs0
AD25
AC25
AB25
AA25
W24
W23
U25
U24
W21
T22
U22
U23
T21
T23
T25
T24
P21
N21
P22
P23
P24
AE23
W22
U21
O
O
O
P25
Data strobe 0 input/output for byte 0 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
IO
AD22
ddr1_dqsn0
ddr1_dqs1
Data strobe 0 invert
IO
IO
AE22
Y24
Data strobe 1 input/output for byte 1 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn1
ddr1_dqs2
Data strobe 1 invert
IO
IO
Y25
V24
Data strobe 2 input/output for byte 2 of the 32-bit data bus. This signal is output to the
EMIF1 memory when writing and input when reading.
ddr1_dqsn2
Data strobe 2 invert
IO
V25
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表 4-6. EMIF Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
TYPE
BALL
ddr1_dqs3
Data strobe 3 input/output for byte 3 of the 32-bit data bus. This signal is output to the
IO
R24
EMIF1 memory when writing and input when reading.
ddr1_dqsn3
ddr1_vref0
Data strobe 3 invert
IO
A
R25
Y20
Reference Power Supply EMIF1
4.3.6 GPMC
注
For more information, see the Memory Subsystem / General-Purpose Memory Controller
section of the device TRM.
表 4-7. GPMC Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_ad0
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
GPMC Data 0 in A/D nonmultiplexed mode and additionally Address 1
in A/D multiplexed mode
IO
F1
GPMC Data 1 in A/D nonmultiplexed mode and additionally Address 2
in A/D multiplexed mode
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
E2
E1
GPMC Data 2 in A/D nonmultiplexed mode and additionally Address 3
in A/D multiplexed mode
GPMC Data 3 in A/D nonmultiplexed mode and additionally Address 4
in A/D multiplexed mode
C1
GPMC Data 4 in A/D nonmultiplexed mode and additionally Address 5
in A/D multiplexed mode
D1
GPMC Data 5 in A/D nonmultiplexed mode and additionally Address 6
in A/D multiplexed mode
D2
GPMC Data 6 in A/D nonmultiplexed mode and additionally Address 7
in A/D multiplexed mode
B1
GPMC Data 7 in A/D nonmultiplexed mode and additionally Address 8
in A/D multiplexed mode
B2
GPMC Data 8 in A/D nonmultiplexed mode and additionally Address 9
in A/D multiplexed mode
C2
GPMC Data 9 in A/D nonmultiplexed mode and additionally Address 10
in A/D multiplexed mode
D3
GPMC Data 10 in A/D nonmultiplexed mode and additionally Address
11 in A/D multiplexed mode
A2
GPMC Data 11 in A/D nonmultiplexed mode and additionally Address
12 in A/D multiplexed mode
B3
GPMC Data 12 in A/D nonmultiplexed mode and additionally Address
13 in A/D multiplexed mode
C3
GPMC Data 13 in A/D nonmultiplexed mode and additionally Address
14 in A/D multiplexed mode
C4
GPMC Data 14 in A/D nonmultiplexed mode and additionally Address
15 in A/D multiplexed mode
A3
GPMC Data 15 in A/D nonmultiplexed mode and additionally Address
16 in A/D multiplexed mode
B4
GPMC Address 0. Only used to effectively address 8-bit data
nonmultiplexed memories
G1, M1
G3, M2
H5, L2
H6, L1
gpmc_a1
GPMC address 1 in A/D nonmultiplexed mode and Address 17 in A/D
multiplexed mode
O
gpmc_a2
GPMC address 2 in A/D nonmultiplexed mode and Address 18 in A/D
multiplexed mode
O
gpmc_a3
GPMC address 3 in A/D nonmultiplexed mode and Address 19 in A/D
multiplexed mode
O
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表 4-7. GPMC Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
gpmc_a4
GPMC address 4 in A/D nonmultiplexed mode and Address 20 in A/D
multiplexed mode
O
K3
gpmc_a5
GPMC address 5 in A/D nonmultiplexed mode and Address 21 in A/D
multiplexed mode
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
K2
J1
gpmc_a6
GPMC address 6 in A/D nonmultiplexed mode and Address 22 in A/D
multiplexed mode
gpmc_a7
GPMC address 7 in A/D nonmultiplexed mode and Address 23 in A/D
multiplexed mode
K1
gpmc_a8
GPMC address 8 in A/D nonmultiplexed mode and Address 24 in A/D
multiplexed mode
K4
gpmc_a9
GPMC address 9 in A/D nonmultiplexed mode and Address 25 in A/D
multiplexed mode
H1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
GPMC address 10 in A/D nonmultiplexed mode and Address 26 in A/D
multiplexed mode
J2
GPMC address 11 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
L3
GPMC address 12 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
G1
GPMC address 13 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
A4, H3, G4
E7, H4, G3
D6, K6, F6
C5, K5, M1
B5, G2, D8
D7, F2, C7
A4(3), C6, H5
A5, E7(3), L4
B6, D6(3), H2
A6, C5(3), H6
B5, H5, C10, G4
D7(3), D10, G3
C6(3), F6, E10
A5(3), M1, B10
B6(3), D8, C7, E8
GPMC address 14 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 15 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 16 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 17 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 18 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 19 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 20 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 21 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 22 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 23 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 24 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 25 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 26 in A/D nonmultiplexed mode and unused in A/D
multiplexed mode
GPMC address 27 in A/D nonmultiplexed mode and Address 27 in A/D
multiplexed mode
gpmc_cs0
gpmc_cs1
gpmc_cs2
gpmc_cs3
gpmc_cs4
gpmc_cs5
gpmc_cs6
GPMC Chip Select 0 (active low)
GPMC Chip Select 1 (active low)
GPMC Chip Select 2 (active low)
GPMC Chip Select 3 (active low)
GPMC Chip Select 4 (active low)
GPMC Chip Select 5 (active low)
GPMC Chip Select 6 (active low)
O
O
O
O
O
O
O
F3
A6
G4
G3
H2
H6
H5
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表 4-7. GPMC Signal Descriptions (continued)
SIGNAL NAME
gpmc_cs7
gpmc_clk(1)(2)
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
DESCRIPTION
TYPE
BALL
L4
GPMC Chip Select 7 (active low)
O
IO
O
O
O
O
O
I
GPMC Clock output
L4
GPMC address valid active low or address latch enable
GPMC output enable active low or read enable
GPMC write enable active low
H5
G5
G6
gpmc_ben0
gpmc_ben1
gpmc_wait0
gpmc_wait1
GPMC lower-byte enable active low
GPMC upper-byte enable active low
GPMC external indication of wait 0
GPMC external indication of wait 1
H2
H6
F6
I
H5, L4
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) The gpio6_16.clkout1 signal can be used as an “always-on” alternative to gpmc_clk provided that the external device can support the
associated timing. See 表 5-47 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default and 表 5-49
GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate for timing information.
(3) The internal pull resistors for balls A4, E7, D6, C5, D7, C6, A5, B6 are permanently disabled when sysboot15 is set to 0 as described in
the section Sysboot Configuration of the Device TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should
be set to 1. If gpmc boot mode is used with SYSBOOT15=0 (not recommended) then external pull-downs should be implemented to
keep the address bus at logic-1 value during boot since the gpmc ms-address bits are high-z during boot.
4.3.7 Timers
注
For more information, see the Timers section of the device TRM.
表 4-8. Timers Signal Descriptions
SIGNAL NAME
timer1
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
H21, H6
H2, K22
H5, K23
A16, L4
A18, K6
B17, H4
B16, H3
B18, G1
A19, L3
E17, J2
E16, H1
F16, K4
J25
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
PWM output/event trigger input
timer2
timer3
timer4
timer5
timer6
timer7
timer8
timer9
timer10
timer11
timer12
timer13
timer14
timer15
timer16
J24
AA6, H24
AD3, H25
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4.3.8 I2C
注
For more information, see the Serial Communication Interface / Multimaster High-Speed I2C
Controller / HS I2C Environment / HS I2C in I2C Mode section of the device TRM.
注
I2C1 and I2C2 do NOT support HS-mode.
表 4-9. I2C Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Inter-Integrated Circuit Interface 1 (I2C1)
i2c1_scl
I2C1 Clock
I2C1 Data
IOD
IOD
G22
G23
i2c1_sda
Inter-Integrated Circuit Interface 2 (I2C2)
i2c2_scl
I2C2 Clock
I2C2 Data
IOD
IOD
G21
F23
i2c2_sda
Inter-Integrated Circuit Interface 3 (I2C3)
i2c3_scl
I2C3 Clock
I2C3 Data
IOD
IOD
C17, K22, L4, Y6
C16, H21, H5, Y5
i2c3_sda
Inter-Integrated Circuit Interface 4 (I2C4)
i2c4_scl
I2C4 Clock
I2C4 Data
IOD
IOD
B25, D17, M1, V5
C23, D16, M2, U5
i2c4_sda
Inter-Integrated Circuit Interface 5 (I2C5)
i2c5_scl
I2C5 Clock
I2C5 Data
IOD
IOD
B14, K3, U6
i2c5_sda
AC3, D14, K2
Inter-Integrated Circuit Interface 6 (I2C6)
i2c6_scl
I2C6 Clock
I2C6 Data
IOD
IOD
A24
D23
i2c6_sda
4.3.9 UART
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Perypheral Booting / Initialization Phase for UART Boot section of the device
TRM.
表 4-10. UART Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Asynchronous Receiver/Transmitter 1 (UART1)
uart1_dcdn
uart1_dsrn
uart1_dtrn
uart1_rin
UART1 Data Carrier Detect active low
UART1 Data Set Ready Active Low
UART1 Data Terminal Ready Active Low
UART1 Ring Indicator
I
I
N23
N25
N22
N24
L25
M25
L20
M24
O
I
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
UART1 Receive Data
I
UART1 Transmit Data
O
I
UART1 clear to send active low
UART1 request to send active low
O
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BALL
表 4-10. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
Universal Asynchronous Receiver/Transmitter 2 (UART2)
uart2_rxd
uart2_txd
uart2_ctsn
uart2_rtsn
UART2 Receive Data
I
N23
N25
N22
N24
UART2 Transmit Data
O
I
UART2 clear to send active low
UART2 request to send active low
O
Universal Asynchronous Receiver/Transmitter 3 (UART3)/IrDA
uart3_rxd
uart3_txd
uart3_ctsn
uart3_rtsn
uart3_rctx
uart3_sd
UART3 Receive Data
I
AA5, G25, N22, N5
AC4, F25, N24, N6
G24, L6, N23, T4
F24, L5, N25, T5
N23
UART3 Transmit Data
O
I
UART3 clear to send active low
UART3 request to send active low
Remote control data
O
O
O
O
Infrared transceiver configure/shutdown
Infrared data output
N25
uart3_irtx
N24
Universal Asynchronous Receiver/Transmitter 4 (UART4)
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
UART4 Receive Data
I
A24, E24, P4
D23, E25, P3
R2
UART4 Transmit Data
O
I
UART4 clear to send active low
UART4 request to send active low
O
R1
Universal Asynchronous Receiver/Transmitter 5 (UART5)
uart5_rxd
uart5_txd
uart5_ctsn
uart5_rtsn
UART5 Receive Data
I
B22, G24, M1, Y4
AA2, B23, F24, M2
AA3, L2
UART5 Transmit Data
O
I
UART5 clear to send active low
UART5 request to send active low
O
L1, W2
Universal Asynchronous Receiver/Transmitter 6 (UART6)
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
UART6 Receive Data
I
D14, K3, U5
B14, K2, V5
C14, J1
UART6 Transmit Data
O
I
UART6 clear to send active low
UART6 request to send active low
O
B15, K1
Universal Asynchronous Receiver/Transmitter 7 (UART7)
uart7_rxd
uart7_txd
uart7_ctsn
uart7_rtsn
UART7 Receive Data
I
A22, L2
A23, L1
B22
UART7 Transmit Data
O
I
UART7 clear to send active low
UART7 request to send active low
O
B23
Universal Asynchronous Receiver/Transmitter 8 (UART8)
uart8_rxd
uart8_txd
uart8_ctsn
uart8_rtsn
UART8 Receive Data
I
C23, H22, J1
B25, H23, K1
A24
UART8 Transmit Data
O
I
UART8 clear to send active low
UART8 request to send active low
O
D23
Universal Asynchronous Receiver/Transmitter 9 (UART9)
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
UART9 Receive Data
I
AC3, E8, L20
B8, M24, U6
AA5, C8
UART9 Transmit Data
O
I
UART9 clear to send active low
UART9 request to send active low
O
AC4, B9
Universal Asynchronous Receiver/Transmitter 10 (UART10)
uart10_rxd
uart10_txd
uart10_ctsn
UART10 Receive Data
I
O
I
A7, H21, N22, Y3
A9, AA1, K22, N24
A8, AA4
UART10 Transmit Data
UART10 clear to send active low
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-10. UART Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
UART10 request to send active low
TYPE
BALL
uart10_rtsn
O
A11, AB1
4.3.10 McSPI
注
For more information, see the Serial Communication Interface / Multichannel Serial
Peripheral Interface (McSPI) section of the device TRM.
表 4-11. SPI Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Serial Peripheral Interface 1
spi1_sclk(1)
SPI1 Clock
IO
IO
IO
IO
IO
IO
IO
C24
D24
D25
B24
C25
E24
E25
spi1_d1
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Data. Can be configured as either MISO or MOSI.
SPI1 Chip Select
spi1_d0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
SPI1 Chip Select
SPI1 Chip Select
SPI1 Chip Select
Serial Peripheral Interface 2
spi2_sclk(1)
SPI2 Clock
IO
IO
IO
IO
IO
IO
IO
G25
F25
G24
F24
C25
E24
E25
spi2_d1
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Data. Can be configured as either MISO or MOSI.
SPI2 Chip Select
spi2_d0
spi2_cs0
spi2_cs1
spi2_cs2
spi2_cs3
SPI2 Chip Select
SPI2 Chip Select
SPI2 Chip Select
Serial Peripheral Interface 3
spi3_sclk(1)
SPI3 Clock
IO
IO
IO
IO
IO
A18, C23, N5, Y1
B17, B25, N6, Y4
A24, AA2, B16, T4
AA3, B18, D23, T5
A19, W2
spi3_d1
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Data. Can be configured as either MISO or MOSI.
SPI3 Chip Select
spi3_d0
spi3_cs0
spi3_cs1
SPI3 Chip Select
Serial Peripheral Interface 4
spi4_sclk(1)
SPI4 Clock
IO
IO
IO
AC3, E8, K4, P4, Y3
AA1, B8, H1, P3, U6
spi4_d1
SPI4 Data. Can be configured as either MISO or MOSI.
SPI4 Data. Can be configured as either MISO or MOSI.
spi4_d0
AA4, AA5, C8, J2,
R2
spi4_cs0
SPI4 Chip Select
IO
AB1, AC4, B9, L3,
R1
spi4_cs1
spi4_cs2
spi4_cs3
SPI4 Chip Select
SPI4 Chip Select
SPI4 Chip Select
IO
IO
IO
G1, N6
H3, T4
H4, T5
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(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.11 QSPI
注
For more information about UART booting, see the Initialization / Device Initialization by
ROM Code / Memory Booting / SPI/QSPI Flash Devices section of the device TRM.
表 4-12. QSPI Signal Descriptions
SIGNAL NAME
qspi1_sclk
DESCRIPTION
TYPE
BALL
F2
QSPI1 Serial Clock
IO
I
qspi1_rtclk
QSPI1 Return Clock Input. Must be connected from QSPI1_SCLK on PCB. Refer
to PCB Guidelines for QSPI1
H3
qspi1_d0
QSPI1 Data[0]. This pin is output data for all commands/writes and for dual read
and quad read modes it becomes input data pin during read phase.
IO
K5
qspi1_d1
qspi1_d2
QSPI1 Data[1]. Input read data in all modes.
IO
IO
G2
K6
QSPI1 Data[2]. This pin is used only in quad read mode as input data pin during
read phase
qspi1_d3
QSPI1 Data[3]. This pin is used only in quad read mode as input data pin during
read phase
IO
H4
qspi1_cs0
qspi1_cs1
qspi1_cs2
qspi1_cs3
QSPI1 Chip Select[0]. This pin is Used for QSPI1 boot modes.
QSPI1 Chip Select[1]
IO
O
O
O
G4
G3
L1
QSPI1 Chip Select[2]
QSPI1 Chip Select[3]
K3
4.3.12 McASP
注
For more information, see the Serial Communication Interface / Multichannel Audio Serial
Port (McASP) section of the device TRM.
表 4-13. McASP Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Multichannel Audio Serial Port 1
McASP1 Transmit/Receive Data
mcasp1_axr0
mcasp1_axr1
mcasp1_axr2
mcasp1_axr3
mcasp1_axr4
mcasp1_axr5
mcasp1_axr6
mcasp1_axr7
mcasp1_axr8
mcasp1_axr9
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D14
B14
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
McASP1 Transmit/Receive Data
C14
B15
A15, J25
A14, J24
A17, H24
A16, H25
A18, H21
B17, K22
B16, K23
B18
A19
E17
E16
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表 4-13. McASP Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
IO
BALL
F16
mcasp1_axr15
mcasp1_fsx
mcasp1_aclkr(1)
McASP1 Transmit/Receive Data
McASP1 Transmit Frame Sync
McASP1 Receive Bit Clock
IO
C17
D16
D17
J25
IO
mcasp1_fsr
McASP1 Receive Frame Sync
McASP1 Transmit High-Frequency Master Clock
McASP1 Transmit Bit Clock
IO
mcasp1_ahclkx
mcasp1_aclkx(1)
O
IO
C16
Multichannel Audio Serial Port 2
McASP2 Transmit/Receive Data
mcasp2_axr0
mcasp2_axr1
mcasp2_axr2
mcasp2_axr3
mcasp2_axr4
mcasp2_axr5
mcasp2_axr6
mcasp2_axr7
mcasp2_axr8
mcasp2_axr9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr12
mcasp2_axr13
mcasp2_axr14
mcasp2_axr15
mcasp2_fsx
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
O
A20
B19
A21
B21
B20
C19
D20
C20
J25
J24
H24
H25
A22
A23
B22
B23
D19
J24
E19
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit/Receive Data
McASP2 Transmit Frame Sync
McASP2 Transmit High-Frequency Master Clock
McASP2 Transmit Bit Clock
mcasp2_ahclkx
mcasp2_aclkx(1)
IO
Multichannel Audio Serial Port 3
mcasp3_axr0
mcasp3_axr1
mcasp3_axr2
mcasp3_axr3
mcasp3_fsx
McASP3 Transmit/Receive Data
IO
IO
IO
IO
IO
O
B22
B23
A21
B21
A23
H24
A22
A22
A23
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit/Receive Data
McASP3 Transmit Frame Sync
McASP3 Transmit High-Frequency Master Clock
McASP3 Transmit Bit Clock
mcasp3_ahclkx
mcasp3_aclkx(1)
mcasp3_aclkr(1)
mcasp3_fsr
IO
IO
IO
McASP3 Receive Bit Clock
McASP3 Receive Frame Sync
Multichannel Audio Serial Port 4
mcasp4_axr0
mcasp4_axr1
mcasp4_axr2
mcasp4_axr3
mcasp4_fsx
McASP4 Transmit/Receive Data
IO
IO
IO
IO
IO
O
A24
D23
A15
A14
B25
H25
C23
C23
B25
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit/Receive Data
McASP4 Transmit Frame Sync
McASP4 Transmit High-Frequency Master Clock
McASP4 Transmit Bit Clock
mcasp4_ahclkx
mcasp4_aclkx(1)
mcasp4_aclkr(1)
mcasp4_fsr
IO
IO
IO
McASP4 Receive Bit Clock
McASP4 Receive Frame Sync
Multichannel Audio Serial Port 5
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表 4-13. McASP Signal Descriptions (continued)
SIGNAL NAME
mcasp5_axr0
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_fsx
DESCRIPTION
TYPE
IO
BALL
AA5
AC4
A17
A16
U6
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit/Receive Data
McASP5 Transmit Frame Sync
McASP5 Transmit High-Frequency Master Clock
McASP5 Transmit Bit Clock
IO
IO
IO
IO
mcasp5_ahclkx
mcasp5_aclkx(1)
mcasp5_aclkr(1)
mcasp5_fsr
O
J25
IO
AC3
AC3
U6
McASP5 Receive Bit Clock
IO
McASP5 Receive Frame Sync
IO
Multichannel Audio Serial Port 6
mcasp6_axr0
mcasp6_axr1
mcasp6_axr2
mcasp6_axr3
mcasp6_ahclkx
mcasp6_aclkx(1)
mcasp6_fsx
McASP6 Transmit/Receive Data
IO
IO
IO
IO
O
A18
B17
C14
B15
J24
B16
B18
B16
B18
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit/Receive Data
McASP6 Transmit High-Frequency Master Clock
McASP6 Transmit Bit Clock
IO
IO
IO
IO
McASP6 Transmit Frame Sync
McASP6 Receive Bit Clock
mcasp6_aclkr(1)
mcasp6_fsr
McASP6 Receive Frame Sync
Multichannel Audio Serial Port 7
mcasp7_aclkr(1)
mcasp7_aclkx(1)
mcasp7_ahclkx
mcasp7_axr0
mcasp7_axr1
mcasp7_axr2
mcasp7_axr3
mcasp7_fsr
McASP7 Receive Bit Clock I/O
IO
IO
O
E16
E16
H24
A19
E17
D16
D17
F16
F16
McASP7 Transmit Bit Clock I/O
McASP7 Transmit High-Frequency Master Clock
McASP7 Transmit/Receive Data I/O
McASP7 Transmit/Receive Data I/O
McASP7 Transmit/Receive Data I/O
McASP7 Transmit/Receive Data I/O
McASP7 Receive Frame Sync I/O
McASP7 Transmit Frame Sync I/O
IO
IO
IO
IO
IO
IO
mcasp7_fsx
Multichannel Audio Serial Port 8
mcasp8_aclkr(1)
mcasp8_aclkx(1)
mcasp8_ahclkx
mcasp8_axr0
mcasp8_axr1
mcasp8_fsr
McASP8 Receive Bit Clock I/O
IO
IO
O
D20
D20
H25
B20
C19
C20
C20
McASP8 Transmit Bit Clock I/O
McASP8 Transmit High-Frequency Master Clock I/O
McASP8 Transmit/Receive Data I/O
McASP8 Transmit/Receive Data I/O
McASP8 Receive Frame Sync I/O
McASP8 Transmit Frame Sync I/O
IO
IO
IO
IO
mcasp8_fsx
(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any non monotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.13 USB
注
For more information, see: Serial Communication Interface / SuperSpeed USB DRD
Subsystem section of the device TRM.
72
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表 4-14. Universal Serial Bus Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
Universal Serial Bus 1
usb1_dm
USB1 USB2.0 differential signal pair (negative)
USB1 USB2.0 differential signal pair (positive)
USB1 Drive VBUS signal
IODS
IODS
O
AB7
AC6
AD3
AE5
AD6
AE3
AD4
usb1_dp
usb1_drvvbus
usb_rxn0(1)
usb_rxp0(1)
usb_txn0(1)
usb_txp0(1)
USB1 USB3.0 receiver negative lane
USB1 USB3.0 receiver positive lane
USB1 USB3.0 transmitter negative lane
USB1 USB3.0 transmitter positive lane
IDS
IDS
ODS
ODS
Universal Serial Bus 2
usb2_dm
USB2 USB2.0 differential signal pair (negative)
USB2 USB2.0 differential signal pair (positive)
USB2 Drive VBUS signal
IO
IO
O
AC5
AB6
AA6
usb2_dp
usb2_drvvbus
Universal Serial Bus 3
usb3_ulpi_d0
usb3_ulpi_d1
usb3_ulpi_d2
usb3_ulpi_d3
usb3_ulpi_d4
usb3_ulpi_d5
usb3_ulpi_d6
usb3_ulpi_d7
usb3_ulpi_nxt
usb3_ulpi_dir
usb3_ulpi_stp
usb3_ulpi_clk
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI 8-bit data bus
USB3 - ULPI next
IODS
IODS
IO
IO
IO
IO
IO
IO
I
R2, W2
AA3, R1
AA2, N2
P2, Y4
N1, Y1
P1, Y2
N3, Y6
N4, Y5
P3, Y3
USB3 - ULPI bus direction
USB3 - ULPI stop
I
AA1, P4
AA4, T5
AB1, T4
O
USB3 - ULPI functional clock
I
(1) Signals are enabled by selecting the correct field in the PCIE_B1C0_MODE_SEL register. There are no CTRL_CORE_PAD* register
involved.
4.3.14 PCIe
注
For more information, see the Serial Communication Interfaces / PCIe Controllers and the
Shared PHY Component Subsystems / PCIe Shared PHY Susbsytem sections of the device
TRM.
表 4-15. PCIe Signal Descriptions
SIGNAL NAME
pcie_rxn0
pcie_rxp0
pcie_txn0
DESCRIPTION
TYPE
IDS
BALL
AE6
AD7
AE8
AD9
AE5
PCIe1_PHY_RX Receive Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_RX Receive Data Lane 0 (positive) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (negative) - mapped to PCIe_SS1 only.
PCIe1_PHY_TX Transmit Data Lane 0 (positive) - mapped to PCIe_SS1 only.
IDS
ODS
ODS
IDS
pcie_txp0
pcie_rxn1
PCIe2_PHY_RX Receive Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
pcie_rxp1
pcie_txn1
pcie_txp1
PCIe2_PHY_RX Receive Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
IDS
ODS
ODS
AD6
AE3
AD4
PCIe2_PHY_TX Transmit Data Lane 1 (negative) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
PCIe2_PHY_TX Transmit Data Lane 1 (positive) - mapped to either PCIe_SS1
(dual lane- mode) or PCIe_SS2 (single lane- mode)
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表 4-15. PCIe Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
ljcb_clkn
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(negative)
IODS
AB9
ljcb_clkp
PCIe1_PHY / PCIe2_PHY shared Reference Clock Input / Output Differential Pair
(positive)
IODS
AC8
4.3.15 DCAN
注
For more information, see the Serial Communication Interface / DCAN section of the device
TRM.
表 4-16. DCAN Signal Descriptions
SIGNAL NAME
DCAN 1
DESCRIPTION
TYPE
BALL
dcan1_rx
DCAN1 receive data pin
DCAN1 transmit data pin
IO
IO
H23, AC10
H22
dcan1_tx
DCAN 2
dcan2_rx
DCAN2 receive data pin
DCAN2 transmit data pin
IO
IO
E25, K22, AB10
E24, H21
dcan2_tx
4.3.16 GMAC_SW
注
For more information, see the Serial Communication Interfaces / Ethernet Controller section
of the device TRM.
表 4-17. GMAC Signal Descriptions
SIGNAL NAME
rgmii0_rxc
DESCRIPTION
TYPE
BALL
N2
RGMII0 Receive Clock
RGMII0 Receive Control
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Receive Data
RGMII0 Transmit Clock
RGMII0 Transmit Enable
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII0 Transmit Data
RGMII1 Receive Clock
RGMII1 Receive Control
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Receive Data
RGMII1 Transmit Clock
I
I
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
P2
I
N4
I
N3
I
P1
I
N1
O
O
O
O
O
O
I
T4
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
rgmii1_rxc
T5
R1
R2
P3
P4
E11
F11
D13
C13
E13
B13
B11
rgmii1_rxctl
rgmii1_rxd0
rgmii1_rxd1
rgmii1_rxd2
rgmii1_rxd3
rgmii1_txc
I
I
I
I
I
O
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表 4-17. GMAC Signal Descriptions (continued)
SIGNAL NAME
rgmii1_txctl
rgmii1_txd0
rgmii1_txd1
rgmii1_txd2
rgmii1_txd3
mii1_col
DESCRIPTION
TYPE
BALL
D11
A13
A12
B12
C11
E13
C13
B11
E10
F10
A10
B10
D11
B13
C11
B12
A12
A13
E11
D13
F11
L5
RGMII1 Transmit Enable
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
RGMII1 Transmit Data
MII1 Collision Detect (Sense) input
MII1 Carrier Sense input
MII1 Receive Clock
O
O
O
O
O
I
mii1_crs
I
mii1_rxclk
mii1_rxd0
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxdv
mii1_rxer
mii1_txclk
mii1_txd0
mii1_txd1
mii1_txd2
mii1_txd3
mii1_txen
mii1_txer
mii0_col
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data
I
MII1 Receive Data Valid input
MII1 Receive Data Error input
MII1 Transmit Clock
I
I
I
MII1 Transmit Data
O
O
O
O
O
O
I
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data
MII1 Transmit Data Enable Output
MII1 Transmit Error
MII0 Collision Detect (Sense) input
MII0 Carrier Sense input
MII0 Receive Clock
mii0_crs
I
P4
mii0_rxclk
mii0_rxd0
mii0_rxd1
mii0_rxd2
mii0_rxd3
mii0_rxdv
mii0_rxer
mii0_txclk
mii0_txd0
mii0_txd1
mii0_txd2
mii0_txd3
mii0_txen
mii0_txer
rmii1_crs
rmii1_rxd0
rmii1_rxd1
rmii1_rxer
rmii1_txd0
rmii1_txd1
rmii1_txen
rmii0_crs
rmii0_rxd0
rmii0_rxd1
I
N6
MII0 Receive Data
I
R1
MII0 Receive Data
I
R2
MII0 Receive Data
I
T5
MII0 Receive Data
I
T4
MII0 Receive Data Valid input
MII0 Receive Data Error input
MII0 Transmit Clock
I
N5
I
P3
I
N2
MII0 Transmit Data
O
O
O
O
O
O
I
N4
MII0 Transmit Data
N3
MII0 Transmit Data
N1
MII0 Transmit Data
P2
MII0 Transmit Data Enable Output
MII0 Transmit Error
P1
L6
RMII1 Carrier Sense input
RMII1 Receive Data
N5
I
T5
RMII1 Receive Data
I
T4
RMII1 Receive Data Error input
RMII1 Transmit Data
I
N6
O
O
O
I
N1
RMII1 Transmit Data
P2
RMII1 Transmit Data Enable output
RMII0 Carrier Sense input
RMII0 Receive Data
N2
P4
I
R1
RMII0 Receive Data
I
R2
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表 4-17. GMAC Signal Descriptions (continued)
SIGNAL NAME
rmii0_rxer
rmii0_txd0
rmii0_txd1
rmii0_txen
mdio_mclk
mdio_d
DESCRIPTION
TYPE
BALL
RMII0 Receive Data Error input
RMII0 Transmit Data
I
P3
O
O
O
O
IO
N4
N3
RMII0 Transmit Data
RMII0 Transmit Data Enable output
Management Data Serial Clock
Management Data
P1
D10, E24, L5, Y5
C10, E25, L6, Y6
4.3.17 eMMC/SD/SDIO
注
For more information, see the HS MMC/SDIO section of the device TRM.
表 4-18. eMMC/SD/SDIO Signal Descriptions
SIGNAL NAME
Multi Media Card 1
mmc1_clk(1)
mmc1_cmd
DESCRIPTION
TYPE
BALL
MMC1 clock
IO
IO
IO
IO
IO
IO
I
U3
V4
V3
V2
W1
V1
U5
V5
MMC1 command
MMC1 data bit 0
MMC1 data bit 1
MMC1 data bit 2
MMC1 data bit 3
MMC1 Card Detect
MMC1 Write Protect
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_sdwp
Multi Media Card 2
mmc2_clk(1)
mmc2_cmd
I
MMC2 clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
I
B5
A6
MMC2 command
MMC2 data bit 0
MMC2 data bit 1
MMC2 data bit 2
MMC2 data bit 3
MMC2 data bit 4
MMC2 data bit 5
MMC2 data bit 6
MMC2 data bit 7
MMC2 Card Detect
MMC2 Write Protect
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_sdcd
mmc2_sdwp
Multi Media Card 3
mmc3_clk(1)
mmc3_cmd
D7
C6
A5
B6
A4
E7
D6
C5
H22
H23
I
MMC3 clock
IO
IO
IO
IO
IO
IO
IO
IO
IO
Y2
Y1
MMC3 command
MMC3 data bit 0
MMC3 data bit 1
MMC3 data bit 2
MMC3 data bit 3
MMC3 data bit 4
MMC3 data bit 5
MMC3 data bit 6
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
Y4
AA2
AA3
W2
Y3
AA1
AA4
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表 4-18. eMMC/SD/SDIO Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
BALL
AB1
E24
mmc3_dat7
mmc3_sdcd
mmc3_sdwp
Multi Media Card 4
mmc4_clk(1)
mmc4_cmd
MMC3 data bit 7
IO
MMC3 Card Detect
MMC3 Write Protect
I
I
E25
MMC4 clock
IO
IO
I
L20
M24
L25
MMC4 command
MMC4 Card Detect
MMC4 Write Protect
MMC4 data bit 0
MMC4 data bit 1
MMC4 data bit 2
MMC4 data bit 3
mmc4_sdcd
mmc4_sdwp
mmc4_dat0
I
M25
N23
N25
N22
N24
IO
IO
IO
IO
mmc4_dat1
mmc4_dat2
mmc4_dat3
(1) By default, this clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer
to serve as the internal reference signal. mmc1_clk and mmc2_clk have an optional software programmable setting to use an 'internal
loopback clock' instead of the default 'pad loopback clock'. If the 'pad loopback clock' is used, series termination is recommended (as
close to device pin as possible) to improve signal integrity of the clock input. Any nonmonotonicity in voltage that occurs at the pad
loopback clock pin between VIH and VIL must be less than VHYS
.
4.3.18 GPIO
注
For more information, see the General-Purpose Interface section of the device TRM.
表 4-19. GPIOs Signal Descriptions
SIGNAL NAME
GPIO 1
DESCRIPTION
TYPE
BALL
gpio1_0
General-Purpose Input
I
AC10
AB10
B20
C20
F1
gpio1_3
General-Purpose Input
I
gpio1_4
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
gpio1_5
gpio1_6
gpio1_7
E2
gpio1_8
E1
gpio1_9
C1
gpio1_10
gpio1_11
gpio1_12
gpio1_13
gpio1_14
gpio1_15
gpio1_16
gpio1_17
gpio1_18
gpio1_19
gpio1_20
gpio1_21
gpio1_22
gpio1_23
D1
D2
B1
B2
H22
H23
N22
N24
C3
C4
A3
B4
Y3
AA1
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表 4-19. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio1_24
gpio1_25
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
DESCRIPTION
TYPE
IO
BALL
AA4
AB1
K3
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
K2
IO
J1
IO
K1
IO
K4
IO
H1
GPIO2
gpio2_0
gpio2_1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
J2
L3
gpio2_2
G1
H3
H4
K6
K5
G2
F2
A4
E7
D6
C5
B5
D7
C6
A5
B6
A6
F3
G4
G3
L4
gpio2_3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
gpio2_20
gpio2_21
gpio2_22
gpio2_23
gpio2_24
gpio2_25
gpio2_26
gpio2_27
gpio2_28
gpio2_29
H5
G5
G6
H2
H6
F6
D20
GPIO 3
gpio3_28
gpio3_29
gpio3_30
gpio3_31
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
D8
B7
C7
E8
GPIO 4
gpio4_0
gpio4_1
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
B8
C8
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表 4-19. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio4_2
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
B9
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
gpio4_3
A7
gpio4_4
A9
gpio4_5
A8
gpio4_6
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
B18
A19
A12
A13
E11
F11
B13
E13
C13
D13
gpio4_7
gpio4_8
gpio4_9
gpio4_10
gpio4_11
gpio4_12
gpio4_13
gpio4_14
gpio4_15
gpio4_16
gpio4_17
gpio4_18
gpio4_24
gpio4_25
gpio4_26
gpio4_27
gpio4_28
gpio4_29
gpio4_30
gpio4_31
GPIO 5
gpio5_0
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D16
D17
D14
B14
C14
B15
A15
A14
A17
A16
A18
B17
B16
A22
A23
L5
gpio5_1
gpio5_2
gpio5_3
gpio5_4
gpio5_5
gpio5_6
gpio5_7
gpio5_8
gpio5_9
gpio5_10
gpio5_11
gpio5_12
gpio5_13
gpio5_14
gpio5_15
gpio5_16
gpio5_17
gpio5_18
gpio5_19
gpio5_20
L6
P5
N5
N6
T4
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表 4-19. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio5_21
gpio5_22
gpio5_23
gpio5_24
gpio5_25
gpio5_26
gpio5_27
gpio5_28
gpio5_29
gpio5_30
gpio5_31
DESCRIPTION
TYPE
IO
BALL
T5
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
P4
IO
P3
IO
R2
R1
N2
P2
IO
IO
IO
IO
N1
P1
IO
IO
N3
N4
IO
GPIO 6
gpio6_4
gpio6_5
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
E17
E16
F16
C19
A21
B21
Y5
gpio6_6
gpio6_7
gpio6_8
gpio6_9
gpio6_10
gpio6_11
gpio6_12
gpio6_13
gpio6_14
gpio6_15
gpio6_16
gpio6_17
gpio6_18
gpio6_19
gpio6_20
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
gpio6_26
gpio6_27
gpio6_28
gpio6_29
gpio6_30
gpio6_31
Y6
AD3
AA6
H21
K22
K23
J25
J24
H24
H25
U3
V4
V3
V2
W1
V1
U5
V5
Y2
Y1
Y4
GPIO 7
gpio7_0
gpio7_1
gpio7_2
gpio7_3
gpio7_4
gpio7_5
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
IO
IO
AA2
AA3
W2
M1
M2
L2
80
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表 4-19. GPIOs Signal Descriptions (continued)
SIGNAL NAME
gpio7_6
DESCRIPTION
TYPE
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
BALL
L1
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
gpio7_7
C24
D24
D25
B24
C25
E24
E25
G25
F25
G24
F24
C2
gpio7_8
gpio7_9
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
gpio7_15
gpio7_16
gpio7_17
gpio7_18
gpio7_19
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
gpio7_28
gpio7_29
gpio7_30
gpio7_31
GPIO 8
D3
L25
M25
L20
M24
N23
N25
A2
B3
C17
C16
gpio8_27
gpio8_28
gpio8_29
gpio8_30
gpio8_31
General-Purpose Input
I
L23
J20
K25
C21
C22
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
General-Purpose Input/Output
IO
IO
IO
IO
4.3.19 PWM
注
For more information, see the Pulse-Width Modulation (PWM) SS section of the device TRM.
表 4-20. PWM Signal Descriptions
SIGNAL NAME
PWMSS1
DESCRIPTION
TYPE
BALL
eCAP1_in_PWM1_out ECAP1 Capture Input / PWM Output
IO
I
A7
A9
A8
B9
ehrpwm1_synci
ehrpwm1_synco
EHRPWM1 Sync Input
EHRPWM1 Sync Output
O
IO
ehrpwm1_tripzone_in EHRPWM1 Trip Zone Input
put
ehrpwm1A
ehrpwm1B
EHRPWM1 Output A
EHRPWM1 Output B
EQEP1 Index Input
O
O
B8
C8
C7
eQEP1_index
IO
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表 4-20. PWM Signal Descriptions (continued)
SIGNAL NAME
eQEP1_strobe
eQEP1A_in
DESCRIPTION
TYPE
BALL
E8
EQEP1 Strobe Input
IO
EQEP1 Quadrature Input A
EQEP1 Quadrature Input B
I
I
D8
eQEP1B_in
B7
PWMSS2
eCAP2_in_PWM2_out ECAP2 Capture Input / PWM Output
IO
IO
B11, Y1
C10, Y2
ehrpwm2_tripzone_in EHRPWM2 Trip Zone Input
put
ehrpwm2A
ehrpwm2B
EHRPWM2 Output A
EHRPWM2 Output B
EQEP2 Index Input
O
O
IO
IO
I
E10, Y5
D10, Y6
A10
eQEP2_index
eQEP2_strobe
eQEP2A_in
eQEP2B_in
EQEP2 Strobe Input
B10
EQEP2 Quadrature Input A
EQEP2 Quadrature Input B
A11
I
F10
PWMSS3
eCAP3_in_PWM3_out ECAP3 Capture Input / PWM Output
IO
IO
AB1, B13
AA4, F11
ehrpwm3_tripzone_in EHRPWM3 Trip Zone Input
put
ehrpwm3A
ehrpwm3B
EHRPWM3 Output A
EHRPWM3 Output B
EQEP3 Index Input
O
O
IO
IO
I
A13, Y3
AA1, E11
AA3, B12
A12, W2
D11, Y4
eQEP3_index
eQEP3_strobe
eQEP3A_in
eQEP3B_in
EQEP3 Strobe Input
EQEP3 Quadrature Input A
EQEP3 Quadrature Input B
I
AA2, C11
4.3.20 Emulation and Debug Subsystem
注
For more information, see the On-Chip Debug Support / Debug Ports section of the device
TRM.
表 4-21. Debug Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
tms
JTAG test port mode select. An external pullup resistor should be used on this
ball.
IO
L21
tdi
JTAG test data
JTAG test port data
JTAG test clock
JTAG test reset
JTAG return clock
Emulator pin 0
Emulator pin 1
Emulator pin 2
Emulator pin 3
Emulator pin 4
Emulator pin 5
Emulator pin 6
Emulator pin 7
Emulator pin 8
I
L23
J20
K21
L22
K25
C21
C22
E14
F14
F13
D8
tdo
O
I
tclk
trstn
I
rtck
O
IO
IO
IO
IO
IO
O
O
O
O
emu0
emu1
emu2
emu3
emu4
emu5
emu6
emu7
emu8
B7
C7
E8
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表 4-21. Debug Signal Descriptions (continued)
SIGNAL NAME
emu9
DESCRIPTION
Emulator pin 9
Emulator pin 10
Emulator pin 11
Emulator pin 12
Emulator pin 13
Emulator pin 14
Emulator pin 15
Emulator pin 16
Emulator pin 17
Emulator pin 18
Emulator pin 19
TYPE
O
BALL
B8
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
O
C8
O
B9
O
A7
O
A9
O
A8
O
A11
F10
A10
B10
E10
O
O
O
O
4.3.21 System and Miscellaneous
4.3.21.1 Sysboot
注
For more information, see the Initialization (ROM Code) section of the device TRM.
表 4-22. Sysboot Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
sysboot6
sysboot7
sysboot8
sysboot9
sysboot10
sysboot11
sysboot12
sysboot13
sysboot14
Boot Mode Configuration 0. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
F1
Boot Mode Configuration 1. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
I
I
I
I
I
I
I
I
I
I
I
I
I
I
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
C3
C4
A3
Boot Mode Configuration 2. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 3. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 4. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 5. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 6. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 7. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 8. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 9. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 10. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 11. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 12. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 13. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
Boot Mode Configuration 14. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
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表 4-22. Sysboot Signal Descriptions (continued)
SIGNAL NAME DESCRIPTION
sysboot15 Boot Mode Configuration 15. The value latched on this pin upon porz reset release
will determine the boot mode configuration of the device.
TYPE
BALL
I
B4
4.3.21.2 Power, Reset, and Clock Management (PRCM)
注
For more information, see PRCM section of the device TRM.
表 4-23. PRCM Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
clkout1
Device Clock output 1. Can be used externally for devices with non-
critical timing requirements, or for debug, or as a reference clock on
GPMC as described in 表 5-47 GPMC/NOR Flash Interface Switching
Characteristics - Synchronous Mode - Default and 表 5-49
GPMC/NOR Flash Interface Switching Characteristics - Synchronous
Mode - Alternate.
O
K23, L4
clkout2
clkout3
porz
Device Clock output 2. Can be used externally for devices with non-
critical timing requirements, or for debug.
O
O
I
H5, J25
H25
Device Clock output 3. Can be used xternally for devices with non-
critical timing requirements, or for debug.
Power on Reset (active low) input must be asserted low during a
device power up sequence or cold reset state when all supplies are
disabled. Typically, an external PMIC is the source and sets porz
high after all supplies reach valid operating levels. Asserting porz low
puts the entire device in a safe reset state.
F19
resetn
rstoutn
Reset (active low) input’s falling edge can trigger a device warm reset
state from an external component. This signal should be high prior to
or simultaneous with, porz rising. If the signal is not used in the
system, resetn should be pulled high with an external pull-up resistor
to vddshv3.
I
K24
E20
Reset out (Active low) output is asserted low whenever any global
reset condition exists. After a brief delay, it will be set high upon
removal of the internal global reset condition (i.e. porz, warm reset). It
is only functional after its output buffer’s reference voltage (vddshv3)
is valid. If it is used as a reset for device peripheral components, then
it should be AND gated with porz to avoid the possibility of reset
signal glitches during a power up sequence.(2)
O
xi_osc0
xi_osc1
System Oscillator OSC0 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC0 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used.
I
I
Y12
Auxiliary Oscillator OSC1 Crystal input / LVCMOS clock input.
Functions as the input connection to a crystal when the internal
oscillator OSC1 is used. Functions as an LVCMOS-compatible input
clock when an external oscillator is used
AC11
xo_osc0
xo_osc1
System Oscillator OSC0 Crystal output
O
O
I
AB12
AA11
J25
Auxiliary Oscillator OSC1 Crystal output
xref_clk0
External Reference Clock 0. For Audio and other Peripherals.
External Reference Clock 1. For Audio and other Peripherals.
External Reference Clock 2. For Audio and other Peripherals.
External Reference Clock 3. For Audio and other Peripherals.
xref_clk1
I
J24
xref_clk2
I
H24
H25
P5
xref_clk3
RMII_MHZ_50_CLK(1)
I
RMII Reference Clock (50MHz). This pin is an input when external
reference is used or output when internal reference is used.
IO
84
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(1) This clock signal is implemented as 'pad loopback' inside the device - the output signal is looped back through the input buffer to serve
as the internal reference signal. Series termination is recommended (as close to device pin as possible) to improve signal integrity of the
clock input. Any nonmonotonicity in voltage that occurs at the pad loopback clock pin between VIH and VIL must be less than VHYS
.
(2) Note that rstoutn is only valid after vddshv3 is valid. If the rstoutn signal will be used as a reset into other devices attached to the SOC, it
must be AND'ed with porz. This will prevent glitches occurring during supply ramping being propagated.
4.3.21.3 System Direct Memory Access (SDMA)
注
For more information, see the DMA Controllers / System DMA section of the device TRM.
表 4-24. SDMA Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
G1, L4
H3, H5
H2
dma_evt1
dma_evt2
dma_evt3
dma_evt4
System DMA Event Input 1
I
I
I
I
System DMA Event Input 2
System DMA Event Input 3
System DMA Event Input 4
H6
4.3.21.4 Interrupt Controllers (INTC)
注
For more information, see the Interrupt Controllers section of the device TRM.
表 4-25. INTC Signal Descriptions
SIGNAL NAME DESCRIPTION
TYPE
BALL
nmin_dsp
Non maskable interrupt input, active-low. This pin can be optionally routed to the
DSP NMI input or as generic input to the Arm cores. Note that by default this pin
has an internal pulldown resistor enabled. This internal pulldown should be disabled
or countered by a stronger external pullup resistor before routing to the DSP or Arm
processors.
I
L24
sys_nirq2
sys_nirq1
External interrupt event to any device INTC
External interrupt event to any device INTC
I
I
AC10
AB10
4.3.22 Power Supplies
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs section of the device TRM.
表 4-26. Power Supply Signal Descriptions
SIGNAL NAME
DESCRIPTION
TYPE
BALL
PWR
J15, J16, J18, K12,
K18, L12, L17, M11,
M13, M15, M17, N11,
N13, N15, N18, P10,
P12, P14, P16, P18,
R10, R12, R14, R16,
R17, T11, T13, T15,
T17, T9, U11, U13,
U15, U18, U9, V10,
V12, V14, V16, V18,
W10, W12, W14, W16
vdd
Core voltage domain supply
vpp(2)
eFuse power supply
PWR
F20
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BALL
表 4-26. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
GND
A1, A25, AA13, AA15,
AA7, AA8, AA9, AB8,
AC13, AE1, AE15,
AE25, G13, G16, G8,
H10, H12, H14, H16,
H18, H19, H8, J10,
J12, J14, J17, K11,
K13, K15, K17, K9,
L11, L13, L15, L18,
L8, M12, M14, M16,
M18, M20, M8, M9,
N12, N14, N16, N17,
N20, P11, P13, P15,
P17, P19, P9, R11,
R13, R15, R18, R19,
R8, R9, T10, T12,
T14, T16, T18, T8,
U10, U12, U14, U16,
U17, U19, V11, V13,
V15, V17, V19, V8,
V9, W19, W9, Y14,
Y16, Y17, Y7
vss
Ground
cap_vbbldo_gpu (1)
cap_vbbldo_iva (1)
cap_vbbldo_mpu (1)
MM (SGX) Back bias supply
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
CAP
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
T7
G14
F17
IVA Back bias supply
MPU back bias supply
(1)
cap_vbbldo_dsp
External capacitor connection for the DSP vbb ldo output
SRAM array supply for core memories
SRAM array supply for core memories
SRAM array supply for core memories
SRAM array supply for SGX (MM) memories
SRAM array supply for IVA memories
External capacitor connection for the DSP
External capacitor connection for the MPU SRAM array ldo output
HS USB1 3p3 supply
F8
cap_vddram_core1(1)
cap_vddram_core3 (1)
cap_vddram_core4 (1)
U20
K7
G19
V7
(1)
cap_vddram_gpu
(1)
cap_vddram_iva
G12
L7
cap_vddram_dsp (1)
cap_vddram_mpu (1)
vdda33v_usb1
vdda33v_usb2
vdda_core_gmac
vdda_csi
G18
AA10
Y10
HS USB1 3p3 supply
DPLL_CORE and CORE HSDIVIDER analog power supply
CSI Interface 1.8v Supply
L9
T6
vdda_dsp_iva
vdda_mpu_abe
vdda_per
DSP PLL and IVA PLL analog power supply
MPU_ABE PLL analog power supply
DPLL_ABE, DPLL_PER, and PER HSDIVIDER analog power supply
HS USB2 1.8V analog power supply
MLBP IO power supply
K10, L10
K16, L16
M10
Y8
vdda_usb2
vdds_mlbp
P7, R7
vdd_dsp
DSP voltage domain supply
H11, H13, H9, J11,
J13, J9
vdda_ddr
vdda_debug
vdda_gpu
vdda_hdmi
vdda_osc
vdda_pcie
vdda_usb1
vdda_usb3
vdda_video
vdds18v
DDR PLL and DDR HSDIVIDER analog power supply
Debug PLL inside IOSC PLL supply
GPU (SGX) PLL analog power supply
HDMI PLL and HDMI analog power supply
HFOSC - 1.8v vdds supply
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
R20
N10
N9
W15, Y15
W13, Y13
W11, Y11
W8
PCIe PLL analog power supply
USB2 PLL analog power supply
USB3 PLL analog power supply
Y9
VIDEO1 and VIDEO2 PLL analog power supply
1.8V bump added for atestv esd supply
K14, L14
G11, H20, W7, Y18
86
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-26. Power Supply Signal Descriptions (continued)
SIGNAL NAME
DESCRIPTION
TYPE
PWR
PWR
BALL
AA19, P20, Y19
G10, G9
vdds18v_ddr1
vddshv1
DDR2 - 1.8v bias supply
VIN2 domain - 1.8/3.3 mode voltage Power cell - secondary power
supply
vddshv3
vddshv4
vddshv7
vddshv8
GENERAL Domain - 1.8/3.3 mode voltage Power cell - secondary
power supply
PWR
PWR
PWR
PWR
G15, G17, H15, H17,
J19, K19
MMC4 Domain (UART4) - 1.8/3.3 mode voltage Power cell - secondary
power supply
M19, N19
WIFI Power Group (MMC3/McASP5) - 1.8/3.3 mode voltage Power cell
- secondary power supply
U7, U8
Dual Voltage (1.8V or 3.3V) power supply for the MMC1 Power Group
pins
N8, P8
vddshv9
vddshv10
vddshv11
vdds_ddr1
RGMII - 1.8/3.3 mode voltage Power cell - secondary power supply
GPMC - 1.8/3.3 mode voltage Power cell - secondary power supply
MMC2 - 1.8/3.3 mode voltage Power cell - secondary power supply
DDR2 - vdds2 can be 1.8 (ddr2)/1.5(ddr3) - secondary power supply
PWR
PWR
PWR
PWR
M7, N7
J7, J8, K8
F7, G7, H7
T19, T20, V20, W17,
W18, W20
vssa_osc0
vssa_osc1
OSC0 Analog ground
OSC1 Analog ground
GND
GND
AA12
AB11
(1) This pin must always be connected via a 1-µF capacitor to vss.
(2) This signal is valid only for High-Security devices. For more details, see 节 5.8 VPP Specification for One-Time Programmable (OTP)
eFUSEs. For General Purpose devices do not connect any signal, test point, or board trace to this signal.
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4.4 Pin Multiplexing
表 4-27 describes the device pin multiplexing (no characteristics are provided in this table).
注
表 4-27, Pin Multiplexing doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in 节
4.3, Signal Descriptions.
注
For more information, see the Control Module / Control Module Functional Description / PAD Functional Multiplexing and Configuration
section of the Device TRM.
注
Configuring two pins to the same input signal is not supported as it can yield unexpected results. This can be easily prevented with the
proper software configuration (Hi-Z mode is not an input signal).
注
When a pad is set into a pin multiplexing mode which is not defined, that pad’s behavior is undefined. This should be avoided.
注
In some cases 表 4-27 may present more than one signal per muxmode for the same ball. First signal in the list is the dominant function
as selected via CTRL_CORE_PAD_* register.
All other signals are virtual functions that present alternate multiplexing options. This virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use this options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
注
Dual rank support is not available on this device, but signal names are retained for consistency with the TDA2xx family of devices.
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表 4-27. Pin Multiplexing
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
6*
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
7
8
9
10
14*
15
P25
ddr1_dqm3
ddr1_d10
ddr1_d27
ddr1_d17
ddr1_a7
Y23
P21
U25
AA20
V25
ddr1_dqsn2
ddr1_ba2
ddr1_d25
ddr1_d28
ddr1_d13
hdmi1_clockx
ddr1_d16
ddr1_d1
AB16
T25
N21
AB25
AE9
W23
AC24
AD16
AA23
AD18
AE19
AC20
U21
ddr1_casn
ddr1_d0
ddr1_odt0
ddr1_a1
ddr1_a9
ddr1_dqm2
ddr1_d8
AA24
AC11
AD1
xi_osc1
csi2_0_dx1
usb_txn0
usb1_dp
AE3
pcie_txn1
pcie_rxp1
AC6
AD6
usb_rxp0
ddr1_ba1
xi_osc0
AA16
Y12
AB15
AC18
AE11
R25
ddr1_a14
ddr1_a0
hdmi1_data0x
ddr1_dqsn3
ddr1_dqs1
ddr1_a8
Y24
Y21
W21
AD20
AA25
AD13
AB9
ddr1_d19
ddr1_a4
ddr1_d14
hdmi1_data1y
ljcb_clkn
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表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
AC25
ddr1_d12
ddr1_d21
ddr1_d4
U22
AB23
AB24
AE16
T22
ddr1_d2
ddr1_ba0
ddr1_d20
ddr1_d23
ddr1_a3
T21
AB19
AE24
AC15
AC21
AD17
AB12
AD23
AD9
ddr1_d7
ddr1_a13
ddr1_a11
ddr1_rasn
xo_osc0
ddr1_d6
pcie_txp0
ddr1_dqs2
ddr1_d22
ddr1_a12
ddr1_d3
V24
U23
AC22
AD24
AC8
ljcb_clkp
AE21
Y20
ddr1_nck
ddr1_vref0
pcie_rxp0
ddr1_dqm0
ddr1_ck
AD7
AE23
AD21
Y25
ddr1_dqsn1
xo_osc1
AA11
AE17
W22
AE12
AE14
AB2
ddr1_rst
ddr1_dqm1
hdmi1_data1x
hdmi1_data2x
csi2_0_dy0
ddr1_cke
usb2_dp
AB18
AB6
AC1
csi2_0_dx0
pcie_txn0
ddr1_csn0
ddr1_a10
pcie_rxn0
AE8
AC19
AA21
AE6
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
AB7
usb1_dm
porz
F19
W25
P24
ddr1_d9
ddr1_d31
ddr1_dqs0
ddr1_d29
ddr1_d18
csi2_0_dy2
ddr1_wen
ddr1_a5
AD22
P22
U24
AD2
AE18
AE20
W24
T24
ddr1_d15
ddr1_d26
ddr1_dqs3
hdmi1_data2y
ddr1_dqsn0
ddr1_a6
R24
AD15
AE22
AA18
AC2
AD12
T23
csi2_0_dy1
hdmi1_data0y
ddr1_d24
hdmi1_clocky
usb_rxn0
csi2_0_dx2
ddr1_d30
usb2_dm
ddr1_d5
AD10
AE5
pcie_rxn1
AE2
P23
AC5
AC23
AD19
AC16
AD25
AD4
ddr1_a2
ddr1_a15
ddr1_d11
usb_txp0
gpmc_ad0
pcie_txp1
0x1400
0x1404
0x1408
0x140C
0x1410
0x1414
CTRL_CORE_PAD_ F1
vin1a_d0
vin1a_d1
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vout3_d0
vout3_d1
vout3_d2
vout3_d3
vout3_d4
vout3_d5
gpio1_6
sysboot0
sysboot1
sysboot2
sysboot3
sysboot4
sysboot5
GPMC_AD0
CTRL_CORE_PAD_ E2
GPMC_AD1
gpmc_ad1
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpio1_7
gpio1_8
gpio1_9
gpio1_10
gpio1_11
CTRL_CORE_PAD_ E1
GPMC_AD2
CTRL_CORE_PAD_ C1
GPMC_AD3
CTRL_CORE_PAD_ D1
GPMC_AD4
CTRL_CORE_PAD_ D2
GPMC_AD5
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表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x1418
CTRL_CORE_PAD_ B1
GPMC_AD6
gpmc_ad6
vin1a_d6
vout3_d6
gpio1_12
sysboot6
0x141C
0x1420
0x1424
0x1428
0x142C
0x1430
0x1434
0x1438
0x143C
0x1440
CTRL_CORE_PAD_ B2
GPMC_AD7
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_a0
vin1a_d7
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vout3_d7
vout3_d8
vout3_d9
vout3_d10
vout3_d11
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d16
gpio1_13
gpio7_18
gpio7_19
gpio7_28
gpio7_29
gpio1_18
gpio1_19
gpio1_20
gpio1_21
sysboot7
sysboot8
sysboot9
sysboot10
sysboot11
sysboot12
sysboot13
sysboot14
sysboot15
Driver off
CTRL_CORE_PAD_ C2
GPMC_AD8
CTRL_CORE_PAD_ D3
GPMC_AD9
CTRL_CORE_PAD_ A2
GPMC_AD10
CTRL_CORE_PAD_ B3
GPMC_AD11
CTRL_CORE_PAD_ C3
GPMC_AD12
CTRL_CORE_PAD_ C4
GPMC_AD13
CTRL_CORE_PAD_ A3
GPMC_AD14
CTRL_CORE_PAD_ B4
GPMC_AD15
CTRL_CORE_PAD_ M1
GPMC_A0
vin1b_d0
i2c4_scl
uart5_rxd
gpio7_3
gpmc_a26
gpmc_a16
0x1444
0x1448
0x144C
0x1450
0x1454
0x1458
0x145C
0x1460
0x1464
0x1468
0x146C
0x1470
CTRL_CORE_PAD_ M2
GPMC_A1
gpmc_a1
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
gpmc_a6
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_a10
gpmc_a11
gpmc_a12
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vout3_d17
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
i2c4_sda
uart7_rxd
uart7_txd
i2c5_scl
uart5_txd
uart5_ctsn
uart5_rtsn
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
spi4_sclk
spi4_d1
gpio7_4
gpio7_5
gpio7_6
gpio1_26
gpio1_27
gpio1_28
gpio1_29
gpio1_30
gpio1_31
gpio2_0
gpio2_1
gpio2_2
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ L2
GPMC_A2
CTRL_CORE_PAD_ L1
GPMC_A3
qspi1_cs2
qspi1_cs3
CTRL_CORE_PAD_ K3
GPMC_A4
CTRL_CORE_PAD_ K2
GPMC_A5
i2c5_sda
uart8_rxd
uart8_txd
CTRL_CORE_PAD_ J1
GPMC_A6
CTRL_CORE_PAD_ K1
GPMC_A7
CTRL_CORE_PAD_ K4
GPMC_A8
vin1a_hsync0 vout3_hsync
vin1a_vsync0 vout3_vsync
vin1b_hsync1 timer12
vin1b_vsync1 timer11
CTRL_CORE_PAD_ H1
GPMC_A9
CTRL_CORE_PAD_ J2
GPMC_A10
vin1a_de0
vin1a_fld0
vout3_de
vout3_fld
vin1b_clk1
vin1b_de1
vin1b_fld1
timer10
timer9
timer8
spi4_d0
CTRL_CORE_PAD_ L3
GPMC_A11
spi4_cs0
spi4_cs1
CTRL_CORE_PAD_ G1
GPMC_A12
gpmc_a0
dma_evt1
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
gpio2_3
15
0x1474
CTRL_CORE_PAD_ H3
GPMC_A13
gpmc_a13
qspi1_rtclk
timer7
timer6
timer5
spi4_cs2
dma_evt2
Driver off
0x1478
0x147C
0x1480
0x1484
0x1488
0x148C
0x1490
0x1494
0x1498
0x149C
0x14A0
0x14A4
0x14A8
0x14AC
0x14B0
0x14B4
0x14B8
CTRL_CORE_PAD_ H4
GPMC_A14
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
gpmc_cs0
gpmc_cs2
qspi1_d3
spi4_cs3
gpio2_4
gpio2_5
gpio2_6
gpio2_7
gpio2_8
gpio2_9
gpio2_10
gpio2_11
gpio2_12
gpio2_13
gpio2_14
gpio2_15
gpio2_16
gpio2_17
gpio2_18
gpio2_19
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ K6
GPMC_A15
qspi1_d2
CTRL_CORE_PAD_ K5
GPMC_A16
qspi1_d0
CTRL_CORE_PAD_ G2
GPMC_A17
qspi1_d1
CTRL_CORE_PAD_ F2
GPMC_A18
qspi1_sclk
mmc2_dat4
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_clk
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
mmc2_cmd
CTRL_CORE_PAD_ A4
GPMC_A19
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
vin2b_d7
vin2b_hsync1
vin2b_vsync1
CTRL_CORE_PAD_ E7
GPMC_A20
CTRL_CORE_PAD_ D6
GPMC_A21
CTRL_CORE_PAD_ C5
GPMC_A22
CTRL_CORE_PAD_ B5
GPMC_A23
CTRL_CORE_PAD_ D7
GPMC_A24
CTRL_CORE_PAD_ C6
GPMC_A25
CTRL_CORE_PAD_ A5
GPMC_A26
CTRL_CORE_PAD_ B6
GPMC_A27
CTRL_CORE_PAD_ A6
GPMC_CS1
CTRL_CORE_PAD_ F3
GPMC_CS0
CTRL_CORE_PAD_ G4
GPMC_CS2
qspi1_cs0
qspi1_cs1
gpmc_cs7
gpio2_20
gpmc_a23
gpmc_a13
0x14BC
CTRL_CORE_PAD_ G3
GPMC_CS3
gpmc_cs3
gpmc_clk
vin1a_clk0
vout3_clk
gpmc_a1
gpmc_a2
gpio2_21
gpmc_a24
gpmc_a14
Driver off
0x14C0
0x14C4
0x14C8
0x14CC
CTRL_CORE_PAD_ L4
GPMC_CLK
clkout1
clkout2
gpmc_wait1
gpmc_wait1
vin2b_clk1
gpmc_a23
timer4
timer3
i2c3_scl
dma_evt1
dma_evt2
gpio2_22
gpmc_a20
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ H5
GPMC_ADVN_ALE
gpmc_advn_al gpmc_cs6
e
i2c3_sda
gpio2_23
gpmc_a19
CTRL_CORE_PAD_ G5
GPMC_OEN_REN
gpmc_oen_re
n
gpio2_24
gpio2_25
CTRL_CORE_PAD_ G6
GPMC_WEN
gpmc_wen
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Terminal Configuration and Functions
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表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x14D0
CTRL_CORE_PAD_ H2
GPMC_BEN0
gpmc_ben0
gpmc_cs4
vin2b_de1
timer2
timer1
dma_evt3
gpio2_26
gpmc_a21
Driver off
0x14D4
0x14D8
CTRL_CORE_PAD_ H6
GPMC_BEN1
gpmc_ben1
gpmc_wait0
gpmc_cs5
vin2b_clk1
gpmc_a3
vin2b_fld1
dma_evt4
gpio2_27
gpmc_a22
Driver off
Driver off
CTRL_CORE_PAD_ F6
GPMC_WAIT0
gpio2_28
gpmc_a25
gpmc_a15
0x1554
CTRL_CORE_PAD_V D8
IN2A_CLK0
vin2a_clk0
vout2_fld
emu5
eQEP1A_in
eQEP1B_in
gpio3_28
gpmc_a27
gpmc_a17
Driver off
0x1558
0x155C
CTRL_CORE_PAD_V B7
IN2A_DE0
vin2a_de0
vin2a_fld0
vin2a_fld0
vin2b_fld1
vin2b_clk1
vin2b_de1
vout2_de
vout2_clk
emu6
emu7
gpio3_29
Driver off
Driver off
CTRL_CORE_PAD_V C7
IN2A_FLD0
eQEP1_index gpio3_30
gpmc_a27
gpmc_a18
0x1560
0x1564
0x1568
0x156C
0x1570
0x1574
0x1578
0x157C
0x1580
0x1584
0x1588
0x158C
0x1590
0x1594
0x1598
0x159C
CTRL_CORE_PAD_V E8
IN2A_HSYNC0
vin2a_hsync0
vin2a_vsync0
vin2a_d0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2b_hsync1 vout2_hsync emu8
vin2b_vsync1 vout2_vsync emu9
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
spi4_sclk
spi4_d1
eQEP1_strob gpio3_31
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
e
gpmc_a27
CTRL_CORE_PAD_V B8
IN2A_VSYNC0
ehrpwm1A
gpio4_0
CTRL_CORE_PAD_V C8
IN2A_D0
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
emu10
emu11
emu12
emu13
emu14
emu15
emu16
emu17
emu18
emu19
spi4_d0
ehrpwm1B
gpio4_1
CTRL_CORE_PAD_V B9
IN2A_D1
spi4_cs0
ehrpwm1_trip gpio4_2
zone_input
CTRL_CORE_PAD_V A7
IN2A_D2
uart10_rxd
uart10_txd
uart10_ctsn
uart10_rtsn
mii1_rxd1
mii1_rxd2
mii1_rxd3
mii1_rxd0
eCAP1_in_P gpio4_3
WM1_out
CTRL_CORE_PAD_V A9
IN2A_D3
ehrpwm1_syn gpio4_4
ci
CTRL_CORE_PAD_V A8
IN2A_D4
ehrpwm1_syn gpio4_5
co
CTRL_CORE_PAD_V A11
IN2A_D5
eQEP2A_in
gpio4_6
CTRL_CORE_PAD_V F10
IN2A_D6
eQEP2B_in
gpio4_7
CTRL_CORE_PAD_V A10
IN2A_D7
eQEP2_index gpio4_8
eQEP2_strob gpio4_9
CTRL_CORE_PAD_V B10
IN2A_D8
e
gpmc_a26
CTRL_CORE_PAD_V E10
IN2A_D9
ehrpwm2A
gpio4_10
gpmc_a25
CTRL_CORE_PAD_V D10
IN2A_D10
mdio_mclk
mdio_d
ehrpwm2B
gpio4_11
gpmc_a24
CTRL_CORE_PAD_V C10
IN2A_D11
ehrpwm2_trip gpio4_12
zone_input gpmc_a23
CTRL_CORE_PAD_V B11
IN2A_D12
rgmii1_txc
rgmii1_txctl
mii1_rxclk
mii1_rxdv
eCAP2_in_P gpio4_13
WM2_out
CTRL_CORE_PAD_V D11
IN2A_D13
eQEP3A_in
gpio4_14
94
Terminal Configuration and Functions
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TDA2E-17
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x15A0
CTRL_CORE_PAD_V C11
vin2a_d14
rgmii1_txd3
vout2_d9
mii1_txclk
eQEP3B_in
gpio4_15
Driver off
IN2A_D14
0x15A4
0x15A8
0x15AC
0x15B0
0x15B4
0x15B8
0x15BC
0x15C0
0x15C4
0x15E4
0x1604
0x1624
0x163C
0x1640
0x1644
0x1648
0x164C
0x1650
0x1654
0x1658
0x165C
0x1660
0x1664
CTRL_CORE_PAD_V B12
IN2A_D15
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxc
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d3
vout2_d2
vout2_d1
vout2_d0
mii1_txd0
mii1_txd1
mii1_txd2
mii1_txd3
mii1_txer
mii1_rxer
mii1_col
eQEP3_index gpio4_16
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_V A12
IN2A_D16
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
emu2
eQEP3_strob gpio4_24
e
CTRL_CORE_PAD_V A13
IN2A_D17
ehrpwm3A
gpio4_25
CTRL_CORE_PAD_V E11
IN2A_D18
ehrpwm3B
gpio4_26
CTRL_CORE_PAD_V F11
IN2A_D19
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
ehrpwm3_trip gpio4_27
zone_input
CTRL_CORE_PAD_V B13
IN2A_D20
eCAP3_in_P gpio4_28
WM3_out
CTRL_CORE_PAD_V E13
IN2A_D21
gpio4_29
gpio4_30
gpio4_31
CTRL_CORE_PAD_V C13
IN2A_D22
mii1_crs
CTRL_CORE_PAD_V D13
IN2A_D23
mii1_txen
CTRL_CORE_PAD_V E14
OUT1_D2
CTRL_CORE_PAD_V F14
OUT1_D10
emu3
CTRL_CORE_PAD_V F13
OUT1_D18
emu4
CTRL_CORE_PAD_ L5
MDIO_MCLK
mdio_mclk
mdio_d
uart3_rtsn
uart3_ctsn
mii0_col
vin2a_clk0
vin2a_d0
vin2a_d11
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
vin2a_de0
vin1b_clk1
vin1b_d0
gpio5_15
gpio5_16
gpio5_17
gpio5_18
gpio5_19
gpio5_20
gpio5_21
gpio5_22
gpio5_23
gpio5_24
gpio5_25
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ L6
MDIO_D
mii0_txer
CTRL_CORE_PAD_R P5
MII_MHZ_50_CLK
RMII_MHZ_50
_CLK
CTRL_CORE_PAD_U N5
ART3_RXD
uart3_rxd
rmii1_crs
rmii1_rxer
rmii1_rxd1
rmii1_rxd0
mii0_rxdv
mii0_rxclk
mii0_rxd3
mii0_rxd2
mii0_crs
vin1b_d1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_de1
spi3_sclk
spi3_d1
CTRL_CORE_PAD_U N6
ART3_TXD
uart3_txd
spi4_cs1
spi4_cs2
spi4_cs3
uart4_rxd
uart4_txd
uart4_ctsn
uart4_rtsn
CTRL_CORE_PAD_R T4
GMII0_TXC
rgmii0_txc
rgmii0_txctl
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
uart3_ctsn
uart3_rtsn
rmii0_crs
usb3_ulpi_clk spi3_d0
usb3_ulpi_stp spi3_cs0
usb3_ulpi_dir spi4_sclk
CTRL_CORE_PAD_R T5
GMII0_TXCTL
CTRL_CORE_PAD_R P4
GMII0_TXD3
CTRL_CORE_PAD_R P3
GMII0_TXD2
rmii0_rxer
rmii0_rxd1
rmii0_rxd0
mii0_rxer
mii0_rxd1
mii0_rxd0
vin2a_hsync0 vin1b_hsync1 usb3_ulpi_nxt spi4_d1
vin2a_vsync0 vin1b_vsync1 usb3_ulpi_d0 spi4_d0
CTRL_CORE_PAD_R R2
GMII0_TXD1
CTRL_CORE_PAD_R R1
GMII0_TXD0
vin2a_d10
usb3_ulpi_d1 spi4_cs0
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
95
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x1668
CTRL_CORE_PAD_R N2
GMII0_RXC
rgmii0_rxc
rmii1_txen
mii0_txclk
vin2a_d5
vin1b_d5
usb3_ulpi_d2
gpio5_26
Driver off
0x166C
0x1670
0x1674
0x1678
0x167C
0x1680
0x1684
0x1688
0x168C
0x1690
0x1694
0x1698
0x169C
0x16A0
0x16A4
0x16A8
0x16AC
0x16B0
0x16B4
0x16B8
0x16BC
0x16C0
0x16C4
CTRL_CORE_PAD_R P2
GMII0_RXCTL
rgmii0_rxctl
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
usb1_drvvbus
usb2_drvvbus
gpio6_14
rmii1_txd1
rmii1_txd0
mii0_txd3
mii0_txd2
mii0_txen
mii0_txd1
mii0_txd0
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_fld0
vin1b_d6
vin1b_d7
usb3_ulpi_d3
usb3_ulpi_d4
usb3_ulpi_d5
usb3_ulpi_d6
usb3_ulpi_d7
gpio5_27
gpio5_28
gpio5_29
gpio5_30
gpio5_31
gpio6_12
gpio6_13
gpio6_14
gpio6_15
gpio6_16
gpio6_17
gpio6_18
gpio6_19
gpio6_20
gpio7_31
gpio7_30
gpio5_0
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_R N1
GMII0_RXD3
CTRL_CORE_PAD_R P1
GMII0_RXD2
rmii0_txen
rmii0_txd1
rmii0_txd0
CTRL_CORE_PAD_R N3
GMII0_RXD1
CTRL_CORE_PAD_R N4
GMII0_RXD0
vin1b_fld1
CTRL_CORE_PAD_U AD3
SB1_DRVVBUS
timer16
CTRL_CORE_PAD_U AA6
SB2_DRVVBUS
timer15
CTRL_CORE_PAD_ H21
GPIO6_14
mcasp1_axr8 dcan2_tx
mcasp1_axr9 dcan2_rx
uart10_rxd
uart10_txd
i2c3_sda
i2c3_scl
clkout1
timer1
CTRL_CORE_PAD_ K22
GPIO6_15
gpio6_15
timer2
CTRL_CORE_PAD_ K23
GPIO6_16
gpio6_16
mcasp1_axr1
0
timer3
CTRL_CORE_PAD_X J25
REF_CLK0
xref_clk0
mcasp2_axr8 mcasp1_axr4 mcasp1_ahclk mcasp5_ahclk
vin1a_d0
clkout2
timer13
timer14
timer15
timer16
i2c3_sda
i2c3_scl
i2c4_sda
i2c4_scl
i2c5_sda
i2c5_scl
x
x
CTRL_CORE_PAD_X J24
REF_CLK1
xref_clk1
mcasp2_axr9 mcasp1_axr5 mcasp2_ahclk mcasp6_ahclk
vin1a_clk0
x
x
CTRL_CORE_PAD_X H24
REF_CLK2
xref_clk2
mcasp2_axr1 mcasp1_axr6 mcasp3_ahclk mcasp7_ahclk
0
x
x
CTRL_CORE_PAD_X H25
REF_CLK3
xref_clk3
mcasp2_axr1 mcasp1_axr7 mcasp4_ahclk mcasp8_ahclk
clkout3
1
x
x
CTRL_CORE_PAD_ C16
MCASP1_ACLKX
mcasp1_aclkx
mcasp1_fsx
vin1a_fld0
vin1a_de0
CTRL_CORE_PAD_ C17
MCASP1_FSX
CTRL_CORE_PAD_ D16
MCASP1_ACLKR
mcasp1_aclkr mcasp7_axr2
CTRL_CORE_PAD_ D17
MCASP1_FSR
mcasp1_fsr
mcasp7_axr3
gpio5_1
CTRL_CORE_PAD_ D14
MCASP1_AXR0
mcasp1_axr0
mcasp1_axr1
uart6_rxd
uart6_txd
uart6_ctsn
uart6_rtsn
vin1a_vsync0
vin1a_hsync0
gpio5_2
CTRL_CORE_PAD_ B14
MCASP1_AXR1
gpio5_3
CTRL_CORE_PAD_ C14
MCASP1_AXR2
mcasp1_axr2 mcasp6_axr2
mcasp1_axr3 mcasp6_axr3
mcasp1_axr4 mcasp4_axr2
gpio5_4
CTRL_CORE_PAD_ B15
MCASP1_AXR3
gpio5_5
CTRL_CORE_PAD_ A15
MCASP1_AXR4
gpio5_6
96
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
gpio5_7
15
0x16C8
CTRL_CORE_PAD_ A14
MCASP1_AXR5
mcasp1_axr5 mcasp4_axr3
mcasp1_axr6 mcasp5_axr2
mcasp1_axr7 mcasp5_axr3
mcasp1_axr8 mcasp6_axr0
mcasp1_axr9 mcasp6_axr1
Driver off
0x16CC
0x16D0
0x16D4
0x16D8
0x16DC
0x16E0
0x16E4
0x16E8
0x16EC
0x16F0
0x16F4
0x16F8
0x1704
0x1708
0x170C
0x1710
0x1714
0x1718
0x171C
0x1720
0x1724
0x1728
0x172C
CTRL_CORE_PAD_ A17
MCASP1_AXR6
gpio5_8
gpio5_9
gpio5_10
gpio5_11
gpio5_12
gpio4_17
gpio4_18
gpio6_4
gpio6_5
gpio6_6
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ A16
MCASP1_AXR7
timer4
CTRL_CORE_PAD_ A18
MCASP1_AXR8
spi3_sclk
spi3_d1
vin1a_d15
vin1a_d14
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d7
vin1a_d6
timer5
timer6
timer7
timer8
timer9
timer10
timer11
timer12
CTRL_CORE_PAD_ B17
MCASP1_AXR9
CTRL_CORE_PAD_ B16
MCASP1_AXR10
mcasp1_axr1 mcasp6_aclkx mcasp6_aclkr spi3_d0
0
CTRL_CORE_PAD_ B18
MCASP1_AXR11
mcasp1_axr1 mcasp6_fsx
1
mcasp6_fsr
spi3_cs0
CTRL_CORE_PAD_ A19
MCASP1_AXR12
mcasp1_axr1 mcasp7_axr0
2
spi3_cs1
CTRL_CORE_PAD_ E17
MCASP1_AXR13
mcasp1_axr1 mcasp7_axr1
3
CTRL_CORE_PAD_ E16
MCASP1_AXR14
mcasp1_axr1 mcasp7_aclkx mcasp7_aclkr
4
CTRL_CORE_PAD_ F16
MCASP1_AXR15
mcasp1_axr1 mcasp7_fsx
5
mcasp7_fsr
CTRL_CORE_PAD_ E19
MCASP2_ACLKX
mcasp2_aclkx
CTRL_CORE_PAD_ D19
MCASP2_FSX
mcasp2_fsx
CTRL_CORE_PAD_ A20
MCASP2_AXR0
mcasp2_axr0
CTRL_CORE_PAD_ B19
MCASP2_AXR1
mcasp2_axr1
CTRL_CORE_PAD_ A21
MCASP2_AXR2
mcasp2_axr2 mcasp3_axr2
mcasp2_axr3 mcasp3_axr3
mcasp2_axr4 mcasp8_axr0
mcasp2_axr5 mcasp8_axr1
vin1a_d5
vin1a_d4
gpio6_8
gpio6_9
gpio1_4
gpio6_7
gpio2_29
gpio1_5
gpio5_13
gpio5_14
CTRL_CORE_PAD_ B21
MCASP2_AXR3
CTRL_CORE_PAD_ B20
MCASP2_AXR4
CTRL_CORE_PAD_ C19
MCASP2_AXR5
CTRL_CORE_PAD_ D20
MCASP2_AXR6
mcasp2_axr6 mcasp8_aclkx mcasp8_aclkr
mcasp2_axr7 mcasp8_fsx mcasp8_fsr
CTRL_CORE_PAD_ C20
MCASP2_AXR7
CTRL_CORE_PAD_ A22
MCASP3_ACLKX
mcasp3_aclkx mcasp3_aclkr mcasp2_axr1 uart7_rxd
2
vin1a_d3
vin1a_d2
vin1a_d1
CTRL_CORE_PAD_ A23
MCASP3_FSX
mcasp3_fsx
mcasp3_fsr
mcasp2_axr1 uart7_txd
3
CTRL_CORE_PAD_ B22
MCASP3_AXR0
mcasp3_axr0
mcasp2_axr1 uart7_ctsn
4
uart5_rxd
版权 © 2016–2018, Texas Instruments Incorporated
Terminal Configuration and Functions
97
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x1730
CTRL_CORE_PAD_ B23
MCASP3_AXR1
mcasp3_axr1
mcasp2_axr1 uart7_rtsn
5
uart5_txd
vin1a_d0
Driver off
0x1734
0x1738
0x173C
0x1740
0x1744
0x1748
0x174C
0x1750
0x1754
0x1758
0x175C
0x1760
0x1764
0x1768
0x176C
0x1770
0x1774
0x1778
0x177C
0x1780
0x1784
0x1788
0x178C
CTRL_CORE_PAD_ C23
MCASP4_ACLKX
mcasp4_aclkx mcasp4_aclkr spi3_sclk
uart8_rxd
uart8_txd
uart8_ctsn
uart8_rtsn
uart9_rxd
uart9_txd
uart9_ctsn
uart9_rtsn
i2c4_sda
i2c4_scl
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ B25
MCASP4_FSX
mcasp4_fsx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsr
spi3_d1
spi3_d0
spi3_cs0
CTRL_CORE_PAD_ A24
MCASP4_AXR0
uart4_rxd
uart4_txd
i2c5_sda
i2c5_scl
i2c6_scl
CTRL_CORE_PAD_ D23
MCASP4_AXR1
i2c6_sda
CTRL_CORE_PAD_ AC3
MCASP5_ACLKX
mcasp5_aclkx mcasp5_aclkr spi4_sclk
CTRL_CORE_PAD_ U6
MCASP5_FSX
mcasp5_fsx
mcasp5_axr0
mcasp5_axr1
mmc1_clk
mcasp5_fsr
spi4_d1
spi4_d0
spi4_cs0
CTRL_CORE_PAD_ AA5
MCASP5_AXR0
uart3_rxd
uart3_txd
CTRL_CORE_PAD_ AC4
MCASP5_AXR1
CTRL_CORE_PAD_ U3
MMC1_CLK
gpio6_21
gpio6_22
gpio6_23
gpio6_24
gpio6_25
gpio6_26
gpio6_27
gpio6_28
gpio6_10
gpio6_11
CTRL_CORE_PAD_ V4
MMC1_CMD
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
mmc1_sdcd
mmc1_sdwp
gpio6_10
CTRL_CORE_PAD_ V3
MMC1_DAT0
CTRL_CORE_PAD_ V2
MMC1_DAT1
CTRL_CORE_PAD_ W1
MMC1_DAT2
CTRL_CORE_PAD_ V1
MMC1_DAT3
CTRL_CORE_PAD_ U5
MMC1_SDCD
uart6_rxd
uart6_txd
i2c4_sda
i2c4_scl
CTRL_CORE_PAD_ V5
MMC1_SDWP
CTRL_CORE_PAD_ Y5
GPIO6_10
mdio_mclk
mdio_d
i2c3_sda
i2c3_scl
usb3_ulpi_d7 vin2b_hsync1
usb3_ulpi_d6 vin2b_vsync1
usb3_ulpi_d5 vin2b_d7
usb3_ulpi_d4 vin2b_d6
usb3_ulpi_d3 vin2b_d5
usb3_ulpi_d2 vin2b_d4
usb3_ulpi_d1 vin2b_d3
vin1a_clk0
vin1a_de0
vin1a_d7
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
ehrpwm2A
ehrpwm2B
CTRL_CORE_PAD_ Y6
GPIO6_11
gpio6_11
CTRL_CORE_PAD_ Y2
MMC3_CLK
mmc3_clk
ehrpwm2_trip gpio6_29
zone_input
CTRL_CORE_PAD_ Y1
MMC3_CMD
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
spi3_sclk
spi3_d1
spi3_d0
spi3_cs0
eCAP2_in_P gpio6_30
WM2_out
CTRL_CORE_PAD_ Y4
MMC3_DAT0
uart5_rxd
uart5_txd
uart5_ctsn
eQEP3A_in
gpio6_31
CTRL_CORE_PAD_ AA2
MMC3_DAT1
eQEP3B_in
gpio7_0
CTRL_CORE_PAD_ AA3
MMC3_DAT2
eQEP3_index gpio7_1
98
Terminal Configuration and Functions
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x1790
CTRL_CORE_PAD_ W2
MMC3_DAT3
mmc3_dat3
spi3_cs1
uart5_rtsn
usb3_ulpi_d0 vin2b_d2
usb3_ulpi_nxt vin2b_d1
usb3_ulpi_dir vin2b_d0
usb3_ulpi_stp vin2b_de1
usb3_ulpi_clk vin2b_clk1
vin1a_d2
eQEP3_strob gpio7_2
e
Driver off
0x1794
0x1798
0x179C
0x17A0
0x17A4
0x17A8
0x17AC
0x17B0
0x17B4
0x17B8
0x17BC
0x17C0
0x17C4
0x17C8
0x17CC
0x17D0
0x17D4
0x17E0
0x17E4
0x17E8
0x17EC
0x17F0
0x17F4
CTRL_CORE_PAD_ Y3
MMC3_DAT4
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
spi1_sclk
spi1_d1
spi4_sclk
spi4_d1
spi4_d0
spi4_cs0
uart10_rxd
uart10_txd
uart10_ctsn
uart10_rtsn
vin1a_d1
vin1a_d0
ehrpwm3A
gpio1_22
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_ AA1
MMC3_DAT5
ehrpwm3B
gpio1_23
CTRL_CORE_PAD_ AA4
MMC3_DAT6
vin1a_hsync0 ehrpwm3_trip gpio1_24
zone_input
CTRL_CORE_PAD_ AB1
MMC3_DAT7
vin1a_vsync0 eCAP3_in_P gpio1_25
WM3_out
CTRL_CORE_PAD_S C24
PI1_SCLK
gpio7_7
CTRL_CORE_PAD_S D24
PI1_D1
gpio7_8
CTRL_CORE_PAD_S D25
PI1_D0
spi1_d0
gpio7_9
CTRL_CORE_PAD_S B24
PI1_CS0
spi1_cs0
spi1_cs1
spi1_cs2
spi1_cs3
spi2_sclk
spi2_d1
gpio7_10
gpio7_11
gpio7_12
gpio7_13
gpio7_14
gpio7_15
gpio7_16
gpio7_17
gpio1_14
gpio1_15
gpio7_22
gpio7_23
gpio7_24
gpio7_25
gpio7_26
gpio7_27
CTRL_CORE_PAD_S C25
PI1_CS1
spi2_cs1
CTRL_CORE_PAD_S E24
PI1_CS2
uart4_rxd
uart4_txd
uart3_rxd
uart3_txd
uart3_ctsn
uart3_rtsn
mmc3_sdcd
spi2_cs2
dcan2_tx
dcan2_rx
mdio_mclk
mdio_d
hdmi1_hpd
hdmi1_cec
CTRL_CORE_PAD_S E25
PI1_CS3
mmc3_sdwp spi2_cs3
CTRL_CORE_PAD_S G25
PI2_SCLK
CTRL_CORE_PAD_S F25
PI2_D1
CTRL_CORE_PAD_S G24
PI2_D0
spi2_d0
uart5_rxd
uart5_txd
CTRL_CORE_PAD_S F24
PI2_CS0
spi2_cs0
dcan1_tx
dcan1_rx
uart1_rxd
uart1_txd
uart1_ctsn
uart1_rtsn
uart2_rxd
uart2_txd
CTRL_CORE_PAD_D H22
CAN1_TX
uart8_rxd
uart8_txd
mmc2_sdcd
hdmi1_hpd
hdmi1_cec
CTRL_CORE_PAD_D H23
CAN1_RX
mmc2_sdwp
mmc4_sdcd
mmc4_sdwp
mmc4_clk
CTRL_CORE_PAD_U L25
ART1_RXD
CTRL_CORE_PAD_U M25
ART1_TXD
CTRL_CORE_PAD_U L20
ART1_CTSN
uart9_rxd
uart9_txd
uart3_rctx
uart3_sd
CTRL_CORE_PAD_U M24
ART1_RTSN
mmc4_cmd
mmc4_dat0
mmc4_dat1
CTRL_CORE_PAD_U N23
ART2_RXD
uart3_ctsn
uart3_rtsn
uart2_rxd
uart2_txd
uart1_dcdn
uart1_dsrn
CTRL_CORE_PAD_U N25
ART2_TXD
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表 4-27. Pin Multiplexing (continued)
MUXMODE FIELD SETTINGS (CTRL_CORE_PAD_*[3:0])
BALL
NUMBER
ADDRESS
REGISTER NAME
0
1
2
3
4*
5
6*
7
8
9
10
14*
15
0x17F8
CTRL_CORE_PAD_U N22
ART2_CTSN
uart2_ctsn
uart3_rxd
mmc4_dat2
uart10_rxd
uart1_dtrn
gpio1_16
Driver off
0x17FC
0x1800
0x1804
0x1808
0x180C
0x1818
0x1824
0x1830
0x1834
0x1838
0x183C
0x1840
0x1844
0x1848
0x184C
0x185C
0x1860
0x1864
CTRL_CORE_PAD_U N24
ART2_RTSN
uart2_rtsn
i2c1_sda
i2c1_scl
i2c2_sda
i2c2_scl
uart3_txd
uart3_irtx
mmc4_dat3
uart10_txd
uart1_rin
gpio1_17
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
Driver off
CTRL_CORE_PAD_I G23
2C1_SDA
CTRL_CORE_PAD_I G22
2C1_SCL
CTRL_CORE_PAD_I F23
2C2_SDA
hdmi1_ddc_sc
l
CTRL_CORE_PAD_I G21
2C2_SCL
hdmi1_ddc_sd
a
CTRL_CORE_PAD_ AC10
WAKEUP0
dcan1_rx
gpio1_0
sys_nirq2
CTRL_CORE_PAD_ AB10
WAKEUP3
sys_nirq1
gpio1_3
dcan2_rx
CTRL_CORE_PAD_T L21
MS
tms
CTRL_CORE_PAD_T L23
DI
tdi
gpio8_27
gpio8_28
CTRL_CORE_PAD_T J20
DO
tdo
CTRL_CORE_PAD_T K21
CLK
tclk
CTRL_CORE_PAD_T L22
RSTN
trstn
CTRL_CORE_PAD_R K25
TCK
rtck
gpio8_29
gpio8_30
gpio8_31
CTRL_CORE_PAD_E C21
MU0
emu0
emu1
resetn
nmin_dsp
rstoutn
CTRL_CORE_PAD_E C22
MU1
CTRL_CORE_PAD_R K24
ESETN
CTRL_CORE_PAD_N L24
MIN_DSP
CTRL_CORE_PAD_R E20
STOUTN
1. NA in table stands for Not Applicable.
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4.5 Connections for Unused Pins
This section describes the connection requirements of the unused and reserved balls.
注
The following balls are reserved: K20, L19, G20, T1, T2, U4, T3, U1, U2
These balls must be left unconnected.
注
All unused power supply balls must be supplied with the voltages specified in the
Section 5.4, Recommended Operating Conditions, unless alternative tie-off options are
included in 节 4.3, Signal Descriptions.
表 4-28. Unused Balls Specific Connection Requirements
Balls
Connection Requirements
These balls must be connected to GND through an external pull
resistor if unused.
Y12 / AC11 / L22 / AC10 / AB10 / AD22 / Y24 / V24 / R24
K21 / L24 / K24 / G22 / G23 / L21 / G21 / F23 / AE22 / Y25 / V25 /
R25
These balls must be connect to the corresponding power supply
through an external pull resistor if unused.
F20 (vpp)
This ball must be left unconnected if unused
注
All other unused signal balls with a Pad Configuration register can be left unconnected with
their internal pullup or pulldown resistor enabled.
注
All other unused signal balls without a Pad Configuration register can be left unconnected.
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5 Specifications
注
For more information, see Power, Reset, and Clock Management / PRCM Subsystem
Environment / External Voltage Inputs or Initialization / Preinitialization / Power Requirements
section of the Device TRM.
注
The index number 1which is part of the EMIF1 signal prefixes (ddr1_*) listed in 表 4-6, EMIF
Signal Descriptions, column "SIGNAL NAME" not to be confused with DDR1 type of SDRAM
memories.
注
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
CAUTION
All IO Cells are NOT Fail-safe compliant and should not be externally driven in
absence of their IO supply.
102
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5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
PARAMETER(1)
MIN
-0.3
-0.3
MAX
1.5
UNIT
V
VSUPPLY (Steady-State)
Supply Voltage Ranges (Steady-
State)
Core (vdd, vdd_dsp)
Analog (vdda_usb1, vdda_usb2,
vdda_per, vdda_ddr, vdda_debug,
vdda_mpu_abe, vdda_usb3,
vdda_csi, vdda_core_gmac,
vdda_gpu, dda_hdmi, vdda_pcie,
vdda_video, vdda_osc)
2.0
V
Analog 3.3V (vdda33v_usb1,
vdda33v_usb2)
-0.3
-0.3
-0.3
-0.3
3.8
2.1
2.1
3.8
V
V
V
V
vdds18v, vdds18v_ddr1,
vdds_mlbp, vdds_ddr1
vddshv1, vddshv3, vddshv4,
vddshv7-11 (1.8V mode)
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9-11 (3.3V mode)
vddshv8 (3.3V mode)
Core I/Os
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
3.6
1.5
2.0
3.5
1.65
1.8
2.1
3.8
V
V
V
V
V
V
V
V
VIO (Steady-State)
Input and Output Voltage Ranges
(Steady-State)
Analog I/Os (except HDMI)
HDMI I/Os
I/O 1.35V
I/O 1.5V
1.8V I/Os
3.3V I/Os (except those powered by
vddshv8)
3.3V I/Os (powered by vddshv8)
-0.3
3.6
105
V
V/s
V
SR
Maximum slew rate, all supplies
VIO (Transient Overshoot /
Undershoot)
Input and Output Voltage Ranges (Transient Overshoot/Undershoot)
Note: valid for up to 20% of the signal period. See 图 5-1.
0.2 ×
VDD (4)
TJ
Operating junction temperature
range
Automotive
-40
+125
°C
TSTG
Storage temperature range after soldered onto PC Board
I-test(5), All I/Os (if different levels then one line per level)
Over-voltage Test(6), All supplies (if different levels then one line per level)
-55
-100
N/A
+150
100
°C
mA
V
Latch-up I-Test
Latch-up OV-Test
1.5 ×
Vsupply
max
(1) Stresses beyond those listed as absolute maximum ratings may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those listed under Section 5.4, Recommended Operating
Conditions, is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.
(3) See I/Os supplied by this power pin in 表 4-1 Pin Attributes
(4) VDD is the voltage on the corresponding power-supply pin(s) for the IO.
(5) Per JEDEC JESD78 at 125°C with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O
voltage and negative 0.5 times maximum recommended I/O voltage.
(6) Per JEDEC JESD78 at 125°C.
(7) The maximum valid input voltage on an IO pin cannot exceed 0.3 volts when the supply powering the IO is turned off. This requirement
applies to all the IO pins which are not fail-safe and for all values of IO supply voltage. Special attention should be applied anytime
peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached
peripheral never sources a voltage outside the valid input voltage range, including power supply ramp-up and ramp-down sequences.
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Overshoot = 20% of nominal
IO supply voltage
Tovershoot
Nominal IO
supply voltage
Tperiod
Tundershoot
VSS
Undershoot = 20% of nominal
IO supply voltage
osus_sprs851
图 5-1. Tovershoot + Tundershoot < 20% of Tperiod
5.2 ESD Ratings
VALUE
±1000
±250
UNIT
Human-Body model (HBM), per AEC Q100-002(1)
All pins
VESD Electrostatic discharge
V
Charged-device model (CDM), per AEC
Q100-011
Corner pins (A1,
A25, AE1, AE25)
±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Power on Hour (POH) Limits
IP
Duty Cycle
Voltage Domain
Voltage (V) (max)
Frequency (MHz)
(max)
Tj(°C)
POH
All
100%
All
All Supported OPPs
Automotive Profile(4)
20000
(1) The information in this section is provided solely for your convenience and does not extend or modify the warranty provided under TI’s
standard terms and conditions for TI semiconductor products.
(2) POH is a functional of voltage, temperature and time. Usage at higher voltages and temperatures will result in a reduction in POH to
achieve the same reliability performance. For assessment of alternate use cases, contact your local TI representative.
(3) Unless specified in the table above, all voltage domains and operating conditions are supported in the device at the noted temperatures.
(4) Automotive profile is defined as 20000 power on hours with junction temperature as follows: 5%@-40°C, 65%@70°C, 20%@110°C,
10%@125°C.
5.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
Input Power Supply Voltage Range
vdd
Core voltage domain supply
DSP voltage domain supply
See 节 5.5
See 节 5.5
V
V
V
vdd_dsp
vdda_usb1
DPLL_USB and HS USB1 1.8V
analog power supply
1.71
1.80
1.836
1.89
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_usb2
HS USB2 1.8V analog power supply
Maximum noise (peak-peak)
1.71
3.135
3.135
1.71
1.836
3.366
3.366
1.836
1.89
3.465
3.465
1.89
V
mVPPmax
vdda33v_usb1(5)
vdda33v_usb2(5)
vdda_per
HS USB1 3.3V analog power supply
Maximum noise (peak-peak)
3.3
50
V
mVPPmax
V
HS USB2 3.3V analog power supply
Maximum noise (peak-peak)
3.3
50
mVPPmax
V
PER PLL and PER HSDIVIDER
analog power supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
vdda_ddr
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
UNIT
DPLL_DDR and DDR HSDIVIDER
analog power supply
1.71
1.80
1.836
1.89
V
Maximum noise (peak-peak)
DPLL_DEBUG analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_debug
1.71
1.71
1.836
1.836
1.89
1.89
V
mVPPmax
V
vdda_core_gmac
DPLL_CORE and CORE HSDIVIDER
analog power supply
1.80
Maximum noise (peak-peak)
DPLL_GPU analog power supply
Maximum noise (peak-peak)
50
1.80
50
mVPPmax
vdda_gpu
1.71
1.71
1.836
1.836
1.89
1.89
V
mVPPmax
V
vdda_hdmi
PLL_HDMI and HDMI analog power
supply
1.80
Maximum noise (peak-peak)
50
mVPPmax
V
vdda_pcie
vdda_usb3
DPLL_PCIe_REF and PCIe analog
power supply
1.71
1.71
1.80
1.836
1.836
1.836
1.89
1.89
Maximum noise (peak-peak)
50
mVPPmax
V
DPLL_USB_OTG_SS and USB3.0
RX/TX analog power supply
1.80
Maximum noise (peak-peak)
DPLL_VIDEO1 analog power supply
Maximum noise (peak-peak)
MLBP IO power supply
50
1.80
50
mVPPmax
vdda_video
vdds_mlbp
vdda_mpu_abe
vdda_osc
1.71
1.71
1.71
1.71
1.71
1.71
1.71
1.89
1.89
1.89
1.89
1.89
1.89
1.89
V
mVPPmax
1.80
50
V
Maximum noise (peak-peak)
DPLL_MPU analog power supply
Maximum noise (peak-peak)
HFOSC analog power supply
Maximum noise (peak-peak)
CSI Interface 1.8v Supply
Maximum noise (peak-peak)
1.8V power supply
mVPPmax
1.80
50
1.836
V
mVPPmax
1.80
50
V
mVPPmax
vdda_csi
1.80
50
1.836
1.836
1.836
V
mVPPmax
vdds18v
1.80
50
V
mVPPmax
V
Maximum noise (peak-peak)
EMIF1 bias power supply
vdds18v_ddr1
vdds_ddr1
1.80
50
Maximum noise (peak-peak)
mVPPmax
V
EMIF1 power supply
(1.5V for DDR3 mode /
1.35V DDR3L mode)
1.35-V
Mode
1.28
1.43
1.35
1.337
1.53
1.42
1.57
1.5-V Mode
1.50
50
Maximum noise (peak-
peak)
1.35-V
Mode
mVPPmax
1.5-V Mode
1.8-V Mode
3.3-V Mode
vddshv1
Dual Voltage (1.8V or
3.3V) power supply for
the VIN2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
vddshv10
DESCRIPTION
MIN (2)
NOM MAX DC (3)
MAX (2)
1.89
UNIT
Dual Voltage (1.8V or
1.8-V Mode
3.3-V Mode
1.71
1.80
3.30
1.836
3.366
V
3.3V) power supply for
the GPMC Power Group
pins
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
vddshv11
vddshv3
vddshv4
vddshv7
vddshv8
vddshv9
Dual Voltage (1.8V or
3.3V) power supply for
the MMC2 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the GENERAL Power
Group pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC4 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the WIFI Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the MMC1 Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
1.8-V Mode
3.3-V Mode
50
mVPPmax
Dual Voltage (1.8V or
3.3V) power supply for
the RGMII Power Group
pins
1.71
1.80
3.30
1.836
3.366
1.89
V
3.135
3.465
Maximum noise (peak-
peak)
1.8-V Mode
3.3-V Mode
50
mVPPmax
vss
Ground supply
0
0
0
V
V
vssa_osc0
vssa_osc1
OSC0 analog ground
OSC1 analog ground
V
(1)
TJ
Operating junction
temperature range
Automotive
-40
+125
°C
ddr1_vref0
Reference Power Supply EMIF1
0.5 × vdds_ddr1
V
(1) Refer to Power on Hours table for limitations.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) Logic functions and parameter values are not assured out of the range specified in the recommended operating conditions.
106
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Recommended Operating Conditions (continued)
over operating free-air temperature range (unless otherwise noted)
(5) USB Analog supply also powers digital IO buffers. This supply cannot be tied to VSS if USB is unused since digital IO buffers must be
powered during device operation.
5.5 Operating Performance Points
This section describes the operating conditions of the device. This section also contains the description of
each OPP (operating performance point) for processor clocks and device core clocks.
表 5-1 describes the maximum supported frequency per speed grade for TDA2Ex devices.
表 5-1. Speed Grade Maximum Frequency
Device Speed
Maximum frequency (MHz)
MPU
800
DSP
750
500
IVA
532
430
GPU
425.6
425.6
IPU
L3
DDR3/DDR3L
667 (DDR-1333)
667 (DDR-1333)
TDA2ExxH
TDA2ExxD
212.8
212.8
266
266
500
(1) N/A in this table stands for Not Applicable.
5.5.1 AVS and ABB Requirements
Adaptive Voltage Scaling (AVS) and Adaptive Body Biasing (ABB) are required on most of the vdd_*
supplies as defined in 表 5-2.
表 5-2. AVS and ABB Requirements per vdd_* Supply
Supply
vdd
AVS Required?
Yes, for all OPPs
Yes, for all OPPs
ABB Required?
No
vdd_dsp
Yes, for all OPPs
5.5.2 Voltage And Core Clock Specifications
表 5-3 shows the recommended OPP per voltage domain.
表 5-3. Voltage Domains Operating Performance Points
DOMAIN
CONDITION
OPP_NOM
NOM (1)
OPP_HIGH
MIN (2)
MAX (2)
MIN (2)
NOM (1)
MAX DC (3)
MAX (2)
(7)
VD_CORE (V)
BOOT (Before AVS is
1.11
1.15
1.2
Not Applicable
(4)
enabled)
After AVS is enabled (4)
AVS
AVS
1.2
Not Applicable
Not Applicable
Voltage
Voltage
(5) – 3.5%
(5)
(8)
VD_DSP (V)
BOOT (Before AVS is
1.02
AVS
1.06
1.16
1.2
(4)
enabled)
After AVS is enabled (4)
AVS
AVS
AVS
AVS
AVS
Voltage(5) Voltage
Voltage(5) Voltage (5) Voltage (5) Voltage(5)
(5)
– 3.5%
– 3.5%
+2%
+ 5%
(1) In a typical implementation, the power supply should target the NOM voltage.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(5) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP Registers. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the
TRM. The power supply should be adjustable over the following ranges for each required OPP:
–
OPP_NOM for DSP: 0.85 V – 1.15 V
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–
–
OPP_NOM for CORE: 0.85 V - 1.15 V
OPP_HIGH: 1.05 V - 1.25 V
The AVS voltages will be within the above specified ranges.
(6) The power supply must be programmed with the AVS voltages for the CORE voltage domain, either just after the ROM boot or at the
earliest possible time in the secondary boot loader before there is significant activity seen on these domains.
(7) The package routes VD_CORE (vdd) to the VD_MPU, VD_SGX, VD_CORE and VD_RTC domains on the die.
(8) The package routes VD_DSP (vdd_dsp) to the VD_DSPEVE and VD_IVA domains on the die.
表 5-4 describes the standard processor clocks speed characteristics vs OPP of the device.
表 5-4. Supported OPP vs Max Frequency (2)
DESCRIPTION
OPP_NOM
OPP_HIGH
Max Freq. (MHz)
Max Freq. (MHz)
VD_CORE
MPU_CLK
GPU_CLK
800
425.6
N/A
N/A
N/A
N/A
N/A
CORE_IPUx_CLK
L3_CLK
212.8
266
DDR3 / DDR3L
667 (DDR-1333)
VD_DSP
IVA_GCLK
DSP_CLK
388.3
600
532
750
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see 表 5-1).
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. 表 5-5 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
表 5-5. Maximum Supported Frequency
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
AES1
AES2
BB2D
AES1_L3_CLK
AES2_L3_CLK
BB2D_FCLK
BB2D_ICLK
Int
Int
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
BB2D_GFCLK
CORE_X2_CLK
CORE_X2_CLK
BB2D_GFCLK
CORE_X2_CLK
SYS_CLK1/610
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
Func
Int
354.6
266
DSS_L3_GICLK
FUNC_32K_CLK
COUNTER_32K COUNTER_32K_FCL
K
Func
0.032
COUNTER_32K_ICL
K
Int
Int
38.4
4.8
WKUPAON_GICLK
L3INSTR_TS_GCLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_ L3INSTR_TS_GCLK
BANDGAP
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
CTRL_MODULE_
CORE
L4CFG_L4_GICLK
Int
Int
133
L4CFG_L4_GICLK
WKUPAON_GICLK
CORE_X2_CLK
DPLL_CORE
CTRL_MODULE_ WKUPAON_GICLK
WKUP
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
108
Specifications
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TDA2E-17
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
DCAN1_FCLK
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
DCAN1
Func
Int
38.4
DCAN1_SYS_CLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
OSC0
OSC1
DCAN1_ICLK
266
WKUPAON_GICLK
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
DCAN2
DCAN2_FCLK
DCAN2_ICLK
DES_CLK_L3
EMIF_DLL_FCLK
FCLK
Func
Int
38.4
266
266
DCAN2_SYS_CLK
L4PER2_L3_GICLK
L4SEC_L3_GICLK
EMIF_DLL_GCLK
SYS_CLK1
CORE_X2_CLK
CORE_X2_CLK
EMIF_DLL_GCLK
SYS_CLK1
OSC0
DPLL_CORE
DPLL_CORE
DPLL_DDR
OSC0
DES3DES
DLL
Int
Func
Int
DLL_AGING
38.4
EMIF_DLL_FC
LK
L3INSTR_DLL_AGING
_GCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
DMM
DPLL_DEBUG
DSP1
DMM_CLK
SYSCLK
Int
Int
266
38.4
EMIF_L3_GICLK
EMU_SYS_CLK
DSP1_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
DSP1_FICLK
Int &
Func
DSP_CLK
DSP_GFCLK
DPLL_DSP
DSS
DSS_HDMI_CEC_CL
K
Func
0.032
48
HDMI_CEC_GFCLK
HDMI_PHY_GFCLK
SYS_CLK1/610
OSC0
DSS_HDMI_PHY_CL
K
Func
FUNC_192M_CLK
DPLL_PER
DSS_CLK
Func
Func
192
DSS_GFCLK
DSS_CLK
SYS_CLK1
SYS_CLK2
CORE_X2_CLK
SYS_CLK1
SYS_CLK2
SYS_CLK1
SYS_CLK2
HDMI_CLK
DPLL_PER
OSC0
HDMI_CLKINP
38.4
HDMI_DPLL_CLK
OSC1
DSS_L3_ICLK
Int
266
DSS_L3_GICLK
DPLL_CORE
OSC0
VIDEO1_CLKINP
Func
38.4
VIDEO1_DPLL_CLK
OSC1
VIDEO2_CLKINP
Func
Func
38.4
VIDEO2_DPLL_CLK
N/A
OSC0
OSC1
DPLL_DSI1_A_CLK1
209.3
DPLL_HDMI
DPLL_VIDEO1
VIDEO1_CLKOUT
1
DPLL_DSI1_B_CLK1
Func
209.3
N/A
VIDEO1_CLKOUT
3
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
DPLL_ABE
DPLL_ABE_X2_CL
K
DPLL_DSI1_C_CLK1
DPLL_HDMI_CLK1
Func
Func
209.3
185.6
N/A
N/A
HDMI_CLK
DPLL_HDMI
VIDEO1_CLKOUT
3
DPLL_VIDEO1
HDMI_CLK
DPLL_HDMI
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表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
LCD1_CLK
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
DSS DISPC
Func
Func
Func
Func
209.3
209.3
209.3
209.3
N/A
DPLL_DSI1_A_CL See DSS data in the
K1
rows above
DSS_CLK
LCD2_CLK
LCD3_CLK
F_CLK
N/A
N/A
N/A
DPLL_DSI1_B_CL
K1
DSS_CLK
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_DSI1_A_CL
K1
DPLL_DSI1_B_CL
K1
DPLL_DSI1_C_CL
K1
DSS_CLK
DPLL_HDMI_CLK1
CORE_X2_CLK
EFUSE_CTRL_C
UST
ocp_clk
sys_clk
Int
133
CUSTEFUSE_L4_GIC
LK
DPLL_CORE
OSC0
Func
38.4
CUSTEFUSE_SYS_GF
CLK
SYS_CLK1
ELM
EMIF_OCP_FW
EMIF_PHY1
EMIF1
ELM_ICLK
L3_CLK
Int
Int
266
266
DDR
266
266
L4PER_L3_GICLK
EMIF_L3_GICLK
EMIF_PHY_GCLK
EMIF_L3_GICLK
GMAC_RFT_CLK
CORE_X2_CLK
CORE_X2_CLK
EMIF_PHY_GCLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_DDR
DPLL_CORE
DPLL_ABE
EMIF_PHY1_FCLK
EMIF1_ICLK
Func
Int
GMAC_SW
CPTS_RFT_CLK
Func
PER_ABE_X1_GF
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_GMAC
DPLL_GMAC
CORE_X2_CLK
GMAC_250M_CLK
MAIN_CLK
Int
125
250
GMAC_MAIN_CLK
GMII_250MHZ_CLK
MHZ_250_CLK
Func
GMII_250MHZ_CL
K
MHZ_5_CLK
MHZ_50_CLK
Func
Func
Func
Func
Int
5
50
RGMII_5MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
RMII_50MHZ_CLK
WKUPAON_GICLK
GMAC_RMII_HS_
CLK
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
DPLL_GMAC
GMAC_RMII_HS_
CLK
RMII1_MHZ_50_CLK
RMII2_MHZ_50_CLK
GPIO1_ICLK
50
GMAC_RMII_HS_
CLK
50
GMAC_RMII_HS_
CLK
GPIO1
38.4
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
GPIO1_DBCLK
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_
OSC0
LK
GFCLK
GPIO2
GPIO3
GPIO2_ICLK
GPIO2_DBCLK
GPIO3_ICLK
Int
Func
Int
266
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
DPLL_CORE
OSC0
GPIO3_DBCLK
Func
0.032
110
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
GPIO4
GPIO4_ICLK
GPIO4_DBCLK
PIDBCLK
Int
266
0.032
0.032
266
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
GPIO_GFCLK
GPIO5
GPIO6
GPIO7
GPIO8
GPIO5_ICLK
GPIO5_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO6_ICLK
GPIO6_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO7_ICLK
GPIO7_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPIO8_ICLK
GPIO8_DBCLK
PIDBCLK
L4PER_L3_GICLK
GPIO_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
DPLL_CORE
OSC0
Func
Func
Int
0.032
0.032
266
GPIO_GFCLK
GPMC
GPU
GPMC_FCLK
GPU_FCLK1
L3MAIN1_L3_GICLK
GPU_CORE_GCLK
CORE_X2_CLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
DPLL_GPU
DPLL_CORE
DPLL_PER
Func
GPU_CLK
GPU_FCLK2
GPU_ICLK
Func
GPU_CLK
GPU_HYD_GCLK
CORE_GPU_CLK
PER_GPU_CLK
GPU_GCLK
Int
266
GPU_L3_GICLK
CORE_X2_CLK
FUNC_192M_CLK
HDMI PHY
I2C1
DSS_HDMI_PHY_CL
K
Func
38.4
HDMI_PHY_GFCLK
I2C1_ICLK
I2C1_FCLK
I2C2_ICLK
I2C2_FCLK
I2C3_ICLK
I2C3_FCLK
I2C4_ICLK
I2C4_FCLK
I2C5_ICLK
I2C5_FCLK
I2C6_ICLK
I2C6_FCLK
PI_L3CLK
Int
Func
Int
266
96
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
L4PER_L3_GICLK
PER_96M_GFCLK
IPU_L3_GICLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
I2C2
I2C3
I2C4
I2C5
I2C6
266
96
Func
Int
266
96
Func
Int
266
96
Func
Int
266
96
Func
Int
IPU_96M_GFCLK
L4PER2_L3_GICLK
IPU_96M_GFCLK
L3INIT_L3_GICLK
266
96
Func
IEEE1500_2_OC
P
Int &
Func
266
IPU1
IPU1_GFCLK
Int &
Func
425.6
IPU1_GFCLK
DPLL_ABE_X2_CL
K
DPLL_ABE
DPLL_CORE
DPLL_CORE
DPLL_IVA
CORE_IPU_ISS_B
OOST_CLK
IPU2
IVA
IPU2_GFCLK
IVA_GCLK
Int &
Func
425.6
IPU2_GFCLK
IVA_GCLK
CORE_IPU_ISS_B
OOST_CLK
Int
IVA_GCLK
IVA_GFCLK
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Specifications
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表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
KBD_FCLK
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
KBD
Func
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_
OSC0
LK
GFCLK
PICLKKBD
0.032
WKUPAON_SYS_GFC
LK
KBD_ICLK
PICLKOCP
Int
Int
38.4
38.4
WKUPAON_GICLK
WKUPAON_GICLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
L3_INSTR
L3_MAIN
L3_CLK
Int
Int
Int
Int
Int
Int
Int
Int
L3_CLK
L3_CLK
L3_CLK
133
L3INSTR_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L4CFG_L3_GICLK
L4PER_L3_GICLK
L4PER2_L3_GICLK
L4PER3_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
L3_CLK1
L3_CLK2
L4_CFG
L4_PER1
L4_PER2
L4_PER3
L4_WKUP
L4_CFG_CLK
L4_PER1_CLK
L4_PER2_CLK
L4_PER3_CLK
L4_WKUP_CLK
133
133
133
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
MAILBOX1
MAILBOX2
MAILBOX3
MAILBOX4
MAILBOX5
MAILBOX6
MAILBOX7
MAILBOX8
MAILBOX9
MAILBOX10
MAILBOX11
MAILBOX12
MAILBOX13
MAILBOX1_FLCK
MAILBOX2_FLCK
MAILBOX3_FLCK
MAILBOX4_FLCK
MAILBOX5_FLCK
MAILBOX6_FLCK
MAILBOX7_FLCK
MAILBOX8_FLCK
MAILBOX9_FLCK
MAILBOX10_FLCK
MAILBOX11_FLCK
MAILBOX12_FLCK
MAILBOX13_FLCK
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
Int
266
266
266
266
266
266
266
266
266
266
266
266
266
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
L4CFG_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
112
Specifications
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TDA2E-17
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP1_AHCLKR
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
MCASP1
Func
100
MCASP1_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP1_AHCLKX
Func
100
MCASP1_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP1_FCLK
MCASP1_ICLK
Func
Int
192
266
MCASP1_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
IPU_L3_GICLK
CORE_X2_CLK
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Specifications
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表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP2_AHCLKR
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
MCASP2
Func
100
MCASP2_AHCLKR
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
OSC0
MLBP_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP2_AHCLKX
Func
100
MCASP2_AHCLKX
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP2_FCLK
MCASP2_ICLK
Func
Int
192
266
MCASP2_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
114
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP3_AHCLKX
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
MCASP3
Func
100
MCASP3_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP3_FCLK
Func
192
MCASP3_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP3_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP4_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP4
MCASP4_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP4_FCLK
MCASP4_ICLK
Func
Int
192
266
MCASP4_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
115
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP5_AHCLKX
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
MCASP5
Func
100
MCASP5_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP5_FCLK
Func
192
MCASP5_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
DPLL_PER
MCASP5_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP6_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
MCASP6
MCASP6_AHCLKX
Func
FUNC_24M_GFCL
K
ATL_CLK0
ATL_CLK1
Module ATL
Module ATL
Module ATL
Module ATL
Module MLB
Module MLB
OSC0
ATL_CLK2
ATL_CLK3
MLB_CLK
MLBP_CLK
ABE_SYS_CLK
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
MCASP6_FCLK
MCASP6_ICLK
Func
Int
192
266
MCASP6_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
L4PER2_L3_GICLK
CORE_X2_CLK
116
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
MCASP7_AHCLKX
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
MCASP7
Func
100
MCASP7_AHCLKX
ABE_24M_GFCLK
ABE_SYS_CLK
DPLL_ABE
OSC0
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP7_FCLK
Func
192
MCASP7_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
HDMI_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_ABE
OSC0
MCASP7_ICLK
Int
266
100
L4PER2_L3_GICLK
MCASP8_AHCLKX
CORE_X2_CLK
ABE_24M_GFCLK
ABE_SYS_CLK
MCASP8
MCASP8_AHCLKX
Func
FUNC_24M_GFCL
K
DPLL_PER
ATL_CLK0
ATL_CLK1
ATL_CLK2
ATL_CLK3
SYS_CLK2
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
MLB_CLK
Module ATL
Module ATL
Module ATL
Module ATL
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
Module MLB
Module MLB
DPLL_ABE
MLBP_CLK
MCASP8_FCLK
Func
192
MCASP8_AUX_GFCL PER_ABE_X1_GF
K
CLK
VIDEO1_CLK
DPLL_ABE
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
HDMI_CLK
MCASP8_ICLK
SPI1_ICLK
SPI1_FCLK
SPI2_ICLK
SPI2_FCLK
SPI3_ICLK
SPI3_FCLK
Int
Int
266
266
48
L4PER2_L3_GICLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
MCSPI1
MCSPI2
MCSPI3
Func
Int
266
48
Func
Int
266
48
Func
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
117
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
MCSPI4
SPI4_ICLK
SPI4_FCLK
MLB_L3_ICLK
MLB_L4_ICLK
MLB_FCLK
CTRLCLK
Int
Func
Int
266
48
L4PER_L3_GICLK
PER_48M_GFCLK
CORE_X2_CLK
PER_48M_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
MLB_SS
CSI2_0
266
133
266
96
MLB_SHB_L3_GICLK
MLB_SPB_L4_GICLK
MLB_SYS_L3_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
Int
Func
Int &
Func
LVDSRX_96M_GFCLK FUNC_192M_CLK
CAL_FCLK
Int &
Func
266
CAL_GICLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
L3_ICLK
CM_CORE_AON
OSC0
MMC1
MMC2
MMC1_CLK_32K
MMC1_FCLK
Func
Func
0.032
192
L3INIT_32K_GFCLK
MMC1_GFCLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
FUNC_256M_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
OSC0
128
MMC1_ICLK1
MMC1_ICLK2
MMC2_CLK_32K
MMC2_FCLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L3INIT_32K_GFCLK
MMC2_GFCLK
133
Func
Func
0.032
192
DPLL_PER
DPLL_PER
DPLL_CORE
DPLL_CORE
DPLL_CORE
OSC0
128
MMC2_ICLK1
MMC2_ICLK2
MMC3_ICLK
Int
Int
266
L3INIT_L3_GICLK
L3INIT_L4_GICLK
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC3_GFCLK
133
MMC3
MMC4
Int
266
MMC3_CLK_32K
MMC3_FCLK
Func
Func
0.032
48
DPLL_PER
192
MMC4_ICLK
MMC4_CLK_32K
MMC4_FCLK
Int
266
L4PER_L3_GICLK
L4PER_32K_GFCLK
MMC4_GFCLK
CORE_X2_CLK
FUNC_32K_CLK
FUNC_192M_CLK
DPLL_CORE
OSC0
Func
Func
0.032
48
DPLL_PER
192
MMU_EDMA
MMU_PCIESS
MPU
MMU1_CLK
MMU2_CLK
MPU_CLK
Int
Int
266
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
MPU_GCLK
CORE_X2_CLK
CORE_X2_CLK
MPU_GCLK
DPLL_CORE
DPLL_CORE
DPLL_MPU
266
Int &
Func
MPU_CLK
MPU_EMU_DBG
FCLK
Int
38.4
EMU_SYS_CLK
SYS_CLK1
MPU_GCLK
OSC0
DPLL_MPU
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_CORE
OCMC_RAM1
OCMC_ROM
OCP_WP_NOC
OCP2SCP1
OCMC1_L3_CLK
OCMC_L3_CLK
PICLKOCPL3
Int
Int
Int
Int
266
266
266
133
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3INSTR_L3_GICLK
L3INIT_L4_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
L4CFG1_ADAPTER_
CLKIN
OCP2SCP2
OCP2SCP3
L4CFG2_ADAPTER_
CLKIN
Int
Int
133
133
L4CFG_L4_GICLK
L3INIT_L4_GICLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
L4CFG3_ADAPTER_
CLKIN
118
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
PCIe_SS1
PCIE1_PHY_WKUP_
CLK
Func
0.032
PCIE_32K_GFCLK
FUNC_32K_CLK
DPLL_CORE
PCIe_SS1_FICLK
PCIEPHY_CLK
Int
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
Func
Func
PCIE_PHY_GCLK
APLL_PCIE
APLL_PCIE
PCIEPHY_CLK_DIV
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE1_REF_CLKIN
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG
_SS_LFPS_TX_CL
K
DPLL_CORE
PCIE1_PWR_CLK
Func
Func
38.4
PCIE_SYS_GFCLK
PCIE_32K_GFCLK
SYS_CLK1
OSC0
PCIe_SS2
PCIE2_PHY_WKUP_
CLK
0.032
FUNC_32K_CLK
DPLL_CORE
PCIe_SS2_FICLK
PCIEPHY_CLK
Func
Func
Func
266
2500
1250
PCIE_L3_GICLK
PCIE_PHY_GCLK
CORE_X2_CLK
PCIE_PHY_GCLK
APLL_PCIE
APLL_PCIE
PCIEPHY_CLK_DIV
PCIE_PHY_DIV_GCLK PCIE_PHY_DIV_G
CLK
PCIE2_REF_CLKIN
Func
34.3
PCIE_REF_GFCLK
CORE_USB_OTG
_SS_LFPS_TX_CL
K
DPLL_CORE
PCIE2_PWR_CLK
32K_CLK
Func
Func
Func
38.4
0.032
38.4
PCIE_SYS_GFCLK
FUNC_32K_CLK
WKUPAON_ICLK
SYS_CLK1
SYS_CLK1/610
SYS_CLK1
OSC0
OSC0
PRCM_MPU
SYS_CLK
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PWMSS1
PWMSS2
PWMSS3
QSPI
PWMSS1_GICLK
PWMSS2_GICLK
PWMSS3_GICLK
Int &
Func
266
266
266
L4PER2_L3_GICLK
L4PER2_L3_GICLK
L4PER2_L3_GICLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
Int &
Func
Int &
Func
QSPI_ICLK
QSPI_FCLK
Int
266
128
L4PER2_L3_GICLK
QSPI_GFCLK
CORE_X2_CLK
FUNC_256M_CLK
PER_QSPI_CLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
DPLL_CORE
DPLL_PER
Func
DPLL_PER
RNG
SAR_ROM
SDMA
RNG_ICLK
PRCM_ROM_CLOCK
SDMA_FCLK
Int
Int
266
266
266
L4SEC_L3_GICLK
L4CFG_L3_GICLK
DMA_L3_GICLK
DPLL_CORE
DPLL_CORE
DPLL_CORE
Int &
Func
SHA2MD51
SHA2MD52
SL2
SHAM_1_CLK
SHAM_2_CLK
IVA_GCLK
MCLK
Int
Int
266
266
L4SEC_L3_GICLK
L4SEC_L3_GICLK
IVA_GCLK
CORE_X2_CLK
CORE_X2_CLK
IVA_GFCLK
DPLL_CORE
DPLL_CORE
DPLL_IVA
DPLL_CORE
OSC0
Int
IVA_GCLK
133
SMARTREFLEX_
CORE
Int
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_
DSP
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
119
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
SMARTREFLEX_
GPU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_
IVAHD
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SMARTREFLEX_
MPU
MCLK
Int
133
COREAON_L4_GICLK
WKUPAON_ICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
SYSCLK
Func
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
SPINLOCK
TIMER1
SPINLOCK_ICLK
TIMER1_ICLK
Int
Int
266
L4CFG_L3_GICLK
WKUPAON_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
TIMER1_FCLK
Func
100
TIMER1_GFCLK
SYS_CLK1
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER2
TIMER2_ICLK
TIMER2_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER2_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
120
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER3
TIMER3_ICLK
TIMER3_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER3_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER4
TIMER4_ICLK
TIMER4_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER4_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER5
TIMER5_ICLK
TIMER5_FCLK
Int
266
100
IPU_L3_GICLK
TIMER5_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
版权 © 2016–2018, Texas Instruments Incorporated
Specifications
121
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER6
TIMER6_ICLK
TIMER6_FCLK
Int
266
100
IPU_L3_GICLK
TIMER6_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER7
TIMER7_ICLK
TIMER7_FCLK
Int
266
100
IPU_L3_GICLK
TIMER7_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
DPLL_CORE
OSC0
CLKOUTMUX[0]
CORE_X2_CLK
SYS_CLK1
TIMER8
TIMER8_ICLK
TIMER8_FCLK
Int
266
100
IPU_L3_GICLK
TIMER8_GFCLK
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
CLKOUTMUX[0]
CLKOUTMUX[0]
122
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER9
TIMER9_ICLK
TIMER9_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER9_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER10
TIMER11
TIMER12
TIMER10_ICLK
TIMER10_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER10_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER11_ICLK
TIMER11_FCLK
Int
266
100
L4PER_L3_GICLK
TIMER11_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
SYS_CLK1
DPLL_VIDEO1
DPLL_HDMI
OSC0
TIMER12_ICLK
TIMER12_FCLK
Int
38.4
WKUPAON_GICLK
OSC_32K_CLK
DPLL_ABE_X2_CL
K
DPLL_ABE
Func
0.032
RC_CLK
RC oscillator
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Specifications
123
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ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER13
TIMER13_ICLK
TIMER13_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER13_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER14
TIMER14_ICLK
TIMER14_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER14_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
OSC0
TIMER15
TIMER15_ICLK
TIMER15_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER15_GFCLK
CORE_X2_CLK
SYS_CLK1
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
124
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-5. Maximum Supported Frequency (continued)
Module
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
Input Clock Name
PRCM Clock Name
TIMER16
TIMER16_ICLK
TIMER16_FCLK
Int
266
100
L4PER3_L3_GICLK
TIMER16_GFCLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
Func
FUNC_32K_CLK
SYS_CLK2
OSC0
OSC1
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
XREF_CLK0
XREF_CLK1
XREF_CLK2
XREF_CLK3
DPLL_ABE
DPLL_ABE_X2_CL
K
VIDEO1_CLK
HDMI_CLK
DPLL_VIDEO1
DPLL_HDMI
DPLL_CORE
DPLL_CORE
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
DPLL_CORE
DPLL_PER
OSC0
TPCC
TPTC1
TPTC2
UART1
TPCC_GCLK
TPTC0_GCLK
TPTC1_GCLK
UART1_FCLK
UART1_ICLK
UART2_FCLK
UART2_ICLK
UART3_FCLK
UART3_ICLK
UART4_FCLK
UART4_ICLK
UART5_FCLK
UART5_ICLK
UART6_FCLK
UART6_ICLK
UART7_FCLK
UART7_ICLK
UART8_FCLK
UART8_ICLK
UART9_FCLK
UART9_ICLK
UART10_FCLK
UART10_ICLK
Int
Int
266
266
266
48
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
L3MAIN1_L3_GICLK
UART1_GFCLK
CORE_X2_CLK
CORE_X2_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
CORE_X2_CLK
FUNC_192M_CLK
SYS_CLK1
Int
Func
Int
266
48
L4PER_L3_GICLK
UART2_GFCLK
UART2
UART3
UART4
UART5
UART6
UART7
UART8
UART9
UART10
Func
Int
266
48
L4PER_L3_GICLK
UART3_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART4_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART5_GFCLK
Func
Int
266
48
L4PER_L3_GICLK
UART6_GFCLK
Func
Int
266
48
IPU_L3_GICLK
Func
Int
UART7_GFCLK
266
48
L4PER2_L3_GICLK
UART8_GFCLK
Func
Int
266
48
L4PER2_L3_GICLK
UART9_GFCLK
Func
Int
266
48
L4PER2_L3_GICLK
UART10_GFCLK
WKUPAON_GICLK
Func
Int
38.4
DPLL_ABE_X2_CL
K
DPLL_ABE
USB1
USB1_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
DPLL_CORE
DPLL_CORE
USB3PHY_REF_CLK
Func
34.3
USB_LFPS_TX_GFCL CORE_USB_OTG
K
_SS_LFPS_TX_CL
K
USB2PHY1_TREF_C
LK
Func
Func
38.4
960
USB_OTG_SS_REF_C
LK
SYS_CLK1
OSC0
USB2PHY1_REF_CL
K
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
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Specifications
125
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-5. Maximum Supported Frequency (continued)
Module
Input Clock Name
USB2_MICLK
Clock Sources
Max. Clock
Allowed
(MHz)
PLL / OSC /
Source Clock
Name
Clock
Type
PLL / OSC / Source
Name
Instance Name
PRCM Clock Name
USB2
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
USB2PHY2_TREF_C
LK
Func
38.4
USB_OTG_SS_REF_C
LK
USB2PHY2_REF_CL
K
Func
960
L3INIT_960M_GFCLK L3INIT_960_GFCL
K
DPLL_USB
USB3
USB3_MICLK
Int
266
L3INIT_L3_GICLK
CORE_X2_CLK
SYS_CLK1
DPLL_CORE
OSC0
USB3PHY_PWRS_C
LK
Func
38.4
USB_OTG_SS_REF_C
LK
USB_PHY1_COR USB2PHY1_WKUP_
CLK
Func
Func
Func
0.032
0.032
0.032
266
COREAON_32K_GFC
LK
SYS_CLK1/610
SYS_CLK1/610
SYS_CLK1/610
CORE_X2_CLK
OSC0
OSC0
OSC0
E
USB_PHY2_COR USB2PHY2_WKUP_
CLK
COREAON_32K_GFC
LK
E
USB_PHY3_COR USB3PHY_WKUP_C
COREAON_32K_GFC
LK
E
LK
VIP1
L3_CLK_PROC_CLK
Int &
Func
VIP1_GCLK
DPLL_CORE
DPLL_CORE
CORE_ISS_MAIN_
CLK
VPE
L3_CLK_PROC_CLK
PIOCPCLK
Int &
Func
300
VPE_GCLK
CORE_ISS_MAIN_
CLK
DPLL_CORE
VIDEO1_CLKOUT
4
DPLL_VIDEO1
WD_TIMER1
Int
38.4
WKUPAON_GICLK
SYS_CLK1
OSC0
DPLL_ABE_X2_CL
K
DPLL_ABE
PITIMERCLK
Func
Int
0.032
38.4
OSC_32K_CLK
RC_CLK
RC oscillator
OSC0
WD_TIMER2
WD_TIMER2_ICLK
WKUPAON_GICLK
SYS_CLK1
DPLL_ABE_X2_CL
K
DPLL_ABE
WD_TIMER2_FCLK
Func
0.032
WKUPAON_SYS_GFC WKUPAON_32K_
LK GFCLK
5.6 Power Consumption Summary
注
Maximum power consumption for this SoC depends on the specific use conditions for the
end system. Contact your TI representative for assistance in estimating maximum power
consumption for the end system use case.
5.7 Electrical Characteristics
注
The interfaces or signals described in 节 5.7 through 节 5.7.3 correspond to the interfaces or
signals available in multiplexing mode 0 (Function 1).
All interfaces or signals multiplexed on the balls described in these tables have the same DC
electrical characteristics, unless multiplexing involves a PHY/GPIO combination in which
case different DC electrical characteristics are specified for the different multiplexing modes
(Functions).
126
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-6. LVCMOS DDR DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0 (Single-Ended Signals): ddr1_d[31:0], ddr1_a[15:0], ddr1_dqm[3:0], ddr1_ba[2:0], ddr1_csn0, ddr1_cke,
ddr1_odt0, ddr1_casn, ddr1_rasn, ddr1_wen, ddr1_rst
Balls: AA23 / AC24 / AB24 / AD24 / AB23 / AC23 / AD23 / AE24 / AA24 / W25 / Y23 / AD25 / AC25 / AB25 / AA25 / W24 / W23 / U25 /
U24 / W21 / T22 / U22 / U23 / T21 / T23 / T25 / T24 / P21 / N21 / P22 / P23 / P24 / AC18 / AE19 / AD19 / AB19 / AD20 / AE20 / AA18 /
AA20 / Y21 / AC20 / AA21 / AC21 / AC22 / AC15 / AB15 / AC16 / AE23 / W22 / U21 / P25 / AE16 / AA16 / AB16 / AC19 / AB18 / AD18 /
AD16 / AD17 / AE18 / AE17
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9 × VDDS
V
V
0.1 × VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
VREF+
-10%vdds
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
Signal Names in MUXMODE 0 (Differential Signals): ddr1_ck, ddr1_nck, ddr1_dqs[3:0], ddr1_dqsn[3:0]
Bottom Balls: AD21 / AE21 / AD22 / AE22 / Y24 / Y25 / V24 / V25 / R24 / R25
Driver Mode
VOH
VOL
CPAD
ZO
High-level output threshold (IOH = 0.1 mA)
Low-level output threshold (IOL = 0.1 mA)
Pad capacitance (including package capacitance)
0.9 × VDDS
V
V
0.1 × VDDS
3
pF
Ω
Output impedance (drive
strength)
l[2:0] = 000
(Imp80)
80
60
48
40
34
l[2:0] = 001
(Imp60)
l[2:0] = 010
(Imp48)
l[2:0] = 011
(Imp40)
l[2:0] = 100
(Imp34)
Single-Ended Receiver Mode
VIH
VIL
High-level input threshold
DDR3/DDR3L
DDR3/DDR3L
VREF+0.1
-0.2
VDDS+0.2
VREF-0.1
V
V
V
Low-level input threshold
VCM
Input common-mode voltage
VREF
VREF+
-10%vdds
10%vdds
CPAD
Pad capacitance (including package capacitance)
3
pF
Differential Receiver Mode
VSWING Input voltage swing
VCM Input common-mode voltage
DDR3/DDR3L
0.2
vdds+0.4
V
V
VREF
VREF+
-10%vdds
10%vdds
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Specifications
127
TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-6. LVCMOS DDR DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
CPAD
Pad capacitance (including package capacitance)
3
pF
(1) VDDS in this table stands for corresponding power supply (i.e. vdds_ddr1). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
(2) VREF in this table stands for corresponding Reference Power Supply (i.e. ddr1_vref0). For more information on the power supply name
and the corresponding ball, see 表 4-1, POWER [10] column.
(3) For more information on the I/O cell configurations (i[2:0], sr[1:0]), see the Chapter Control Module of the Device TRM.
表 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: i2c1_scl; i2c1_sda; i2c2_scl; i2c_sda
Balls: G22 / G23 / G21 / F23
MIN
NOM
MAX
UNIT
I2C Standard Mode – 1.8 V
VIH
VIL
Input high-level threshold
Input low-level threshold
Hysteresis
0.7 × VDDS
0.1 × VDDS
V
V
0.3 × VDDS
Vhys
IIN
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS
IOLmin
tOF
Low-level output current @VOL=0.2 × VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
I2C Fast Mode – 1.8 V
VIH
VIL
Input high-level threshold
0.7 × VDDS
0.1 × VDDS
V
V
Input low-level threshold
Hysteresis
0.3 × VDDS
Vhys
IIN
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
12
12
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.2 × VDDS
IOLmin
tOF
Low-level output current @VOL=0.2 × VDDS
3
mA
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 400 pF
20+0.1 × Cb
250
I2C Standard Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7 × VDDS
V
V
Input low-level threshold
Hysteresis
0.3 × VDDS
80
Vhys
IIN
0.05 × VDDS
31
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDS
µA
128
Specifications
版权 © 2016–2018, Texas Instruments Incorporated
TDA2E-17
www.ti.com.cn
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
表 5-7. Dual Voltage LVCMOS I2C DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
80
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 5 pF to 400 pF
250
ns
I2C Fast Mode – 3.3 V
VIH
VIL
Input high-level threshold
0.7 × VDDS
V
V
Input low-level threshold
Hysteresis
0.3 × VDDS
Vhys
IIN
0.05 × VDDS
31
V
Input current at each I/O pin with an input voltage
between 0.1 × VDDS to 0.9 × VDDSS
80
80
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
31
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
CIN
Input capacitance
10
pF
V
VOL3
Output low-level threshold open-drain at 3-mA
sink current
0.4
IOLmin
IOLmin
Low-level output current @VOL=0.4V
3
6
mA
mA
Low-level output current @VOL=0.6V for full drive
load (400pF/400KHz)
tOF
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 10 pF to 200 pF (Proper
External Resistor Value should be used as per
I2C spec)
20+0.1 × Cb
250
290
ns
Output fall time from VIHmin to VILmax with a bus
capacitance CB from 300 pF to 400 pF (Proper
External Resistor Value should be used as per
I2C spec)
40
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
(2) For more information on the I/O cell configurations, see the Control Module section of the Device TRM.
表 5-8. IQ1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signal Names in MUXMODE 0: tclk
Balls: K21
1.8-V Mode
VIH
Input high-level threshold (Does not meet JEDEC VIH
Input low-level threshold (Does not meet JEDEC VIL)
Input hysteresis voltage
)
0.75 ×
VDDS
V
V
VIL
0.25 ×
VDDS
VHYS
100
mV
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Specifications
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TDA2E-17
ZHCSII3E –AUGUST 2016–REVISED JULY 2018
www.ti.com.cn
表 5-8. IQ1833 Buffers DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
µA
IIN
Input current at each I/O pin
2
11
1
CPAD
3.3-V Mode
VIH
Pad capacitance (including package capacitance)
pF
Input high-level threshold (Does not meet JEDEC VIH
Input low-level threshold (Does not meet JEDEC VIL)
Input hysteresis voltage
)
2.0
V
V
VIL
0.6
VHYS
IIN
400
5
mV
µA
pF
Input current at each I/O pin
11
1
CPAD
Pad capacitance (including package capacitance)
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv3). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [11] column.
表 5-9. IHHV1833 Buffers DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in MUXMODE 0: porz / wakeup3 / wakeup0
Balls: AB10/ AC10/ F19
MIN
NOM
MAX
UNIT
1.8-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
0.02
1
1
CPAD
3.3-V Mode
VIH
Input high-level threshold
1.2
V
V
VIL
Input low-level threshold
0.4
VHYS
IIN
Input hysteresis voltage
40
5
mV
µA
pF
Input current at each I/O pin
Pad capacitance (including package capacitance)
8
1
CPAD
表 5-10. LVCMOS CSI2 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
Signals MUXMODE 0 : csi2_0_dx[2:0]; csi2_0_dy[2:0]
Bottom Balls: AC1 / AB2 / AD1 / AC2 / AE2 / AD2
MIPI D-PHY Mode Low-Power Receiver (LP-RX)
VIH
VIL
Input high-level voltage
Input low-level voltage
Input high-level threshold(1)
Input low-level threshold(2)
Input hysteresis(3)
880
1350
550
mV
mV
mV
mV
mV
VITH
VITL
VHYS
880
550
25
MIPI D-PHY Mode Ultralow Power Receiver (ULP-RX)
VIL
VITL
VHYS
Input low-level voltage
Input low-level threshold(4)
Input hysteresis(3)
300
mV
mV
mV
300
25
MIPI D-PHY Mode High-Speed Receiver (HS-RX)
VIDTH Differential input high-level threshold
70
mV
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表 5-10. LVCMOS CSI2 DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
–70
270
460
UNIT
mV
mV
mV
mV
mV
Ω
VIDTL
VIDMAX
VIHHS
Differential input low-level threshold
Maximum differential input voltage(7)
Single-ended input high voltage(5)
Single-ended input low voltage(5)
Differential input common-mode voltage(5)(6)
Differential input impedance
VILHS
–40
70
VCMRXDC
ZID
330
125
80
100
(1) VITH is the voltage at which the receiver is required to detect a high state in the input signal.
(2) VITL is the voltage at which the receiver is required to detect a low state in the input signal. VITL is larger than the maximum single-ended
line high voltage during HS transmission. Therefore, both low-power (LP) receivers will detect low during HS signaling.
(3) To reduce noise sensitivity on the received signal, the LP receiver is required to incorporate a hysteresis, VHYST. VHYST is the difference
between the VITH threshold and the VITL threshold.
(4) VITL is the voltage at which the receiver is required to detect a low state in the input signal. Specification is relaxed for detecting 0 during
ultralow power (ULP) state. The LP receiver is not required to detect HS single-ended voltage as 0 in this state.
(5) Excluding possible additional RF interference of 200 mVPP beyond 450 MHz.
(6) This value includes a ground difference of 50 mV between the transmitter and the receiver, the static common-mode level tolerance and
variations below 450 MHz.
(7) This number corresponds to the VODMAX transmitter.
(8) Common mode is defined as the average voltage level of X and Y: VCMRX = (VX + VY) / 2.
(9) Common mode ripple may be due to tR or tF and transmission line impairments in the PCB.
(10) For more information regarding the pin name (or ball name) and corresponding signal name, see 表 4-5 CSI 2 Signal Descriptions.
表 5-11. Dual Voltage SDIO1833 DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0]
Bottom Balls: U3 / V4 / V3 / V2 / W1 / V1
1.8-V Mode
MIN
NOM
MAX
UNIT
VIH
VIL
Input high-level threshold
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
1.27
V
V
0.58
(2)
VHYS
IIN
50
mV
µA
µA
30
30
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
50
60
120
120
210
200
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
5
pF
V
1.4
0.45
V
3.3-V Mode
VIH
Input high-level threshold
0.625 ×
VDDS
V
VIL
Input low-level threshold
Input hysteresis voltage
Input current at each I/O pin
0.25 × VDDS
110
V
(2)
VHYS
IIN
40
mV
µA
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表 5-11. Dual Voltage SDIO1833 DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
IOZ
IOZ(IPAD Current) for BIDI cell. This current is contributed by the
tristated driver leakage + input current of the Rx + weak
pullup/pulldown leakage. PAD is swept from 0 to VDDS and the
Max(I(PAD)) is measured and is reported as IOZ
110
µA
IIN with
pulldown
enabled
Input current at each I/O pin with weak pulldown enabled
measured when PAD = VDDS
40
10
100
100
290
290
5
µA
µA
IIN with
pullup
Input current at each I/O pin with weak pullup enabled measured
when PAD = 0
enabled
CPAD
VOH
VOL
Pad capacitance (including package capacitance)
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
pF
V
0.75 × VDDS
0.125 ×
VDDS
V
(1) VDDS in this table stands for corresponding power supply (i.e. vddshv8). For more information on the power supply name and the
corresponding ball, see 表 4-1, POWER [10] column.
(2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register.
表 5-12. Dual Voltage LVCMOS DC Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
1.8-V Mode
VIH
MIN
NOM
MAX
0.35 × VDDS
0.45
UNIT
Input high-level threshold
0.65 × VDDS
V
V
VIL
Input low-level threshold
VHYS
Input hysteresis voltage
100
mV
V
VOH
Output high-level threshold (IOH = 2 mA)
Output low-level threshold (IOL = 2 mA)
VDDS-0.45
VOL
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
IIN
Input current at each I/O pin
16
16
µA
µA
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
50
60
120
120
210
200
4
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
3.3-V Mode
VIH
Input high-level threshold
2
V
V
VIL
Input low-level threshold
0.8
VHYS
VOH
Input hysteresis voltage
200
mV
V
Output high-level threshold (IOH = 100 µA)
Output low-level threshold (IOL = 100 µA)
VDDS-0.2
VOL
0.2
65
V
IDRIVE
Pin Drive strength at PAD Voltage = 0.45V or
VDDS-0.45V
6
mA
IIN
Input current at each I/O pin
µA
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表 5-12. Dual Voltage LVCMOS DC Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
MIN
NOM
MAX
UNIT
IOZ
IOZ(IPAD Current) for BIDI cell. This current is
contributed by the tristated driver leakage + input
current of the Rx + weak pullup/pulldown leakage.
65
µA
PAD is swept from 0 to VDDS and the Max(I(PAD)
)
is measured and is reported as IOZ
IIN with pulldown
enabled
Input current at each I/O pin with weak pulldown
enabled measured when PAD = VDDS
40
10
100
100
200
290
4
µA
µA
IIN with pullup
enabled
Input current at each I/O pin with weak pullup
enabled measured when PAD = 0
CPAD
Pad capacitance (including package capacitance)
Output impedance (drive strength)
pF
ZO
40
Ω
(1) VDDS in this table stands for corresponding power supply. For more information on the power supply name and the corresponding ball,
see 表 4-1, POWER [10] column.
5.7.1 USBPHY DC Electrical Characteristics
注
USB1 instance is compliant with the USB3.0 SuperSpeed Transmitter and Receiver
Normative Electrical Parameters as defined in the USB3.0 Specification Rev 1.0 dated Jun 6,
2011.
注
USB1 and USB2 Electrical Characteristics are compliant with USB2.0 Specification Rev 2.0
dated April 27, 2000 including ECNs and Errata as applicable.
5.7.2 HDMIPHY DC Electrical Characteristics
注
The HDMIPHY DC Electrical Characteristics are compliant with the HDMI 1.4a specification
and are not reproduced here.
5.7.3 PCIEPHY DC Electrical Characteristics
注
The PCIe interfaces are compliant with the electrical parameters specified in PCI Express®
Base Specification Revision 3.0.
5.8 VPP Specifications for One-Time Programmable (OTP) eFuses
This section specifies the operating conditions required for programming the OTP eFuses and is
applicable only for High-Security Devices.
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表 5-13. Recommended Operating Conditions for OTP eFuse Programming
over operating free-air temperature range (unless otherwise noted)
PARAMETER
DESCRIPTION
MIN
NOM
MAX
UNIT
vdd
vpp
Supply voltage range for the core domain
during OTP operation
1.11
1.15
1.2
V
Supply voltage range for the eFuse ROM
domain during normal operation
NC
V
V
Supply voltage range for the eFuse ROM
domain during OTP programming(1)(2)
1.8
25
Tj
Temperature (ambient)
0
85
ºC
(1) Supply voltage range includes DC errors and peak-to-peak noise. TI power management solutions TLV70718 from the TLV707x family
meet the supply voltage range needed for vpp.
(2) During normal operation, no voltage should be applied to vpp. This can be typically achieved by disabling the regulator attached to the
vpp terminal. For more details, see TLV707, TLV707P 200-mA, Low-IQ, Low-Noise, Low-Dropout Regulator for Portable Devices.
5.8.1 Hardware Requirements
The following hardware requirements must be met when programming keys in the OTP eFuses:
•
•
The vpp power supply must be disabled when not programming OTP registers.
The vpp power supply must be ramped up after the proper device power-up sequence (for more
details, see Section 5.10.3).
5.8.2 Programming Sequence
Programming sequence for OTP eFuses:
1. Power on the board per the power-up sequencing. No voltage should be applied on the vpp terminal
during power up and normal operation.
2. Load the OTP write software required to program the eFuse (contact your local TI representative for
the OTP software package).
3. Apply the voltage on the vpp terminal according to the specification in 表 5-13.
4. Run the software that programs the OTP registers.
5. After validating the content of the OTP registers, remove the voltage from the vpp terminal.
5.8.3 Impact to Your Hardware Warranty
You accept that e-Fusing the TI Devices with security keys permanently alters them. You acknowledge
that the e-Fuse can fail, for example, due to incorrect or aborted program sequence or if you omit a
sequence step. Further the TI Device may fail to secure boot if the error code correction check fails for the
Production Keys or if the image is not signed and optionally encrypted with the current active Production
Keys. These types of situations will render the TI Device inoperable and TI will be unable to confirm
whether the TI Devices conformed to their specifications prior to the attempted e-Fuse.
CONSEQUENTLY, TI WILL HAVE NO LIABILITY (WARRANTY OR OTHERWISE) FOR ANY TI
DEVICES THAT HAVE BEEN e-FUSED WITH SECURITY KEYS.
5.9 Thermal Resistance Characteristics for CBD Package
For reliability and operability concerns, the maximum junction temperature of the Device has to be at or
below the TJ value identified in Section 5.4, Recommended Operating Conditions.
A BCI compact thermal model for this Device is available and recommended for use when modeling
thermal performance in a system.
Therefore, it is recommended to perform thermal simulations at the system level with the worst case
device power consumption.
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5.9.1 Package Thermal Characteristics
表 5-14 provides the thermal resistance characteristics for the package used on this device.
注
Power dissipation of 3.0 W and an ambient temperature of 85ºC is assumed for CBD
package.
表 5-14. Thermal Resistance Characteristics
NO.
T1
PARAMETER
RΘJC
DESCRIPTION
°C/W(1)
0.23
3.65
12.8
10.4
9.6
AIR FLOW (m/s)(2)
Junction-to-case
Junction-to-board
Junction-to-free air
N/A
N/A
0
T2
RΘJB
T3
T4
0.5
1
T5
RΘJA
Junction-to-moving air
T6
8.8
2
T7
8.3
3
T8
0.1
0
T9
0.1
0.5
1
T10
T11
T12
T13
T14
T15
T16
T17
ΨJT
Junction-to-package top
0.1
0.1
2
0.1
3
3.7
0
3.7
0.5
1
ΨJB
Junction-to-board
3.6
3.6
2
3.5
3
(1) These measurements were conducted in a JEDEC defined 2S2P system (with the exception of the Theta JC [RΘJC] measurement,
which was conducted in a JEDEC defined 1S0P system) and will change based on environment as well as application. For more
information, see these EIA/JEDEC standards:
–
–
–
–
JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Packages
(2) m/s = meters per second
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5.10 Timing Requirements and Switching Characteristics
5.10.1 Timing Parameters and Information
The timing parameter symbols used in the timing requirement and switching characteristic tables are
created in accordance with JEDEC Standard 100. To shorten the symbols, some of pin names and other
related terminologies have been abbreviated as follows:
Table 5-15. Timing Parameters
SUBSCRIPTS
SYMBOL
PARAMETER
Cycle time (period)
Delay time
c
d
dis
en
h
Disable time
Enable time
Hold time
su
START
t
Setup time
Start bit
Transition time
Valid time
v
w
Pulse duration (width)
Unknown, changing, or don't care level
Fall time
X
F
H
High
L
Low
R
Rise time
V
Valid
IV
AE
FE
LE
Z
Invalid
Active Edge
First Edge
Last Edge
High impedance
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5.10.1.1 Parameter Information
Tester Pin Electronics
Transmission Line
Data Sheet Timing Reference Point
42 Ω
3.5 nH
Output
Under
Test
Z0 = 50 Ω
(see Note)
Device Pin
(see Note)
4.0 pF
1.85 pF
NOTE: The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its transmission line effects must be
taken into account.Atransmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is
intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device pin.
pm_tstcirc_prs403
Figure 5-2. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals.
This load capacitance value does not indicate the maximum load the device is capable of driving.
5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. Vref = (VDD
I/O)/2.
Vref
pm_io_volt_prs403
Figure 5-3. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL
MAX and VOH MIN for output clocks.
Vref = VIH MIN (or VOH MIN)
Vref = VIL MAX (or VOL MAX)
pm_transvolt_prs403
Figure 5-4. Rise and Fall Transition Time Voltage Reference Levels
5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
The default SLEWCONTROL settings in each pad configuration register must be used to guaranteed
timings, unless specific instructions otherwise are given in the individual timing sub-sections of the
datasheet.
All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns).
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5.10.1.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routes. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends using the available I/O buffer information
specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS models to
attain accurate timing analysis for a given system, see the Using IBIS Models for timing Analysis
application report (literature number SPRA839). If needed, external logic hardware such as buffers may be
used to compensate any timing differences.
5.10.2 Interface Clock Specifications
5.10.2.1 Interface Clock Terminology
The interface clock is used at the system level to sequence the data and/or to control transfers accordingly
with the interface protocol.
5.10.2.2 Interface Clock Frequency
The two interface clock characteristics are:
•
•
The maximum clock frequency
The maximum operating frequency
The interface clock frequency documented in this document is the maximum clock frequency, which
corresponds to the maximum frequency programmable on this output clock. This frequency defines the
maximum limit supported by the Device IC and does not take into account any system consideration
(PCB, peripherals).
The system designer will have to consider these system considerations and the Device IC timing
characteristics as well to define properly the maximum operating frequency that corresponds to the
maximum frequency supported to transfer the data on this interface.
5.10.3 Power Supply Sequences
This section describes the power-up and power-down sequence required to ensure proper device
operation. The power supply names described in this section comprise a superset of a family of
compatible devices. Some members of this family will not include a subset of these power supplies and
their associated device modules. Refer to the 节 4.2, Pin Attributes of the 节 4, Terminal Configuration and
Functions to determine which power supplies are applicable.
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Figure 5-5 through Figure 5-9 and associated notes described the device Recommended Power
Sequencing.
T0 T1 T2 T3
T4
T5 T6
T7
T8
vdds18v, vdds_mlbp, vdds18v_ddr1
Note 4
Note 5
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_video, vdda_osc, vdda_mpu_abe
(VDDA_PLL group)
vdds_ddr1, ddr1_vref0
Note 6
vdd
Note 7
vdd_dsp
Note 8
Note 9
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_csi, vdda_pcie, vdda_usb3
(VDDA_PHY group)
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9,
vddshv10, vddshv11
Note 10
vdda33v_usb1, vdda33v_usb2
Note 11
vddshv8
xi_osc0
Note 12
resetn/porz
Note 13
Note 14
sysboot[15:0]
Valid Config
Note 15
rstoutn
SPRS960_ELCH_04
Figure 5-5. Recommended Power-Up Sequencing
(1) T0 = 0ms, T1 = 0.55ms, T2 = 1.1ms, T3 = 1.65ms, T4 = 2.2ms, T5 = 2.75ms, T6 = 3.3ms, T7 = 6.9ms, T8 ≈ 9ms. All “Tn” markers show
total elapsed time from T0.
(2) Terminology:
–
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance per Section 5.4,
Recommended Operating Conditions.
–
Ramp Up = transition time from VOFF to V OPR MIN
(3) General timing diagram items:
–
–
Grey shaded areas show valid transition times for supplies between V OPR MIN and VOFF.
Dashed horizontal lines are not valid ramp times but show alternate transition times based upon common sources and clarified in
associated note.
–
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power sequencer circuit performance.
(4) vdda_* rails should not be combined with vdds18v_* for best performance to avoid transient switching noise impacts on analog domains.
vdda_* should not ramp-up before vdds18v_* but could ramp concurrently if design ensures final operational voltage will not be reached
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until after vdds18v. The preferred sequence has vdda_* following vdds18v_* to ensure circuit components and PCB design do not cause
an inadvertent violation.
(5) vdds_ddr1 should not ramp-up before vdds18v_*. The preferred sequence has vdds_ddr1 following vdds18v_* to ensure circuit
components and PCB design do not cause an inadvertent violation. vdds_ddr1 can ramp-up before, concurrently or after vdda_*, there
are no dependencies between vdds_ddr1 and vdda_* domains.
–
For DDR2 mode of operation (1.8V), vdds_ddr1 supplies can be combined with all vdds18v_* supplies and ramped up together for
simplified PDN and power sequencing.
–
If vdds_ddr1 is combined with vdds18v_ddr1 but kept separate from vdds18v on board, then this combined 1.8V DDR supply can
come up together or after the vdds18v supply. The 1.8V DDR supply should never ramp up before the vdds18v.
(6) vdd should not ramp-up before vdds18v_* or vdds_ddr1 domains have reached VOPR MIN
.
(7) vdd_dsp could ramp concurrently with vdd if design ensures:
–
–
Final vdd_dsp operational voltage will not be reached until after vdd.
vdd_dsp maintains a voltage level at least 150mV less than vdd during entire ramp time. The preferred sequence has vdd_dsp
following vdd to ensure circuit components and PCB design do not cause an inadvertent violation.
(8) VDDA_PHY group:
–
should ramp up concurrently or after vdda33v_usb[1-2] to avoid unintended current path between vdda_pcie to vdda33v_usb1
during power sequencing.
–
could ramp up concurrently with VDDA_PLL group only if the vdda33v_usb1 power resource has an “off impedance” greater than
100Ω.
(9) vddshv[1, 3-4, 7, 9-11] domains:
–
–
If 1.8V I/O signaling is needed, then 1.8V must be sourced from common vdds18v supply and ramp up concurrently with vdds18v.
If any 3.3V I/O signaling is needed, then the desired 3.3V vddshv[1, 3-4, 7, 9-11] rails must ramp up after vdd_dsp.
(10) vdda33v_usb[1-2] domain should:
–
ramp up before or concurrently with VDDA_PHY group if USB signaling is needed and to avoid unintended current path between
vdda_pcie to vdda33v_usb[1-2] during power sequencing.
–
connect to 3.3V vddshv[1, 3-4, 7, 9-11] common supply if USB signaling is not needed since USB analog power ball also supplies
digital IO buffers that must be powered during operation.
(11) vddshv8 shows two ramp up options for 1.8V I/O or 3.3V I/O or SD Card operation:
–
–
–
If 1.8V I/O signaling is needed, then vddshv8 must ramp up after vdd and before or concurrently with 3.3V vddshv* rails.
If 3.3V I/O signaling is needed, then vddshv8 must be combined with other 3.3V vddshv* rails.
If SD Card operation is needed, then vddshv8 must be sourced from a dual voltage (3.3/1.8V) power source per SDIO specifications
and ramp up concurrently with 3.3V vddshv* rails.
(12) porz must remain asserted low until both of the following conditions are met:
–
–
Minimum of 12 *P, where P = 1 / (SYS_CLK1/610), units in ns.
All device supply rails reach stable operational levels.
(12)
(13) Setup time: sysboot[15:0] pins must be valid 2P before porz is de-asserted high.
(12)
(14) Hold time: sysboot[15:0] pins must be valid 15P after porz is de-asserted high.
(15) rstoutn will be set high after global reset, due to porz, is de-asserted following an internal 2ms delay. rstoutn is only valid after vddshv3
reaches an operational level. If used as a peripheral component reset, it should be AND gated with porz to avoid possible reset glitches
during power up.
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T0
T1
T2
T3
T4
Note 4
porz
Note 5
vddshv1, vddshv3, vddshv4,
vddshv7, vddshv9,vddshv10,
vddshv11
Note 6
V1
Note 7
vddshv8
Note 8
vdda33v_usb1, vdda33v_usb2
Note 9
Note 13
vdda_usb1, vdda_usb2, vdda_hdmi,
vdda_csi, vdda_pcie, vdda_usb3
(VDDA_PHY group)
Note 10
Note 11
vdd_dsp
vdd
Note 12
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
vdda_core_gmac, vdda_gpu,
vdda_video, vdda_osc, vdda_mpu_abe
(VDDA_PLL group)
Note 13
Note 14
vdds18v, vdds_mlbp, vdds18v_ddr1
xi_osc0
SPRS960_ELCH_05
Figure 5-6. Recommended Power-Down Sequencing
(1) T1 ≥ 100 µs; T2 = 500 µs; T3 = 1.0 ms; T4 = 1.5ms; V1 = 2.7 V. All "Tn" markers are intended to show total elapsed time, not interval
times.
(2) Terminology:
–
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,
Recommended Operating Conditions.
–
–
VOFF = OFF Voltage level is defined to be less than 0.6 V where any current draw has no impact to POH.
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
(3) General timing diagram items:
–
–
–
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
Blue dashed lines are not valid windows but show alternate ramp possibilities based on the associated note.
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit
performance.
(4) PORz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
(5) vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 V:
–
–
–
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100 µs min after PORz is asserted low.
must be in first group of supplies ramping down after PORz has been asserted low for 100 µs min.
must not exceed vdds18v by more than 2 V during ramp down, see Figure 5-7, "vdds18v versus vddshv[1, 3-4, 7, 9-11] Discharge
Relationship".
(6) vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v
supply.
(7) vddshv8 supporting SD Card:
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–
must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 V) operation as required to be compliant
to SDIO specification
–
–
must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
if SDIO operation is not needed, must be grouped and ramped down with other vddshv[1, 3-4, 7, 9-11] domains as noted above.
(8) vdda33v_usb[1-2] domains:
–
–
can start ramping down 100 µs after low assertion of PORz
can ramp down concurrently or before VDDA_PHY group
(9) VDDA_PHY domain group must ramp down concurrently or after vdda33v_usb[1-2].
(10) vdd_dsp domain can ramp down before or concurrently with vdd.
(11) vdd must ramp down after or concurrently with vdd_dsp.
(12) vdds_ddr1 domain:
–
–
should ramp down after vdd begins ramping down.
If DDR2 memory is used (requiring 1.8V supply),
–
then vdds_ddr1 can be combined with vdds18v and vdds18v_ddr1 domains and sourced from a common supply. Accordingly,
all domains can ramp down concurrently with vdds18v.
–
if vdds_ddr1 and vdds18v_ddr1 are combined but kept separate from vdds18v, then the combined 1.8V DDR supply can ramp
down before or concurrently with vdds18v.
(13) vdda_* domains:
–
–
–
can ramp down before, concurrently or after vdds_ddr1, there is no dependency between these supplies.
can ramp down before or concurrently with vdds18v.
must satisfy the vdds18v versus vdda_* discharge relationship (see Figure 5-9) if any of the vdda_* disable point is later or
discharge rate is slower than vdds18v.
(14) vdds18v domain:
–
–
should maintain VOPR MIN (VNOM -5% = 1.71 V) until all other supplies start to ramp down.
must satisfy the vdds18v versus vddshv[1, 3-4, 7, 9-11] discharge relationship (see Figure 5-7) if any of the vddshv[1, 3-4, 7, 9-11]
is operating at 3.3 V.
–
must satisfy the vdds18v versus vdds_ddr1 discharge relationship ( see Figure 5-8) if vdds_ddr1 discharge rate is slower than
vdds18v.
Figure 5-7 describes vddshv[1, 3-4, 7, 9-11] Supplies Falling Before vdds18v Supplies Delta.
vddshv1, vddshv3,
vddshv4, vddshv7,
vddshv9, vddshv10,
(2)
vddshv11, vddshv8
vdds18v
Vdelta
(Note1)
SPRS85v_ELCH_06
Figure 5-7. vdds18v versus vddshv[1, 3-4, 7, 9-11] Discharge Relationship
(1) Vdelta MAX = 2V.
(2) If vddshv8 is powered by the same supply source as the other vddshv[1, 3-4, 7, 9-11] rails.
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If vdds18v and vdds_ddr1 are disabled at the same time due to a loss of input power event or if
vdds_ddr1 discharges more slowly than vdds18v, analysis has shown no reliability impacts when the
elapsed time period beginning with vdds18v dropping below 1.0 V and ending with vdds_ddr1 dropping
below 0.6 V is less than 10 ms (Figure 5-8).
vdds18v
vdds_ddr1
V1
V2
T1
SPRS85v_ELCH_07
Figure 5-8. vdds18v and vdds_ddr1 Discharge Relationship(1)
(1) V1 > 1.0 V; V2 < 0.6 V; T1 < 10ms.
Note 1
vdds18v
vdda_*
V1
Note 2
V2
SPRS85v_ELCH_08
Figure 5-9. vdds18v and vdda_* Discharge Relationship(3)
(1) vdda_* can be ≥ vdds18v, until vdds18v drops below 1.62 V.
(2) vdds18v must be ≥ vdda_*, until vdds18v reaches 0.6 V.
(3) V1 = 1.62 V; V2 < 0.6 V.
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Figure 5-7 through Figure 5-10 and associated notes described the device Abrupt Power Down Sequence.
A ”loss of input power event” occurs when the system’s input power is unexpectedly removed. Normally,
the recommended power-down sequence should be followed and can be accomplished within 1.5-2 ms of
elapsed time. This is the typical range of elapsed time available following a loss of power event, see 节
7.3.7 for design recommendations. If sufficient elapse time is not provided, then an “abrupt” power-down
sequence can be supported without impacting POH reliability if all of the following conditions are met
(Figure 5-10).
Tdelta1
Note 4
porz
V2
vddshv[1, 3-4, 7, 9-11](5)
V3
vddshv8(7)
V1
vdda33v_usb[1-2](8)
Note 9
vdd, vdd_dsp
Note 9, Note 10
V4
vdds_ddr1, ddr1_vref0
vdda_per, vdda_ddr, vdda_debug,
Note 9, Note 11
V7
V8
vdda_core_gmac, vdda_gpu, vdda_video,
vdda_osc, vdda_mpu_abe, vdda_usb[1-3],
vdda_hdmi,vdda_csi, vdda_pcie,
V5
V6
Tdelta2
vddshv[1, 3-4, 7, 9-11](6)
vdds18v, vdds_mlbp, vdds18v_ddr1
V9
Note 12
V10
V11
xi_osc0
SPRS960_ELCH_09
Figure 5-10. Abrupt Power-Down Sequencing(1)
(1) V1 = 2.7 V; V2 = 3.3 V; V3 = 2.0 V; V4 = V5 = V6 = 0.6 V; V7 = V8 = 1.62 V; V9 = 1.3 V; V10 = 1.0 V; V11 = 0.0 V; Tdelta1 > 100 µs;
Tdelta2 < 10 ms.
(2) Terminology:
–
VOPR MIN = Minimum Operational Voltage level that ensures device functionality and specified performance in Section 5.4,
Recommended Operating Conditions.
–
–
VOFF = OFF Voltage level is defined to be less than 0.6 V, where any current draw has no impact to POH.
Ramp Down = transition time from VOPR MIN to VOFF and is slew rate independent.
(3) General timing diagram items:
–
–
Grey shaded areas show valid transition times for supplies between VOPR MIN and VOFF.
Dashed vertical lines show approximate elapse times based upon TI recommended PMIC power-down sequencer circuit
performance.
(4) PORz must be asserted low for 100 µs min to ensure SoC is set to a safe functional state before any voltage begins to ramp down.
(5) vddshv[1, 3-4, 7, 9-11] domains supplied by 3.3 V:
–
–
must remain greater than 2.7 V to enable Dual Voltage GPIO selector circuit operation for 100µs min, after PORz is asserted low.
must not exceed vdds18v voltage level by more than 2V during ramp down, until vdds18v drops below VOFF (0.6 V).
(6) vddshv[1, 3-4, 7, 9-11] domains supplied by 1.8 V must ramp down concurrently with vdds18v and be sourced from common vdds18v
supply.
(7) vddshv8 supporting SD Card:
–
–
must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
must be sourced from independent power resource that can provide dual voltage (3.3 / 1.8 V) operation as required to be compliant
to SDIO specification.
–
if SDIO operation is not needed, must be grouped with other vddshv[1, 3-4, 7, 9-11] domains.
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(8) vdda33v_usb[1-2] domains must be in first group of supplies to ramp down after PORz has been asserted low for 100 µs min.
(9) vdd_dsp, vdd, vdds_ddr1, vdda_* domains can all start to ramp down in any order after 100 µs low assertion of PORz.
(10) vdds_ddr1 domain:
–
–
can remain at VOPR MIN or a level greater than vdds18v during ramp down.
elapsed time from vdds18v dropping below 1.0 V to vdds_ddr1 dropping below 0.6 V must not exceed 10 ms.
(11) vdda_* domains:
–
–
can start to ramp down before or concurrently with vdds18v.
must not exceed vdds18v voltage level after vdds18v drops below 1.62 V until vdds18v drops below VOFF (0.6 V).
(12) vdds18v domain should maintain a minimum level of 1.62 V (VNOM – 10%) until vdd_dsp and vdd start to ramp down.
5.10.4 Clock Specifications
NOTE
For more information, see Power Reset and Clock Management / PRCM Environment /
External Clock Signal and Power Reset / PRCM Functional Description / PRCM Clock
Manager Functional Description section of the Device TRM.
NOTE
Audio Back End (ABE) module is not supported for this family of devices, but “ABE” name is
still present in some clock or DPLL names.
The device operation requires the following clocks:
•
The system clocks, SYS_CLK1 (Mandatory) and SYS_CLK2 (Optional) are the main clock sources of
the device. They supply the reference clock to the DPLLs as well as functional clock to several
modules.
The Device also embeds an internal free-running 32-kHz oscillator that is always active as long as the the
wake-up (WKUP) domain is supplied.
Figure 5-11 shows the external input clock sources and the output clocks to peripherals.
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DEVICE
rstoutn
Warm reset output.
Device reset input.
Power ON Reset.
resetn
porz
From quartz (19.2, 20 or 27 MHz)
or from CMOS square clock source (19.2, 20 or 27MHz).
xi_osc0
xo_osc0
To quartz (from oscillator output).
From quartz (range from 19.2 to 32 MHz)
or from CMOS square clock source(range from 12 to 38.4 MHz).
xi_osc1
xo_osc1
clkout1
clkout2
clkout3
To quartz (from oscillator output).
Output clkout[3:1] clocks come from:
• Either the input system clock and alternate clock (xi_osc0 or xi_osc1)
• Or a CORE clock (from CORE output)
• Or a 192-MHz clock (from PER DPLL output).
xref_clk0
xref_clk1
xref_clk2
External Reference Clock [3:0].
For Audio and other Peripherals
xref_clk3
Boot Mode Configuration
sysboot[15:0]
Figure 5-11. Clock Interface
5.10.4.1 Input Clocks / Oscillators
•
The source of the internal system clock (SYS_CLK1) could be either:
–
A CMOS clock that enters on the xi_osc0 ball (with xo_osc0 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc0 and xo_osc0.
•
The source of the internal system clock (SYS_CLK2) could be either:
–
A CMOS clock that enters on the xi_osc1 ball (with xo_osc1 left unconnected on the CMOS clock
case).
–
A crystal oscillator clock managed by xi_osc1 and xo_osc1.
SYS_CLK1 is received directly from oscillator OSC0. For more information about SYS_CLK1 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.10.4.1.1 OSC0 External Crystal
An external crystal is connected to the device pins. Figure 5-12 describes the crystal implementation.
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Device
xo_osc0
vssa_osc0
xi_osc0
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_03
Figure 5-12. OSC0 Crystal Implementation
NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-12, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc0, xo_osc0, and vssa_osc0 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-13. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-16 summarizes
the required electrical constraints.
and Table 5-20
Table 5-16. OSC0 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX UNIT
19.2, 20, 27
MHz
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
pF
pF
Cf2
ESR(Cf1,Cf2)
Crystal ESR
100
7
Ω
(1)
ESR = 30 Ω
ESR = 40 Ω
19.2 MHz, 20 MHz, 27 MHz
pF
19.2 MHz, 20 MHz
27 MHz
7
5
7
pF
pF
pF
-
ESR = 50 Ω
19.2 MHz, 20 MHz
27 MHz
ESR = 60 Ω
ESR = 80 Ω
ESR = 100 Ω
CO
Crystal shunt capacitance
Not Supported
Not Supported
19.2 MHz, 20 MHz
27 MHz
5
3
pF
-
19.2 MHz, 20 MHz
27 MHz
pF
-
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
Crystal motional capacitance
mH
fF
CM
3.42
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Table 5-16. OSC0 Crystal Electrical Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX UNIT
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
ppm
±100
tj(xiosc0)
Frequency accuracy(1), xi_osc0
Ethernet MII using derived
clock
MLB using derived clock
±50
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must consider the temperature and aging characteristics of a
based on the worst case environment and expected life expectancy of the system.
Table 5-17 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-17. Oscillator Switching Characteristics—Crystal Mode
NAME
fp
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
ms
Oscillation frequency
Start-up time
19.2, 20, 27 MHz
tsX
4
5.10.4.1.2 OSC0 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK1 clock input to the system. The external connections to support this are shown in Figure 5-14.
The xi_osc0 pin is connected to the 1.8-V LVCMOS-Compatible clock source. The xi_osc0 pin is left
unconnected. The vssa_osc0 pin is connected to board ground (VSS).
Device
xo_osc0
vssa_osc0
xi_osc0
NC
SPRS906_CLK_04
Figure 5-14. 1.8-V LVCMOS-Compatible Clock Input
Table 5-18 summarizes the OSC0 input clock electrical characteristics.
Table 5-18. OSC0 Input Clock Electrical Characteristics—Bypass Mode
NAME
DESCRIPTION
MIN
TYP
19.2, 20, 27
2.384
MAX
UNIT
MHz
pF
f
Frequency
CIN
IIN
Input capacitance
2.184
4
2.584
10
Input current (3.3V mode)
6
µA
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Table 5-19 details the OSC0 input clock timing requirements.
Table 5-19. OSC0 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
1 /
tc(xiosc0)
CK0
Frequency, xi_osc0
19.2, 20, 27
MHz
0.55 ×
tc(xiosc0)
0.45
tc(xiosc0)
×
CK1
tw(xiosc0) Pulse duration, xi_osc0 low or high
tj(xiosc0) Period jitter(1), xi_osc0
ns
ns
0.01 ×
tc(xiosc0)
tR(xiosc0) Rise time, xi_osc0
tF(xiosc0) Fall time, xi_osc0
5
5
ns
ns
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc0) Frequency accuracy(2), xi_osc0
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Period jitter is meant here as follows:
– The maximum value is the difference between the longest measured clock period and the expected clock period
– The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
CK0
CK1
CK1
xi_osc0
SPRS906_CLK_05
Figure 5-15. xi_osc0 Input Clock
5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
SYS_CLK2 is received directly from oscillator OSC1. For more information about SYS_CLK2 see Device
TRM, Chapter: Power, Reset, and Clock Management.
5.10.4.1.3.1 OSC1 External Crystal
An external crystal is connected to the device pins. Figure 5-16 describes the crystal implementation.
Device
xo_osc1
xi_osc1
vssa_osc1
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_CLK_06
Figure 5-16. Crystal Implementation
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NOTE
The load capacitors, Cf1 and Cf2 in Figure 5-16, should be chosen such that the below
equation is satisfied. CL in the equation is the load specified by the crystal manufacturer. All
discrete components used to implement the oscillator circuit should be placed as close as
possible to the associated oscillator xi_osc1, xo_osc1, and vssa_osc1 pins.
Cf1Cf2
C
= (Cf1+Cf2)
L
Figure 5-17. Load Capacitance Equation
The crystal must be in the fundamental mode of operation and parallel resonant. Table 5-20 summarizes
the required electrical constraints.
Table 5-20. OSC1 Crystal Electrical Characteristics
NAME
fp
DESCRIPTION
Parallel resonance crystal frequency
MIN
TYP
MAX
UNIT
MHz
pF
pF
Ω
Range from 19.2 to 32
Cf1
Cf1 load capacitance for crystal parallel resonance with Cf1 = Cf2
Cf2 load capacitance for crystal parallel resonance with Cf1 = Cf2
12
12
24
24
100
7
Cf2
ESR(Cf1,Cf2) Crystal ESR
ESR = 30 Ω 19.2 MHz ≤ fp ≤ 32 MHz
ESR = 40 Ω 19.2 MHz ≤ fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 25 MHz
pF
pF
pF
pF
-
5
7
ESR = 50 Ω 25 MHz < fp ≤ 27 MHz
27 MHz < fp ≤ 32 MHz
5
Not Supported
Not Supported
Not Supported
19.2 MHz ≤ fp ≤ 23 MHz
7
5
pF
pF
-
CO
Crystal shunt capacitance
ESR = 60 Ω 23 MHz < fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 23 MHz
5
3
pF
pF
-
ESR = 80 Ω 23 MHz ≤ fp ≤ 25 MHz
25 MHz < fp ≤ 32 MHz
19.2 MHz ≤ fp ≤ 20 MHz
ESR = 100 Ω
3
pF
-
20 MHz < fp ≤ 32 MHz
Not Supported
10.16
LM
Crystal motional inductance for fp = 20 MHz
mH
fF
CM
Crystal motional capacitance
3.42
Ethernet and MLB not used
±200
±50
Ethernet RGMII and RMII
using derived clock
tj(xiosc1)
Frequency accuracy(1), xi_osc1
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Crystal characteristics should account for tolerance+stability+aging.
When selecting a crystal, the system design must take into account the temperature and aging
characteristics of a crystal versus the user environment and expected lifetime of the system.
Table 5-21 details the switching characteristics of the oscillator and the requirements of the input clock.
Table 5-21. Oscillator Switching Characteristics—Crystal Mode
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
fp
Oscillation frequency
Range from 19.2 to 32
MHz
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Table 5-21. Oscillator Switching Characteristics—Crystal Mode (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
tsX
Start-up time
4
ms
5.10.4.1.3.2 OSC1 Input Clock
A 1.8-V LVCMOS-Compatible Clock Input can be used instead of the internal oscillator to provide the
SYS_CLK2 clock input to the system. The external connections to support this are shown in, Figure 5-18.
The xi_osc1 pin is connected to the 1.8-V LVCMOS-Compatible clock sources. The xo_osc1 pin is left
unconnected. The vssa_osc1 pin is connected to board ground (vss).
Device
xo_osc1
vssa_osc1
xi_osc1
NC
SPRS906_CLK_07
Figure 5-18. 1.8-V LVCMOS-Compatible Clock Input
Table 5-22 summarizes the OSC1 input clock electrical characteristics.
Table 5-22. OSC1 Input Clock Electrical Characteristics—Bypass Mode
NAME
f
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
pF
Frequency
Range from 12 to 38.4
CIN
IIN
Input capacitance
2.819
3.019
6
See(2)
3.219
10
Input current (3.3V mode)
Start-up time(1)
4
µA
tsX
ms
(1) To switch from bypass mode to crystal or from crystal mode to bypass mode, there is a waiting time about 100 μs; however, if the chip
comes from bypass mode to crystal mode the crystal will start-up after time mentioned in Table 5-21, tsX parameter.
(2) Before the processor boots up and the oscillator is set to bypass mode, there is a waiting time when the internal oscillator is in
application mode and receives a wave. The switching time in this case is about 100 μs.
Table 5-23 details the OSC1 input clock timing requirements.
Table 5-23. OSC1 Input Clock Timing Requirements
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
1 /
tc(xiosc1)
CK0
Frequency, xi_osc1
Range from 12 to 38.4
MHz
0.45 ×
tc(xiosc1)
0.55 ×
tc(xiosc1)
CK1
tw(xiosc1) Pulse duration, xi_osc1 low or high
tj(xiosc1) Period jitter(1), xi_osc1
ns
ns
0.01 ×
tc(xiosc1)
(3)
tR(xiosc1) Rise time, xi_osc1
tF(xiosc1) Fall time, xi_osc1
5
5
ns
ns
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Table 5-23. OSC1 Input Clock Timing Requirements (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
Ethernet and MLB not used
±200
Ethernet RGMII and RMII
using derived clock
±50
tj(xiosc1) Frequency accuracy(2), xi_osc1
ppm
Ethernet MII using derived
clock
±100
±50
MLB using derived clock
(1) Period jitter is meant here as follows:
–
–
The maximum value is the difference between the longest measured clock period and the expected clock period
The minimum value is the difference between the shortest measured clock period and the expected clock period
(2) Crystal characteristics should account for tolerance+stability+aging.
(3) The Period jitter requirement for osc1 can be relaxed to 0.02 × tc(xiosc1) under the following constraints:
a.The osc1/SYS_CLK2 clock bypasses all device PLLs
b.The osc1/SYS_CLK2 clock is only used to source the DSS pixel clock outputs
CK0
CK1
CK1
xi_osc1
SPRS906_CLK_08
Figure 5-19. xi_osc1 Input Clock
5.10.4.1.4 RC On-die Oscillator Clock
NOTE
The OSC_32K_CLK clock, provided by the On-die 32K RC oscillator, inside of the SoC, is
not accurate 32kHz clock.
The frequency may significantly vary with temperature and silicon characteristics.
For more information about OSC_32K_CLK see the Device TRM, Chapter: Power, Reset, and Clock
Management.
5.10.4.2 Output Clocks
The device provides three output clocks. Summary of these output clocks are as follows:
•
•
•
clkout1 - Device Clock output 1. Can be used as a system clock for other devices. The source of the
clkout1 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
clkout2 - Device Clock output 2. Can be used as a system clock for other devices. The source of the
clkout2 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
clkout3 - Device Clock output 3. Can be used as a system clock for other devices. The source of the
clkout3 could be either:
–
–
–
The input system clock and alternate clock (xi_osc0 or xi_osc1)
CORE clock (from CORE output)
192-MHz clock (from PER DPLL output)
For more information about Output Clocks see Device TRM, Chapter: Power, Reset, and Clock
Management.
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5.10.4.3 DPLLs, DLLs
NOTE
For more information, see:
•
Power, Reset, and Clock Management / Clock Management Functional / Internal Clock
Sources / Generators / Generic DPLL Overview Section
and
•
Display Subsystem / Display Subsystem Overview section of the Device TRM.
To generate high-frequency clocks, the device supports multiple on-chip DPLLs controlled directly by the
PRCM module. They are of two types: type A and type B DPLLs.
•
They have their own independent power domain (each one embeds its own switch and can be
controlled as an independent functional power domain)
•
They are fed with ALWAYS ON system clock, with independent control per DPLL.
The different DPLLs managed by the PRCM are listed below:
•
•
•
•
DPLL_MPU: It supplies the MPU subsystem clocking internally.
DPLL_IVA: It feeds the IVA subsystem clocking.
DPLL_CORE: It supplies all interface clocks and also few module functional clocks.
DPLL_PER: It supplies several clock sources: a 192-MHz clock for the display functional clock, a
96-MHz functional clock to subsystems and peripherals.
•
•
•
•
•
•
DPLL_ABE: It provides clocks to various modules within the device.
DPLL_USB: It provides 960M clock for USB modules (USB1/2/3/4).
DPLL_GMAC: It supplies several clocks for the Gigabit Ethernet Switch (GMAC_SW).
DPLL_DSP: It feeds the DSP Subsystem clocking.
DPLL_GPU: It supplies clock for the GPU Subsystem.
DPLL_DDR: It generates clocks for the two External Memory Interface (EMIF) controllers and their
associated EMIF PHYs.
•
•
DPLL_PCIE_REF: It provides reference clock for the APLL_PCIE in PCIE Subsystem.
APLL_PCIE: It feeds clocks for the device Peripheral Component Interconnect Express (PCIe)
controllers.
NOTE
The following DPLLs are controlled by the clock manager located in the always-on Core
power domain (CM_CORE_AON):
•
DPLL_MPU, DPLL_IVA, DPLL_CORE, DPLL_ABE, DPLL_DDR, DPLL_GMAC,
DPLL_PCIE_REF, DPLL_PER, DPLL_USB, DPLL_DSP, DPLL_GPU, APLL_PCIE_REF.
For more information on CM_CORE_AON and CM_CORE or PRCM DPLLs, see the Power, Reset, and
Clock Management (PRCM) chapter of the Device TRM.
The following DPLLs are not managed by the PRCM:
•
•
•
•
DPLL_VIDEO1; (It is controlled from DSS)
DPLL_HDMI; (It is controlled from DSS)
DPLL_DEBUG; (It is controlled from DEBUGSS)
DPLL_USB_OTG_SS; (It is controlled from OCP2SCP1)
NOTE
For more information for not controlled from PRCM DPLL’s see the related chapters in TRM.
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5.10.4.3.1 DPLL Characteristics
The DPLL has three relevant input clocks. One of them is the reference clock (CLKINP) used to generated
the synthesized clock but can also be used as the bypass clock whenever the DPLL enters a bypass
mode. It is therefore mandatory. The second one is a fast bypass clock (CLKINPULOW) used when
selected as the bypass clock and is optional. The third clock (CLKINPHIF) is explained in the next
paragraph.
The DPLL has three output clocks (namely CLKOUT, CLKOUTX2, and CLKOUTHIF). CLKOUT and
CLKOUTX2 run at the bypass frequency whenever the DPLL enters a bypass mode. Both of them are
generated from the lock frequency divided by a post-divider (namely M2 post-divider). The third clock,
CLKOUTHIF, has no automatic bypass capability. It is an output of a post-divider (M3 post-divider) with
the input clock selectable between the internal lock clock (Fdpll) and CLKINPHIF input of the PLL through
an asynchronous multplexing.
For more information, see the Power Reset Controller Management chapter of the Device TRM.
Table 5-24 summarizes DPLL type described in Section 5.10.4.3, DPLLs, DLLs Specifications
introduction.
Table 5-24. DPLL Control Type
DPLL NAME
DPLL_ABE
TYPE
CONTROLLED BY PRCM
(1)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-26 (Type B)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-26 (Type B)
Table 5-26 (Type B)
Table 5-26 (Type B)
Table 5-25 (Type A)
Table 5-25 (Type A)
Table 5-25 (Type A)
Yes
(1)
DPLL_CORE
Yes
(2)
DPLL_DEBUGSS
DPLL_DSP
No
(1)
Yes
(1)
DPLL_GMAC
Yes
(2)
DPLL_HDMI
No
(1)
DPLL_IVA
Yes
(1)
DPLL_MPU
Yes
(1)
DPLL_PER
Yes
(1)
APLL_PCIE
Yes
(1)
DPLL_PCIE_REF
DPLL_USB
Yes
(1)
Yes
(2)
DPLL_USB_OTG_SS
DPLL_VIDEO1
No
(2)
No
(1)
DPLL_DDR
Yes
(1)
DPLL_GPU
Yes
(1) DPLL is in the always-on domain.
(2) DPLL is not controlled by the PRCM.
Table 5-25 and Table 5-26 summarize the DPLL characteristics and assume testing over recommended
operating conditions.
Table 5-25. DPLL Type A Characteristics
NAME
finput
DESCRIPTION
MIN
0.032
0.15
10
TYP
MAX
52
UNIT
MHz
MHz
MHz
COMMENTS
CLKINP input frequency
Internal reference frequency
CLKINPHIF input frequency
FINP
finternal
52
REFCLK
FINPHIF
fCLKINPHIF
1400
Bypass mode: fCLKOUT
=
fCLKINPULOW
CLKINPULOW input frequency
CLKOUT output frequency
0.001
600
MHz
MHz
fCLKINPULOW / (M1 + 1) if
ulowclken = 1
(6)
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)
(2)
fCLKOUT
20
1800
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Table 5-25. DPLL Type A Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
MHz
MHz
MHz
COMMENTS
2 × [M / (N + 1)] × FINP × [1 /
M2] (in locked condition)
(1)
(2)
fCLKOUTx2
CLKOUTx2 output frequency
40
2200
(3)
(4)
20
1400
2200
FINPHIF / M3 if clkinphifsel = 1
fCLKOUTHIF
CLKOUTHIF output frequency
2 × [M / (N + 1)] × FINP × [1 /
M3] if clkinphifsel = 0
(3)
(4)
40
DCOCLKLDO output
frequency
2 × [M / (N + 1)] × FINP (in
locked condition)
fCLKDCOLDO
tlock
40
2800
MHz
µs
6 + 350 ×
REFCLK
Frequency lock time
Phase lock time
6 + 500 ×
REFCLK
plock
µs
Relock time—Frequency
lock(5) (LP relock time from
bypass)
Relock time—Phase lock(5)
(LP relock time from bypass)
6 + 70 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
trelock-L
prelock-L
trelock-F
prelock-F
µs
µs
µs
µs
6 + 120 ×
REFCLK
DPLL in LP relock time:
lowcurrstdby = 1
Relock time—Frequency
lock(5) (fast relock time from
bypass)
Relock time—Phase lock(5)
(fast relock time from bypass)
3.55 + 70 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
3.55 + 120 ×
REFCLK
DPLL in fast relock time:
lowcurrstdby = 0
(1) The minimum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
For M2 > 1, the minimum frequency on these clocks will further scale down by factor of M2.
(2) The maximum frequencies on CLKOUT and CLKOUTX2 are assuming M2 = 1.
(3) The minimum frequency on CLKOUTHIF is assuming M3 = 1. For M3 > 1, the minimum frequency on this clock will further scale down
by factor of M3.
(4) The maximum frequency on CLKOUTHIF is assuming M3 = 1.
(5) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(6) Bypass mode: fCLKOUT = FINP if ulowclken = 0. For more information, see the Device TRM.
Table 5-26. DPLL Type B Characteristics
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
finput
CLKINP input clock frequency
0.62
60
MHz
FINP
REFCLK internal reference
clock frequency
finternal
0.62
2.5
MHz
[1 / (N + 1)] × FINP
Bypass mode: fCLKOUT
=
CLKINPULOW bypass input
clock frequency
fCLKINPULOW
0.001
600
MHz
fCLKINPULOW / (M1 + 1) If
(4)
ulowclken = 1
CLKOUTLDO output clock
frequency
M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
fCLKLDOOUT
fCLKOUT
fCLKDCOLDO
20
2500
MHz
MHz
CLKOUT output clock
frequency
[M / (N + 1)] × FINP × [1 / M2]
(in locked condition)
(1)(5)
(2)(5)
20
1450
(5)
(5)
750
1500
MHz
MHz
Internal oscillator (DCO) output
clock frequency
[M / (N + 1)] × FINP (in locked
condition)
(5)
(5)
1250
2500
CLKOUTLDO period jitter
CLKOUT period jitter
The period jitter at the output
clocks is ± 2.5% peak to peak
tJ
–2.5%
2.5%
CLKDCOLDO period jitter
350 ×
REFCLKs
tlock
plock
Frequency lock time
µs
µs
µs
500 ×
REFCLKs
Phase lock time
Relock time—Frequency lock(3)
(LP relock time from bypass)
9 + 30 ×
REFCLKs
trelock-L
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Table 5-26. DPLL Type B Characteristics (continued)
NAME
DESCRIPTION
MIN
TYP
MAX
UNIT
COMMENTS
Relock time—Phase lock(3) (LP
relock time from bypass)
9 + 125 ×
REFCLKs
prelock-L
µs
(1) The minimum frequency on CLKOUT is assuming M2 = 1.
For M2 > 1, the minimum frequency on this clock will further scale down by factor of M2.
(2) The maximum frequency on CLKOUT is assuming M2 = 1.
(3) Relock time assumes typical operating conditions, 10°C maximum temperature drift.
(4) Bypass mode: fCLKOUT = FINP if ULOWCLKEN = 0. For more information, see the Device TRM.
(5) For output clocks, there are two frequency ranges according to the SELFREQDCO setting. For more information, see the Device TRM.
5.10.4.3.2 DLL Characteristics
Table 5-27 summarizes the DLL characteristics and assumes testing over recommended operating
conditions.
Table 5-27. DLL Characteristics
NAME
finput
DESCRIPTION
Input clock frequency (EMIF_DLL_FCLK)
MIN
TYP
MAX
266
50k
UNIT
MHz
tlock
Lock time
cycles
cycles
trelock
Relock time (a change of the DLL frequency implies that DLL must relock)
50k
5.10.4.3.3 DPLL and DLL Noise Isolation
NOTE
For more information on DPLL and DLL decoupling capacitor requirements, see the External
Capacitors / Voltage Decoupling Capacitors / I/O and Analog Voltage Decoupling / VDDA
Power Domain section.
5.10.5 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic
manner. Monotonic transitions are more easily guaranteed with faster switching signals. Slower input
transitions are more susceptible to glitches due to noise and special care should be taken for slow input
clocks.
5.10.6 Peripherals
5.10.6.1 Timing Test Conditions
All timing requirements and switching characteristics are valid over the recommended operating conditions
unless otherwise specified.
5.10.6.2 Virtual and Manual I/O Timing Modes
Some of the timings described in the following sections require the use of Virtual or Manual I/O Timing
Modes. 表 5-28 provides a summary of the Virtual and Manual I/O Timing Modes across all device
interfaces. The individual interface timing sections found later in this document provide the full description
of each applicable Virtual and Manual I/O Timing Mode. Refer to the "Pad Configuration" section of the
TRM for the procedure on implementing the Virtual and Manual Timing Modes in a system.
表 5-28. Modes Summary
Virtual or Manual IO Mode Name
DPI Video Output
Data Manual Timing Mode
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表 5-28. Modes Summary (continued)
Virtual or Manual IO Mode Name
No Virtual or Manual IO Timing Mode Required
DSS_VIRTUAL1
Data Manual Timing Mode
DPI3 Video Output Default Timings - Rising-edge Clock Reference
DPI3 Video Output Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET1 Alternate Timings
VOUT2_IOSET1_MANUAL1
VOUT2_IOSET1_MANUAL2
DPI2 Video Output IOSET1 Default Timings - Rising-edge Clock Reference
DPI2 Video Output IOSET1 Default Timings - Falling-edge Clock Reference
DPI2 Video Output IOSET1 MANUAL4 Timings
VOUT2_IOSET1_MANUAL3
VOUT2_IOSET1_MANUAL4
VOUT2_IOSET1_MANUAL5
DPI2 Video Output IOSET1 MANUAL5 Timings
VOUT3_MANUAL1
DPI3 Video Output Alternate Timings
VOUT3_MANUAL4
DPI3 Video Output MANUAL4 Timings
VOUT3_MANUAL5
DPI3 Video Output MANUAL5 Timings
GPMC
No Virtual or Manual IO Timing Mode Required
GPMC_VIRTUAL1
GPMC Asynchronous Mode Timings and Synchronous Mode - Default Timings
GPMC Synchronous Mode - Alternate Timings
McASP
No Virtual or Manual IO Timing Mode Required
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP2_VIRTUAL1_SYNC_RX_80M
MCASP2_VIRTUAL2_ASYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL4_ASYNC_RX_80M
No Virtual or Manual IO Timing Mode Required
MCASP3_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP4_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP5_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP6_VIRTUAL1_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP7_VIRTUAL2_SYNC_RX
No Virtual or Manual IO Timing Mode Required
MCASP8_VIRTUAL1_SYNC_RX
eMMC/SD/SDIO
McASP1 Asynchronous and Synchronous Transmit Timings
See 表 5-72
See 表 5-72
McASP2 Asynchronous and Synchronous Transmit Timings
See 表 5-73
See 表 5-73
See 表 5-73
See 表 5-73
McASP3 Synchronous Transmit Timings
See 表 5-74
McASP4 Synchronous Transmit Timings
See 表 5-75
McASP5 Synchronous Transmit Timings
See 表 5-76
McASP6 Synchronous Transmit Timings
See 表 5-77
McASP7 Synchronous Transmit Timings
See 表 5-78
McASP8 Synchronous Transmit Timings
See 表 5-79
No Virtual or Manual IO Timing Mode Required
MMC1 DS (Pad Loopback), HS (Internal Loopback and Pad Loopback), SDR12
(Internal Loopback and Pad Loopback), and SDR25 Timings (Internal Loopback and
Pad Loopback) Timings
MMC1_VIRTUAL1
MMC1 SDR50 (Pad Loopback) Timings
MMC1_VIRTUAL4
MMC1 DS (Internal Loopback) Timings
MMC1_VIRTUAL5
MMC1 SDR50 (Internal Loopback) Timings
MMC1 DDR50 (Internal Loopback) Timings
MMC1 DDR50 (Pad Loopback) Timings
MMC1_VIRTUAL6
MMC1_MANUAL1
MMC1_MANUAL2
MMC1 SDR104 Timings
No Virtual or Manual IO Timing Mode Required
MMC2_VIRTUAL2
MMC2 Standard (Pad Loopback), High Speed (Pad Loopback) Timings
MMC2 Standard (Internal Loopback), High Speed (Internal Loopback) Timings
MMC2 DDR (Pad Loopback) Timings
MMC2_MANUAL1
MMC2_MANUAL2
MMC2 DDR (Internal Loopback Manual) Timings
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表 5-28. Modes Summary (continued)
Virtual or Manual IO Mode Name
MMC2_MANUAL3
Data Manual Timing Mode
MMC2 HS200 Timings
No Virtual or Manual IO Timing Mode Required
MMC3_MANUAL1
MMC3 DS, SDR12, HS, SDR25 Timings
MMC3 SDR50 Timings
No Virtual or Manual IO Timing Mode Required
QSPI
MMC4 DS, SDR12, HS, SDR25 Timings
No Virtual or Manual IO Timing Mode Required
QSPI1_MANUAL1
QSPI Mode 3 Timings
QSPI Mode 0 Timings
GMAC
No Virtual or Manual IO Timing Mode Required
GMAC_RGMII0_MANUAL1
GMAC_RGMII1_MANUAL1
GMAC_RMII0_MANUAL1
GMAC_RMII1_MANUAL1
VIP
GMAC MII0/1 Timings
GMAC RGMII0 with Transmit Clock Internal Delay Enabled
GMAC RGMII1 with Transmit Clock Internal Delay Enabled
GMAC RMII0 Timings
GMAC RMII1 Timings
VIP_MANUAL3
VIN2A (IOSET4/5/6) Rise-Edge Capture Mode Timings
VIN2B (IOSET7/8/9) Rise-Edge Capture Mode Timings
VIN2A (IOSET4/5/6) Fall-Edge Capture Mode Timings
VIN2B (IOSET7/8/9) Fall-Edge Capture Mode Timings
VIP_MANUAL4
VIP_MANUAL5
VIP_MANUAL6
VIP_MANUAL7
VIN1A (IOSET2) and VIN2B (IOSET1/10) Rise-Edge Capture Mode Timings
VIN1B (IOSET6/7) Rise-Edge Capture Mode Timings
VIP_MANUAL9
VIP_MANUAL10
VIN2B (IOSET2/11) Rise-Edge Capture Mode Timings
VIN2B (IOSET2/11) Fall-Edge Capture Mode Timings
VIP_MANUAL11
VIP_MANUAL12
VIN1A (IOSET2) and VIN2B (IOSET1/10) Fall-Edge Capture Mode Timings
VIN1B (IOSET6/7) Fall-Edge Capture Mode Timings
VIP_MANUAL14
VIP_MANUAL15
VIN1A (IOSET8/9/10) Rise-Edge Capture Mode Timings
VIN1A (IOSET8/9/10) Fall-Edge Capture Mode Timings
VIP_MANUAL16
HDMI, EMIF, Timers, I2C, UART, McSPI, USB, PCIe, DCAN, GPIO, PWM, JTAG, TPIU, SDMA, INTC
No Virtual or Manual IO Timing Mode Required
All Modes
5.10.6.3 VIP
The Device includes 1 Video Input Port (VIP).
表 5-29, 图 5-20 and 图 5-21 present timings and switching characteristics of the VIP.
CAUTION
The I/O timings provided in this section are valid only for VIN1 and VIN2 if
signals within a single IOSET are used. The IOSETs are defined in 表 5-30.
表 5-29. Timing Requirements for VIP (3)(4)(5)
NO.
V1
PARAMETER
tc(CLK)
DESCRIPTION
MIN
6.06 (2)
MAX
UNIT
ns
Cycle time, vinx_clki (3) (5)
Pulse duration, vinx_clki high (3) (5)
V2
tw(CLKH)
0.45 × P
ns
(2)
V3
V4
tw(CLKL)
Pulse duration, vinx_clki low (3) (5)
0.45 × P
ns
ns
(2)
tsu(CTL/DATA-CLK)
Input setup time, Control (vinx_dei, vinx_vsynci, vinx_fldi,
3.11 (2)
vinx_hsynci) and Data (vinx_dn) valid to vinx_clki transition (3) (4) (5)
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表 5-29. Timing Requirements for VIP (3)(4)(5) (continued)
NO.
PARAMETER
th(CLK-CTL/DATA)
DESCRIPTION
MIN
-0.05 (2)
MAX
UNIT
V6
Input hold time, Control (vinx_dei, vinx_vsynci, vinx_fldi, vinx_hsynci)
and Data (vinx_dn) valid from vinx_clki transition (3) (4) (5)
ns
(1) For maximum frequency of 165 MHz.
(2) P = vinx_clki period.
(3) x in vinx = 1a, 1b, 2a, 2b.
(4) n in dn = 0 to 7 when x = 1b, 2b.
n = 0 to 23 when x = 1a, 2a.
(5) i in clki, dei, vsynci, hsynci and fldi = 0 or 1.
V3
V2
V1
vinx_clki
SPRS906_TIMING_VIP_01
图 5-20. Video Input Ports clock signal
vinx_clki
(positive-edge clocking)
vinx_clki
(negative-edge clocking)
V5
V4
vinx_d[23:0]/sig
SPRS8xx_VIP_02
图 5-21. Video Input Ports timings
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In 表 5-30 and 表 5-31 are presented the specific groupings of signals (IOSET) for use with vin1 and vin2.
表 5-30. VIN1 IOSETs
SIGNALS
IOSET2
IOSET6 (1)
BALL MUX
IOSET7 (1)
BALL MUX
IOSET8
IOSET9
IOSET10
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin1a
vin1a_clk0
vin1a_hsync0
vin1a_vsync0
vin1a_fld0
vin1a_de0
vin1a_d0
G3
K4
H1
L3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Y5
9
9
9
J24
B14
D14
C16
C17
J25
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
J24
B14
D14
C16
C17
B23
B22
A23
A22
B21
A21
D19
E19
F16
E16
E17
A19
B18
B16
B17
A18
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
AA4
AB1
J2
Y6
AA1
Y3
9
9
9
9
9
9
9
9
9
F1
E2
E1
C1
D1
D2
B1
B2
C2
D3
A2
B3
C3
C4
A3
B4
M1
M2
L2
vin1a_d1
B22
A23
A22
B21
A21
D19
E19
F16
E16
E17
A19
B18
B16
B17
A18
vin1a_d2
W2
AA3
AA2
Y4
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
Y1
vin1a_d7
Y2
vin1a_d8
vin1a_d9
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
vin1a_d14
vin1a_d15
vin1a_d16
vin1a_d17
vin1a_d18
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
L1
K3
K2
J1
K1
160
Specifications
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表 5-30. VIN1 IOSETs (continued)
SIGNALS
IOSET2
BALL
IOSET6 (1)
IOSET7 (1)
IOSET8
IOSET9
BALL MUX
IOSET10
BALL MUX
MUX
BALL
MUX
BALL
MUX
vin1b
BALL
MUX
vin1b_clk1
vin1b_hsync1
vin1b_vsync1
vin1b_fld1
vin1b_de1
vin1b_d0
L5
P3
R2
N4
P4
L6
5
5
5
5
5
5
5
5
5
5
5
5
5
J2
K4
H1
G1
L3
M1
M2
L2
L1
K3
K2
J1
6
6
6
6
6
6
6
6
6
6
6
6
6
vin1b_d1
N5
N6
T4
T5
N2
P2
N1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
vin1b_d6
vin1b_d7
K1
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad
Configuration Registers.
表 5-31. VIN2 IOSETs
SIGNALS
IOSET1
BALL MUX
IOSET2
BALL MUX
IOSET4
IOSET5
BALL MUX
vin2a
IOSET6
IOSET7 (1)
BALL MUX
IOSET8 (1)
BALL MUX
IOSET9 (1)
BALL MUX
BALL
MUX
BALL
MUX
vin2a_clk0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
vin2a_de0
vin2a_d0
D8
E8
B8
C7
B7
C8
B9
A7
A9
A8
0
0
0
0
0
0
0
0
0
0
D8
E8
B8
B7
0
0
0
1
L5
P3
R2
N4
P4
L6
N5
N6
T4
T5
4
4
4
4
4
4
4
4
4
4
C8
B9
A7
A9
A8
0
0
0
0
0
vin2a_d1
vin2a_d2
vin2a_d3
vin2a_d4
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IOSET9 (1)
表 5-31. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
IOSET5
IOSET6
IOSET7 (1)
IOSET8 (1)
BALL
MUX
BALL
MUX
BALL
MUX
0
BALL
MUX
0
BALL
MUX
BALL
MUX
BALL
MUX
BALL
MUX
vin2a_d5
vin2a_d6
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
A11
F10
A10
B10
E10
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
N2
P2
N1
P1
N3
R1
P5
4
4
4
4
4
4
4
0
0
vin2a_d7
0
0
vin2a_d8
0
0
vin2a_d9
0
0
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
vin2b
vin2b_clk1
vin2b_hsync1
vin2b_vsync1
vin2b_fld1
vin2b_de1
vin2b_d0
L4
B6
A6
H6
H2
A4
E7
D6
C5
B5
D7
C6
6
6
6
6
6
6
6
6
6
6
6
6
H6
B6
A6
4
6
6
C7
E8
B8
2
3
3
C7
E8
B8
B7
2
3
3
2
AB1
Y5
4
4
4
Y6
H2
A4
E7
D6
C5
B5
D7
C6
6
6
6
6
6
6
6
6
B7
3
2
2
2
2
2
2
2
AA4
AA1
Y3
4
4
4
4
4
4
4
4
D13
C13
E13
B13
F11
E11
A13
D13
C13
E13
B13
F11
E11
A13
2
2
2
2
2
2
2
vin2b_d1
vin2b_d2
W2
AA3
AA2
Y4
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
Y1
162
Specifications
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表 5-31. VIN2 IOSETs (continued)
SIGNALS
IOSET1
IOSET2
IOSET4
BALL MUX
IOSET5
BALL MUX
IOSET6
BALL MUX
IOSET7 (1)
IOSET8 (1)
IOSET9 (1)
BALL
A5
MUX
BALL
A5
MUX
BALL
A12
MUX
BALL
A12
MUX
BALL
Y2
MUX
vin2b_d7
6
6
2
2
4
(1) The IOSET under this column is only applicable for pins with alternate functionality which allows either VIN1 or VIN2 signals to be mapped to the pins. These alternate functions are
controlled via CTRL_CORE_VIP_MUX_SELECT register. For more information on how to use these options, please refer to Device TRM, Chapter Control Module, Section Pad
Configuration Registers.
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the
Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module
Chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-32 Manual Functions Mapping for VIN2A (IOSET4/5/6) for a definition of the Manual modes.
表 5-32 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-32. Manual Functions Mapping for VIN2A (IOSET4/5/6)
BALL
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
0
1
4
P5
RMII_MHZ_50_CL
K
2616
1379
2798
1294
CFG_RMII_MHZ_50_CLK_IN
-
-
vin2a_d11
L6
L5
mdio_d
2558
998
1105
463
2790
1029
2896
2844
2856
2804
2801
2807
2835
2831
2764
2843
2816
954
431
CFG_MDIO_D_IN
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
vin2a_d0
vin2a_clk0
vin2a_d5
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
N2
P2
N4
N3
P1
N1
T4
T5
R1
R2
P3
2658
2658
2638
2641
2641
2644
2638
2672
2604
2683
2563
862
651
1628
1123
1737
1676
1828
1454
1663
1442
1598
1483
1518
888
vin2a_d6
vin2a_fld0
vin2a_d9
1702
1652
1790
1396
1640
1417
1600
1344
vin2a_d8
vin2a_d7
vin2a_d3
vin2a_d4
vin2a_d10
vin2a_vsync0
vin2a_hsync0
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表 5-32. Manual Functions Mapping for VIN2A (IOSET4/5/6) (continued)
BALL
BALL NAME
VIP_MANUAL3
VIP_MANUAL5
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
0
1
4
P4
N5
rgmii0_txd3
uart3_rxd
uart3_txd
vin2a_clk0
vin2a_d0
2717
2445
2650
0
1461
1145
1197
0
2913
2743
2842
0
1310
923
1080
0
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
CFG_VIN2A_CLK0_IN
CFG_VIN2A_D0_IN
CFG_VIN2A_D1_IN
CFG_VIN2A_D10_IN
CFG_VIN2A_D11_IN
CFG_VIN2A_D12_IN
CFG_VIN2A_D13_IN
CFG_VIN2A_D14_IN
CFG_VIN2A_D15_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D2_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_D3_IN
CFG_VIN2A_D4_IN
CFG_VIN2A_D5_IN
CFG_VIN2A_D6_IN
CFG_VIN2A_D7_IN
CFG_VIN2A_D8_IN
CFG_VIN2A_D9_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
CFG_VIN2A_VSYNC0_IN
-
-
vin2a_de0
-
-
vin2a_d1
N6
-
-
vin2a_d2
D8
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
C8
1812
1701
1720
1622
1350
1613
1149
1530
1512
1293
2140
2041
1675
1972
1957
2011
1962
1457
1535
1676
1513
1616
1286
1544
1732
1461
1877
1566
102
439
215
0
1936
2229
2031
1702
1819
1476
1701
2021
2044
1839
2494
1699
1736
2412
2391
2446
2395
1943
1601
2052
1571
1855
1224
1373
1949
1983
1943
1612
0
-
B9
vin2a_d1
10
0
-
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
A7
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
-
0
-
412
147
516
450
449
488
371
275
35
0
-
260
0
-
-
0
-
11
5
-
-
0
-
611
0
-
-
B13
E13
C13
D13
A9
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
441
556
433
523
361
0
88
161
102
145
0
-
-
-
-
-
A8
vin2a_d4
0
-
A11
F10
A10
B10
E10
B7
vin2a_d5
271
0
0
-
vin2a_d6
0
-
vin2a_d7
141
437
265
208
562
0
0
-
vin2a_d8
618
509
0
-
vin2a_d9
-
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
vin2a_fld0
C7
151
0
-
-
-
E8
B8
0
0
164
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Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-33 Manual Functions Mapping for VIN2B (IOSET7/8/9) for a definition of the Manual modes.
表 5-33 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-33. Manual Functions Mapping for VIN2B (IOSET7/8/9)
BALL
BALL NAME
VIP_MANUAL4
VIP_MANUAL6
CFG REGISTER
MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps)
2
3
4
Y5
Y6
gpio6_10
gpio6_11
2829
2648
2794
2789
2689
2605
2616
2760
2757
2688
2638
995
884
1033
1074
1162
1180
1219
703
1235
880
1177
1165
182
0
3009
2890
2997
2959
2897
2891
2947
2931
2979
2894
2894
1202
1739
1568
2217
2029
2202
2313
2334
2288
2048
0
892
1096
1089
1210
1269
1219
590
1342
891
1262
1187
107
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
-
-
vin2b_hsync1
-
-
vin2b_vsync1
Y2
mmc3_clk
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_VIN2A_D16_IN
CFG_VIN2A_D17_IN
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
CFG_VIN2A_DE0_IN
CFG_VIN2A_FLD0_IN
CFG_VIN2A_HSYNC0_IN
CFG_VIN2A_VSYNC0_IN
-
-
vin2b_d7
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_de0
vin2a_fld0
vin2a_hsync0
vin2a_vsync0
-
-
vin2b_d6
Y4
-
-
vin2b_d5
AA2
AA3
W2
Y3
-
-
vin2b_d4
-
-
vin2b_d3
-
-
vin2b_d2
-
-
vin2b_d1
AA1
AA4
AB1
A12
A13
E11
F11
B13
E13
C13
D13
B7
-
-
vin2b_d0
-
-
vin2b_de1
-
-
vin2b_clk1
1423
1253
2080
1849
1881
1917
1955
1899
1568
0
vin2b_d7
vin2b_d6
vin2b_d5
vin2b_d4
vin2b_d3
vin2b_d2
vin2b_d1
vin2b_d0
vin2b_fld1
vin2b_clk1
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
0
-
0
0
-
0
0
-
50
0
-
167
79
0
-
0
-
145
261
0
0
-
0
vin2b_de1
-
C7
0
E8
1793
1382
0
2011
1632
0
vin2b_hsync1
vin2b_vsync1
B8
0
0
-
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Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-34 Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10) for a definition of the
Manual modes.
表 5-34 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-34. Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10)
BALL
BALL NAME
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
6
M1
M2
J2
gpmc_a0
gpmc_a1
3080
2958
3073
3014
1385
3041
859
1792
1890
1653
1784
0
3376
3249
3388
3290
1246
3322
720
1632
1749
1433
1693
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A19_IN
CFG_GPMC_A2_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
CFG_GPMC_A8_IN
CFG_GPMC_A9_IN
CFG_GPMC_AD0_IN
CFG_GPMC_AD1_IN
CFG_GPMC_AD10_IN
CFG_GPMC_AD11_IN
CFG_GPMC_AD12_IN
CFG_GPMC_AD13_IN
vin1a_d16
vin1a_d17
vin1a_de0
vin1a_fld0
-
-
-
gpmc_a10
gpmc_a11
gpmc_a19
gpmc_a2
-
L3
A4
L2
E7
D6
C5
B5
D7
C6
A5
B6
L1
K3
K2
J1
-
vin2b_d0
1960
0
1850
0
vin1a_d18
-
-
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_a3
vin2b_d1
1465
1210
1111
1137
1402
1298
934
0
1334
1064
954
0
-
vin2b_d2
0
0
-
vin2b_d3
0
0
-
vin2b_d4
0
1051
1283
1153
870
0
-
vin2b_d5
0
0
-
vin2b_d6
0
0
-
vin2b_d7
0
0
-
vin2b_hsync1
3019
3063
3021
3062
3260
3033
2991
2907
2858
2920
2719
2845
2765
2145
1981
1954
1716
1889
1702
1905
1342
1321
1384
1310
1135
1225
3296
3357
3304
3348
3583
3328
3281
3181
3132
3223
3019
3160
3045
2050
1829
1840
1592
1631
1547
1766
1255
1234
1204
1198
917
1119
vin1a_d19
vin1a_d20
vin1a_d21
vin1a_d22
vin1a_d23
vin1a_hsync0
vin1a_vsync0
vin1a_d0
vin1a_d1
vin1a_d10
vin1a_d11
vin1a_d12
vin1a_d13
-
-
-
-
-
-
-
-
-
-
-
-
-
gpmc_a4
gpmc_a5
gpmc_a6
K1
K4
H1
F1
E2
A2
B3
C3
C4
gpmc_a7
gpmc_a8
gpmc_a9
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
166
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表 5-34. Manual Functions Mapping for VIN1A (IOSET2) and VIN2B (IOSET1/10) (continued)
BALL
BALL NAME
VIP_MANUAL7
VIP_MANUAL12
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
2
6
A3
B4
E1
C1
D1
D2
B1
B2
C2
D3
H2
H6
L4
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_ben0
gpmc_ben1
gpmc_clk
2845
2766
2951
2825
2927
2923
2958
2900
2845
2779
1555
1501
0
1150
1453
1296
1154
1245
1251
1342
1244
1585
1343
0
3153
3044
3226
3121
3246
3217
3238
3174
3125
3086
1425
1397
0
952
1355
1209
997
1014
1098
1239
1157
1482
1223
0
CFG_GPMC_AD14_IN
CFG_GPMC_AD15_IN
CFG_GPMC_AD2_IN
CFG_GPMC_AD3_IN
CFG_GPMC_AD4_IN
CFG_GPMC_AD5_IN
CFG_GPMC_AD6_IN
CFG_GPMC_AD7_IN
CFG_GPMC_AD8_IN
CFG_GPMC_AD9_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CLK_IN
CFG_GPMC_CS1_IN
CFG_GPMC_CS3_IN
vin1a_d14
vin1a_d15
vin1a_d2
vin1a_d3
vin1a_d4
vin1a_d5
vin1a_d6
vin1a_d7
vin1a_d8
vin1a_d9
-
-
-
-
-
-
-
-
-
-
-
vin2b_de1
vin2b_fld1
vin2b_clk1
vin2b_vsync1
-
0
0
-
0
0
-
A6
G3
gpmc_cs1
gpmc_cs3
1192
1324
0
1102
1466
0
-
374
353
vin1a_clk0
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-35 Manual Functions Mapping for VIN1B (IOSET6/7) for a definition of the Manual modes.
表 5-35 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-35. Manual Functions Mapping for VIN1B (IOSET6/7)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
5
-
-
-
-
-
-
-
-
-
6
M1
M2
J2
gpmc_a0
gpmc_a1
gpmc_a10
gpmc_a11
gpmc_a12
gpmc_a2
gpmc_a3
gpmc_a4
gpmc_a5
1873
1629
0
702
772
0
2202
2057
0
441
413
0
CFG_GPMC_A0_IN
CFG_GPMC_A1_IN
CFG_GPMC_A10_IN
CFG_GPMC_A11_IN
CFG_GPMC_A12_IN
CFG_GPMC_A2_IN
CFG_GPMC_A3_IN
CFG_GPMC_A4_IN
CFG_GPMC_A5_IN
vin1b_d0
vin1b_d1
vin1b_clk1
vin1b_de1
vin1b_fld1
vin1b_d2
vin1b_d3
vin1b_d4
vin1b_d5
L3
G1
L2
L1
K3
K2
1851
2009
1734
1757
1794
1726
1011
601
898
1076
893
853
2126
2289
2131
2106
2164
2120
856
327
573
812
559
523
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表 5-35. Manual Functions Mapping for VIN1B (IOSET6/7) (continued)
BALL
BALL NAME
VIP_MANUAL9
VIP_MANUAL14
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
612
A_DELAY (ps)
G_DELAY (ps)
338
5
-
6
J1
K1
K4
H1
L6
L5
N2
P2
N4
N1
T4
T5
R2
P3
P4
N5
N6
gpmc_a6
gpmc_a7
1792
2117
1758
1705
1945
255
2153
2389
2140
2067
2265
337
CFG_GPMC_A6_IN
CFG_GPMC_A7_IN
vin1b_d6
610
304
-
vin1b_d7
gpmc_a8
653
308
CFG_GPMC_A8_IN
-
vin1b_hsync1
gpmc_a9
899
646
CFG_GPMC_A9_IN
-
vin1b_vsync1
mdio_d
671
414
CFG_MDIO_D_IN
vin1b_d0
vin1b_clk1
vin1b_d5
vin1b_d6
vin1b_fld1
vin1b_d7
vin1b_d3
vin1b_d4
vin1b_vsync1
vin1b_hsync1
vin1b_de1
vin1b_d1
vin1b_d2
-
-
-
-
-
-
-
-
-
-
-
-
-
mdio_mclk
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd3
rgmii0_txc
rgmii0_txctl
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
uart3_rxd
uart3_txd
119
0
CFG_MDIO_MCLK_IN
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD3_IN
CFG_RGMII0_TXC_IN
CFG_RGMII0_TXCTL_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
CFG_UART3_RXD_IN
CFG_UART3_TXD_IN
2057
2121
2070
2092
2088
2143
2078
1928
2255
1829
2030
909
2341
2323
2336
2306
2328
2312
2324
2306
2401
2220
2324
646
1139
655
988
340
1357
1205
1383
1189
1125
971
1216
1079
1311
1065
763
846
747
400
837
568
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-36 Manual Functions Mapping for VIN2B (IOSET2/11) for a definition of the Manual modes.
表 5-36 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-36. Manual Functions Mapping for VIN2B (IOSET2/11)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
4
-
-
-
-
-
-
-
6
A4
E7
D6
C5
B5
D7
C6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
1600
1440
1602
1395
1571
1463
1426
943
621
2023
1875
2021
1822
2045
1893
1842
477
136
604
519
200
396
732
CFG_GPMC_A19_IN
CFG_GPMC_A20_IN
CFG_GPMC_A21_IN
CFG_GPMC_A22_IN
CFG_GPMC_A23_IN
CFG_GPMC_A24_IN
CFG_GPMC_A25_IN
vin2b_d0
vin2b_d1
vin2b_d2
vin2b_d3
vin2b_d4
vin2b_d5
vin2b_d6
1066
983
716
832
1166
168
Specifications
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表 5-36. Manual Functions Mapping for VIN2B (IOSET2/11) (continued)
BALL
BALL NAME
VIP_MANUAL10
VIP_MANUAL11
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
4
6
A5
B6
H2
H6
A6
gpmc_a26
gpmc_a27
gpmc_ben0
gpmc_ben1
gpmc_cs1
1362
1283
1978
0
1094
809
780
0
1797
1760
2327
0
584
338
389
0
CFG_GPMC_A26_IN
CFG_GPMC_A27_IN
CFG_GPMC_BEN0_IN
CFG_GPMC_BEN1_IN
CFG_GPMC_CS1_IN
-
vin2b_d7
vin2b_hsync1
vin2b_de1
-
-
-
vin2b_clk1
-
1411
982
1857
536
vin2b_vsync1
Manual IO Timings Modes must be used to guaranteed some IO timings for VIP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-37 Manual Functions Mapping for VIN1A (IOSET8/9/10) for a definition of the Manual modes.
表 5-37 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-37. Manual Functions Mapping for VIN1A (IOSET8/9/10)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
7
9
Y5
gpio6_10
2131
3720
2447
3061
3113
2803
3292
2854
2813
2471
2815
2965
3082
2898
2413
2478
2806
2861
1583
2198
2170
4106
3042
3380
3396
3362
3357
3145
3229
3053
3225
3427
3253
3368
2972
3062
3175
2936
1878
2180
2448
0
CFG_GPIO6_10_IN
CFG_GPIO6_11_IN
-
vin1a_clk0
Y6
gpio6_11
2732
0
-
vin1a_de0
C16
D14
B14
B16
B18
A19
E17
E16
F16
A18
B17
C17
E19
A21
B21
D19
A22
mcasp1_aclkx
mcasp1_axr0
mcasp1_axr1
mcasp1_axr10
mcasp1_axr11
mcasp1_axr12
mcasp1_axr13
mcasp1_axr14
mcasp1_axr15
mcasp1_axr8
mcasp1_axr9
mcasp1_fsx
CFG_MCASP1_ACLKX_IN
CFG_MCASP1_AXR0_IN
CFG_MCASP1_AXR1_IN
CFG_MCASP1_AXR10_IN
CFG_MCASP1_AXR11_IN
CFG_MCASP1_AXR12_IN
CFG_MCASP1_AXR13_IN
CFG_MCASP1_AXR14_IN
CFG_MCASP1_AXR15_IN
CFG_MCASP1_AXR8_IN
CFG_MCASP1_AXR9_IN
CFG_MCASP1_FSX_IN
CFG_MCASP2_ACLKX_IN
CFG_MCASP2_AXR2_IN
CFG_MCASP2_AXR3_IN
CFG_MCASP2_FSX_IN
CFG_MCASP3_ACLKX_IN
vin1a_fld0
vin1a_vsync0
vin1a_hsync0
vin1a_d13
vin1a_d12
vin1a_d11
vin1a_d10
vin1a_d9
vin1a_d8
vin1a_d15
vin1a_d14
vin1a_de0
vin1a_d7
vin1a_d5
vin1a_d4
vin1a_d6
vin1a_d3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
0
292
304
0
0
0
0
546
320
196
0
0
0
0
0
201
83
0
0
440
139
0
0
mcasp2_aclkx
mcasp2_axr2
mcasp2_axr3
mcasp2_fsx
0
0
0
0
242
599
0
78
0
mcasp3_aclkx
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表 5-37. Manual Functions Mapping for VIN1A (IOSET8/9/10) (continued)
BALL
BALL NAME
VIP_MANUAL15
VIP_MANUAL16
CFG REGISTER
MUXMODE
A_DELAY (ps)
G_DELAY (ps)
0
A_DELAY (ps)
G_DELAY (ps)
375
7
9
-
B22
B23
A23
Y2
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mmc3_clk
2873
1625
2792
3907
3892
3786
3673
3818
3902
3905
3807
3724
3775
1971
0
3109
2072
3146
4260
4242
4156
4053
4209
4259
4259
4167
4123
4159
2472
0
CFG_MCASP3_AXR0_IN
CFG_MCASP3_AXR1_IN
CFG_MCASP3_FSX_IN
CFG_MMC3_CLK_IN
CFG_MMC3_CMD_IN
CFG_MMC3_DAT0_IN
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT7_IN
CFG_XREF_CLK0_IN
CFG_XREF_CLK1_IN
vin1a_d1
1400
0
1023
257
vin1a_d0
-
vin1a_d2
-
2744
2768
2765
2961
2447
2903
2622
2824
2818
2481
0
2450
2470
2522
2667
2096
2672
2342
2595
2491
2161
0
-
vin1a_d7
vin1a_d6
vin1a_d5
vin1a_d4
vin1a_d3
vin1a_d2
vin1a_d1
vin1a_d0
vin1a_hsync0
vin1a_vsync0
-
Y1
mmc3_cmd
mmc3_dat0
mmc3_dat1
mmc3_dat2
mmc3_dat3
mmc3_dat4
mmc3_dat5
mmc3_dat6
mmc3_dat7
xref_clk0
-
Y4
-
AA2
AA3
W2
Y3
-
-
-
-
AA1
AA4
AB1
J25
J24
-
-
-
vin1a_d0
vin1a_clk0
xref_clk1
192
603
-
170
Specifications
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5.10.6.4 DSS
Two Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 2 and DPI
Video Output 3.
注
The DPI Video Output i (i = 2, 3) interface is also referred to as VOUTi.
Every VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
注
For more information, see the Display Subsystem chapter of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-42.
CAUTION
The I/O Timings provided in this section are valid only for some DSS usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
CAUTION
All pads/balls configured as vouti_* signals must be programmed to use slow
slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL]
register field to SLOW (0b1).
表 5-38, 表 5-39 and 图 5-22 assume testing over the recommended operating conditions and electrical
characteristic conditions.
表 5-38. DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2)
PARAMETE
NO.
DESCRIPTION
MODE
MIN
MAX UNIT
R
D1
D2
tc(clk)
tw(clkL)
Cycle time, output pixel clock vouti_clk
DPI2/3
11.76
ns
ns
Pulse duration, output pixel clock vouti_clk low
P × 0.5-
(1)
1
D3
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P × 0.5-
ns
(1)
1
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MAX UNIT
表 5-38. DPI Video Output i (i = 2, 3) Default Switching Characteristics(1)(2) (continued)
PARAMETE
R
NO.
DESCRIPTION
MODE
MIN
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
2.5
2.5
ns
ns
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
-2.5
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
-2.5
-2.5
2.5
2.5
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 5-39. DPI Video Output i (i = 2, 3) Alternate Switching Characteristics(2)
PARAMETE
NO.
DESCRIPTION
MODE
MIN
MAX UNIT
R
D1
D2
tc(clk)
Cycle time, output pixel clock vouti_clk
DPI2/3
6.06
ns
ns
tw(clkL)
Pulse duration, output pixel clock vouti_clk low
P × 0.5-
(1)
1
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P × 0.5-
ns
(1)
1
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to output
data vouti_d[23:0] valid
DPI3
DPI3
1.51
1.51
4.55
4.55
ns
ns
Delay time, output pixel clock vouti_clk transition to output
control signals vouti_vsync, vouti_hsync, vouti_de, and
vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 5-40. DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2)
NO.
D1
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.06 (3)
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
tw(clkL)
P*0.5-1
(1)
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
(1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI1
DPI1
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
D5
td(clk-ctlV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
2.85
5.56
ns
172
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表 5-40. DPI Video Output i (i = 2, 3) MANUAL4 Switching Characteristics (2) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
D6
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
2.85
5.56
ns
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
2.85
2.85
5.56
5.56
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
表 5-41. DPI Video Output i (i = 2, 3) MANUAL5 Switching Characteristics (2)
NO.
D1
PARAMETER
tc(clk)
DESCRIPTION
MODE
MIN
6.06 (3)
MAX UNIT
Cycle time, output pixel clock vouti_clk
Pulse duration, output pixel clock vouti_clk low
DPI2/3
ns
ns
D2
tw(clkL)
P*0.5-1
(1)
D3
D5
D6
tw(clkH)
Pulse duration, output pixel clock vouti_clk high
P*0.5-1
ns
(1)
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI1
DPI1
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (vin2a_fld0 clock
reference)
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (vin2a_fld0 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI2 (xref_clk2 clock
reference)
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
DPI2 (xref_clk2 clock
reference)
D5
D6
td(clk-ctlV)
td(clk-dV)
Delay time, output pixel clock vouti_clk transition to
output data vouti_d[23:0] valid
DPI3
DPI3
3.55
3.55
6.61
6.61
ns
ns
Delay time, output pixel clock vouti_clk transition to
output control signals vouti_vsync, vouti_hsync,
vouti_de, and vouti_fld valid
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(1) P = output vouti_clk period in ns.
(2) All pads/balls configured as vouti_* signals must be programmed to use slow slew rate by setting the corresponding
CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1).
(3) SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
D2
D3
D1
D6
D4
Falling-edge Clock Reference
Rising-edge Clock Reference
vouti_clk
vouti_clk
vouti_vsync
D6
vouti_hsync
vouti_d[23:0]
vouti_de
D5
data_1 data_2
D6
data_n
D6
even
vouti_fld
odd
SWPS049-018
图 5-22. DPI Video Output(1)(2)(3)
(1) The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
(2) The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the device TRM.
(3) The vouti_clk frequency can be configured, refer to the DSS section of the device TRM.
In 表 5-42 are presented the specific groupings of signals (IOSET) for use with VOUT2.
表 5-42. VOUT2 IOSETs
SIGNALS
IOSET1
BALL
C8
MUX
4
vout2_d23
vout2_d22
vout2_d21
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_d13
vout2_d12
vout2_d11
vout2_d10
B9
4
A7
4
A9
4
A8
4
A11
F10
A10
B10
E10
D10
C10
B11
D11
4
4
4
4
4
4
4
4
4
174
Specifications
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表 5-42. VOUT2 IOSETs (continued)
SIGNALS
IOSET1
BALL
C11
B12
A12
A13
E11
F11
B13
E13
C13
D13
B8
MUX
4
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_vsync
vout2_hsync
vout2_clk
vout2_fld
vout2_de
4
4
4
4
4
4
4
4
4
4
E8
4
C7
4
D8
4
B7
4
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-27 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-43 Virtual
Functions Mapping for VOUT3 for a definition of the Virtual modes.
表 5-43 presents the values for DELAYMODE bitfield.
表 5-43. Virtual Functions Mapping for DSS VOUT3
BALL
BALL NAME
Delay Mode Value
MUXMODE
3
DSS_VIRTUAL1
B4
K4
D1
F1
C4
L2
gpmc_ad15
gpmc_a8
14
15
14
14
14
15
14
15
15
14
15
15
15
14
14
14
vout3_d15
vout3_hsync
vout3_d4
vout3_d0
vout3_d13
vout3_d18
vout3_d1
vout3_d20
vout3_d22
vout3_d14
vout3_d17
vout3_clk
vout3_vsync
vout3_d11
vout3_d6
vout3_d2
gpmc_ad4
gpmc_ad0
gpmc_ad13
gpmc_a2
E2
K3
J1
gpmc_ad1
gpmc_a4
gpmc_a6
A3
M2
G3
H1
B3
B1
E1
gpmc_ad14
gpmc_a1
gpmc_cs3
gpmc_a9
gpmc_ad11
gpmc_ad6
gpmc_ad2
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表 5-43. Virtual Functions Mapping for DSS VOUT3 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
DSS_VIRTUAL1
3
C1
K1
L1
gpmc_ad3
gpmc_a7
14
15
15
14
14
15
15
14
14
15
14
15
14
vout3_d3
vout3_d23
vout3_d19
vout3_d10
vout3_d7
vout3_de
vout3_d21
vout3_d8
vout3_d5
vout3_d16
vout3_d12
vout3_fld
vout3_d9
gpmc_a3
A2
B2
J2
gpmc_ad10
gpmc_ad7
gpmc_a10
gpmc_a5
K2
C2
D2
M1
C3
L3
gpmc_ad8
gpmc_ad5
gpmc_a0
gpmc_ad12
gpmc_a11
gpmc_ad9
D3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT2. See 表 5-28, Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-44, Manual
Functions Mapping for DSS VOUT2 IOSET1 for a definition of the Manual modes.
表 5-44 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
176
Specifications
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表 5-44. Manual Functions Mapping for DSS VOUT2 IOSET1
BALL
BALL
NAME
VOUT2_IOSET1
_MANUAL1
VOUT2_IOSET1
_MANUAL2
VOUT2_IOSET1
_MANUAL3
VOUT2_IOSET1
_MANUAL4
VOUT2_IOSET1
_MANUAL5
CFG REGISTER
MUXMODE
4
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2571
2124
2103
2091
2142
2920
2776
2904
2670
2814
3002
1893
1698
2193
1736
1636
1628
1538
1997
2528
2038
1746
2213
2268
2170
2102
0
(ps)
(ps)
1059
589
568
557
608
1816
1872
1769
1665
1908
1897
358
163
658
202
101
93
(ps)
(ps)
1025
577
557
545
596
1783
1838
1757
1632
1878
1865
347
151
646
190
89
(ps)
(ps)
4110
3613
3442
3430
3481
3943
3799
3869
3792
3837
4024
3432
3237
3531
3075
3074
3266
2968
3335
3867
3577
3285
3552
3607
3509
3841
0
(ps)
(ps)
4980
4483
4312
4200
4251
4713
4669
4739
4662
4707
4894
4302
4007
4401
3945
3944
4036
3838
4205
4537
4347
4055
4272
4277
4379
4611
0
(ps)
D8
C8
vin2a_clk0
vin2a_d0
vin2a_d1
vin2a_d10
vin2a_d11
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
vin2a_d18
vin2a_d19
vin2a_d2
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
vin2a_d3
vin2a_d4
vin2a_d5
vin2a_d6
vin2a_d7
vin2a_d8
vin2a_d9
vin2a_de0
vin2a_fld0
0
0
0
0
0
CFG_VIN2A_CLK0_OUT
CFG_VIN2A_D0_OUT
CFG_VIN2A_D1_OUT
CFG_VIN2A_D10_OUT
CFG_VIN2A_D11_OUT
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
CFG_VIN2A_D18_OUT
CFG_VIN2A_D19_OUT
CFG_VIN2A_D2_OUT
CFG_VIN2A_D20_OUT
CFG_VIN2A_D21_OUT
CFG_VIN2A_D22_OUT
CFG_VIN2A_D23_OUT
CFG_VIN2A_D3_OUT
CFG_VIN2A_D4_OUT
CFG_VIN2A_D5_OUT
CFG_VIN2A_D6_OUT
CFG_VIN2A_D7_OUT
CFG_VIN2A_D8_OUT
CFG_VIN2A_D9_OUT
CFG_VIN2A_DE0_OUT
CFG_VIN2A_FLD0_OUT
vout2_fld
vout2_d23
vout2_d22
vout2_d13
vout2_d12
vout2_d11
vout2_d10
vout2_d9
vout2_d8
vout2_d7
vout2_d6
vout2_d5
vout2_d4
vout2_d21
vout2_d3
vout2_d2
vout2_d1
vout2_d0
vout2_d20
vout2_d19
vout2_d18
vout2_d17
vout2_d16
vout2_d15
vout2_d14
vout2_de
vout2_clk
0
0
0
0
0
B9
0
0
0
0
0
D10
C10
B11
D11
C11
B12
A12
A13
E11
F11
A7
0
0
0
0
0
0
0
0
0
0
385
322
0
255
192
0
276
213
0
601
538
174
473
371
415
0
601
538
174
473
371
415
0
257
155
199
0
127
31
69
0
148
43
89
0
0
0
0
0
0
0
0
0
0
0
B13
E13
C13
D13
A9
0
0
0
0
0
0
0
0
0
0
0
0
81
0
0
0
0
0
0
0
0
0
0
0
462
993
503
211
678
733
635
568
1398
974
0
450
982
492
200
666
721
623
556
1385
936
0
0
0
A8
0
0
0
0
0
A11
F10
A10
B10
E10
B7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
C7
983
0
1185
0
1202
0
994
0
994
0
E8
vin2a_hsy
nc0
2482
4021
4891
CFG_VIN2A_HSYNC0_ vout2_hsync
OUT
B8
vin2a_vsy
nc0
2296
0
784
0
750
0
3935
0
4805
0
CFG_VIN2A_VSYNC0_O vout2_vsync
UT
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Specifications
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Manual IO Timings Modes must be used to guaranteed some IO timings for VOUT3. See 表 5-28, Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-45, Manual
Functions Mapping for DSS VOUT3 for a definition of the Manual modes.
表 5-45 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-45. Manual Functions Mapping for DSS VOUT3
BALL
BALL
NAME
VOUT3_MANUAL1
VOUT3_MANUAL4
VOUT3_MANUAL5
CFG REGISTER
MUXMODE
3
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
2395
2412
2473
2906
2360
2391
2626
2338
2374
2432
3155
2309
2360
2420
2235
2253
1949
2318
2123
2195
2617
2350
2324
2371
2231
2440
2479
2355
0
(ps)
0
(ps)
3909
3957
3980
4253
3873
4112
4336
3840
3913
3947
4309
3842
3652
3762
3456
3584
3589
3547
3302
3532
3859
3590
3534
3609
3416
3661
3714
3593
0
(ps)
0
(ps)
4779
4827
4850
5123
4743
4982
5206
4710
4783
4817
5179
4712
4522
4632
4326
4454
4459
4417
4172
4402
4729
4460
4404
4479
4286
4531
4584
4463
0
(ps)
0
M1
M2
J2
gpmc_a0
gpmc_a1
CFG_GPMC_A0_OUT
CFG_GPMC_A1_OUT
CFG_GPMC_A10_OUT
CFG_GPMC_A11_OUT
CFG_GPMC_A2_OUT
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A5_OUT
CFG_GPMC_A6_OUT
CFG_GPMC_A7_OUT
CFG_GPMC_A8_OUT
CFG_GPMC_A9_OUT
CFG_GPMC_AD0_OUT
CFG_GPMC_AD1_OUT
CFG_GPMC_AD10_OUT
CFG_GPMC_AD11_OUT
CFG_GPMC_AD12_OUT
CFG_GPMC_AD13_OUT
CFG_GPMC_AD14_OUT
CFG_GPMC_AD15_OUT
CFG_GPMC_AD2_OUT
CFG_GPMC_AD3_OUT
CFG_GPMC_AD4_OUT
CFG_GPMC_AD5_OUT
CFG_GPMC_AD6_OUT
CFG_GPMC_AD7_OUT
CFG_GPMC_AD8_OUT
CFG_GPMC_AD9_OUT
CFG_GPMC_CS3_OUT
vout3_d16
vout3_d17
vout3_de
vout3_fld
0
0
0
gpmc_a10
gpmc_a11
gpmc_a2
0
0
0
L3
0
0
0
L2
0
0
0
vout3_d18
vout3_d19
vout3_d20
vout3_d21
vout3_d22
vout3_d23
vout3_hsync
vout3_vsync
vout3_d0
vout3_d1
vout3_d10
vout3_d11
vout3_d12
vout3_d13
vout3_d14
vout3_d15
vout3_d2
vout3_d3
vout3_d4
vout3_d5
vout3_d6
vout3_d7
vout3_d8
vout3_d9
vout3_clk
L1
gpmc_a3
0
0
0
K3
K2
J1
gpmc_a4
0
0
0
gpmc_a5
0
0
0
gpmc_a6
0
0
0
K1
K4
H1
F1
E2
A2
B3
C3
C4
A3
B4
E1
C1
D1
D2
B1
B2
C2
D3
G3
gpmc_a7
0
0
0
gpmc_a8
0
105
0
105
0
gpmc_a9
0
gpmc_ad0
gpmc_ad1
gpmc_ad10
gpmc_ad11
gpmc_ad12
gpmc_ad13
gpmc_ad14
gpmc_ad15
gpmc_ad2
gpmc_ad3
gpmc_ad4
gpmc_ad5
gpmc_ad6
gpmc_ad7
gpmc_ad8
gpmc_ad9
gpmc_cs3
0
0
0
0
0
0
0
0
0
0
0
0
427
0
0
0
0
0
0
0
0
29
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
641
905
905
5.10.6.5 HDMI
The High-Definition Multimedia Interface is provided for transmitting digital television audiovisual signals
from DVD players, set-top boxes and other audiovisual sources to television sets, projectors and other
video displays. The HDMI interface is aligned with the HDMI TMDS single stream standard v1.4a (720p
@60Hz to 1080p @24Hz) and the HDMI v1.3 (1080p @60Hz): 3 data channels, plus 1 clock channel is
supported (differential).
In are presented the specific groupings of signals (IOSET) for use with HDMI.
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Specifications
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注
For more information, see the High-Definition Multimedia Interface chapter of the device
TRM
5.10.6.6 CSI2
注
For more information, see the Camera Serial Interface 2 CAL Bridge chapter of the device
TRM
The camera adaptation layer (CAL) deals with the processing of the pixel data coming from an external
image sensor, data from memory. The CAL is a key component for the following multimedia applications:
camera viewfinder, video record, and still image capture. The CAL has one serial camera interface :
•
The primary serial interface (CSI2 Port A) is compliant with MIPI CSI-2 protocol with four data lanes.
5.10.6.6.1 CSI-2 MIPI D-PHY
The CSI-2 port A is compliant with the MIPI D-PHY RX specification v1.00.00 and the MIPI CSI-2
specification v1.00, with 2 data differential lanes plus 1 clock differential lane in synchronous mode,
double data rate:
•
1.5 Gbps (750 MHz) @OPP_NOM for each lane.
5.10.6.7 EMIF
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
•
•
•
16-bit or 32-bit data path to external SDRAM memory
Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices
One interface with associated DDR3/DDR3L PHYs
注
For more information, see the EMIF Controller section of the Device TRM.
5.10.6.8 GPMC
The GPMC is the unified memory controller that interfaces external memory devices such as:
•
•
•
Asynchronous SRAM-like memories and ASIC devices
Asynchronous page mode and synchronous burst NOR flash
NAND flash
注
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
5.10.6.8.1 GPMC/NOR Flash Interface Synchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
180
Specifications
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表 5-46 and 表 5-47 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-23, 图 5-24, 图 5-25, 图 5-26, 图 5-27 and 图 5-28).
表 5-46. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default
NO.
PARAMETER
DESCRIPTION
MIN
3
MAX UNIT
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
ns
ns
ns
ns
1.1
2.5
1.3
注
Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of
wait monitoring feature, see the Device TRM.
表 5-47. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default
NO.
F0
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, output clock gpmc_clk period
MIN
MAX UNIT
11.3
ns
(7)
(7)
F2
td(clkH-nCSV)
td(clkH-nCSIV)
td(ADDV-clk)
td(clkH-ADDIV)
td(nBEV-clk)
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
td(clkH-nOE)
td(clkH-nOEIV)
td(clkH-nWE)
td(clkH-Data)
td(clkH-nBE)
tw(nCSV)
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
F-1.7
F+4.3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
F3
E-1.7 (6) E+4.2 (6)
B-1.8 (3) B+4.3 (3)
-1.8
F4
F5
F6
B-4.3(3)
B+1.5(3)
F7
D-1.5(5) D+4.3(5)
G-1.3 (8) G+4.2 (8)
D-1.3 (5) G+4.2 (5)
H-1.0 (9) H+3.2 (9)
E-1.0 (6) E+3.2 (6)
I-0.9 (10) I+4.2 (10)
F8
F9
F10
F11
F14
F15
F17
F18
F19
F20
F23
(11)
(11)
J-2.1
J-1.5
J+4.6
J+4.3
(11)
(11)
A (2)
(4)
tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
tw(nADVV)
Pulse duration, gpmc_advn_ale low
K (12)
td(CLK-GPIO)
Delay time, gpmc_clk transition to gpio6_16 transition
0.5
7.5
表 5-48. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate
NO.
PARAMETER
DESCRIPTION
MIN
2.5
1.9
2.5
1.9
MAX UNIT
F12 tsu(dV-clkH)
F13 th(clkH-dV)
F21 tsu(waitV-clkH)
F22 th(clkH-waitV)
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
ns
ns
ns
ns
表 5-49. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate
NO.
F0
PARAMETER
tc(clk)
td(clkH-nCSV)
DESCRIPTION
Cycle time, output clock gpmc_clk period (13)
MIN
MAX UNIT
15.04
ns
(7)
(7)
F2
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition
F+0.6
F+7.0
ns
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MAX UNIT
表 5-49. GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode -
Alternate (continued)
NO.
F3
F4
F5
F6
F7
F8
F9
PARAMETER
td(clkH-nCSIV)
td(ADDV-clk)
DESCRIPTION
MIN
Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid
Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge
Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid
Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid
Delay time, gpmc_clk rising edge to gpmc_advn_ale transition
Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid
Delay time, gpmc_clk rising edge to gpmc_oen_ren transition
Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid
Delay time, gpmc_clk rising edge to gpmc_wen transition
Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition
Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition
Pulse duration, gpmc_cs[7:0] low
E+0.6 (6) E+7.0 (6)
B-0.7 (3) B+7.0 (3)
-0.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(clkH-ADDIV)
td(nBEV-clk)
B-7.0
D-0.4
B+0.4
D+7.0
td(clkH-nBEIV)
td(clkH-nADV)
td(clkH-nADVIV)
G+0.7 (8) G+6.1 (8)
D+0.7 (5) D+6.1 (5)
H+0.7 (9) H+5.1 (9)
E+0.7 (6) E+5.1 (6)
I+0.7 (10) I+6.1 (10)
F10 td(clkH-nOE)
F11 td(clkH-nOEIV)
F14 td(clkH-nWE)
F15 td(clkH-Data)
F17 td(clkH-nBE)
F18 tw(nCSV)
(11)
(11)
J-0.4
J-0.4
J+4.9
J+4.9
(11)
(11)
A (2)
(4)
F19 tw(nBEV)
Pulse duration, gpmc_ben[1:0] low
C
F20 tw(nADVV)
F23 td(CLK-GPIO)
Pulse duration, gpmc_advn_ale low
Delay time, gpmc_clk transition to gpio6_16.clkout1 transition (14)
K (12)
0.5
7.5
(1) Total GPMC load on any signal at 3.3V must not exceed 10pF.
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
with n the page burst access number.
(3) B = ClkActivationTime × GPMC_FCLK
(4) For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: C = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For Burst write: C = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK with n the page burst
access number.
(5) For single read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: D = (RdCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: D = (WrCycleTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(6) For single read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: E = (CSRdOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: E = (CSWrOffTime - AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(7) For nCS falling edge (CS activated):
Case GpmcFCLKDivider = 0 :
F = 0.5 × CSExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1:
F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 3)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 3)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
F = (3 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
(8) For ADV falling edge (ADV activated):
Case GpmcFCLKDivider = 0 :
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are
even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime - ClkActivationTime - 2) is a multiple of 3)
For ADV rising edge (ADV desactivated) in Reading mode:
182
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Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime - ClkActivationTime - 3) is a multiple of 4)
For ADV rising edge (ADV desactivated) in Writing mode:
Case GpmcFCLKDivider = 0:
G = 0.5 × ADVExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime
are even)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 3)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 3)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime) is a multiple of 4)
G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 1) is a multiple of 4)
G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 2) is a multiple of 4)
G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime - ClkActivationTime - 3) is a multiple of 4)
(9) For OE falling edge (OE activated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay)) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
For OE rising edge (OE desactivated):
Case GpmcFCLKDivider = 0:
- H = 0.5 × OEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are
even)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 3)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 3)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime - ClkActivationTime) is a multiple of 4)
- H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 1) is a multiple of 4)
- H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 2) is a multiple of 4)
- H = (3 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime - ClkActivationTime - 3) is a multiple of 4)
(10) For WE falling edge (WE activated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 3)
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- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
For WE rising edge (WE desactivated):
Case GpmcFCLKDivider = 0:
- I = 0.5 × WEExtraDelay × GPMC_FCLK
Case GpmcFCLKDivider = 1:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are
even)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
Case GpmcFCLKDivider = 2:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 3)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 3)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 3)
Case GpmcFCLKDivider = 3:
- I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
- I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
- I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
- I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
(11) J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
(12) For read:
K = (ADVRdOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For write: K = (ADVWrOffTime - ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(13) The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx
configuration register bit fields GpmcFCLKDivider
(14) gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK),
CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
(15) CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay
mode is not timed.
184
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F19
F7
F7
gpmc_ben1
gpmc_ben0
F6
F19
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F4
F5
F12
D 0
gpmc_ad[15:0]
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_01
图 5-23. GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F0
F1
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F6
F7
F7
F19
gpmc_ben1
F6
F19
gpmc_ben0
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F13
F12
D 0
gpmc_ad[15:0]
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_02
图 5-24. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F7
F7
F19
gpmc_ben1
gpmc_ben0
Valid
F6
F19
Valid
F8
F8
F9
F20
gpmc_advn_ale
gpmc_oen_ren
F10
F5
F11
F12
F4
F13
D1
F12
gpmc_ad[15:0]
D0
D2
D3
Address (LSB)
F22
F21
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_03
图 5-25. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i= 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
Address
F7
F6
F19
gpmc_ben1
Valid
F7
F6
F19
gpmc_ben0
Valid
F8
F8
F20
F9
gpmc_advn_ale
gpmc_oen_ren
F10
F11
F12
F13
D1
F12
gpmc_ad[15:0]
D0
D3
D2
F21
F22
gpmc_waitj
F23
F23
gpio6_16.clkout1
GPMC_04
图 5-26. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In gpmc_csi, i = 0 to 7.
(2) In gpmc_waitj, j = 0 to 1.
188
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
F6
F6
gpmc_a[10:1]
gpmc_a[27]
Address (MSB)
F17
F17
F17
F17
gpmc_ben1
gpmc_ben0
F17
F17
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
Address (LSB)
D 0
D 3
F22
F21
F23
F23
gpio6_16.clkout1
GPMC_05
图 5-27. GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 0 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
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F1
F1
F0
gpmc_clk
F2
F3
F18
gpmc_csi
F4
gpmc_a[27:1]
gpmc_ben1
gpmc_ben0
Address
F17
F17
F6
F6
F17
F17
F17
F17
F8
F20
F8
F9
gpmc_advn_ale
F14
F14
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
F15
D 1
F15
D 2
F15
D 0
D 3
F21
F22
F23
F23
gpio6_16.clkout1
GPMC_06
图 5-28. GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
(1) In “gpmc_csi”, i = 1 to 7.
(2) In “gpmc_waitj”, j = 0 to 1.
5.10.6.8.2 GPMC/NOR Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-50 and 表 5-51 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-29, 图 5-30, 图 5-31, 图 5-32, 图 5-33 and 图 5-34).
表 5-50. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode
NO.
PARAMETER
tacc(DAT)
DESCRIPTION
MIN
MAX
UNIT
cycles
cycles
(1)
FA5
Data Maximum Access Time (GPMC_FCLK cycles)
H
FA20 tacc1-pgmode(DAT)
Page Mode Successive Data Maximum Access Time (GPMC_FCLK
cycles)
P (2)
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表 5-50. GPMC/NOR Flash Interface Timing Requirements - Asynchronous Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
cycles
ns
(1)
FA21 tacc2-pgmode(DAT)
Page Mode First Data Maximum Access Time (GPMC_FCLK cycles)
Setup time, read gpmc_ad[15:0] valid before gpmc_oen_ren high
Hold time, read gpmc_ad[15:0] valid after gpmc_oen_ren high
H
-
-
tsu(DV-OEH)
th(OEH-DV)
1.9
1
ns
(1) H = Access Time × (TimeParaGranularity + 1)
(2) P = PageBurstAccessTime × (TimeParaGranularity + 1)
表 5-51. GPMC/NOR Flash Interface Switching Characteristics - Asynchronous Mode
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX UNIT
-
-
4.067
4.463
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fallling time, gpmc_ad[15:0] output data
(1)
FA0 tw(nBEV)
Pulse duration, gpmc_ben[1:0] valid time
N
(2)
FA1 tw(nCSV)
Pulse duration, gpmc_cs[7:0] low
A
(3)
(3)
FA3 td(nCSV-nADVIV)
FA4 td(nCSV-nOEIV)
FA9 td(AV-nCSV)
FA10 td(nBEV-nCSV)
FA12 td(nCSV-nADVV)
FA13 td(nCSV-nOEV)
FA16 tw(AIV)
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale invalid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Single read)
Delay time, address bus valid to gpmc_cs[7:0] valid
Delay time, gpmc_ben[1:0] valid to gpmc_cs[7:0] valid
Delay time, gpmc_cs[7:0] valid to gpmc_advn_ale valid
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, address invalid between 2 successive R/W accesses
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren invalid (Burst read)
Pulse duration, address valid : 2nd, 3rd and 4th accesses
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_cs[7:0] valid to gpmc_wen invalid
Delay time, gpmc_ wen valid to data bus valid
B - 2
B + 4
(4)
(5)
(4)
(5)
(5)
(6)
(7)
C - 2
J - 2
J - 2
K - 2
L - 2
G
C + 4
J + 4
J + 4
K + 4
L + 4
(5)
(6)
(7)
(8)
(9)
(9)
FA18 td(nCSV-nOEIV)
FA20 tw(AV)
I - 2
D
I + 4
(10)
(11)
(12)
(11)
(12)
FA25 td(nCSV-nWEV)
FA27 td(nCSV-nWEIV)
FA28 td(nWEV-DV)
FA29 td(DV-nCSV)
FA37 td(nOEV-AIV)
E - 2
F - 2
E + 4
F + 4
2
(5)
(5)
Delay time, data bus valid to gpmc_cs[7:0] valid
J - 2
J + 4
Delay time, gpmc_oen_ren valid to gpmc_ad[15:0] multiplexed address bus
phase end
2
(1) For single read: N = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: N = WrCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: N = (RdCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: N = (WrCycleTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For single write: A = (CSWrOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(3) For reading: B = ((ADVRdOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
For writing: B = ((ADVWrOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
(4) C = ((OEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(5) J = (CSOnTime × (TimeParaGranularity + 1) + 0.5 × CSExtraDelay) × GPMC_FCLK
(6) K = ((ADVOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay - CSExtraDelay)) × GPMC_FCLK
(7) L = ((OEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(8) G = Cycle2CycleDelay × GPMC_FCLK × (TimeParaGranularity +1)
(9) I = ((OEOffTime + (n - 1) × PageBurstAccessTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay - CSExtraDelay)) ×
GPMC_FCLK
(10) D = PageBurstAccessTime × (TimeParaGranularity + 1) × GPMC_FCLK
(11) E = ((WEOnTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK
(12) F = ((WEOffTime - CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay - CSExtraDelay)) × GPMC_FCLK
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GPMC_FCLK
gpmc_clk
FA5
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
gpmc_ben0
Valid
FA0
gpmc_ben1
FA10
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data IN 0
Data IN 0
gpmc_waitj
FA15
FA14
OUT
IN
OUT
DIR
GPMC_07
图 5-29. GPMC / NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value must be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
gpmc_csi
FA5
FA5
FA1
FA1
FA16
FA9
FA9
gpmc_a[27:1]
Address 0
FA0
Address 1
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
Valid
FA0
Valid
FA0
Valid
Valid
FA10
FA10
FA3
FA12
FA3
FA12
gpmc_advn_ale
FA4
FA4
FA13
FA13
gpmc_oen_ren
gpmc_ad[15:0]
Data Upper
gpmc_waitj
FA15
FA15
FA14
OUT
FA14
OUT
DIR
IN
IN
GPMC_08
图 5-30. GPMC / NOR Flash - Asynchronous Read - 32-bit Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA21
FA20
Add1
FA20 FA20
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Add0
Add2
Add3
Add4
FA0
FA10
gpmc_ben0
FA0
FA10
gpmc_ben1
FA12
gpmc_advn_ale
FA18
FA13
gpmc_oen_ren
gpmc_ad[15:0]
D3
D2
D3
D0
D1
gpmc_waitj
FA15
FA14
OUT
OUT
DIR
IN
SPRS91v_GPMC_09
图 5-31. GPMC / NOR Flash - Asynchronous Read - Page Mode 4x16-bit Timing(1)(2)(3)(4)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC
functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data will be internally sampled
by active functional clock edge. FA21 calculation is detailled in a separated application note and should be stored inside AccessTime
register bits field.
(3) FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of GPMC
functional clock cycles. After each access to input Page Data, next input Page Data will be internally sampled by active functional clock
edge after FA20 functional clock cycles. FA20 is also the duration of address phases for successive input Page Data (excluding first
input Page Data). FA20 value should be stored in PageBurstAccessTime register bits field.
(4) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(5) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
194
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gpmc_fclk
gpmc_clk
FA1
gpmc_csi
FA9
gpmc_a[27:1]
Valid Address
FA0
FA10
FA10
gpmc_ben0
gpmc_ben1
FA0
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
FA29
Data OUT
OUT
GPMC_10
图 5-32. GPMC / NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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GPMC_FCLK
gpmc_clk
FA1
FA5
gpmc_csi
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
gpmc_ben0
Valid
FA0
FA10
gpmc_ben1
Valid
FA3
FA12
gpmc_advn_ale
FA4
FA13
gpmc_oen_ren
FA29
FA37
gpmc_ad[15:0]
Data IN
Data IN
Address (LSB)
FA15
FA14
OUT
DIR
OUT
IN
gpmc_waitj
GPMC_11
图 5-33. GPMC / Multiplexed NOR Flash - Asynchronous Read - Single Word Timing(1)(2)(3)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1
(2) FA5 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional clock
cycles. From start of read cycle and after FA5 functional clock cycles, input Data will be internally sampled by active functional clock
edge. FA5 value should be stored inside AccessTime register bits field.
(3) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally
(4) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
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gpmc_fclk
gpmc_clk
gpmc_csi
FA1
FA9
gpmc_a27
gpmc_a[10:1]
Address (MSB)
FA0
FA10
FA10
gpmc_ben0
FA0
gpmc_ben1
FA3
FA12
gpmc_advn_ale
FA27
FA25
gpmc_wen
gpmc_ad[15:0]
gpmc_waitj
DIR
FA29
FA28
Valid Address (LSB)
Data OUT
OUT
GPMC_12
图 5-34. GPMC / Multiplexed NOR Flash - Asynchronous Write - Single Word Timing(1)
(1) In “gpmc_csi”, i = 0 to 7. In “gpmc_waitj”, j = 0 to 1.
(2) The "DIR" (direction control) output signal is NOT pinned out on any of the device pads. It is an internal signal only representing a signal
direction on the GPMC data bus.
5.10.6.8.3 GPMC/NAND Flash Interface Asynchronous Timing
CAUTION
The I/O Timings provided in this section are valid only for some GPMC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-52 and 表 5-53 assume testing over the recommended operating conditions and electrical
characteristic conditions below (see 图 5-35, 图 5-36, 图 5-37 and 图 5-38).
表 5-52. GPMC/NAND Flash Interface Timing Requirements
NO.
GNF12
-
PARAMETER
tacc(DAT)
tsu(DV-OEH)
DESCRIPTION
MIN
MAX
J (1)
UNIT
cycles
ns
Data maximum access time (GPMC_FCLK Cycles)
Setup time, read gpmc_ad[15:0] valid before
gpmc_oen_ren high
1.9
1
-
th(OEH-DV)
Hold time, read gpmc_ad[15:0] valid after
gpmc_oen_ren high
ns
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(1) J = AccessTime × (TimeParaGranularity + 1)
表 5-53. GPMC/NAND Flash Interface Switching Characteristics
NO.
PARAMETER
tr(DO)
tf(DO)
DESCRIPTION
Rising time, gpmc_ad[15:0] output data
MIN
0.447
0.43
MAX UNIT
-
-
4.067
4.463
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Fallling time, gpmc_ad[15:0] output data
GNF0 tw(nWEV)
Pulse duration, gpmc_wen valid time
A (1)
(2)
(2)
GNF1 td(nCSV-nWEV)
GNF2 td(CLEH-nWEV)
GNF3 td(nWEV-DV)
GNF4 td(nWEIV-DIV)
GNF5 td(nWEIV-CLEIV)
GNF6 td(nWEIV-nCSIV)
GNF7 td(ALEH-nWEV)
GNF8 td(nWEIV-ALEIV)
GNF9 tc(nWE)
Delay time, gpmc_cs[7:0] valid to gpmc_wen valid
Delay time, gpmc_ben[1:0] high to gpmc_wen valid
Delay time, gpmc_ad[15:0] valid to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_ad[15:0] invalid
Delay time, gpmc_wen invalid to gpmc_ben[1:0] invalid
Delay time, gpmc_wen invalid to gpmc_cs[7:0] invalid
Delay time, gpmc_advn_ale high to gpmc_wen valid
Delay time, gpmc_wen invalid to gpmc_advn_ale invalid
Cycle time, write cycle time
B - 2
B + 4
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(3)
(4)
(5)
(6)
(7)
(3)
(6)
(8)
(9)
C - 2
D - 2
E - 2
F - 2
G - 2
C - 2
F - 2
C + 4
D + 4
E + 4
F + 4
G + 4
C + 4
F + 4
H
(9)
GNF10 td(nCSV-nOEV)
GNF13 tw(nOEV)
Delay time, gpmc_cs[7:0] valid to gpmc_oen_ren valid
Pulse duration, gpmc_oen_ren valid time
I - 2
I + 4
K (10)
(11)
GNF14 tc(nOE)
Cycle time, read cycle time
L
(12)
(12)
GNF15 td(nOEIV-nCSIV)
Delay time, gpmc_oen_ren invalid to gpmc_cs[7:0] invalid
M - 2
M + 4
(1) A = (WEOffTime – WEOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
(2) B = ((WEOnTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – CSExtraDelay)) × GPMC_FCLK
(3) C = ((WEOnTime – ADVOnTime) × (TimeParaGranularity + 1) + 0.5 × (WEExtraDelay – ADVExtraDelay)) × GPMC_FCLK
(4) D = (WEOnTime × (TimeParaGranularity + 1) + 0.5 × WEExtraDelay ) × GPMC_FCLK
(5) E = (WrCycleTime – WEOffTime × (TimeParaGranularity + 1) – 0.5 × WEExtraDelay ) × GPMC_FCLK
(6) F = (ADVWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (ADVExtraDelay – WEExtraDelay ) × GPMC_FCLK
(7) G = (CSWrOffTime – WEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – WEExtraDelay ) × GPMC_FCLK
(8) H = WrCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(9) I = ((OEOffTime + (n – 1) × PageBurstAccessTime – CSOnTime) × (TimeParaGranularity + 1) + 0.5 × (OEExtraDelay – CSExtraDelay))
× GPMC_FCLK
(10) K = (OEOffTime – OEOnTime) × (1 + TimeParaGranularity) × GPMC_FCLK
(11) L = RdCycleTime × (1 + TimeParaGranularity) × GPMC_FCLK
(12) M = (CSRdOffTime – OEOffTime × (TimeParaGranularity + 1) + 0.5 × (CSExtraDelay – OEExtraDelay ) × GPMC_FCLK
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GPMC_FCLK
GNF1
GNF2
GNF6
GNF5
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
gpmc_wen
GNF0
GNF3
GNF4
Command
gpmc_ad[15:0]
GPMC_13
图 5-35. GPMC / NAND Flash - Command Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
GPMC_FCLK
GNF1
GNF7
GNF6
GNF8
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
Address
GPMC_14
图 5-36. GPMC / NAND Flash - Address Latch Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
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GPMC_FCLK
GNF12
GNF10
GNF15
gpmc_csi
gpmc_ben0
gpmc_advn_ale
GNF14
GNF13
gpmc_oen_ren
gpmc_ad[15:0]
DATA
gpmc_waitj
GPMC_15
图 5-37. GPMC / NAND Flash - Data Read Cycle Timing(1)(2)(3)
(1) GNF12 parameter illustrates amount of time required to internally sample input Data. It is expressed in number of GPMC functional
clock cycles. From start of read cycle and after GNF12 functional clock cycles, input data will be internally sampled by active functional
clock edge. GNF12 value must be stored inside AccessTime register bits field.
(2) GPMC_FCLK is an internal clock (GPMC functional clock) not provided externally.
(3) In gpmc_csi, i = 0 to 7. In gpmc_waitj, j = 0 to 1.
GPMC_FCLK
GNF1
GNF6
gpmc_csi
gpmc_ben0
gpmc_advn_ale
gpmc_oen_ren
GNF9
GNF0
gpmc_wen
GNF3
GNF4
gpmc_ad[15:0]
DATA
GPMC_16
图 5-38. GPMC / NAND Flash - Data Write Cycle Timing(1)
(1) In gpmc_csi, i = 0 to 7.
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-27 and described in Device TRM, Control
Module Chapter.
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Virtual IO Timings Modes must be used to guaranteed some IO timings for GPMC. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 5-54 Virtual Functions Mapping for GPMC for a definition of the Virtual modes.
表 5-54 presents the values for DELAYMODE bitfield.
表 5-54. Virtual Functions Mapping for GPMC
BALL
BALL NAME
Delay Mode Value
GPMC_VIRTUAL1
15
MUXMODE
0
1
2
3
5
6
14(1)
14(1)
H5
gpmc_advn_al
e
gpmc_advn_al
e
gpmc_cs6
gpmc_wait1
gpmc_a2
gpmc_a23
B4
B1
E1
E10
G6
A3
H3
K4
H4
D1
A5
F1
gpmc_ad15
gpmc_ad6
gpmc_ad2
vin2a_d9
13
13
13
9
gpmc_ad15
gpmc_ad6
gpmc_ad2
gpmc_a25
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
15
13
15
14
15
13
15
13
15
9
gpmc_wen
gpmc_ad14
gpmc_a13
gpmc_a8
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
vin2a_d11
gpmc_ad1
gpmc_ad13
gpmc_a2
gpmc_a14
gpmc_ad4
gpmc_a26
gpmc_ad0
gpmc_wait0
gpmc_a20
F6
C10
E2
C4
L2
gpmc_a23
13
13
14
13
9
gpmc_ad1
gpmc_ad13
gpmc_a2
D2
B10
F3
gpmc_ad5
vin2a_d8
gpmc_ad5
gpmc_a26
gpmc_a27
gpmc_cs0
vin2a_hsync0
gpmc_a4
15
9
gpmc_cs0
E8
K3
H2
J1
14
15
14
15
13
gpmc_a4
gpmc_ben0
gpmc_a6
gpmc_ben0
gpmc_a6
gpmc_cs4
K6
B3
gpmc_a15
gpmc_ad11
gpmc_a15
gpmc_ad11
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表 5-54. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
K5
M2
D7
B5
C2
A2
C3
E7
D10
G3
G5
H1
A6
C1
B2
K1
L1
gpmc_a16
gpmc_a1
15
14
15
15
13
13
13
15
9
gpmc_a16
gpmc_a1
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
vin2a_d10
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a24
gpmc_a23
gpmc_ad8
gpmc_ad10
gpmc_ad12
gpmc_a20
gpmc_a18
gpmc_a17
gpmc_a14
gpmc_a22
gpmc_a24
14
15
14
15
13
13
14
14
15
15
15
15
11
14
15
15
14
15
15
13
15
15
14
gpmc_cs3
gpmc_oen_ren
gpmc_a9
gpmc_a1
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
gpmc_cs1
gpmc_ad3
gpmc_ad7
gpmc_a7
gpmc_a3
gpmc_a3
H6
L4
gpmc_ben1
gpmc_clk
gpmc_ben1
gpmc_clk
gpmc_cs5
gpmc_cs7
gpmc_a3
gpmc_a0
gpmc_wait1
C5
G4
C7
J2
gpmc_a22
gpmc_cs2
vin2a_fld0
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
gpmc_a22
gpmc_cs2
gpmc_a16
gpmc_a27
gpmc_a18
gpmc_a10
gpmc_a12
gpmc_a17
gpmc_a5
G1
G2
K2
D6
B6
D3
A4
C6
M1
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a21
gpmc_a27
gpmc_ad9
gpmc_a19
gpmc_a25
gpmc_a0
gpmc_a15
gpmc_a21
gpmc_a13
gpmc_a19
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表 5-54. Virtual Functions Mapping for GPMC (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
GPMC_VIRTUAL1
0
1
2
3
5
6
14(1)
14(1)
D8
F2
L3
vin2a_clk0
gpmc_a18
gpmc_a11
11
15
14
gpmc_a27
gpmc_a17
gpmc_a18
gpmc_a11
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(1) Some signals listed are virtual functions that present alternate multiplexing options. These virtual functions are controlled via
CTRL_CORE_ALT_SELECT_MUX or CTRL_CORE_VIP_MUX_SELECT registers. For more information on how to use these options,
please refer to Device TRM, Chapter Control Module, Section Pad Configuration Registers.
5.10.6.9 Timers
The device has 16 general-purpose (GP) timers (TIMER1 - TIMER16), two watchdog timers, and a 32-kHz
synchronized timer (COUNTER_32K) that have the following features:
•
Dedicated input trigger for capture mode and dedicated output trigger/pulse width modulation (PWM)
signal
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Supported modes:
–
–
–
Compare and capture modes
Auto-reload mode
Start-stop mode
•
On-the-fly read/write register (while counting)
The device has two system watchdog timer (WD_TIMER1 and WD_TIMER2) that have the following
features:
•
•
•
Free-running 32-bit upward counter
On-the-fly read/write register (while counting)
Reset upon occurrence of a timer overflow condition
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2, also called the MPU
watchdog timer.
The watchdog timer is used to provide a recovery mechanism for the device in the event of a fault
condition, such as a non-exiting code loop.
In are presented the specific groupings of signals (IOSET) for use with TIMERS.
注
For additional information on the Timer Module, see the Device TRM.
5.10.6.10 I2C
The device includes 6 inter-integrated circuit (I2C) modules which provide an interface to other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus™) specification version 2.1. External
components attached to this 2-wire serial bus can transmit/receive 8-bit data to/from the device through
the I2C module.
注
Note that, on I2C1 and I2C2, due to characteristics of the open drain IO cells, HS mode is
not supported.
注
Inter-integrated circuit i (i=1 to 6) module is also referred to as I2Ci.
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注
For more information, see the Multimaster High-Speed I2C Controller section of the Device
TRM.
表 5-55, 表 5-56 and 图 5-39 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-55. Timing Requirements for I2C Input Timings(1)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
3
th(SDAL-SCLL)
µs
4
5
6
7
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
100(2)
0(3)
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
th(SCLL-SDAV)
Setup time, SDA valid before SCL high
Hold time, SDA valid after SCL low
250
0(3)
3.45(4)
0.9(4) µs
Pulse duration, SDA high between STOP and
START conditions
8
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
20 + 0.1Cb
9
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300(3) ns
300(3) ns
300(3) ns
300(3) ns
µs
(5)
20 + 0.1Cb
10
11
12
13
(5)
20 + 0.1Cb
(5)
20 + 0.1Cb
300
(5)
Setup time, SCL high before SDA high (for
STOP condition)
tsu(SCLH-SDAH)
tw(SP)
4
0.6
0
14
15
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
50 ns
(5)
Cb
400
400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus™ device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥ 250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line tr max + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
表 5-56. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
Cb = 400 pF (2)
UNIT
MIN
0.294
160
MAX
MIN
MAX
1
2
tc(SCL)
Cycle time, SCL
0.588
µs
ns
tsu(SCLH-SDAL)
Set-up time, SCL high before
SDA low (for a repeated START
condition)
160
3
4
th(SDAL-SCLL)
Hold time, SCL low after SDA
low (for a repeated START
condition)
160
160
160
320
ns
ns
tw(SCLL)
LOW period of the SCLH clock
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表 5-56. Timing Requirements for I2C HS-Mode (I2C3/4/5/6 Only)(1) (continued)
NO.
PARAMETER
DESCRIPTION
Cb = 100 pF MAX
Cb = 400 pF (2)
UNIT
MIN
60
MAX
MIN
120
10
MAX
ns
5
6
tw(SCLH)
HIGH period of the SCLH clock
tsu(SDAV-SCLH)
Setup time, SDA valid vefore
SCL high
10
ns
(3)
(3)
7
th(SCLL-SDAV)
tsu(SCLH-SDAH)
tw(SP)
Hold time, SDA valid after SCL
low
0
70
0
150
ns
ns
ns
pF
pF
13
14
15
16
Setup time, SCL high before
SDA high (for a STOP condition)
160
0
160
0
Pulse duration, spike (must be
suppressed)
10
100
400
10
400
400
(2)
Cb
Capacitive load for SDAH and
SCLH lines
Cb
Capacitive load for SDAH + SDA
line and SCLH + SCL line
(1) I2C HS-Mode is only supported on I2C3/4/5/6. I2C HS-Mode is not supported on I2C1/2.
(2) For bus line loads Cb between 100 and 400 pF the timing parameters must be linearly interpolated.
(3) A device must internally provide a Data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH
signal. An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.
9
11
I2Ci_SDA
I2Ci_SCL
6
8
14
4
13
5
10
1
12
3
7
2
3
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_01
图 5-39. I2C Receive Timing
表 5-57 and 图 5-40 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-57. Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings(2)
STANDARD MODE
FAST MODE
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
MIN
MAX
16
17
tc(SCL)
Cycle time, SCL
10
2.5
µs
µs
Setup time, SCL high before SDA low (for a
repeated START condition)
tsu(SCLH-SDAL)
4.7
4
0.6
0.6
Hold time, SCL low after SDA low (for a
START and a repeated START condition)
18
th(SDAL-SCLL)
µs
19
20
21
tw(SCLL)
Pulse duration, SCL low
4.7
4
1.3
0.6
µs
µs
ns
tw(SCLH)
Pulse duration, SCL high
tsu(SDAV-SCLH)
Setup time, SDA valid before SCL high
250
100
Hold time, SDA valid after SCL low (for I2C
bus devices)
22
th(SCLL-SDAV)
0
3.45
0
0.9 µs
206
Specifications
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表 5-57. Switching Characteristics Over Recommended Operating Conditions for I2C Output
Timings(2) (continued)
STANDARD MODE
FAST MODE
MIN MAX
NO.
PARAMETER
DESCRIPTION
UNIT
MIN
MAX
Pulse duration, SDA high between STOP and
START conditions
23
24
25
26
27
tw(SDAH)
tr(SDA)
tr(SCL)
tf(SDA)
tf(SCL)
4.7
1.3
µs
20 + 0.1Cb
Rise time, SDA
Rise time, SCL
Fall time, SDA
Fall time, SCL
1000
1000
300
300(3) ns
300(3) ns
300(3) ns
300(3) ns
(1) (3)
20 + 0.1Cb
(1) (3)
20 + 0.1Cb
(1) (3)
20 + 0.1Cb
300
(1) (3)
Setup time, SCL high before SDA high (for
STOP condition)
28
29
tsu(SCLH-SDAH)
Cp
4
0.6
µs
Capacitance for each I2C pin
10
10 pF
(1) Cb = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
(2) Software must properly configure the I2C module registers to achieve the timings shown in this table. See the Device TRM for details.
(3) These timings apply only to I2C1 and I2C2. I2C3, I2C4, I2C5 and I2C6 use standard LVCMOS buffers to emulate open-drain buffers
and their rise/fall times should be referenced in the device IBIS model.
注
I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z instead of
driving high when transmitting logic-1.
26
24
I2Ci_SDA
I2Ci_SCL
21
23
19
28
20
25
27
16
18
22
17
18
Stop
Start
Repeated
Start
Stop
SPRS906_TIMING_I2C_02
图 5-40. I2C Transmit Timing
In are presented the specific groupings of signals (IOSET) for use with I2C1/2/3/4/5.
5.10.6.11 UART
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the CPU. There are 10 UART modules in the device. Only one
UART supports IrDA features. Each UART can be used for configuration and data exchange with a
number of external peripheral devices or interprocessor communication between devices
The UARTi (where i = 1 to 10) include the following features:
•
16C750 compatibility
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•
•
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Baud generation based on programmable divisors N (where N = 1…16 384) operating from a fixed
functional clock of 48 MHz or 192 MHz
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
Only UART1 module has extended modem control signals (CD, RI, DTR, DSR)
Only UART3 supports IrDA
注
For more information, see the UART section of the Device TRM.
表 5-58, 表 5-59 and 图 5-41 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-58. Timing Requirements for UART
NO.
4
PARAMETER
DESCRIPTION
MIN
0.96U(1)
0.96U(1)
P(2)
MAX UNIT
tw(RX)
Pulse width, receive data bit, 15/30/100pF high or low
Pulse width, receive start bit, 15/30/100pF high or low
Delay time, transmit start bit to transmit data
Delay time, receive start bit to transmit data
1.05U(1)
1.05U(1)
ns
ns
ns
ns
5
tw(CTS)
td(RTS-TX)
td(CTS-TX)
P(2)
(1) U = UART baud time = 1/programmed baud rate
(2) P = Clock period of the reference clock (FCLK, usually 48 MHz or 192MHz).
表 5-59. Switching Characteristics Over Recommended Operating Conditions for UART
NO.
PARAMETER
DESCRIPTION
MIN
MAX UNIT
15 pF
30 pF
100 pF
12
f(baud)
Maximum programmable baud rate
0.23
MHz
0.115
2
3
tw(TX)
Pulse width, transmit data bit, 15/30/100 pF high or low
Pulse width, transmit start bit, 15/30/100 pF high or low
U - 2(1)
U - 2(1)
U + 2(1)
U + 2(1)
ns
ns
tw(RTS)
(1) U = UART baud time = 1/programmed baud rate
3
2
Start
Bit
UARTi_TXD
Data Bits
5
4
Start
Bit
UARTi_RXD
Data Bits
SPRS906_TIMING_UART_01
图 5-41. UART Timing
208
Specifications
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In are presented the specific groupings of signals (IOSET) for use with UART.
5.10.6.12 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1,
SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip
selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
SPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], whete i = 1 to 4.
注
For more information, see the Serial Communication Interface section of the device TRM.
注
The McSPIm module (m = 1 to 4) is also referred to as SPIm.
CAUTION
The I/O timings provided in this section are applicable for all combinations of
signals for SPI1 and SPI2. However, the timings are valid only for SPI3 and
SPI4 if signals within a single IOSET are used. The IOSETS are defined in 表
5-62.
表 5-60, 图 5-42 and 图 5-43 present Timing Requirements for McSPI - Master Mode.
表 5-60. Timing Requirements for SPI - Master Mode (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SM1
tc(SPICLK)
Cycle time, spi_sclk (1) (2)
SPI1/2/3/
4
20.8 (3)
ns
SM2
SM3
tw(SPICLKL)
tw(SPICLKH)
Typical Pulse duration, spi_sclk low (1)
Typical Pulse duration, spi_sclk high (1)
0.5 × P-1
ns
ns
(4)
0.5 × P-1
(4)
SM4
SM5
tsu(MISO-SPICLK)
th(SPICLK-MISO)
Setup time, spi_d[x] valid before spi_sclk active edge (1)
Hold time, spi_d[x] valid after spi_sclk active edge (1)
3.5
3.7
ns
ns
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表 5-60. Timing Requirements for SPI - Master Mode (1) (continued)
NO.
PARAMETER
DESCRIPTION
Delay time, spi_sclk active edge to spi_d[x] transition (1)
MODE
SPI1
SPI2
SPI3
SPI4
MIN
-3.57
-3.9
MAX
UNIT
ns
SM6
td(SPICLK-SIMO)
4.1
3.6
4.7
4.5
5
ns
-4.9
ns
-4.3
ns
SM7
SM8
td(CS-SIMO)
Delay time, spi_cs[x] active edge to spi_d[x] transition
Delay time, spi_cs[x] active to spi_sclk first edge (1)
ns
td(CS-SPICLK)
MASTER B-4.2 (6)
ns
_PHA0
(5)
MASTER A-4.2 (7)
ns
ns
ns
_PHA1
(5)
SM9
td(SPICLK-CS)
Delay time, spi_sclk last edge to spi_cs[x] inactive (1)
MASTER A-4.2 (7)
_PHA0
(5)
MASTER B-4.2 (6)
_PHA1
(5)
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) Related to the SPI_CLK maximum frequency.
(3) 20.8ns cycle time = 48MHz
(4) P = SPICLK period.
(5) SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
(6) B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
(7) When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS
+ 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
210
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spim_cs(OUT)
spim_sclk(OUT)
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PHA=0
EPOL=1
SM1
SM3
SM8
SM2
SM9
POL=0
POL=1
SM1
SM3
SM2
spim_sclk(OUT)
spim_d(OUT)
SM7
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(OUT)
SM1
SM2
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
spim_d(OUT)
SM6
Bit n-1
SM6
Bit n-2
SM6
Bit n-3
SM6
Bit 1
Bit0
SPRS906_TIMING_McSPI_01
图 5-42. McSPI - Master Mode Transmit
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PHA=0
EPOL=1
spim_cs(OUT)
SM1
SM3
SM8
SM2
SM9
POL=0
spim_sclk(OUT)
SM1
SM3
SM2
POL=1
spim_sclk(OUT)
SM5
SM5
SM4
Bit n-1
SM4
Bit n-2
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(OUT)
SM2
SM1
SM8
SM3
SM2
SM9
POL=0
POL=1
spim_sclk(OUT)
SM1
SM3
spim_sclk(OUT)
SM5
SM4
SM5
SM4
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_02
图 5-43. McSPI - Master Mode Receive
表 5-61, 图 5-44 and 图 5-45 present Timing Requirements for McSPI - Slave Mode.
表 5-61. Timing Requirements for SPI - Slave Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
SS1 (1) tc(SPICLK)
SS2 (1) tw(SPICLKL)
SS3 (1) tw(SPICLKH)
Cycle time, spi_sclk
62.5 (2)
ns
(3)
Typical Pulse duration, spi_sclk low
Typical Pulse duration, spi_sclk high
0.45 × P
ns
ns
(4)
0.45 × P
(4)
SS4 (1) tsu(SIMO-SPICLK)
SS5 (1) th(SPICLK-SIMO)
SS6 (1) td(SPICLK-SOMI)
Setup time, spi_d[x] valid before spi_sclk active edge
Hold time, spi_d[x] valid after spi_sclk active edge
Delay time, spi_sclk active edge to mcspi_somi transition
5
5
2
2
ns
ns
ns
ns
SPI1/2/3
SPI4
26.6
20.1
212
Specifications
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表 5-61. Timing Requirements for SPI - Slave Mode (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX
UNIT
ns
SS7 (5) td(CS-SOMI)
SS8 (1) tsu(CS-SPICLK)
SS9 (1) th(SPICLK-CS)
Delay time, spi_cs[x] active edge to mcspi_somi transition
Setup time, spi_cs[x] valid before spi_sclk first edge
Hold time, spi_cs[x] valid after spi_sclk last edge
20.95
5
5
ns
SPI1/2
SPI3
ns
7.5
6
ns
SPI4
ns
(1) This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2) When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
(3) 62.5ns Cycle time = 16 MHz
(4) P = SPICLK period.
(5) PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
SS1
SS2
spim_sclk(IN)
spim_d(OUT)
SS7
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
Bit n-4
Bit 0
PHA=1
EPOL=1
spim_cs(IN)
spim_sclk(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
SS1
SS3
spim_sclk(IN)
spim_d(OUT)
SS6
Bit n-1
SS6
Bit n-2
SS6
Bit n-3
SS6
Bit 1
Bit 0
SPRS906_TIMING_McSPI_03
图 5-44. McSPI - Slave Mode Transmit
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PHA=0
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS3
SS9
POL=0
POL=1
spim_sclk(IN)
spim_sclk(IN)
SS1
SS2
SS5
SS4
Bit n-1
SS4
SS5
Bit n-2
Bit n-3
Bit n-4
Bit 0
spim_d(IN)
PHA=1
EPOL=1
spim_cs(IN)
SS1
SS2
SS8
SS3
SS2
SS9
POL=0
POL=1
spim_sclk(IN)
spim_sclk(IN)
SS1
SS3
SS4
SS5
SS4
SS5
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
spim_d(IN)
SPRS906_TIMING_McSPI_04
图 5-45. McSPI - Slave Mode Receive
In 表 5-62 are presented the specific groupings of signals (IOSET) for use with SPI3 and SPI4.
表 5-62. McSPI3/4 IOSETs
SIGNALS
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
BALL
MUX
MUX
MUX
MUX
MUX
McSPI3
B18
spi3_cs0
spi3_cs1
spi3_d0
spi3_d1
spi3_sclk
T5
W2
T4
7
1
7
7
7
3
3
3
3
3
D23
2
AA3
W2
AA2
Y4
1
1
1
1
1
A19
B16
A24
B25
C23
2
2
2
N6
N5
B17
A18
Y1
McSPI4
R1
spi4_cs0
spi4_cs1
spi4_cs2
L3
G1
H3
8
8
8
B9
G1
H3
8
8
8
7
8
8
AC4
N6
2
8
8
AB1
N6
1
8
8
N6
T4
T4
T4
214
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SIGNALS
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表 5-62. McSPI3/4 IOSETs (continued)
IOSET1
BALL
IOSET2
BALL
IOSET3
BALL
IOSET4
BALL
IOSET5
BALL
MUX
MUX
MUX
MUX
MUX
spi4_cs3
spi4_d0
spi4_d1
spi4_sclk
H4
J2
8
8
8
8
H4
C8
B8
E8
8
8
8
8
T5
R2
P3
P4
8
7
7
7
T5
AA5
U6
8
2
2
2
T5
AA4
AA1
Y3
8
1
1
1
H1
K4
AC3
5.10.6.13 QSPI
The Quad SPI (QSPI) module is a type of SPI module that allows single, dual or quad read access to
external SPI devices. This module has a memory mapped register interface, which provides a direct
interface for accessing data from external SPI devices and thus simplifying software requirements. It
works as a master only. There is one QSPI module in the device and it is primary intended for fast
booting from quad-SPI flash memories.
General SPI features:
•
•
•
•
•
•
•
•
Programmable clock divider
Six pin interface (DCLK, CS_N, DOUT, DIN, QDIN1, QDIN2)
4 external chip select signals
Support for 3-, 4- or 6-pin SPI interface
Programmable CS_N to DOUT delay from 0 to 3 DCLKs
Programmable signal polarities
Programmable active clock edge
Software controllable interface allowing for any type of SPI transfer
注
For more information, see the Quad Serial Peripheral Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are only valid when all QSPI Chip
Selects used in a system are configured to use the same Clock Mode (either
Clock Mode 0 or Clock Mode 3).
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-63 and 表 5-64 Present Timing and Switching Characteristics for Quad SPI Interface.
表 5-63. Switching Characteristics for QSPI
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q1
tc(SCLK)
Cycle time, sclk
Default Timing Mode,
Clock Mode 0
11.71
ns
Default Timing Mode,
Clock Mode 3
20.8
ns
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表 5-63. Switching Characteristics for QSPI (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q2
tw(SCLKL)
Pulse duration, sclk low
Y × P-1
ns
(1)
Q3
Q4
tw(SCLKH)
Pulse duration, sclk high
Y × P-1
ns
(1)
td(CS-SCLK)
Delay time, sclk falling edge to cs active edge, CS3:0
Default Timing Mode
Default Timing Mode
Default Timing Mode
-M × P-
-M ×
ns
ns
1.6 (2)
P+2.6
(3)
(2) (3)
Q5
td(SCLK-CS)
Delay time, sclk falling edge to cs inactive edge,
CS3:0
N × P-
N ×
1.6 (2)
P+2.6
(3)
(2) (3)
Q6
Q7
Q8
Q9
td(SCLK-D0)
tena(CS-D0LZ)
tdis(CS-D0Z)
td(SCLK-D0)
Delay time, sclk falling edge to d[0] transition
Enable time, cs active edge to d[0] driven (lo-z)
Disable time, cs active edge to d[0] tri-stated (hi-z)
Delay time, sclk first falling edge to first d[0] transition
-1.6
2.6
ns
ns
ns
ns
-P-3.5 -P+2.5
-P-2.5 -P+2.0
PHA=0 Only, Default
Timing Mode
-1.6- 2.6-P(2)
P(2)
(1) The Y parameter is defined as follows:
If DCLK_DIV is 0 or ODD then, Y equals 0.5.
If DCLK_DIV is EVEN then, Y equals (DCLK_DIV/2) / (DCLK_DIV+1).
For best performance, it is recommended to use a DCLK_DIV of 0 or ODD to minimize the duty cycle distortion. The HSDIVIDER on
CLKOUTX2_H13 output of DPLL_PER can be used to achieve the desired clock divider ratio. All required details about clock division
factor DCLK_DIV can be found in the device-specific Technical Reference Manual.
(2) P = SCLK period.
(3) M=QSPI_SPI_DC_REG.DDx + 1 when Clock Mode 0.
M=QSPI_SPI_DC_REG.DDx when Clock Mode 3.
N = 2 when Clock Mode 0.
N = 3 when Clock Mode 3.
cs
Q5
Q1
PHA=1
POL=1
Q4
Q3
Q2
sclk
Q15
Q14
Q12
Q6
Q13
Read Data
Bit 1
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 0
d[0]
Q15
Q14
Q12 Q13
Read Data
Bit 1
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_01
图 5-46. QSPI Read (Clock Mode 3)
216
Specifications
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cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
rtclk
POL=0
Q12
Q13
Q12 Q13
Read Data
Bit 0
Q6
Q7
Q9
Command
Bit n-1
Command
Bit n-2
Read Data
Bit 1
d[0]
Q12 Q13
Read Data
Bit 1
Q12 Q13
Read Data
Bit 0
d[3:1]
SPRS91v_QSPI_02
图 5-47. QSPI Read (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-64. Timing Requirements for QSPI(3)(2)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
Q2
tsu(D-RTCLK)
Setup time, d[3:0] valid before falling rtclk edge
Default Timing Mode,
Clock Mode 0
4.6
ns
tsu(D-SCLK)
th(RTCLK-D)
th(SCLK-D)
tsu(D-SCLK)
th(SCLK-D)
Setup time, d[3:0] valid before falling sclk edge
Hold time, d[3:0] valid after falling rtclk edge
Hold time, d[3:0] valid after falling sclk edge
Default Timing Mode,
Clock Mode 3
12.3
-0.1
0.1
ns
ns
ns
ns
ns
Q13
Default Timing Mode,
Clock Mode 0
Default Timing Mode,
Clock Mode 3
Q14
Q15
Setup time, final d[3:0] bit valid before final falling sclk
edge
Default Timing Mode,
Clock Mode 3
12.3-P
(1)
Hold time, final d[3:0] bit valid after final falling sclk
edge
Default Timing Mode,
Clock Mode 3
0.1+P
(1)
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(1) P = SCLK period.
(2) Clock Modes 1 and 2 are not supported.
(3) The Device captures data on the falling clock edge in Clock Mode 0 and 3, as opposed to the traditional rising clock edge. Although
non-standard, the falling-edge-based setup and hold time timings have been designed to be compatible with standard SPI devices that
launch data on the falling edge in Clock Modes 0 and 3.
cs
Q5
Q1
PHA=1
Q4
Q3
Q2
POL=1
sclk
Q8
Q6
Q6
Q6
Q6
Q7
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_03
图 5-48. QSPI Write (Clock Mode 3)
cs
Q5
Q4
Q1
PHA=0
POL=0
Q2
Q3
sclk
Q8
Q6
Q6
Q7
Q9
Q6
Command
Bit n-1
Command
Bit n-2
Write Data
Bit 1
Write Data
Bit 0
d[0]
d[3:1]
SPRS91v_QSPI_04
图 5-49. QSPI Write (Clock Mode 0)
CAUTION
The I/O Timings provided in this section are valid only for some QSPI usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
218
Specifications
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注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for QSPI. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-65 Manual
Functions Mapping for QSPI for a definition of the Manual modes.
表 5-65 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-65. Manual Functions Mapping for QSPI
BALL
BALL NAME
QSPI1_MANUAL1
CFG REGISTER
MUXMODE
1
A_DELAY (ps)
G_DELAY (ps)
L1
K3
H3
H4
K6
K5
K5
G2
F2
G4
G3
gpmc_a3
gpmc_a4
0
0
0
0
CFG_GPMC_A3_OUT
CFG_GPMC_A4_OUT
CFG_GPMC_A13_IN
CFG_GPMC_A14_IN
CFG_GPMC_A15_IN
CFG_GPMC_A16_IN
CFG_GPMC_A16_OUT
CFG_GPMC_A17_IN
CFG_GPMC_A18_OUT
CFG_GPMC_CS2_OUT
CFG_GPMC_CS3_OUT
qspi1_cs2
qspi1_cs3
qspi1_rtclk
qspi1_d3
qspi1_d2
qspi1_d0
qspi1_d0
qspi1_d1
qspi1_sclk
qspi1_cs0
qspi1_cs1
gpmc_a13
gpmc_a14
gpmc_a15
gpmc_a16
gpmc_a16
gpmc_a17
gpmc_a18
gpmc_cs2
gpmc_cs3
0
0
2247
2176
2229
0
1186
1197
1268
0
2251
0
1217
0
0
0
0
0
5.10.6.14 McASP
The multichannel audio serial port (McASP) functions as a general-purpose audio serial port optimized for
the needs of multichannel audio applications. The McASP is useful for time-division multiplexed (TDM)
stream, Inter-Integrated Sound (I2S) protocols, and intercomponent digital audio interface transmission
(DIT).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
•
•
•
McASP1 and McASP2 modules supporting 16 channels with independent TX/RX clock/sync domain
McASP3 through McASP7 modules supporting 4 channels with independent TX/RX clock/sync domain
McASP8 module supporting 2 channels with independent TX/RX clock/sync domain
注
For more information, see the Serial Communication Interface section of the Device TRM.
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-66, 表 5-67, 表 5-68 and 图 5-50 present Timing Requirements for McASP1 to McASP8
.
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表 5-66. Timing Requirements for McASP1(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
20
MAX
UNIT
ns
Cycle time, AHCLKX
2
tw(AHCLKX)
tc(ACLKRX)
Pulse duration, AHCLKX high or low
Cycle time, ACLKR/X
0.35P (2)
ns
3
20
ns
4
tw(ACLKRX)
Pulse duration, ACLKR/X high or low
0.5R - 3
ns
(3)
5
6
7
8
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKR/X
Hold time, AXR input valid after ACLKR/X
ACLKR/X int
20.5
4
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.7
in
ACLKR/X ext
out
ACLKR/X int
21.6
11.5
ns
ns
ACLKR/X ext
in
ACLKR/X ext
out
ACLKR/X int
-1
ns
ns
ACLKR/X ext
1.8
in
ACLKR/X ext
out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 5-67. Timing Requirements for McASP2(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
(2)
3
4
tc(ACLKX)
Cycle time, ACLKX
Any Other Conditions
20
ns
ns
ACLKX/AFSX (In Sync Mode)
and AXR are all inputs "80M"
Virtual IO Timing Modes
12.5
tw(ACLKX)
Pulse duration, ACLKX high or low
Any Other Conditions
0.5R - 3
ns
ns
(3)
ACLKX/AFSX (In Sync Mode)
and AXR are all inputs "80M"
Virtual IO Timing Modes
0.38R
(3)
5
tsu(AFSX-ACLK)
Setup time, AFSX input valid before ACLKX
ACLKX int
20.3
4.5
ns
ns
ACLKX ext in
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
220
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表 5-67. Timing Requirements for McASP2(1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
-1
MAX UNIT
6
th(ACLK-AFSX)
tsu(AXR-ACLK)
th(ACLK-AXR)
Hold time, AFSX input valid after ACLKX
ACLKX int
ns
ns
ACLKX ext in
ACLKX ext out
1.8
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
7
8
Setup time, AXR input valid before ACLKX
Hold time, AXR input valid after ACLKX
ACLKX int
21.1
4.5
ns
ns
ACLKX ext in
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
ACLKX int
-1
ns
ns
ACLKX ext in
1.8
ACLKX ext out
ACLKX ext in
ACLKX ext out "80M" Virtual IO
Timing Modes
3
ns
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKX period in ns.
表 5-68. Timing Requirements for McASP3/4/5/6/7/8(1)
NO.
1
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
2
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.35P
(2)
3
4
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5R - 3
(3)
5
6
tsu(AFSRX-ACLK)
th(ACLK-AFSRX)
tsu(AXR-ACLK)
Setup time, AFSR/X input valid before ACLKR/X
Hold time, AFSR/X input valid after ACLKR/X
Setup time, AXR input valid before ACLKX
ACLKR/X int
19.7
5.6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKR/X int
-1.1
2.5
ns
ns
ACLKR/X ext in
ACLKR/X ext out
ACLKX int
(ASYNC=0)
20.3
5.1
ns
ns
ns
ns
ACLKR/X ext in
ACLKR/X ext out
8
th(ACLK-AXR)
Hold time, AXR input valid after ACLKX
ACLKX int
(ASYNC=0)
-0.8
2.5
ACLKR/X ext in
ACLKR/X ext out
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1 (NOT SUPPORTED)
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
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2
1
2
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
4
3
4
(A)
(B)
ACLKR/X (CLKRP = CLKXP = 0)
ACLKR/X (CLKRP = CLKXP = 1)
6
5
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
8
7
AXR[n] (Data In/Receive)
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_01
A. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
B. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
图 5-50. McASP Input Timing
CAUTION
The I/O Timings provided in this section are valid only for some McASP usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-69, 表 5-70, 表 5-71 and 图 5-51 present Switching Characteristics Over Recommended Operating
Conditions for McASP1 to McASP8.
222
Specifications
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表 5-69. Switching Characteristics Over Recommended Operating Conditions for McASP1(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-0.9
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
23.1
td(ACLK-AXR)
ACLKR/X int
-1.4
2
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
表 5-70. Switching Characteristics Over Recommended Operating Conditions for McASP2 (1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKX)
tw(ACLKX)
Cycle time, ACLKX
20
ns
ns
Pulse duration, ACLKX high or low
0.5P -
2.5 (3)
13
14
td(ACLK-AFSX)
Delay time, ACLKX transmit edge to AFSX output valid
Delay time, ACLKX transmit edge to AXR output valid
ACLKX int
-1
2
6
ns
ns
ACLKX ext in
ACLKX ext out
23.2
td(ACLK-AXR)
ACLKX int
-1.3
2
6
ns
ns
ACLKX ext in
23.7
ACLKX ext out
(1) ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKX period in ns.
表 5-71. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1)
NO.
9
PARAMETER
tc(AHCLKX)
DESCRIPTION
MODE
MIN
MAX UNIT
Cycle time, AHCLKX
20
ns
ns
10
tw(AHCLKX)
Pulse duration, AHCLKX high or low
0.5P -
2.5 (2)
11
12
tc(ACLKRX)
tw(ACLKRX)
Cycle time, ACLKR/X
20
ns
ns
Pulse duration, ACLKR/X high or low
0.5P -
2.5 (3)
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表 5-71. Switching Characteristics Over Recommended Operating Conditions for
McASP3/4/5/6/7/8(1) (continued)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
-0.5
1.9
MAX UNIT
13
td(ACLK-AFSXR)
Delay time, ACLKR/X transmit edge to AFSX/R output valid
ACLKR/X int
6
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.5
14
td(ACLK-AXR)
Delay time, ACLKR/X transmit edge to AXR output valid
ACLKR/X int
-1.4
1.1
7.1
ns
ns
ACLKR/X ext in
ACLKR/X ext out
24.2
(1) ACLKR internal: ACLKRCTL.CLKRM=1, PDIR.ACLKR = 1
ACLKR external input: ACLKRCTL.CLKRM=0, PDIR.ACLKR=0
ACLKR external output: ACLKRCTL.CLKRM=0, PDIR.ACLKR=1
ACLKX internal: ACLKXCTL.CLKXM=1, PDIR.ACLKX = 1
ACLKX external input: ACLKXCTL.CLKXM=0, PDIR.ACLKX=0
ACLKX external output: ACLKXCTL.CLKXM=0, PDIR.ACLKX=1
(2) P = AHCLKX period in ns.
(3) R = ACLKR/X period in ns.
224
Specifications
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10
10
9
AHCLKX (Falling Edge Polarity)
AHCLKX (Rising Edge Polarity)
12
11
12
(A)
(B)
ACLKR/X (CLKRP = CLKXP = 1)
ACLKR/X (CLKRP = CLKXP = 0)
13
13
13
13
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/T ransmit)
13
13
13
14
15
A0 A1
A30 A31 B0 B1
B30 B31 C0 C1 C2 C3
C31
SPRS906_TIMING_McASP_02
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
图 5-51. McASP Output Timing
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-27 and described in Device TRM, Control
Module Chapter.
表 5-72 through 表 5-79 explain all cases with Virtual Mode Details for McASP1/2/3/4/5/6/7/8 (see 图 5-52
through 图 5-59).
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表 5-72. Virtual Mode Case Details for McASP1
No.
CASE
CASE Description
Virtual Mode Settings
Notes
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX: Output
CLKR / FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
CLKX / FSR: Output
CLKR / FSX: Input
MCASP1_VIRTUAL2_ASYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
CLKR / FSR: Output
CLKX / FSX: Input
CLKR / FSX: Output
CLKX / FSR: Input
MCASP1_VIRTUAL2_ASYNC_RX
Default (No Virtual Mode)
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output CLKX:
Input
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX: Input
CO-FI-
CLKX: Output FSX:
Input
Default (No Virtual Mode)
表 5-73. Virtual Mode Case Details for McASP2
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
FSX: Output
CLKX: Input
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL3_SYNC_RX(1)
MCASP2_VIRTUAL1_SYNC_RX_80M(2)
Default (No Virtual Mode)
CLKX / FSX:
Input
8
CO-FI-
CLKX: Output
FSX: Input
See 图 5-59
Default (No Virtual Mode)
(1) Used up to 50MHz. Should also be used in a CI-FI- mixed case where AXR operate as both inputs and outputs (that is, AXR are
bidirectional).
(2) Used in 80MHz input only mode when AXR, CLKX and FSX are all inputs.
表 5-74. Virtual Mode Case Details for McASP3
No.
CASE
CASE
Description
Virtual Mode Settings
Virtual Mode Value
Notes
Signals
IP Mode : ASYNC
1
COIFOI
CLKX /
FSX: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
226
Specifications
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表 5-74. Virtual Mode Case Details for McASP3 (continued)
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
Default (No Virtual Mode)
2
COIFIO
CIOFIO
CIOFOI
CLKX /
FSR: Output
CLKR /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
See 图 5-53
MCASP3_VIRTUAL2_SYNC_RX
FSX: Input
3
4
CLKR /
FSR: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
See 图 5-54
See 图 5-55
FSX: Input
CLKR /
FSX: Output
CLKX /
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
FSR: Input
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX /
FSX: Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
MCASP3_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX /
FSX: Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 5-75. Virtual Mode Case Details for McASP4
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
Virtual Mode Value
IP Mode : ASYNC
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
MCASP4_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
MCASP4_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX: Output
FSX: Input
Default (No Virtual Mode)
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表 5-76. Virtual Mode Case Details for McASP5
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
MCASP5_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX /
FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX /
FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
MCASP5_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX: Output
FSX: Input
Default (No Virtual Mode)
表 5-77. Virtual Mode Case Details for McASP6
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
MCASP6_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
MCASP6_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
228
Specifications
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表 5-78. Virtual Mode Case Details for McASP7
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
MCASP7_VIRTUAL2_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
MCASP7_VIRTUAL2_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
表 5-79. Virtual Mode Case Details for McASP8
No.
CASE
CASE
Virtual Mode Settings
Notes
Description
Signals
IP Mode : ASYNC
Virtual Mode Value
1
2
3
4
COIFOI
COIFIO
CIOFIO
CIOFOI
CLKX / FSX:
Output CLKR
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
See 图 5-52
See 图 5-53
See 图 5-54
See 图 5-55
MCASP8_VIRTUAL1_SYNC_RX
CLKX / FSR:
Output CLKR
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
Default (No Virtual Mode)
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSR:
Output CLKX
/ FSX: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
CLKR / FSX:
Output CLKX
/ FSR: Input
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKR/FSR
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
IP Mode : SYNC (CLKR / FSR internally generated from CLKX / FSX)
5
6
7
8
CO-FO-
CI-FO-
CI-FI-
CLKX / FSX:
Output
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
AXR(Outputs)/CLKX/FSX
AXR(Inputs)/CLKX/FSX
Default (No Virtual Mode)
Default (No Virtual Mode)
See 图 5-56
See 图 5-57
See 图 5-58
See 图 5-59
FSX: Output
CLKX: Input
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
MCASP8_VIRTUAL1_SYNC_RX
Default (No Virtual Mode)
CLKX / FSX:
Input
CO-FI-
CLKX:
Output FSX:
Input
Default (No Virtual Mode)
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_01
图 5-52. McASP1-8 COIFOI – ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_02
图 5-53. McASP1-8 COIFIO – ASYNC Mode
230
Specifications
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_03
图 5-54. McASP1-8 CIOFIO – ASYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_04
图 5-55. McASP1-8 CIOFOI – ASYNC Mode
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_05
图 5-56. McASP1-8 CO-FO- – SYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_06
图 5-57. McASP1-8 CI-FO- – SYNC Mode
232
Specifications
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SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_07
图 5-58. McASP1-8 CI-FI- – SYNC Mode
SoC IOs
McASP
CLKX
FSX
TXDATA
CLKR
FSR
RXDATA
SPRS906_MCASP_uc_08
图 5-59. McASP1-8 CO-FI- – SYNC Mode
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP1. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 5-80 Virtual Functions Mapping for McASP1 for a definition of the Virtual modes.
表 5-80 presents the values for DELAYMODE bitfield.
表 5-80. Virtual Functions Mapping for McASP1
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP1_VIRTUAL1_SYNC_RX
MCASP1_VIRTUAL2_ASYNC_RX
0
2
C16
H21
E17
A15
H24
B17
A16
A19
K23
K22
H25
A17
B16
D17
A18
B18
C14
C17
E16
F16
B14
D16
A14
J24
mcasp1_aclkx
gpio6_14
15
14
15
14
14
15
14
15
14
14
14
14
15
N/A
15
15
14
15
15
15
15
N/A
14
15
15
14
15
14
13
14
13
13
14
13
14
13
13
13
13
14
14
14
14
13
14
14
14
14
14
13
14
14
13
14
mcasp1_aclkx
mcasp1_axr8
mcasp1_axr13
mcasp1_axr4
xref_clk2
mcasp1_axr13
mcasp1_axr4
mcasp1_axr6
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
gpio6_16
mcasp1_axr9
mcasp1_axr7
mcasp1_axr12
mcasp1_axr10
mcasp1_axr9
gpio6_15
xref_clk3
mcasp1_axr7
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
xref_clk1
mcasp1_axr6
mcasp1_axr10
mcasp1_fsr
mcasp1_axr8
mcasp1_axr11
mcasp1_axr2
mcasp1_fsx
mcasp1_axr14
mcasp1_axr15
mcasp1_axr1
mcasp1_aclkr
mcasp1_axr5
mcasp1_axr5
mcasp1_axr4
D14
B15
J25
mcasp1_axr0
mcasp1_axr3
xref_clk0
mcasp1_axr0
mcasp1_axr3
234
Specifications
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Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP2. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Virtual IO Timings Modes. See 表 5-81 Virtual Functions Mapping for McASP2 for a definition of the Virtual modes.
表 5-81 presents the values for DELAYMODE bitfield.
表 5-81. Virtual Functions Mapping for McASP2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MCASP2_VIRTUAL1
_SYNC_RX_80M
MCASP2_VIRTUAL2
MCASP2_VIRTUAL3
_SYNC_RX
MCASP2_VIRTUAL4
_ASYNC_RX_80M
0
2
_ASYNC_RX
B22
D20
C19
D19
H24
B21
A22
E19
C20
H25
B23
A23
A21
B20
J24
mcasp3_axr0
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
xref_clk2
15
14
14
15
12
15
15
15
14
12
15
15
15
14
10
14
14
10
14
13
13
14
11
14
14
14
13
11
14
14
14
13
9
10
12
12
10
10
10
10
10
12
10
10
10
10
12
8
9
11
11
9
mcasp2_axr14
mcasp2_axr6
mcasp2_axr5
mcasp2_fsx
9
mcasp2_axr10
mcasp2_axr11
mcasp2_axr3
mcasp3_aclkx
mcasp2_aclkx
mcasp2_axr7
xref_clk3
9
mcasp2_axr3
9
mcasp2_axr12
9
mcasp2_aclkx
mcasp2_axr7
11
9
mcasp3_axr1
mcasp3_fsx
mcasp2_axr2
mcasp2_axr4
xref_clk1
8
mcasp2_axr15
mcasp2_axr13
9
9
mcasp2_axr2
mcasp2_axr4
11
6
mcasp2_axr9
mcasp2_axr8
B19
A20
J25
mcasp2_axr1
mcasp2_axr0
xref_clk0
13
13
9
12
12
8
11
11
6
mcasp2_axr1
mcasp2_axr0
Virtual IO Timings Modes must be used to guaranteed some IO timings for McASP3/4/5/6/7/8. See 表 5-28 Modes Summary for a list of IO timings
requiring the use of Virtual IO Timings Modes. See 表 5-82 Virtual Functions Mapping for McASP3/4/5/6/7/8 for a definition of the Virtual modes.
表 5-82 presents the values for DELAYMODE bitfield.
表 5-82. Virtual Functions Mapping for McASP3/4/5/6/7/8
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
0
2
MCASP3_VIRTUAL2_SYNC_RX
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表 5-82. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
B21
A22
B22
B23
A23
A21
mcasp2_axr3
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
8
8
8
6
8
8
mcasp3_axr3
mcasp3_aclkr
mcasp3_aclkx
mcasp3_axr0
mcasp3_axr1
mcasp3_fsx
mcasp3_fsr
mcasp2_axr2
mcasp3_axr2
MCASP4_VIRTUAL1_SYNC_RX
B25
C23
A24
D23
A14
A15
mcasp4_fsx
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp1_axr5
mcasp1_axr4
14
14
14
14
12
12
mcasp4_fsx
mcasp4_aclkx
mcasp4_axr0
mcasp4_axr1
mcasp4_fsr
mcasp4_aclkr
mcasp4_axr3
mcasp4_axr2
MCASP5_VIRTUAL1_SYNC_RX
AC3
U6
mcasp5_aclkx
mcasp5_fsx
14
14
14
12
14
12
mcasp5_aclkx
mcasp5_aclkr
mcasp5_fsr
mcasp5_fsx
AC4
A17
AA5
A16
mcasp5_axr1
mcasp1_axr6
mcasp5_axr0
mcasp1_axr7
mcasp5_axr1
mcasp5_axr2
mcasp5_axr3
mcasp5_axr0
MCASP6_VIRTUAL1_SYNC_RX
C14
B15
B16
B17
A18
B18
mcasp1_axr2
mcasp1_axr3
mcasp1_axr10
mcasp1_axr9
mcasp1_axr8
mcasp1_axr11
12
mcasp6_axr2
mcasp6_axr3
mcasp6_aclkx
mcasp6_axr1
mcasp6_axr0
mcasp6_fsx
12
10
mcasp6_aclkr
mcasp6_fsr
10
10
10
MCASP7_VIRTUAL2_SYNC_RX
A19
F16
E16
E17
mcasp1_axr12
mcasp1_axr15
mcasp1_axr14
mcasp1_axr13
10
10
10
10
mcasp7_axr0
mcasp7_fsx
mcasp7_fsr
mcasp7_aclkx
mcasp7_axr1
mcasp7_aclkr
236
Specifications
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表 5-82. Virtual Functions Mapping for McASP3/4/5/6/7/8 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
1
2
D16
D17
mcasp1_aclkr
mcasp1_fsr
13
13
mcasp7_axr2
mcasp7_axr3
MCASP8_VIRTUAL1_SYNC_RX
B20
C20
D20
C19
mcasp2_axr4
mcasp2_axr7
mcasp2_axr6
mcasp2_axr5
10
10
10
10
mcasp8_axr0
mcasp8_fsx
mcasp8_fsr
mcasp8_aclkx
mcasp8_axr1
mcasp8_aclkr
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5.10.6.15 USB
SuperSpeed USB DRD Subsystem has four instances in the device providing the following functions:
•
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY.
•
•
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY.
USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs.
注
For more information, see the SuperSpeed USB DRD section of the Device TRM.
5.10.6.15.1 USB1 DRD PHY
The USB1 DRD interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
•
USB3.0 Super-Speed PHY port (1.8 V): this asynchronous differential super-speed interface is
compliant with the USB3.0 RX/TX PHY standard (USB3.0 standard v1.0) for a maximum data bit rate
of 5Gbps.
5.10.6.15.2 USB2 PHY
The USB2 interface supports the following applications:
•
USB2.0 High-Speed PHY port (1.8 V and 3.3 V): this asynchronous high-speed interface is compliant
with the USB2.0 PHY standard with an internal transceiver (USB2.0 standard v2.0), for a maximum
data rate of 480 Mbps.
5.10.6.16 USB3 DRD ULPI—SDR—Slave Mode—12-pin Mode
TheUSB3 DRD interfaces support the following application:
•
USB ULPI port: this synchronous interface is compliant with the USB2.0 ULPI SDR standard (UTMI+
v1.22), for alternative off-chip USB2.0 PHY interface; that is, with external transceiver with a maximum
frequency of 60 MHz (synchronous slave mode, SDR, 12-pin, 8-data-bit).
注
The Universal Serial Bus k ULPI modules are also refered as USBk where k = 3, 4.
表 5-83, 表 5-84 and 图 5-60 assume testing over the recommended operating conditions and electrical
characteristic conditions.
表 5-83. Timing Requirements for ULPI SDR Slave Mode
NO.
US1
US5
PARAMETER
tc(clk)
tsu(ctrlV-clkH)
DESCRIPTION
Cycle time, usb_ulpi_clk period
MIN
16.66
6.73
MAX
UNIT
ns
Setup time, usb_ulpi_dir/usb_ulpi_nxt valid before usb_ulpi_clk
rising edge
ns
US6
th(clkH-ctrlV)
Hold time, usb_ulpi_dir/usb_ulpi_nxt valid after usb_ulpi_clk
rising edge
-0.41
ns
US7
US8
tsu(dV-clkH)
th(clkH-dV)
Setup time, usb_ulpi_d[7:0] valid before usb_ulpi_clk rising edge
Hold time, usb_ulpi_d[7:0] valid after usb_ulpi_clk rising edge
6.73
ns
ns
-0.41
238
Specifications
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表 5-84. Switching Characteristics for ULPI SDR Slave Mode
NO.
PARAMETER
td(clkH-stpV)
DESCRIPTION
MIN
MAX
UNIT
US4
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_stp valid
0.44
8.35
ns
US9
td(clkL-doV)
Delay time, usb_ulpi_clk rising edge high to output
usb_ulpi_d[7:0] valid
0.44
8.35
ns
US1
US2
US3
usbk_ulpi_clk
US4
US4
usbk_ulpi_stp
usbk_ulpi_dir_&_nxt
usbk_ulpi_d[7:0]
US6
US5
US7
US9
US8
US9
Data_IN
Data_OUT
SPRS906_TIMING_USB_01
图 5-60. HS USB3 ULPI —SDR—Slave Mode—12-pin Mode
In 表 5-85 are presented the specific groupings of signals (IOSET) for use with USB3 signals.
表 5-85. USB3 IOSETs
SIGNALS
IOSET2
IOSET3
BALL
Y5
MUX
3
BALL
N4
N3
P1
MUX
6
usb3_ulpi_d7
usb3_ulpi_d6
usb3_ulpi_d5
usb3_ulpi_d4
usb3_ulpi_d3
usb3_ulpi_d2
usb3_ulpi_d1
usb3_ulpi_d0
usb3_ulpi_nxt
usb3_ulpi_dir
usb3_ulpi_stp
usb3_ulpi_clk
Y6
3
6
Y2
3
6
Y1
3
N1
P2
6
Y4
3
6
AA2
AA3
W2
Y3
3
N2
R1
R2
P3
6
3
6
3
6
3
6
AA1
AA4
AB1
3
P4
6
3
T5
6
3
T4
6
5.10.6.17 PCIe3
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus
interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe
subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane)
(Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
•
•
•
•
16-bit operation @250 MHz on PIPE interface (per 16-bit lane)
Supports 2 ports x 1 lane or 1 port x 2 lanes configuration
Single virtual channel (VC0), single traffic class (TC0)
Single function in end-point mode
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•
•
•
•
•
•
•
•
•
Automatic width and speed negotiation
Max payload: 128 byte outbound, 256 byte inbound
Automatic credit management
ECRC generation and checking
Configurable BAR filtering
Legacy interrupt reception (RC) and generation (EP)
MSI generation and reception
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
All PCI Device Power Management D-states with the exception of D3cold / L2 state
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and
the PCI Local Bus Specification, revision 3.0.
注
For more information, see the PCIe Controller section of the Device TRM.
5.10.6.18 DCAN
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Direct access to Message RAM during test mode
CAN Rx/Tx pins are configurable as general-purpose IO pins
Two interrupt lines (plus additional parity-error interrupts line)
RAM initialization
DMA support
注
For more information, see the DCAN section of the Device TRM.
注
The Controller Area Network Interface x (x = 1 to 2) is also referred to as DCANx.
注
Refer to the CAN Specification for calculations necessary to validate timing compliance. Jitter
tolerance calculations must be performed to validate the implementation.
表 5-86 and 表 5-87 present timing and switching characteristics for DCANx Interface.
240
Specifications
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表 5-86. Timing Requirements for DCANx Receive
NO.
PARAMETER
DESCRIPTION
Maximum programmable baud rate
MIN
NOM
MAX UNIT
-
-
f(baud)
1
Mbps
ns
td(DCANRX)
Delay time, DCANx_RX pin to receive shift register
15
表 5-87. Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
NO.
PARAMETER
f(baud)
td(DCANTX)
DESCRIPTION
Maximum programmable baud rate
Delay time, Transmit shift register to DCANx_TX pin(1)
MIN
MAX UNIT
-
-
1
Mbps
ns
23
(1) These values do not include rise/fall times of the output buffer.
5.10.6.19 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the Gigabit Media Independent Interface (G/MII)
in MII mode, Reduced Gigabit Media Independent Interface (RGMII), Reduced Media Independent
Interface (RMII), and the Management Data Input/Output (MDIO) for physical layer device (PHY)
management.
注
For more information, see the Ethernet Subsystem section of the Device TRM.
注
The Gigabit, Reduced and Media Independent Interface n (n = 0 to 1) are also referred to as
MIIn, RMIIn and RGMIIn.
CAUTION
The I/O Timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-92, 表 5-95, 表 5-100 and 表
5-107.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
5.10.6.19.1 GMAC MII Timings
表 5-88 and 图 5-61 present timing requirements for MIIn in receive operation.
表 5-88. Timing Requirements for miin_rxclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(RX_CLK)
Cycle time, miin_rxclk
ns
2
3
tw(RX_CLKH)
Pulse duration, miin_rxclk high
Pulse duration, miin_rxclk low
140
14
260
26
ns
ns
tw(RX_CLKL)
140
14
260
26
ns
ns
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表 5-88. Timing Requirements for miin_rxclk - MII Operation (continued)
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
MIN
MAX
UNIT
ns
4
tt(RX_CLK)
Transition time, miin_rxclk
3
3
ns
1
4
2
3
miin_rxclk
4
SPRS906_TIMING_GMAC_MIIRXCLK_01
图 5-61. Clock Timing (GMAC Receive) - MIIn operation
表 5-89 and 图 5-62 present timing requirements for MIIn in transmit operation.
表 5-89. Timing Requirements for miin_txclk - MII Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
10 Mbps
100 Mbps
MIN
400
40
MAX
UNIT
ns
1
tc(TX_CLK)
Cycle time, miin_txclk
ns
2
3
4
tw(TX_CLKH)
tw(TX_CLKL)
tt(TX_CLK)
Pulse duration, miin_txclk high
Pulse duration, miin_txclk low
Transition time, miin_txclk
140
14
260
26
260
26
3
ns
ns
140
14
ns
ns
ns
3
ns
1
4
2
3
miin_txclk
4
SPRS906_TIMING_GMAC_MIITXCLK_02
图 5-62. Clock Timing (GMAC Transmit) - MIIn operation
表 5-90 and 图 5-63 present timing requirements for GMAC MIIn Receive 10/100Mbit/s.
表 5-90. Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
NO.
PARAMETER
tsu(RXD-RX_CLK)
DESCRIPTION
MIN
MAX
UNIT
1
2
tsu(RX_DV-RX_CLK)
tsu(RX_ER-RX_CLK)
th(RX_CLK-RXD)
Setup time, receive selected signals valid before miin_rxclk
8
ns
th(RX_CLK-RX_DV)
th(RX_CLK-RX_ER)
Hold time, receive selected signals valid after miin_rxclk
8
ns
242
Specifications
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1
2
miin_rxclk (Input)
miin_rxd3−miin_rxd0,
miin_rxdv, miin_rxer (Inputs)
SPRS906_TIMING_GMAC_MIIRCV_03
图 5-63. GMAC Receive Interface Timing MIIn operation
表 5-91 and 图 5-64 present timing requirements for GMAC MIIn Transmit 10/100Mbit/s.
表 5-91. Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(TX_CLK-TXD)
DESCRIPTION
MIN
MAX
UNIT
1
Delay time, miin_txclk to transmit selected signals valid
0
25
ns
td(TX_CLK-TX_EN)
1
miin_txclk (input)
miin_txd3 − miin_txd0,
miin_txen (outputs)
SPRS906_TIMING_GMAC_MIITX_04
图 5-64. GMAC Transmit Interface Timing MIIn operation
In 表 5-92 are presented the specific groupings of signals (IOSET) for use with GMAC MII signals.
表 5-92. GMAC MII IOSETs
SIGNALS
IOSET5
IOSET6
BALL
MUX
GMAC MII1
BALL
MUX
mii1_txd3
mii1_txd2
mii1_txd1
mii1_txd0
mii1_rxd3
mii1_rxd2
mii1_rxd1
mii1_rxd0
mii1_col
E11
A13
A12
B12
B10
A10
F10
E10
E13
B13
F11
D13
C13
B11
C11
D11
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
mii1_rxer
mii1_txer
mii1_txen
mii1_crs
mii1_rxclk
mii1_txclk
mii1_rxdv
GMAC MII0
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表 5-92. GMAC MII IOSETs (continued)
SIGNALS
IOSET5
IOSET6
BALL
MUX
BALL
P2
N1
N3
N4
T4
MUX
3
mii0_txd3
mii0_txd2
mii0_txd1
mii0_txd0
mii0_rxd3
mii0_rxd2
mii0_rxd1
mii0_rxd0
mii0_txclk
mii0_txer
mii0_rxer
mii0_rxdv
mii0_crs
3
3
3
3
T5
3
R2
R1
N2
L6
3
3
3
3
P3
N5
P4
L5
3
3
3
mii0_col
3
mii0_rxclk
mii0_txen
N6
P1
3
3
5.10.6.19.2 GMAC MDIO Interface Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-93, 表 5-93 and 图 5-65 present timing requirements for MDIO.
表 5-93. Timing Requirements for MDIO Input
No
PARAMETER
tc(MDC)
DESCRIPTION
MIN
400
160
160
90
MAX
UNIT
ns
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
Cycle time, MDC
tw(MDCH)
Pulse Duration, MDC High
ns
tw(MDCL)
Pulse Duration, MDC Low
ns
tsu(MDIO-MDC)
th(MDIO_MDC)
Setup time, MDIO valid before MDC High
Hold time, MDIO valid from MDC High
ns
0
ns
表 5-94. Switching Characteristics Over Recommended Operating Conditions for MDIO Output
NO
PARAMETER
tt(MDC)
DESCRIPTION
Transition time, MDC
MIN
MAX
5
UNIT
ns
MDIO6
MDIO7
td(MDC-MDIO)
Delay time, MDC High to MDIO valid
10
390
ns
244
Specifications
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1
MDIO2
MDIO3
MDCLK
MDIO6
MDIO6
MDIO4
MDIO5
MDIO
(input)
MDIO7
MDIO
(output)
SPRS906_TIMING_GMAC_MDIO_05
图 5-65. GMAC MDIO diagrams
In 表 5-95 are presented the specific groupings of signals (IOSET) for use with GMAC MDIO signals.
表 5-95. GMAC MDIO IOSETs
SIGNALS
IOSET7
IOSET8
IOSET9
IOSET10
BALL
C10
MUX
BALL
L6
MUX
BALL
Y6
MUX
BALL
E25
MUX
mdio_d
3
3
0
0
1
1
5
5
mdio_mclk
D10
L5
Y5
E24
5.10.6.19.3 GMAC RMII Timings
The main reference clock REF_CLK (RMII_50MHZ_CLK) of RMII interface is internally supplied from
PRCM. The source of this clock could be either externally sourced from the RMII_MHZ_50_CLK pin of the
device or internally generated from DPLL_GMAC output clock GMAC_RMII_HS_CLK. Please see the
PRCM chapter of the device TRM for full details about RMII reference clock.
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-96, 表 5-97 and 图 5-66 present timing requirements for GMAC RMIIn Receive.
表 5-96. Timing Requirements for GMAC REF_CLK - RMII Operation
NO.
PARAMETER
DESCRIPTION
MIN
20
7
MAX
UNIT
ns
RMII1 tc(REF_CLK)
RMII2 tw(REF_CLKH)
RMII3 tw(REF_CLKL)
RMII4 ttt(REF_CLK)
Cycle time, REF_CLK
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
7
ns
ns
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表 5-97. Timing Requirements for GMAC RMIIn Receive
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
RMII5
tsu(RXD-REF_CLK)
tsu(CRS_DV-REF_CLK)
tsu(RX_ER-REF_CLK)
th(REF_CLK-RXD)
Setup time, receive selected signals valid before REF_CLK
4
ns
RMII6
Hold time, receive selected signals valid after REF_CLK
2
ns
th(REF_CLK-CRS_DV)
th(REF_CLK-RX_ER)
RMII1
RMII3
RMII2
RMII4
RMII6
RMII5
REF_CLK (PRCM)
rmiin_rxd1−rmiin_rxd0,
rmiin_crs, rmin_rxer (inputs)
SPRS906_TIMING_GMAC_RGMIITX_09
图 5-66. GMAC Receive Interface Timing RMIIn operation
表 5-98, 表 5-98 and 图 5-67 present switching characteristics for GMAC RMIIn Transmit 10/100Mbit/s.
表 5-98. Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII
Operation
NO.
PARAMETER
tc(REF_CLK)
DESCRIPTION
MIN
20
7
MAX UNIT
RMII7
RMII8
RMII9
Cycle time, REF_CLK
ns
tw(REF_CLKH)
tw(REF_CLKL)
Pulse duration, REF_CLK high
Pulse duration, REF_CLK low
Transistion time, REF_CLK
13
13
3
ns
ns
ns
7
RMII10 tt(REF_CLK)
表 5-99. Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit
10/100 Mbits/s
NO.
PARAMETER
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
td(REF_CLK-TXD)
tdd(REF_CLK-TXEN)
DESCRIPTION
RMIIn
MIN
MAX UNIT
RMII0
2
13.5
13.8
ns
ns
Delay time, REF_CLK high to selected transmit signals
valid
RMII11
RMII1
2
RMII7
RMII8
RMII9
RMII10
RMII11
REF_CLK (PRCM)
rmiin_txd1−rmiin_txd0,
rmiin_txen (Outputs)
SPRS906_TIMING_GMAC_RMIITX_07
图 5-67. GMAC Transmit Interface Timing RMIIn Operation
In 表 5-100 are presented the specific groupings of signals (IOSET) for use with GMAC RMII signals.
246
Specifications
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表 5-100. GMAC RMII IOSETs
SIGNALS
IOSET1
IOSET2
BALL
MUX
GMAC RMII1
BALL
MUX
RMII_MHZ_50_CLK
rmii1_txd1
P5
P2
N1
T4
T5
N6
N2
N5
0
2
2
2
2
2
2
2
rmii1_txd0
rmii1_rxd1
rmii1_rxd0
rmii1_rxer
rmii1_txen
rmii1_crs
GMAC RMII0
RMII_MHZ_50_CLK
rmii0_txd1
P5
N3
N4
R2
R1
P1
P3
P4
0
1
1
1
1
1
1
1
rmii0_txd0
rmii0_rxd1
rmii0_rxd0
rmii0_txen
rmii0_rxer
rmii0_crs
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-101 Manual
Functions Mapping for GMAC RMII0 for a definition of the Manual modes.
表 5-101 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-101. Manual Functions Mapping for GMAC RMII0
BALL
BALL NAME
GMAC_RMII0_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
1
P5
R1
R2
P3
P4
RMII_MHZ_50_CLK
rgmii0_txd0
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXD0_IN
CFG_RGMII0_TXD1_IN
CFG_RGMII0_TXD2_IN
CFG_RGMII0_TXD3_IN
RMII_MHZ_50_CLK
2444
2453
2356
2415
804
981
847
993
rmii0_rxd0
rmii0_rxd1
rmii0_rxer
rmii0_crs
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-102 Manual
Functions Mapping for GMAC RMII1 for a definition of the Manual modes.
表 5-102 list the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-102. Manual Functions Mapping for GMAC RMII1
BALL
BALL NAME
GMAC_RMII1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
2
P5
T5
RMII_MHZ_50_CLK
rgmii0_txctl
0
0
CFG_RMII_MHZ_50_CLK_IN
CFG_RGMII0_TXCTL_IN
RMII_MHZ_50_CLK
2450
909
rmii1_rxd0
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表 5-102. Manual Functions Mapping for GMAC RMII1 (continued)
BALL
BALL NAME
GMAC_RMII1_MANUAL1
CFG REGISTER
MUXMODE
A_DELAY
(ps)
G_DELAY
(ps)
0
2
T4
N6
N5
rgmii0_txc
uart3_txd
uart3_rxd
2327
2553
1943
926
443
CFG_RGMII0_TXC_IN
CFG_UART3_TXD_IN
CFG_UART3_RXD_IN
rmii1_rxd1
rmii1_rxer
rmii1_crs
1110
5.10.6.19.4 GMAC RGMII Timings
CAUTION
The I/O Timings provided in this section are valid only for some GMAC usage
modes when the corresponding Virtual I/O Timings or Manual I/O Timings are
configured as described in the tables found in this section.
表 5-103, 表 5-104 and 图 5-68 present timing requirements for receive RGMIIn operation.
表 5-103. Timing Requirements for rgmiin_rxc - RGMIIn Operation
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX UNIT
1
tc(RXC)
Cycle time, rgmiin_rxc
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(RXCH)
tw(RXCL)
tt(RXC)
Pulse duration, rgmiin_rxc high
Pulse duration, rgmiin_rxc low
Transition time, rgmiin_rxc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-104. Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps (1)
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
5
tsu(RXD-RXCH)
Setup time, receive selected signals valid before
rgmiin_rxc high/low
RGMII0/1
1
ns
6
th(RXCH-RXD)
Hold time, receive selected signals valid after
rgmiin_rxc high/low
RGMII0/1
1
ns
248
Specifications
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(1) For RGMII, receive selected signals include: rgmiin_rxd[3:0] and rgmiin_rxctl.
1
4
2
4
3
rgmiin_rxc(A)
5
1st Half-byte
2nd Half-byte
6
rgmiin_rxd[3:0](B)
rgmiin_rxctl(B)
RGRXD[3:0]
RXDV
RGRXD[7:4]
RXERR
SPRS906_TIMING_GMAC_RGMIIRX_08
A. rgmiin_rxc must be externally delayed relative to the data and control pins.
B. Data and control information is received using both edges of the clocks. rgmiin_rxd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_rxc and data bits 7-4 on the falling edge ofrgmiin_rxc. Similarly, rgmiin_rxctl carries RXDV on
rising edge of rgmiin_rxc and RXERR on falling edge of rgmiin_rxc.
图 5-68. GMAC Receive Interface Timing, RGMIIn operation
表 5-105, 表 5-106 and 图 5-69 present switching characteristics for transmit - RGMIIn for
10/100/1000Mbit/s.
表 5-105. Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn
Operation for 10/100/1000 Mbit/s
NO.
PARAMETER
DESCRIPTION
SPEED
10 Mbps
MIN
360
36
MAX UNIT
1
tc(TXC)
Cycle time, rgmiin_txc
440
44
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
100 Mbps
1000 Mbps
10 Mbps
7.2
160
16
8.8
2
3
4
tw(TXCH)
tw(TXCL)
tt(TXC)
Pulse duration, rgmiin_txc high
Pulse duration, rgmiin_txc low
Transition time, rgmiin_txc
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
160
16
4.4
240
24
100 Mbps
1000 Mbps
10 Mbps
3.6
4.4
0.75
0.75
0.75
100 Mbps
1000 Mbps
表 5-106. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps (1)
NO. PARAMETER
tosu(TXD-TXC)
DESCRIPTION
MODE
MIN
MAX UNIT
5
Output Setup time, transmit selected signals valid to
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
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表 5-106. Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
(1) (continued)
NO. PARAMETER
toh(TXC-TXD)
DESCRIPTION
MODE
MIN
MAX UNIT
6
Output Hold time, transmit selected signals valid after
rgmiin_txc high/low
RGMII0, Internal Delay
Enabled, 1000 Mbps
1.05
ns
(2)
RGMII0, Internal Delay
Enabled, 10/100 Mbps
1.2
ns
ns
ns
RGMII1, Internal Delay
Enabled, 1000 Mbps
1.05
(3)
RGMII1, Internal Delay
Enabled, 10/100 Mbps
1.2
(1) For RGMII, transmit selected signals include: rgmiin_txd[3:0] and rgmiin_txctl.
(2) RGMII0 requires that the 4 data pins rgmii0_txd[3:0] and rgmii0_txctl have their board propagation delays matched within 50pS of
rgmii0_txc.
(3) RGMII1 requires that the 4 data pins rgmii1_txd[3:0] and rgmii1_txctl have their board propagation delays matched within 50pS of
rgmii1_txc.
1
4
2
4
3
rgmiin_txc(A)
[internal delay enabled]
5
rgmiin_txd[3:0](B)
rgmiin_txctl(B)
1st Half-byte
TXEN
2nd Half-byte
TXERR
6
SPRS906_TIMING_GMAC_RGMIITX_09
A. TXC is delayed internally before being driven to the rgmiin_txc pin. This internal delay is always enabled.
B. Data and control information is transmitted using both edges of the clocks. rgmiin_txd[3:0] carries data bits 3-0 on the
rising edge of rgmiin_txc and data bits 7-4 on the falling edge of rgmiin_txc. Similarly, rgmiin_txctl carries TXEN on
rising edge of rgmiin_txc and TXERR of falling edge of rgmiin_txc.
图 5-69. GMAC Transmit Interface Timing RGMIIn operation
In 表 5-107 are presented the specific groupings of signals (IOSET) for use with GMAC RGMII signals.
表 5-107. GMAC RGMII IOSETs
SIGNALS
IOSET3
IOSET4
BALL
MUX
GMAC RGMII1
BALL
MUX
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
rgmii1_rxctl
rgmii1_txc
C11
B12
A12
A13
B13
E13
C13
D13
F11
B11
D11
3
3
3
3
3
3
3
3
3
3
3
rgmii1_txctl
250
Specifications
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表 5-107. GMAC RGMII IOSETs (continued)
SIGNALS
IOSET3
IOSET4
BALL
MUX
BALL
MUX
rgmii1_rxc
E11
3
GMAC RGMII0
rgmii0_txd3
rgmii0_txd2
rgmii0_txd1
rgmii0_txd0
rgmii0_rxd3
rgmii0_rxd2
rgmii0_rxd1
rgmii0_rxd0
rgmii0_txc
P4
P3
R2
R1
N1
P1
N3
N4
T4
P2
N2
T5
0
0
0
0
0
0
0
0
0
0
0
0
rgmii0_rxctl
rgmii0_rxc
rgmii0_txctl
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section "Manual IO Timing Modes" of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information please see the Control Module Chapter in the Device TRM.
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-108 Manual Functions Mapping for GMAC RGMII0 for a definition of the Manual modes.
表 5-108 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-108. Manual Functions Mapping for GMAC RGMII0
BALL
BALL NAME
GMAC_RGMII0_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
N2
P2
N4
N3
P1
N1
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
413
27
3
0
CFG_RGMII0_RXC_IN
CFG_RGMII0_RXCTL_IN
CFG_RGMII0_RXD0_IN
CFG_RGMII0_RXD1_IN
CFG_RGMII0_RXD2_IN
CFG_RGMII0_RXD3_IN
rgmii0_rxc
rgmii0_rxctl
rgmii0_rxd0
rgmii0_rxd1
rgmii0_rxd2
rgmii0_rxd3
2296
1721
1786
1966
2057
134
40
0
T4
T5
R1
R2
P3
P4
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
0
0
0
0
0
0
60
60
60
0
CFG_RGMII0_TXC_OUT
CFG_RGMII0_TXCTL_OUT
CFG_RGMII0_TXD0_OUT
CFG_RGMII0_TXD1_OUT
CFG_RGMII0_TXD2_OUT
CFG_RGMII0_TXD3_OUT
rgmii0_txc
rgmii0_txctl
rgmii0_txd0
rgmii0_txd1
rgmii0_txd2
rgmii0_txd3
60
120
252
Specifications
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Manual IO Timings Modes must be used to guaranteed some IO timings for GMAC. See 表 5-28 Modes Summary for a list of IO timings requiring
the use of Manual IO Timings Modes. See 表 5-109 Manual Functions Mapping for GMAC RGMII1 for a definition of the Manual modes.
表 5-109 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.
表 5-109. Manual Functions Mapping for GMAC RGMII1
BALL
BALL NAME
GMAC_RGMII1_MANUAL1
CFG REGISTER
MUXMODE
3
A_DELAY (ps)
G_DELAY (ps)
E11
F11
B13
E13
C13
D13
vin2a_d18
vin2a_d19
vin2a_d20
vin2a_d21
vin2a_d22
vin2a_d23
530
71
0
CFG_VIN2A_D18_IN
CFG_VIN2A_D19_IN
CFG_VIN2A_D20_IN
CFG_VIN2A_D21_IN
CFG_VIN2A_D22_IN
CFG_VIN2A_D23_IN
rgmii1_rxc
rgmii1_rxctl
rgmii1_rxd3
rgmii1_rxd2
rgmii1_rxd1
rgmii1_rxd0
1099
1337
1517
1331
1328
142
114
171
0
B11
D11
C11
B12
A12
A13
vin2a_d12
vin2a_d13
vin2a_d14
vin2a_d15
vin2a_d16
vin2a_d17
0
170
150
0
0
0
0
0
0
0
CFG_VIN2A_D12_OUT
CFG_VIN2A_D13_OUT
CFG_VIN2A_D14_OUT
CFG_VIN2A_D15_OUT
CFG_VIN2A_D16_OUT
CFG_VIN2A_D17_OUT
rgmii1_txc
rgmii1_txctl
rgmii1_txd3
rgmii1_txd2
rgmii1_txd1
rgmii1_txd0
60
60
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5.10.6.20 eMMC/SD/SDIO
The Device includes the following external memory interfaces 4 MultiMedia Card/Secure Digital/Secure
Digital Input Output Interface (MMC/SD/SDIO)
注
The eMMC/SD/SDIOi (i = 1 to 4) controller is also referred to as MMCi.
5.10.6.20.1 MMC1—SD Card Interface
MMC1 interface is compliant with the SD Standard v3.01 and it supports the following SD Card
applications:
•
•
•
•
•
•
•
Default speed, 4-bit data, SDR, half-cycle
High speed, 4-bit data, SDR, half-cycle
SDR12, 4-bit data, half-cycle
SDR25, 4-bit data, half-cycle
UHS-I SDR50, 4-bit data, half-cycle
UHS-I SDR104, 4-bit data, half-cycle
UHS-I DDR50, 4-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
5.10.6.20.1.1 Default speed, 4-bit data, SDR, half-cycle
表 5-110 and 表 5-111 present Timing requirements and Switching characteristics for MMC1 - Default
Speed in receiver and transmitter mode (see 图 5-70 and 图 5-71).
表 5-110. Timing Requirements for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
DSSD5 tsu(cmdV-clkH)
DSSD6 th(clkH-cmdV)
DSSD7 tsu(dV-clkH)
DSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
20.46
5.11
ns
ns
20.46
ns
表 5-111. Switching Characteristics for MMC1 - SD Card Default Speed Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DSSD0 fop(clk)
DSSD1 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5 × P-
(1)
0.185
DSSD2 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
DSSD3 td(clkL-cmdV)
DSSD4 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
254
Specifications
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(1) P = output mmc1_clk period in ns
DSSD2
DSSD1
DSSD0
mmc1_clk
mmc1_cmd
DSSD6
DSSD5
DSSD8
DSSD7
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_01
图 5-70. MMC/SD/SDIO in - Default Speed - Receiver Mode
DSSD2
DSSD1
DSSD0
mmc1_clk
DSSD3
DSSD4
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_02
图 5-71. MMC/SD/SDIO in - Default Speed - Transmitter Mode
5.10.6.20.1.2 High speed, 4-bit data, SDR, half-cycle
表 5-112 and 表 5-113 present Timing requirements and Switching characteristics for MMC1 - High Speed
in receiver and transmitter mode (see 图 5-72 and 图 5-73).
表 5-112. Timing Requirements for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
HSSD3 tsu(cmdV-clkH)
HSSD4 th(clkH-cmdV)
HSSD7 tsu(dV-clkH)
HSSD8 th(clkH-dV)
Setup time, mmc1_cmd valid before mmc1_clk rising clock edge
Hold time, mmc1_cmd valid after mmc1_clk rising clock edge
Setup time, mmc1_dat[3:0] valid before mmc1_clk rising clock edge
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising clock edge
ns
ns
ns
表 5-113. Switching Characteristics for MMC1 - SD Card High Speed
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HSSD1 fop(clk)
HSSD2H tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5 × P-
(1)
0.185
HSSD2L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
HSSD5 td(clkL-cmdV)
HSSD6 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-7.6
-7.6
3.6
3.6
ns
ns
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(1) P = output mmc1_clk period in ns
HSSD1
HSSD2H
HSSD4
HSSD2L
mmc1_clk
mmc1_cmd
HSSD3
HSSD7
HSSD8
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_03
图 5-72. MMC/SD/SDIO in - High Speed - Receiver Mode
HSSD1
HSSD2H
HSSD2L
HSSD5
mmc1_clk
mmc1_cmd
HSSD5
HSSD6
HSSD6
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_04
图 5-73. MMC/SD/SDIO in - High Speed - Transmitter Mode
5.10.6.20.1.3 SDR12, 4-bit data, half-cycle
表 5-114 and 表 5-115 present Timing requirements and Switching characteristics for MMC1 - SDR12 in
receiver and transmitter mode (see 图 5-74 and 图 5-75).
表 5-114. Timing Requirements for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR12 tsu(cmdV-clkH)
5
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
25.99
ns
SDR12 th(clkH-cmdV)
6
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
ns
Internal Loopback Clock
SDR12 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
25.99
SDR12 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 5-115. Switching Characteristics for MMC1 - SD Card SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
24
0.5 × P-
(1)
0.185
SDR122 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185(1)
ns
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
256
Specifications
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(1) P = output mmc1_clk period in ns
SDR122
SDR121
SDR120
mmc1_clk
mmc1_cmd
SDR126
SDR125
SDR128
SDR127
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_05
图 5-74. MMC/SD/SDIO in - High Speed SDR12 - Receiver Mode
SDR122
SDR121
SDR120
SDR123
SDR124
mmc1_clk
mmc1_cmd
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_06
图 5-75. MMC/SD/SDIO in - High Speed SDR12 - Transmitter Mode
5.10.6.20.1.4 SDR25, 4-bit data, half-cycle
表 5-116 and 表 5-117 present Timing requirements and Switching characteristics for MMC1 - SDR25 in
receiver and transmitter mode (see 图 5-76 and 图 5-77).
表 5-116. Timing Requirements for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR25 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
5.3
ns
SDR25 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.6
5.3
ns
ns
SDR25 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
SDR25 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.6
1.6
ns
ns
Internal Loopback Clock
表 5-117. Switching Characteristics for MMC1 - SD Card SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR252L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
ns
(1)
SDR255 td(clkL-cmdV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
-8.8
6.6
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表 5-117. Switching Characteristics for MMC1 - SD Card SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR256 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
(1) P = output mmc1_clk period in ns
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmc1_clk
mmc1_cmd
SDR257
SDR258
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_07
图 5-76. MMC/SD/SDIO in - High Speed SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
HSSDR255
SDR256
mmc1_clk
mmc1_cmd
SDR255
SDR256
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_08
图 5-77. MMC/SD/SDIO in - High Speed SDR25 - Transmitter Mode
5.10.6.20.1.5 UHS-I SDR50, 4-bit data, half-cycle
表 5-118 and 表 5-119 present Timing requirements and Switching characteristics for MMC1 - SDR50 in
receiver and transmitter mode (see 图 5-78 and 图 5-79).
表 5-118. Timing Requirements for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
SDR50 tsu(cmdV-clkH)
3
Setup time, mmc1_cmd valid before mmc1_clk rising
clock edge
1.48
ns
SDR50 th(clkH-cmdV)
4
Hold time, mmc1_cmd valid after mmc1_clk rising
clock edge
1.7
ns
ns
SDR50 tsu(dV-clkH)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
rising clock edge
1.48
SDR50 th(clkH-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk rising
clock edge
Pad Loopback Clock
1.7
1.6
ns
ns
Internal Loopback Clock
表 5-119. Switching Characteristics for MMC1 - SD Card SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
96
SDR502 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR502L tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-8.8
6.6
ns
ns
-3.66
1.46
258
Specifications
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(1) P = output mmc1_clk period in ns
SDR501
SDR502L
SDR502H
SDR504
mmc1_clk
mmc1_cmd
SDR503
SDR507
SDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_09
图 5-78. MMC/SD/SDIO in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmc1_clk
mmc1_cmd
SDR505
SDR506
SDR506
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_10
图 5-79. MMC/SD/SDIO in - High Speed SDR50 - Transmitter Mode
5.10.6.20.1.6 UHS-I SDR104, 4-bit data, half-cycle
表 5-120 presents Timing requirements and Switching characteristics for MMC1 - SDR104 in receiver and
transmitter mode (see 图 5-80 and 图 5-81).
表 5-120. Switching Characteristics for MMC1 - SD Card SDR104 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR1041 fop(clk)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
192
SDR1042 tw(clkH)
H
0.5 × P-
(1)
0.185
SDR1042 tw(clkL)
L
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
SDR1045 td(clkL-cmdV)
SDR1046 td(clkL-dV)
Delay time, mmc1_clk falling clock edge to mmc1_cmd transition
Delay time, mmc1_clk falling clock edge to mmc1_dat[3:0] transition
-1.09
-1.09
0.49
0.49
ns
ns
(1) P = output mmc1_clk period in ns
SDR1041
SDR1042L
SDR1042H
SDR1044
mmc1_clk
mmc1_cmd
SDR1043
SDR1047
SDR1048
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_11
图 5-80. MMC/SD/SDIO in - High Speed SDR104 - Receiver Mode
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SDR1041
SDR1042H
SDR1042L
SDR1045
mmc1_clk
mmc1_cmd
SDR1045
SDR1046
SDR1046
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_12
图 5-81. MMC/SD/SDIO in - High Speed SDR104 - Transmitter Mode
5.10.6.20.1.7 UHS-I DDR50, 4-bit data
表 5-121 and 表 5-122 present Timing requirements and Switching characteristics for MMC1 - DDR50 in
receiver and transmitter mode (see 图 5-82 and 图 5-83).
表 5-121. Timing Requirements for MMC1 - SD Card DDR50 Mode
PARAME
NO.
DESCRIPTION
MODE
MIN
MAX UNIT
TER
DDR50 tsu(cmdV-clk) Setup time, mmc1_cmd valid before mmc1_clk
transition
1.79
ns
5
DDR50 th(clk-cmdV) Hold time, mmc1_cmd valid after mmc1_clk transition
6
2
ns
DDR50 tsu(dV-clk)
7
Setup time, mmc1_dat[3:0] valid before mmc1_clk
transition
Pad Loopback
1.79
1.79
2
ns
ns
ns
ns
Internal Loopback
Pad Loopback
DDR50 th(clk-dV)
8
Hold time, mmc1_dat[3:0] valid after mmc1_clk
transition
Internal Loopback
1.6
表 5-122. Switching Characteristics for MMC1 - SD Card DDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
DDR500 fop(clk)
DDR501 tw(clkH)
Operating frequency, mmc1_clk
Pulse duration, mmc1_clk high
48
0.5 × P-
(1)
0.185
DDR502 tw(clkL)
Pulse duration, mmc1_clk low
0.5 × P-
0.185
ns
(1)
DDR503 td(clk-cmdV)
DDR504 td(clk-dV)
Delay time, mmc1_clk transition to mmc1_cmd transition
Delay time, mmc1_clk transition to mmc1_dat[3:0] transition
1.225
1.225
6.6
6.6
ns
ns
(1) P = output mmc1_clk period in ns
DDR500
DDR501
DDR502
mmc1_clk
DDR505
DDR506
mmc1_cmd
DDR507
DDR508
DDR507
DDR508
mmc1_dat[3:0]
SPRS906_TIMING_MMC1_13
图 5-82. SDMMC - High Speed SD - DDR - Data/Command Receive
260
Specifications
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DDR500
DDR501
DDR502
mmc1_clk
DDR503(max)
DDR503(min)
mmc1_cmd
DDR504(max)
DDR504(min)
DDR504(max)
DDR504(min)
mmc1_dat[3:0]
MMC1_14
图 5-83. SDMMC - High Speed SD - DDR - Data/Command Transmit
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-27 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-123 Virtual
Functions Mapping for MMC1 for a definition of the Virtual modes.
表 5-123 presents the values for DELAYMODE bitfield.
表 5-123. Virtual Functions Mapping for MMC1
BALL
BALL NAME
Delay Mode Value
MUXMODE
0
MMC1_
MMC1_
MMC1_
MMC1_
VIRTUAL1
VIRTUAL4
VIRTUAL5
VIRTUAL6
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
15
15
15
15
15
15
12
12
12
12
12
12
11
11
11
11
11
11
10
10
10
10
10
10
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC1. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-124 Manual
Functions Mapping for MMC1 for a definition of the Manual modes.
表 5-124 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
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表 5-124. Manual Functions Mapping for MMC1
BALL
BALL NAME
MMC1_MANUAL1
MMC1_MANUAL2
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
A_DELAY (ps)
G_DELAY (ps)
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
588
0
0
0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
CFG_MMC1_CLK_IN
CFG_MMC1_CMD_IN
CFG_MMC1_DAT0_IN
CFG_MMC1_DAT1_IN
CFG_MMC1_DAT2_IN
CFG_MMC1_DAT3_IN
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1000
1375
1000
1000
1000
U3
V4
V3
V2
W1
V1
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
1230
0
0
0
0
0
0
0
520
0
320
0
CFG_MMC1_CLK_OUT
CFG_MMC1_CMD_OUT
CFG_MMC1_DAT0_OUT
CFG_MMC1_DAT1_OUT
CFG_MMC1_DAT2_OUT
CFG_MMC1_DAT3_OUT
mmc1_clk
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
56
76
91
99
40
83
98
106
0
0
0
0
V4
V3
V2
W1
V1
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
0
0
0
0
0
0
0
0
0
0
51
0
0
0
0
0
0
CFG_MMC1_CMD_OEN
CFG_MMC1_DAT0_OEN
CFG_MMC1_DAT1_OEN
CFG_MMC1_DAT2_OEN
CFG_MMC1_DAT3_OEN
mmc1_cmd
mmc1_dat0
mmc1_dat1
mmc1_dat2
mmc1_dat3
363
199
273
5.10.6.20.2 MMC2 — eMMC
MMC2 interface is compliant with the JC64 eMMC Standard v4.5 and it supports the following eMMC applications:
•
•
•
•
Standard JC64 SDR, 8-bit data, half cycle
High-speed JC64 SDR, 8-bit data, half cycle
High-speed HS200 JEDS84, 8-bit data, half cycle
High-speed JC64 DDR, 8-bit data
注
For more information, see the eMMC/SD/SDIO chapter of the Device TRM.
262
Specifications
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5.10.6.20.2.1 Standard JC64 SDR, 8-bit data, half cycle
表 5-125 and 表 5-126 present Timing requirements and Switching characteristics for MMC2 - Standart SDR in receiver and transmitter mode (see
图 5-84 and 图 5-85).
表 5-125. Timing Requirements for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
13.19
8.4
MAX
UNIT
ns
SSDR5
SSDR6
SSDR7
SSDR8
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
13.19
8.4
ns
th(clkH-dV)
ns
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表 5-126. Switching Characteristics for MMC2 - JC64 Standard SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SSDR1 fop(clk)
SSDR2H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
24
0.5 × P-
(1)
0.172
SSDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
SSDR3 td(clkL-cmdV)
SSDR4 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-16.96
-16.96
16.96
16.96
ns
ns
(1) P = output mmc2_clk period in ns
SSDR2
SSDR1
SSDR2
mmc2_clk
SSDR6
SSDR8
SSDR5
mmc2_cmd
SSDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_01
图 5-84. MMC/SD/SDIO in - Standard JC64 - Receiver Mode
SSDR2
SSDR2
SSDR1
SSDR3
SSDR4
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_02
图 5-85. MMC/SD/SDIO in - Standard JC64 - Transmitter Mode
5.10.6.20.2.2 High-speed JC64 SDR, 8-bit data, half cycle
表 5-127 and 表 5-128 present Timing requirements and Switching characteristics for MMC2 - High speed
SDR in receiver and transmitter mode (see 图 5-86 and 图 5-87).
表 5-127. Timing Requirements for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.6
2.6
5.6
2.6
MAX
UNIT
ns
JC643 tsu(cmdV-clkH)
JC644 th(clkH-cmdV)
JC647 tsu(dV-clkH)
JC648 th(clkH-dV)
Setup time, mmc2_cmd valid before mmc2_clk rising clock edge
Hold time, mmc2_cmd valid after mmc2_clk rising clock edge
Setup time, mmc2_dat[7:0] valid before mmc2_clk rising clock edge
Hold time, mmc2_dat[7:0] valid after mmc2_clk rising clock edge
ns
ns
ns
264
Specifications
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表 5-128. Switching Characteristics for MMC2 - JC64 High Speed SDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
JC641 fop(clk)
JC642H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
48
0.5 × P-
(1)
0.172
JC642L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
JC645 td(clkL-cmdV)
JC646 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-6.64
-6.64
6.64
6.64
ns
ns
(1) P = output mmc2_clk period in ns
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC643
JC644
JC647
JC648
SPRS906_TIMING_MMC2_03
图 5-86. MMC/SD/SDIO in - High Speed JC64 - Receiver Mode
JC641
JC642L
JC642H
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
JC645
JC645
JC646
JC646
MMC2_04
图 5-87. MMC/SD/SDIO in - High Speed JC64 - transmitter Mode
5.10.6.20.2.3 High-speed HS200 JEDS84 SDR, 8-bit data, half cycle
表 5-129 presents Switching characteristics for MMC2 - HS200 in transmitter mode (see 图 5-88).
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表 5-129. Switching Characteristics for MMC2 - JEDS84 HS200 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
HS2001 fop(clk)
HS2002H tw(clkH)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
192
0.5 × P-
(1)
0.172
HS2002L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
HS2005 td(clkL-cmdV)
HS2006 td(clkL-dV)
Delay time, mmc2_clk falling clock edge to mmc2_cmd transition
Delay time, mmc2_clk falling clock edge to mmc2_dat[7:0] transition
-1.136
-1.136
0.536
0.536
ns
ns
(1) P = output mmc2_clk period in ns
HS2001
HS2002H
HS2002L
mmc2_clk
mmc2_cmd
mmc2_dat[7:0]
HS2005
HS2006
HS2005
HS2006
MMC2_05
图 5-88. eMMC in - HS200 SDR - Transmitter Mode
5.10.6.20.2.4 High-speed JC64 DDR, 8-bit data
表 5-130 and 表 5-131 present Timing requirements and Switching characteristics for MMC2 - High speed
DDR in receiver and transmitter mode (see 图 5-89 and 图 5-90).
表 5-130. Timing Requirements for MMC2 - JC64 High Speed DDR Mode
NO. PARAMETER
DESCRIPTION
MODE
MIN
MAX UNIT
DDR3 tsu(cmdV-clk)
Setup time, mmc2_cmd valid before mmc2_clk
transition
1.8
ns
DDR4 th(clk-cmdV)
DDR7 tsu(dV-clk)
DDR8 th(clk-dV)
Hold time, mmc2_cmd valid after mmc2_clk
transition
1.6
1.8
ns
ns
ns
ns
ns
ns
ns
Setup time, mmc2_dat[7:0] valid before mmc2_clk
transition
Hold time, mmc2_dat[7:0] valid after mmc2_clk
transition
Pad Loopback (1.8V and 3.3V),
Boot
1.6
Internal Loopback (1.8V with
MMC2_VIRTUAL2)
1.86
1.95
Internal Loopback (3.3V with
MMC2_VIRTUAL2)
Internal Loopback (1.8V with
MMC2_MANUAL2)
Internal Loopback (3.3V with
MMC2_MANUAL2)
1.6
表 5-131. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
48
UNIT
MHz
ns
DDR1
fop(clk)
Operating frequency, mmc2_clk
Pulse duration, mmc2_clk high
DDR2H tw(clkH)
0.5 × P-
(1)
0.172
DDR2L tw(clkL)
Pulse duration, mmc2_clk low
0.5 × P-
0.172
ns
(1)
266
Specifications
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表 5-131. Switching Characteristics for MMC2 - JC64 High Speed DDR Mode (continued)
NO.
PARAMETER
td(clk-cmdV)
td(clk-dV)
DESCRIPTION
MIN
2.9
MAX
7.14
7.14
UNIT
ns
DDR5
DDR6
Delay time, mmc2_clk transition to mmc2_cmd transition
Delay time, mmc2_clk transition to mmc2_dat[7:0] transition
2.9
ns
(1) P = output mmc2_clk period in ns
DDR1
DDR2H
DDR2L
DDR3
mmc2_clk
DDR4
mmc2_cmd
DDR8
DDR8
DDR8
DDR7
DDR7
DDR7
DDR7
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_07
图 5-89. MMC/SD/SDIO in - High Speed DDR JC64 - Receiver Mode
DDR1
DDR2
DDR2
DDR5
mmc2_clk
DDR5
DDR5
DDR5
mmc2_cmd
DDR6
DDReMMC6
DDReMMC6
DDR6
DDR6
DDR6
mmc2_dat[7:0]
SPRS906_TIMING_MMC2_08
图 5-90. MMC/SD/SDIO in - High Speed DDR JC64 - Transmitter Mode
注
To configure the desired virtual mode the user must set MODESELECT bit and
DELAYMODE bitfield for each corresponding pad control register.
The pad control registers are presented in 表 4-27 and described in Device TRM, Control
Module Chapter.
Virtual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Virtual IO Timings Modes. See 表 5-132 Virtual
Functions Mapping for MMC2 for a definition of the Virtual modes.
表 5-132 presents the values for DELAYMODE bitfield.
表 5-132. Virtual Functions Mapping for MMC2
BALL
BALL NAME
Delay Mode Value
MUXMODE
1
MMC2_VIRTUAL2
A6
A4
gpmc_cs1
gpmc_a19
13
13
mmc2_cmd
mmc2_dat4
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表 5-132. Virtual Functions Mapping for MMC2 (continued)
BALL
BALL NAME
Delay Mode Value
MUXMODE
MMC2_VIRTUAL2
1
E7
D6
C5
B5
D7
C6
A5
B6
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
13
13
13
13
13
13
13
13
mmc2_dat5
mmc2_dat6
mmc2_dat7
mmc2_clk
mmc2_dat0
mmc2_dat1
mmc2_dat2
mmc2_dat3
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC2. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-133 Manual
Functions Mapping for MMC2 for a definition of the Manual modes.
表 5-133 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-133. Manual Functions Mapping for MMC2
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
(ps)
(ps)
A4
E7
D6
C5
B5
D7
C6
A5
B6
A6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
14
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CFG_GPMC_A19_IN mmc2_dat4
CFG_GPMC_A20_IN mmc2_dat5
CFG_GPMC_A21_IN mmc2_dat6
CFG_GPMC_A22_IN mmc2_dat7
119
0
0
127
22
72
410
82
0
0
0
0
18
894
30
0
0
0
0
4000
CFG_GPMC_A23_IN
mmc2_clk
0
0
0
0
0
0
CFG_GPMC_A24_IN mmc2_dat0
CFG_GPMC_A25_IN mmc2_dat1
CFG_GPMC_A26_IN mmc2_dat2
CFG_GPMC_A27_IN mmc2_dat3
CFG_GPMC_CS1_IN mmc2_cmd
0
23
0
0
77
0
0
0
0
0
A4
E7
D6
C5
B5
D7
C6
A5
B6
A6
gpmc_a19
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a23
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
152
206
78
2
0
0
0
0
0
0
0
0
0
0
152
206
78
2
0
0
0
0
0
0
0
0
0
0
285
189
0
0
0
CFG_GPMC_A19_OUT mmc2_dat4
CFG_GPMC_A20_OUT mmc2_dat5
CFG_GPMC_A21_OUT mmc2_dat6
CFG_GPMC_A22_OUT mmc2_dat7
CFG_GPMC_A23_OUT mmc2_clk
CFG_GPMC_A24_OUT mmc2_dat0
CFG_GPMC_A25_OUT mmc2_dat1
CFG_GPMC_A26_OUT mmc2_dat2
CFG_GPMC_A27_OUT mmc2_dat3
CFG_GPMC_CS1_OUT mmc2_cmd
120
70
360
0
0
266
0
266
0
730
0
0
0
0
0
43
0
43
0
70
0
0
0
0
0
0
120
A4
gpmc_a19
0
0
0
0
0
0
CFG_GPMC_A19_OEN mmc2_dat4
268
Specifications
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表 5-133. Manual Functions Mapping for MMC2 (continued)
BAL BALL NAME
L
MMC2_MANUAL1
MMC2_MANUAL2
MMC2_MANUAL3
CFG REGISTER
MUXMODE
1
A_DELAY G_DELAY A_DELAY G_DELAY A_DELAY G_DELAY
(ps)
0
(ps)
0
(ps)
0
(ps)
0
(ps)
231
39
(ps)
0
E7
D6
C5
D7
C6
A5
B6
A6
gpmc_a20
gpmc_a21
gpmc_a22
gpmc_a24
gpmc_a25
gpmc_a26
gpmc_a27
gpmc_cs1
CFG_GPMC_A20_OEN mmc2_dat5
CFG_GPMC_A21_OEN mmc2_dat6
CFG_GPMC_A22_OEN mmc2_dat7
CFG_GPMC_A24_OEN mmc2_dat0
CFG_GPMC_A25_OEN mmc2_dat1
CFG_GPMC_A26_OEN mmc2_dat2
CFG_GPMC_A27_OEN mmc2_dat3
0
0
0
0
0
0
0
0
0
91
0
0
0
0
0
176
0
0
0
0
0
0
0
0
0
0
0
101
0
0
0
0
0
0
0
0
0
0
0
360
0
CFG_GPMC_CS1_OE mmc2_cmd
N
5.10.6.20.3 MMC3 and MMC4—SDIO/SD
MMC3 and MMC4 interfaces are compliant with the SDIO3.0 standard v1.0, SD Part E1 and for generic
SDIO devices, it supports the following applications:
•
•
•
MMC3 8-bit data and MMC4 4-bit data, SD Default speed, SDR
MMC3 8-bit data and MMC4 4-bit data, SD High speed, SDR
MMC3 8-bit data and MMC4 4-bit data, UHS-1 SDR12 (SD Standard v3.01), 4-bit data, SDR, half
cycle
•
•
MMC3 8-bit data and MMC4 4-bit data, UHS-I SDR25 (SD Standard v3.01), 4-bit data, SDR, half cycle
MMC3 8-bit data, UHS-I SDR50
注
The eMMC/SD/SDIOj (j = 3 to 4) controller is also referred to as MMCj.
注
For more information, see the MMC/SDIO chapter of the Device TRM.
5.10.6.20.3.1 MMC3 and MMC4, SD Default Speed
图 5-91, 图 5-92, and 表 5-134 through 表 5-137 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD Default speed in receiver and transmitter mode.
(1)
表 5-134. Timing Requirements for MMC3 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 7
(2)
表 5-135. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5 × P-
(1)
0.270
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(2)
表 5-135. Switching Characteristics for MMC3 - SD/SDIO Default Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
DS2
tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-136. Timing Requirements for MMC4 - Default Speed Mode
NO.
DS5
DS6
DS7
DS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.11
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
20.46
5.11
ns
ns
th(clkH-dV)
20.46
ns
(1) i in [i:0] = 3
(2)
表 5-137. Switching Characteristics for MMC4 - Default Speed Mode
NO.
DS0
DS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5 × P-
(1)
0.270
DS2
tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
DS3
DS4
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-14.93
-14.93
14.93
14.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
DS2
DS1
DS0
mmcj_clk
mmcj_cmd
DS6
DS5
DS8
DS7
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_07
图 5-91. MMC/SD/SDIOj in - Default Speed - Receiver Mode
270
Specifications
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DS2
DS1
DS0
mmcj_clk
DS3
mmcj_cmd
DS4
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_08
图 5-92. MMC/SD/SDIOj in - Default Speed - Transmitter Mode
5.10.6.20.3.2 MMC3 and MMC4, SD High Speed
图 5-93, 图 5-94, and 表 5-138 through 表 5-141 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO High speed in receiver and transmitter mode.
(1)
表 5-138. Timing Requirements for MMC3 - SD/SDIO High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
2.6
5.3
2.6
MAX
UNIT
ns
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 7
(2)
表 5-139. Switching Characteristics for MMC3 - SD/SDIO High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
HS2H
0.5 × P-
(1)
0.270
HS2L
tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-7.6
-7.6
3.6
3.6
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-140. Timing Requirements for MMC4 - High Speed Mode
NO.
HS3
HS4
HS7
HS8
PARAMETER
tsu(cmdV-clkH)
th(clkH-cmdV)
tsu(dV-clkH)
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
th(clkH-dV)
ns
(1) i in [i:0] = 3
(2)
表 5-141. Switching Characteristics for MMC4 - High Speed Mode
NO.
HS1
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
fop(clk)
tw(clkH)
Operating frequency, mmc4_clk
48
HS2H
Pulse duration, mmc4_clk high
0.5 × P-
(1)
0.270
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(2)
表 5-141. Switching Characteristics for MMC4 - High Speed Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
HS2L
tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
HS5
HS6
td(clkL-cmdV)
td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS4
HS3
HS7
HS8
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_09
图 5-93. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Receiver Mode
HS1
HS2H
HS2L
mmcj_clk
mmcj_cmd
HS5
HS5
HS6
HS6
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_10
图 5-94. MMC/SD/SDIOj in - High Speed 3.3V Signaling - Transmitter Mode
5.10.6.20.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
图 5-95, 图 5-96, and 表 5-142, through 表 5-145 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR12 in receiver and transmitter mode.
(1)
表 5-142. Timing Requirements for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 5-143. Switching Characteristics for MMC3 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
24
0.5 × P-
(1)
0.270
272
Specifications
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(2)
表 5-143. Switching Characteristics for MMC3 - SDR12 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR122 tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
SDR123 td(clkL-cmdV)
SDR124 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-144. Timing Requirements for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
25.99
1.6
MAX
UNIT
ns
SDR125 tsu(cmdV-clkH)
SDR126 th(clkH-cmdV)
SDR127 tsu(dV-clkH)
SDR128 th(clkH-dV)
(1) j in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
25.99
1.6
ns
ns
(2)
表 5-145. Switching Characteristics for MMC4 - SDR12 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR120 fop(clk)
SDR121 tw(clkH)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
24
0.5 × P-
(1)
0.270
SDR122 tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
SDR125 td(clkL-cmdV)
SDR126 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-19.13
-19.13
16.93
16.93
ns
ns
(1) P = output mmc4_clk period in ns
(2) j in [i:0] = 3
SDR122
SDR121
SDR120
mmcj_clk
mmcj_cmd
SDR126
SDR125
SDR128
SDR127
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_11
图 5-95. MMC/SD/SDIOj in - SDR12 - Receiver Mode
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SDR122
SDR121
SDR120
mmcj_clk
SDR123
SDR124
mmcj_cmd
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_12
图 5-96. MMC/SD/SDIOj in - SDR12 - Transmitter Mode
5.10.6.20.3.4 MMC3 and MMC4, SD SDR25 Mode
图 5-97, 图 5-98, and 表 5-146, through 表 5-149 present Timing requirements and Switching
characteristics for MMC3 and MMC4 - SD and SDIO SDR25 in receiver and transmitter mode.
(1)
表 5-146. Timing Requirements for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR253 tsu(cmdV-clkH)
SDR254 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
ns
ns
(2)
表 5-147. Switching Characteristics for MMC3 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.270
SDR252L tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
(1)
表 5-148. Timing Requirements for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
5.3
1.6
5.3
1.6
MAX
UNIT
ns
SDR255 tsu(cmdV-clkH)
SDR256 th(clkH-cmdV)
SDR257 tsu(dV-clkH)
SDR258 th(clkH-dV)
(1) i in [i:0] = 3
Setup time, mmc4_cmd valid before mmc4_clk rising clock edge
Hold time, mmc4_cmd valid after mmc4_clk rising clock edge
Setup time, mmc4_dat[i:0] valid before mmc4_clk rising clock edge
Hold time, mmc4_dat[i:0] valid after mmc4_clk rising clock edge
ns
ns
ns
(2)
表 5-149. Switching Characteristics for MMC4 - SDR25 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR251 fop(clk)
Operating frequency, mmc4_clk
Pulse duration, mmc4_clk high
48
SDR252 tw(clkH)
H
0.5 × P-
(1)
0.270
274
Specifications
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(2)
表 5-149. Switching Characteristics for MMC4 - SDR25 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
SDR252L tw(clkL)
Pulse duration, mmc4_clk low
0.5 × P-
0.270
ns
(1)
SDR255 td(clkL-cmdV)
SDR256 td(clkL-dV)
Delay time, mmc4_clk falling clock edge to mmc4_cmd transition
Delay time, mmc4_clk falling clock edge to mmc4_dat[i:0] transition
-8.8
-8.8
6.6
6.6
ns
ns
(1) P = output mmc4_clk period in ns
(2) i in [i:0] = 3
SDR251
SDR252L
SDR253
SDR252H
SDR254
mmcj_clk
mmcj_cmd
SDR257
SDR258
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_13
图 5-97. MMC/SD/SDIOj in - SDR25 - Receiver Mode
SDR251
SDR252H
SDR252L
SDR255
mmcj_clk
mmcj_cmd
SDR255
SDR256
SDR256
mmcj_dat[i:0]
SPRS906_TIMING_MMC3_14
图 5-98. MMC/SD/SDIOj in - SDR25 - Transmitter Mode
5.10.6.20.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
图 5-99, 图 5-100, 表 5-150, and 表 5-151 present Timing requirements and Switching characteristics for
MMC3 - SDIO High speed SDR50 in receiver and transmitter mode.
(1)
表 5-150. Timing Requirements for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
1.48
1.6
MAX
UNIT
ns
SDR503 tsu(cmdV-clkH)
SDR504 th(clkH-cmdV)
SDR507 tsu(dV-clkH)
SDR508 th(clkH-dV)
(1) i in [i:0] = 7
Setup time, mmc3_cmd valid before mmc3_clk rising clock edge
Hold time, mmc3_cmd valid after mmc3_clk rising clock edge
Setup time, mmc3_dat[i:0] valid before mmc3_clk rising clock edge
Hold time, mmc3_dat[i:0] valid after mmc3_clk rising clock edge
ns
1.48
1.6
ns
ns
(2)
表 5-151. Switching Characteristics for MMC3 - SDR50 Mode
NO.
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
MHz
ns
SDR501 fop(clk)
Operating frequency, mmc3_clk
Pulse duration, mmc3_clk high
64
SDR502 tw(clkH)
H
0.5 × P-
(1)
0.270
SDR502L tw(clkL)
Pulse duration, mmc3_clk low
0.5 × P-
0.270
ns
(1)
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(2)
表 5-151. Switching Characteristics for MMC3 - SDR50 Mode (continued)
NO.
PARAMETER
DESCRIPTION
MIN
-3.66
-3.66
MAX
UNIT
ns
SDR505 td(clkL-cmdV)
SDR506 td(clkL-dV)
Delay time, mmc3_clk falling clock edge to mmc3_cmd transition
Delay time, mmc3_clk falling clock edge to mmc3_dat[i:0] transition
1.46
1.46
ns
(1) P = output mmc3_clk period in ns
(2) i in [i:0] = 7
SDR501
SDR502L
SDR502H
SDR504
mmcj_clk
mmcj_cmd
SDR503
SDR507
SDR508
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_05
图 5-99. MMC/SD/SDIOj in - High Speed SDR50 - Receiver Mode
SDR501
SDR502H
SDR502L
SDR505
mmcj_clk
mmcj_cmd
SDR505
SDR506
SDR506
mmcj_dat[7:0]
SPRS906_TIMING_MMC3_06
图 5-100. MMC/SD/SDIOj in - High Speed SDR50 - Transmitter Mode
注
To configure the desired Manual IO Timing Mode the user must follow the steps described in
section Manual IO Timing Modes of the Device TRM.
The associated registers to configure are listed in the CFG REGISTER column. For more
information see the Control Module chapter in the Device TRM.
Manual IO Timings Modes must be used to guaranteed some IO timings for MMC3. See 表 5-28 Modes
Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See 表 5-152 Manual
Functions Mapping for MMC3 for a definition of the Manual modes.
表 5-152 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the
CFG_x registers.
表 5-152. Manual Functions Mapping for MMC3
BALL
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
Y2
Y2
Y1
Y1
Y1
Y4
mmc3_clk
mmc3_clk
1085
1269
0
21
0
CFG_MMC3_CLK_IN
CFG_MMC3_CLK_OUT
CFG_MMC3_CMD_IN
CFG_MMC3_CMD_OEN
CFG_MMC3_CMD_OUT
CFG_MMC3_DAT0_IN
mmc3_clk
mmc3_clk
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
mmc3_cmd
mmc3_cmd
mmc3_cmd
mmc3_dat0
0
128
98
0
0
0
0
276
Specifications
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表 5-152. Manual Functions Mapping for MMC3 (continued)
BALL NAME
MMC3_MANUAL1
CFG REGISTER
MUXMODE
0
A_DELAY (ps)
G_DELAY (ps)
Y4
Y4
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
362
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CFG_MMC3_DAT0_OEN
CFG_MMC3_DAT0_OUT
CFG_MMC3_DAT1_IN
CFG_MMC3_DAT1_OEN
CFG_MMC3_DAT1_OUT
CFG_MMC3_DAT2_IN
CFG_MMC3_DAT2_OEN
CFG_MMC3_DAT2_OUT
CFG_MMC3_DAT3_IN
CFG_MMC3_DAT3_OEN
CFG_MMC3_DAT3_OUT
CFG_MMC3_DAT4_IN
CFG_MMC3_DAT4_OEN
CFG_MMC3_DAT4_OUT
CFG_MMC3_DAT5_IN
CFG_MMC3_DAT5_OEN
CFG_MMC3_DAT5_OUT
CFG_MMC3_DAT6_IN
CFG_MMC3_DAT6_OEN
CFG_MMC3_DAT6_OUT
CFG_MMC3_DAT7_IN
CFG_MMC3_DAT7_OEN
CFG_MMC3_DAT7_OUT
mmc3_dat0
mmc3_dat0
mmc3_dat1
mmc3_dat1
mmc3_dat1
mmc3_dat2
mmc3_dat2
mmc3_dat2
mmc3_dat3
mmc3_dat3
mmc3_dat3
mmc3_dat4
mmc3_dat4
mmc3_dat4
mmc3_dat5
mmc3_dat5
mmc3_dat5
mmc3_dat6
mmc3_dat6
mmc3_dat6
mmc3_dat7
mmc3_dat7
mmc3_dat7
AA2
AA2
AA2
AA3
AA3
AA3
W2
7
333
0
0
402
0
203
549
1
W2
W2
Y3
121
440
206
336
283
174
320
443
0
Y3
Y3
AA1
AA1
AA1
AA4
AA4
AA4
AB1
AB1
AB1
2
344
0
5.10.6.21 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks. Each GPIO
module provides up to 32 dedicated general-purpose pins with input and output capabilities; thus, the
general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations
•
Wake-up request generation in idle mode upon the detection of external events
注
For more information, see the General-Purpose Interface chapter of the Device TRM.
注
The general-purpose input/output i (i = 1 to 8) bank is also referred to as GPIOi.
5.10.6.22 System and Miscellaneous interfaces
The Device includes the following System and Miscellaneous interfaces:
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•
•
•
Sysboot Interface
System DMA Interface
Interrupt Controllers (INTC) Interface
5.10.7 Emulation and Debug Subsystem
The Device includes the following Test interfaces:
•
•
IEEE 1149.1 Standard-Test-Access Port (JTAG)
Trace Port Interface Unit (TPIU)
5.10.7.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
The JTAG (IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture)
interface is used for BSDL testing and emulation of the device. The trstn pin only needs to be released
when it is necessary to use a JTAG controller to debug the device or exercise the device's boundary scan
functionality. For maximum reliability, the device includes an internal Pulldown (IPD) on the trstn pin to
ensure that trstn is always asserted upon power up and the device's internal emulation logic is always
properly initialized. JTAG controllers from Texas Instruments actively drive trstn high. However, some
third-party JTAG controllers may not drive trstn high but expect the use of a Pullup resistor on trstn. When
using this type of JTAG controller, assert trstn to initialize the device after powerup and externally drive
trstn high before attempting any emulation or boundary-scan operations.
The main JTAG features include:
•
•
•
•
•
32KB embedded trace buffer (ETB)
5-pin system trace interface for debug
Supports Advanced Event Triggering (AET)
All processors can be emulated via JTAG ports
All functions on EMU pins of the device:
–
–
EMU[1:0] - cross-triggering, boot mode (WIR), STM trace
EMU[4:2] - STM trace only (single direction)
5.10.7.1.1 JTAG Electrical Data/Timing
表 5-153, 表 5-154 and 图 5-101 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
表 5-153. Timing Requirements for IEEE 1149.1 JTAG
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
6.23
ns
31.15
31.15
ns
ns
表 5-154. Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
NO.
PARAMETER
td(TCKL-TDOV)
DESCRIPTION
Delay time, TCK low to TDO valid
MIN
MAX
UNIT
2
0
30.5
ns
278
Specifications
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1
1a
1b
TCK
TDO
2
3
4
TDI/TMS
SPRS906_TIMING_JTAG_01
图 5-101. JTAG Timing
表 5-155, 表 5-156 and 图 5-102 assume testing over the recommended operating conditions and
electrical characteristic conditions below.
表 5-155. Timing Requirements for IEEE 1149.1 JTAG With RTCK
NO.
1
PARAMETER
tc(TCK)
DESCRIPTION
MIN
62.29
24.92
24.92
6.23
MAX
UNIT
ns
Cycle time, TCK
1a
1b
tw(TCKH)
Pulse duration, TCK high (40% of tc)
Pulse duration, TCK low (40% of tc)
Input setup time, TDI valid to TCK high
Input setup time, TMS valid to TCK high
Input hold time, TDI valid from TCK high
Input hold time, TMS valid from TCK high
ns
tw(TCKL)
ns
tsu(TDI-TCK)
tsu(TMS-TCK)
th(TCK-TDI)
th(TCK-TMS)
ns
3
4
6.23
ns
31.15
31.15
ns
ns
表 5-156. Switching Characteristics Over Recommended Operating Conditions for
IEEE 1149.1 JTAG With RTCK
NO.
PARAMETER
td(TCK-RTCK)
DESCRIPTION
MIN
MAX
UNIT
Delay time, TCK to RTCK with no selected subpaths (i.e. ICEPick is
the only tap selected - when the Arm is in the scan chain, the delay
time is a function of the Arm functional clock).
5
0
27
ns
6
7
8
tc(RTCK)
Cycle time, RTCK
62.29
24.92
24.92
ns
ns
ns
tw(RTCKH)
tw(RTCKL)
Pulse duration, RTCK high (40% of tc)
Pulse duration, RTCK low (40% of tc)
5
TCK
6
7
8
RTCK
SPRS906_TIMING_JTAG_02
图 5-102. JTAG With RTCK Timing
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5.10.7.2 Trace Port Interface Unit (TPIU)
CAUTION
The I/O timings provided in this section are valid only if signals within a single
IOSET are used. The IOSETs are defined in 表 5-158.
5.10.7.2.1 TPIU PLL DDR Mode
表 5-157 and 图 5-103 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
表 5-157. Switching Characteristics for TPIU
NO.
PARAMETER
tc(clk)
DESCRIPTION
Cycle time, TRACECLK period
MIN
5.56
MAX
UNIT
ns
TPIU1
TPIU4
TPIU5
td(clk-ctlV)
Skew time, TRACECLK transition to TRACECTL transition
Skew time, TRACECLK transition to TRACEDATA[17:0]
-1.61
-1.61
1.98
1.98
ns
td(clk-dataV)
ns
TPIU1
TPIU2
TPIU3
TRACECLK
TPIU4
TPIU4
TRACECTL
TPIU5
TPIU5
TRACEDATA[X:0]
SPRS906_TIMING_TIMER_01
图 5-103. TPIU—PLL DDR Transmit Mode(1)
(1) In d[X:0], X is equal to 15 or 17.
In 表 5-158 are presented the specific groupings of signals (IOSET) for use with TPIU signals.
表 5-158. TPIU IOSETs
SIGNALS
IOSET1
IOSET2
BALL
E10
B10
A10
F10
A11
A8
MUX
5
BALL
MUX
emu19
emu18
emu17
emu16
emu15
emu14
emu13
emu12
emu11
emu10
emu9
5
5
5
5
5
A9
5
A7
5
B9
5
C8
5
B8
5
emu8
E8
5
emu7
C7
5
emu6
B7
5
280
Specifications
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表 5-158. TPIU IOSETs (continued)
SIGNALS
IOSET1
IOSET2
BALL
D8
MUX
BALL
MUX
emu5
emu1
emu0
5
0
0
C22
C21
C22
C21
0
0
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6 Detailed Description
6.1 Description
TI’s new TDA2Ex System-on-Chip (SoC) is a highly optimized and scalable family of devices designed to
meet the requirements of leading Advanced Driver Assistance Systems (ADAS). The TDA2Ex family
enables broad ADAS applications in today’s automobile by integrating an optimal mix of performance, low
power, and ADAS vision analytics processing that aims to facilitate a more autonomous and collision-free
driving experience.
The TDA2Ex SoC enables sophisticated embedded vision technology in today’s automobile by enabling a
board range of ADAS applications including park assist, surround view and sensor fusion on a single
architecture.
The TDA2Ex SoC incorporates a heterogeneous, scalable architecture that includes a mix of TI’s fixed
and floating-point TMS320C66x digital signal processor (DSP) generation core, Arm Cortex-A15 MPCore
and dual-Cortex-M4 processors. The integration of a video accelerator for decoding multiple video streams
over an Ethernet AVB network, along with graphics accelerator for rendering virtual views, enable a 3D
viewing experience. The TDA2Ex SoC also integrates a host of peripherals including multicamera
interfaces (both parallel and serial, including CSI-2) to enable Ethernet or LVDS-based surround view
systems, displays and GigB Ethernet AVB.
Additionally, TI provides a complete set of development tools for the Arm and DSP, including C compilers,
a DSP assembly optimizer to simplify programming and scheduling, and a debugging interface for visibility
into source code execution.
Cryptographic acceleration is available in all devices. All other supported security features, including
support for secure boot, debug security and support for trusted execution environment are available on
High-Security (HS) devices. For more information about HS devices, contact your TI representative.
The TDA2Ex ADAS processor is qualified according to the AEC-Q100 standard.
6.2 Functional Block Diagram
图 6-1 is functional block diagram for the device.
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TDA2Ex
CAL
CSI2
MPU
IVA HD
(1x Arm
Cortex–A15)
1080p Video
Co-Processor
IPU 1
(Dual Cortex–M4)
Display Subsystem
GPU
Secure Boot
Debug
(1x SGX544 3D)
IPU 2
(Dual Cortex–M4)
LCD2
Security
TEE
1xGFX / 3xVID
LCD3
Blend / Scale
DSP
BB2D
(HS devices)
HDMI 1.4a
(C66x Co-Processor)
(GC320 2D)
EDMA
JTAG
MMU x2
VIP x1
VPE
High-Speed Interconnect
System
Connectivity
Spinlock
Mailbox x13
GPIO x8
Timers x16
WDT
SDMA
1x USB 3.0
Dual Mode FS/HS/SS
w/ PHY
PCIe SS x2
GMAC AVB
PWM SS x3
2x USB 2.0
Dual Mode FS/HS
1x PHY, 1x ULPI
Program/Data Storage
Serial Interfaces
GPMC / ELM
(NAND/NOR/
Async)
EMIF
1x 32-bit
DDR3/DDR3L
QSPI
McASP x8
I2C x6
UART x10
McSPI x4
DCAN x2
512-KB
RAM
256-KB ROM
OCMC
MMC / SD x4
DMM
intro-001
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图 6-1. TDA2Ex Block Diagram
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6.3 MPU
The Cortex®-A15 microprocessor unit (MPU) subsystem serves the applications processing role by
running the high-level operating system (HLOS) and application code.
The MPU subsystem incorporates one Cortex-A15 MPU core (MPU_C0), individual level 1 (L1) caches,
level 2 (L2) cache (MPU_L2CACHE) shared between them, and various other shared peripherals. To aid
software development, the processor core can be kept cache-coherent with the L2 cache.
The MPU subsystem provides a high-performance computing platform with high peak-computing
performance and low memory latency.
The Arm subsystem supports the following key features:
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•
Arm® Cortex-A15 MP Core (MPU_CLUSTER)
–
One Cortex-A15 MPU core (revision r2p2) which has the following features:
•
Superscalar, dynamic multi-issue technology
–
–
Out-of-order (OoO) instruction dispatch and completion
Dynamic branch prediction with branch target buffer (BTB), global history buffer (GHB), and
48-entry return stack
–
–
–
–
Continuous fetch and decoding of three instructions per clock cycle
Dispatch of up to four instructions and completion of eight instructions per clock cycle
Provides optimal performance from binaries compiled for previous Arm processors
Five execution units handle simple instructions, branch instructions, Neon™ and floating
point instructions, multiply instructions, and load and store instructions.
–
Simple instructions take two cycles from dispatch, while complex instructions take up to 11
cycles.
–
–
Can issue two simple instructions in a cycle
Can issue a load and a store instruction in the same cycle
•
•
Integrated Neon processing engine to include the Arm Neon Advanced SIMD (single instruction,
multiple data) support for accelerated media and signal processing computation
Includes VFPv4-compatible hardware to support single- and double-precision add, subtract,
divide, multiply and accumulate, and square root operations
•
•
Extensive support to accelerate virtualization using a hypervisor
32-KiB L1 instruction (L1I) and 32-KiB L1 data (L1D) cache:
–
–
64-byte line size
2-way set associative
•
Memory management unit (MMU):
–
Two-level translation lookaside buffer (TLB) organization
–
First level is an 32-entry, fully associative micro-TLB implemented for each of instruction
fetch, load, and store.
–
Second level is a unified, 4-way associative, 512-entry main TLB
–
Supports hardware TLB table-walk for backward-compatible and new 64-bit entry page table
formats
–
–
New page table format can produce 40-bit physical addresses
Two-stage translation where first stage is HLOS-controlled and the second level may be
controlled by a hypervisor. Second stage always uses the new page table format
–
Integrated L2 cache (MPU_L2CACHE) and snoop control unit (SCU):
•
1-MiB of unified (instructions and data) cache organized as 16 ways of 1024 sets of 64-byte
lines
•
Redundant L1 data (cache) tags to perform snoop filtering (L1 instruction cache tags are not
duplicated)
•
•
Operates at Cortex-A15 MPU core clock rate
Integrated L2 cache controller (MPU_L2CACHE_CTRL):
–
–
–
Sixteen 64-byte line buffers that handle evictions, line fills and snoop transfers
One 128-bit AMBA4 Coherent Bus (AXI4-ACE) port
Auto-prefetch buffer for up to 16 streams and detecting forward and backward strides
–
Generalized interrupt controller (GIC, also referred to as MPU_INTC): An interrupt controller
supplied by Arm. The single GIC in the MPU_CLUSTER routes interrupts to the MPU core. The
GIC supports:
•
•
•
Number of shared peripheral interrupts (SPI): 160
Number of software generated interrupts (SGI): 16
Number of CPU interfaces: 1
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•
Virtual CPU interface for virtualization support. This allows the majority of guest operating
system (OS) interactions with the GIC to be handled in hardware, but with physical interrupts
still requiring hypervisor intervention to assign them to the appropriate virtual machine.
–
–
Integrated timer counter and one timer block
Arm CoreSight debug and trace modules. For more information, see chapter On-Chip Debug
Support of the Device TRM..
•
MPU_AXI2OCP bridge (local interconnect):
–
Connected to Memory Adapter (MPU_MA), which routes the non-EMIF address space transactions
to MPU_AXI2OCP
–
–
Single request multiple data (SRMD) protocol on L3_MAIN port
Multiple targets:
•
•
•
64-bit port to the L3_MAIN interconnect. Interface frequency is 1/4 or 1/8 of core frequency
MPU_ROM
Internal MPU subsystem peripheral targets, including Memory Adapter LISA Section Manager
(MA_LSM), wake-up generator (MPU_WUGEN), watchdog timer (MPU_WD_TIMER), and local
PRCM module (MPU_PRCM) configuration
•
Internal AXI target, CoreSight System Trace Module (CS_STM)
•
Memory adapter (MPU_MA): Helps decrease the latency of accesses between the MPU_L2CACHE
and the external memory interface (EMIF1) by providing a direct path between the MPU subsystem
and EMIF1:
–
–
–
Connected to 128-bit AMBA4 interface of MPU_CLUSTER
Direct 128-bit interface to EMIF1
Interface speed between MPU_CLUSTER and MPU_MA is at half-speed of the MPU core
frequency
–
–
Quarter-speed interface to EMIF
Uses firewall logic to check access rights of incoming addresses
•
•
Local PRCM (MPU_PRCM):
–
–
Handles MPU_C0 power domain
Supports SR3-APG (SmartReflex3 Automatic Power Gating) power management technology inside
the MPU_CLUSTER
–
MPU subsystem has five power domains
Wake-up generator (MPU_WUGEN)
Responsible for waking up the MPU core
–
•
•
Standby controller: Handles the power transitions inside the MPU subsystem
Realtime (master) counter (COUNTER_REALTIME): Produces the count used by the private timer
peripheral in the MPU_CLUSTER
•
•
Watchdog timer (MPU_WD_TIMER): Used to generate a chip-level watchdog reset request to global
PRCM
On-chip boot ROM (MPU_ROM): The MPU_ROM size is 48-KiB, and the address range is from
0x4003 8000 to 0x4004 3FFF. For more information about booting from this memory, see chapter
Initialization of the Device TRM..
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•
Interfaces:
–
–
–
128-bit interface to EMIF1
64-bit master port to the L3_MAIN interconnect
32-bit slave port from the L4_CFG_EMU interconnect (debug subsystem) for configuration of the
MPU subsystem debug modules
–
32-bit slave port from the L4_CFG interconnect for memory adapter firewall (MPU_MA_NTTP_FW)
configuration
–
–
32-bit ATB output for transmitting debug and trace data
160 peripheral interrupt inputs
For more information, see section Arm Cortex-A15 Subsystem in chapter Processors and Accelerators of
the device TRM.
6.4 DSP Subsystem
The device includes a single instance (DSP1) of a digital signal processor (DSP) subsystem, based on the
TI's standard TMS320C66x™ DSP CorePac core.
The TMS320C66x DSP core enhances the TMS320C674x™ core, which merges the C674x™ floating
point and the C64x+™ fixed-point instruction set architectures. The C66x DSP is object-code compatible
with the C64x+/C674x DSPs.
For more information on the TMS320C66x core CPU, see the TMS320C66x DSP CPU and Instruction Set
Reference Guide, (SPRUGH7).
The DSP subsystem integrated in the device includes the following components:
•
A TMS320C66x™ CorePac DSP core that encompasses:
–
–
–
–
–
–
–
L1 program-dedicated (L1P) cacheable memory
L1 data-dedicated (L1D) cacheable memory
L2 (program and data) cacheable memory
Extended Memory Controller (XMC)
External Memory Controller (EMC)
DSP CorePac located interrupt controller (INTC)
DSP CorePac located power-down controller (PDC)
•
Dedicated enhanced data memory access engine - EDMA, to transfer data from/to memories and
peripherals external to the DSP subsystem and to local DSP memory (most commonly L2 SRAM). The
external DMA requests are passed through DSP system level (SYS) wakeup logic, and collected from
the DSP1 dedicated outputs of the device DMA Events Crossbar for the subsystem.
•
•
•
A level 2 (L2) interconnect network (DSP NoC) to allow connectivity between different modules of the
subsystem or the remainder of the device via the device L3_MAIN interconnect.
Two memory management units (on EDMA L2 interconnect and DSP MDMA paths) for accessing the
device L3_MAIN interconnect address space
Dedicated system control logic (DSP_SYSTEM) responsible for power management, clock generation,
and connection to the device power, reset, and clock management (PRCM) module
The TMS320C66x Instruction Set Architecture (ISA) is the latest for the C6000 family. As with its
predecessors (C64x, C64x+ and C674x), the C66x is an advanced VLIW architecture with 8 functional
units (two multiplier units and six arithmetic logic units) that operate in parallel. The C66x CPU has a total
of 64 general-purpose 32-bit registers.
Some features of the DSP C6000 family devices are:
•
Advanced VLIW CPU with eight functional units (two multipliers and six ALUs) which:
–
–
Executes up to eight instructions per cycle for up to ten times the performance of typical DSPs
Allows designers to develop highly effective RISC-like code for fast development time
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•
•
•
Instruction packing
–
–
Gives code size equivalence for eight instructions executed serially or in parallel
Reduces code size, program fetches, and power consumption
Conditional execution of most instructions
–
–
Reduces costly branching
Increases parallelism for higher sustained performance
Efficient code execution on independent functional units
–
–
Industry's most efficient C compiler on DSP benchmark suite
Industry's first assembly optimizer for fast development and improved parallelization
•
•
8-/16-/32-bit/64-bit data support, providing efficient memory support for a variety of applications
40-bit arithmetic options which add extra precision for vocoders and other computationally intensive
applications
•
•
Saturation and normalization to provide support for key arithmetic operations
Field manipulation and instruction extract, set, clear, and bit counting support common operation found
in control and data manipulation applications.
The C66x CPU has the following additional features:
•
•
•
•
Each multiplier can perform two 16 × 16-bit or four 8 × 8 bit multiplies every clock cycle.
Quad 8-bit and dual 16-bit instruction set extensions with data flow support
Support for non-aligned 32-bit (word) and 64-bit (double word) memory accesses
Special communication-specific instructions have been added to address common operations in error-
correcting codes.
•
•
Bit count and rotate hardware extends support for bit-level algorithms.
Compact instructions: Common instructions (AND, ADD, LD, MPY) have 16-bit versions to reduce
code size.
•
Protected mode operation: A two-level system of privileged program execution to support higher-
capability operating systems and system features such as memory protection.
•
•
Exceptions support for error detection and program redirection to provide robust code execution
Hardware support for modulo loop operation to reduce code size and allow interrupts during fully-
pipelined code
•
•
Each multiplier can perform 32 × 32 bit multiplies
Additional instructions to support complex multiplies allowing up to eight 16-bit multiply/add/subtracts
per clock cycle
The TMS320C66x has the following key improvements to the ISA:
•
•
•
•
4x Multiply Accumulate improvement for both fixed and floating point
Improvement of the floating point arithmetic
Enhancement of the vector processing capability for fixed and floating point
Addition of domain-specific instructions for complex arithmetic and matrix operations
On the C66x ISA, the vector processing capability is improved by extending the width of the SIMD
instructions. The C674x DSP supports 2-way SIMD operations for 16-bit data and 4-way SIMD
operations for 8-bit data. C66x enhances this capabilities with the addition of SIMD instructions for 32-bit
data allowing operation on 128-bit vectors. For example the QMPY32 instruction is able to perform the
element to element multiplication between two vectors of four 32-bit data each.
C66x ISA includes a set of specific instructions to handle complex arithmetic and matrix operations.
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•
TMS320C66x DSP CorePac memory components:
–
A 32-KiB L1 program memory (L1P) configurable as cache and/or SRAM:
•
When configured as a cache, the L1P is a 1-way set-associative cache with a 32-byte cache
line
•
The DSP CorePac L1P memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
•
The L1P is capable of cache block and global coherence operations
The L1P controller has an Error Detection (ED) mechanism, including necessary SRAM
The L1P memory can be fully configured as a cache or SRAM
Page size for L1P memory is 2KB
–
A 32-KiB L1 data memory (L1D) configurable as cache and / or SRAM:
•
When configured as a cache, the L1D is a 2-way set-associative cache with a 64-byte cache
line
•
The DSP CorePac L1D memory controller provides bandwidth management, memory
protection, and power-down functions
•
•
•
The L1D memory can be fully configured as a cache or SRAM
No support for error correction or detection
Page size for L1D memory is 2KB
–
A 288-KiB (program and data) L2 memory, only part of which is cacheable:
•
When configured as a cache, the L2 memory is a 4-way set associative cache with a 128-byte
cache line
•
•
•
Only 256 KiB of L2 memory can be configured as cache or SRAM
32 KiB of the L2 memory is always mapped as SRAM
The L2 memory controller has an Error Correction Code (ECC) and ED mechanism, including
necessary SRAM
•
•
The L2 memory controller supports hardware prefetching and also provides bandwidth
management, memory protection, and power-down functions.
Page size for L2 memory is 16KB
•
The External Memory Controller (EMC) is a bridge from the C66x CorePac to the rest of the DSP
subsystem and device. It has :
–
a 32-bit configuration port (CFG) providing access to local subsystem resources (like DSP_EDMA,
DSP_SYSTEM, and so forth) or to L3_MAIN resources accessible via the CFG address range.
–
a 128-bit slave-DMA port (SDMA) which provides accesses of system masters outside the DSP
subsystem to resources inside the DSP subsystem or C66x DSP CorePac memories, i.e. when the
DSP subsystem is the slave in a transaction.
•
•
The Extended Memory Controller (XMC) processes requests from the L2 Cache Controller (which
are a result of CPU instruction fetches, load/store commands, cache operations) to device resources
via the C66x DSP CorePac 128-bit master DMA (MDMA) port:
–
Memory protection for addresses outside C66x DSP CorePac generated over device L3_MAIN on
the MDMA port
–
Prefetch, multi-in-flight requests
A DSP local Interrupt Controller (INTC) in the DSP C66x CorePac, interfaces the system events to
the DSP C66x core CPU interrupt and exceptions inputs. The DSP subsystem C66x CorePac interrupt
controller supports up to 128 system events of which 64 interrupts are external to DSP subsystem,
collected from the DSP1 dedicated outputs of the device Interrupt Crossbar.
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•
Local Enhanced Direct Memory Access (EDMA) controller features:
–
–
Channel controller (CC) : 64-channel, 128 PaRAM, 2 Queues
2 x Third-party Transfer Controllers (TPTC0 and TPTC1):
•
•
Each TC has a 128-bit read port and a 128-bit write port
2KiB FIFOs on each TPTC
–
–
1-dimensional/2-dimensional (1D/2D) addressing
Chaining capability
•
DSP subsystem integrated MMUs:
Two MMUs are integrated:
–
•
The MMU0 is located between DSP MDMA master port and the device L3_MAIN interconnect
and can be optionally bypassed
•
The MMU1 is located between the EDMA master port and the device L3_MAIN interconnect
•
•
A DSP local Power-Down Controller (PDC) is responsible to power-down various parts of the DSP
C66x CorePac, or the entire DSP C66x CorePac.
The DSP subsystem System Control logic provides:
–
–
–
–
Slave idle and master standby protocols with device PRCM for powerdown
OCP Disconnect handshake for init and target busses
Asynchronous reset
Power-down modes:
•
"Clockstop" mode featuring wake-up on interrupt event. The DMA event wake-up is managed in
software.
•
•
The device DSP subsystem is supplied by a PRCM DPLL, but DSP1 has integrated its own PLL
module outside the C66x CorePac for clock gating and division.
The device DSP subsystem has following port instances to connect to remaining part of the
device. See also :
–
–
–
–
A 128-bit initiator (DSP MDMA master) port for MDMA/Cache requests
A 128-bit initiator (DSP EDMA master) port for EDMA requests
A 32-bit initiator (DSP CFG master) port for configuration requests
A 128-bit target (DSP slave) port for requests to DSP memories and various peripherals
•
C66x DSP subsystem (DSPSS) safety aspects:
–
–
–
Above mentioned memory ECC/ED mechanisms
MMUs enable mapping of only the necessary application space to the processor
Memory Protection Units internal to the DSPSS (in L1P, L1D and L2 memory controllers) and
external to DSPSS (firewalls) to help define legal accesses and raise exceptions on illegal
accesses
–
Exceptions: Memory errors, various DSP errors, MMU errors and some system errors are detected
and cause exceptions. The exceptions could be handled by the DSP or by a designated safety
processor at the chip level. Note that it may not be possible for the safety processor to completely
handle some exceptions
Unsupported features on the C66x DSP core for the device are:
•
The Extended Memory Controller MPAX (memory protection and address extension) 36-bit addressing
is NOT supported
Known DSP subsystem powermode restrictions for the device are:
•
"Full logic / RAM retention" mode featuring wake-up on both interrupt or DMA event (logic in “always
on” domain). Only OFF mode is supported by DSP subsystem, requiring full boot.
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Fore more information about:
C66x debug/trace support, see chapter On-Chip Debug of the device TRM.
•
6.5 IVA
The IVA supports resolutions up to 1080 p/i with full performance of 60 fps (or 120 fields), achievable for
encode or decode only (not for simultaneous encode and decode).
The IVA subsystem is composed of:
•
•
A primary sequencer, including its memories and an imaging controller: ICONT1
A video direct memory access (VDMA) processor, which can be used as a secondary sequencer:
ICONT2
•
•
•
•
•
•
•
•
•
•
•
•
A VDMA engine: DMA_IVA
An entropy codec: ECD3
A motion compensation engine: MC3
A transform and quantization calculation engine: CALC3
A loop filter acceleration engine: ILF3
A motion estimation acceleration engine: IME3
An intraprediction estimation engine: IPE3
Shared level 2 (L2) interface and memory
Local interconnect (L4_IVA)
A message interface for communication between SYNCBOXes
Mailbox
A debug module for trace event and software instrumentation: SMSET
注
The IVA allows execution of compliant codecs through the software development kit (SDK).
Refer to the SDK documentation for details.
For more information, see chapter IVA Subsystem of the device TRM.
6.6 IPU
The device instantiates two dual Cortex®-M4 image processor unit (IPU) subsystems:
•
•
IPU1 subsystem is available for general purpose usage
IPU2 subsystem is dedicated to IVA support and is not available for other processing
注
The two IPU subsystems are identical from functional point of view. Thus, a unified name
IPUx shall be used throughout the chapter for simplification.
Each IPU subsystem contains two Arm® Cortex-M4 processors (IPUx_C0 and IPUx_C1) that share a
common level 1 (L1) cache (called unicache [IPUx_UNICACHE]). The two Cortex-M4 cores are
completely homogeneous to one another. Any task possible using one Cortex-M4 core is also possible
using the other Cortex-M4 core. It is software responsibility to distribute the various tasks between each
Cortex-M4 core for optimal performance.
The integrated interrupt handling of the IPUx subsystem allows it to function as an efficient control unit.
Each IPU subsystem integrates the following:
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•
Two Arm Cortex-M4 microprocessors (IPUx_C0 and IPUx_C1):
–
–
–
–
–
–
Armv7-M and Thumb®-2 instruction set architecture (ISA)
Armv6 SIMD and digital signal processor (DSP) extensions
Single-cycle MAC
Integrated nested vector interrupt controller (NVIC) (also called IPUx_Cx_INTC, where x = 0, 1)
Integrated bus matrix
Registers:
•
•
•
•
•
Thirteen general-purpose 32-bit registers
Link register (LR)
Program counter (PC)
Program status register, xPSR
Two banked SP registers
–
–
Integrated power management
Extensive debug capabilities
•
Unicache interface:
–
–
Instruction and data interface
Supports paralleled accesses
•
•
Level 2 (L2) master interface (MIF) splitter for access to memory or configuration port
Configuration port: Used for unicache maintenance and unicache memory management unit
(IPUx_UNICACHE_MMU) configuration
•
Unicache:
–
–
–
–
32 KiB divided into 16 banks
4-way
Cache configuration lock/freeze/preload
Internal MMU:
•
•
•
•
16-entry region-based address translation
Read/write control and access type control
Execute Never (XN) MMU protection policy
Little-endian format
•
•
•
•
•
•
Subsystem counter timer module (IPUx_UNICACHE_SCTM, or just SCTM)
On-chip ROM (IPUx_ROM) and banked RAM (IPUx_RAM) memory
Emulation/debug: Emulation feature embedded in Cortex-M4
L2 MMU (IPUx_MMU): 32 entries with table walking logic
Wake-up generator (IPUx_WUGEN): Generates wake-up request from external interrupts
Power management:
–
–
–
–
Local power-management control: Configurable through the IPUx_WUGEN registers.
Three sleep modes supported, controlled by the local power-management module.
IPUx is clock-gated in all sleep modes.
IPUx_Cx_INTC interrupt interface stays awake.
For more information, see chapter Dual Cortex-M4 IPU Subsystem of the device TRM.
6.7 GPU
The 3D graphics processing unit (GPU) accelerates 2-dimensional (2D) and 3-dimensional (3D) graphics
and compute applications. It is based on the POWERVR SGX544-MP subsystem from Imagination
Technologies.
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SGX is a new generation of programmable POWERVR graphics and video processing subsystems. The
POWERVR SGX is a scalable architecture which efficiently processes a number of differing multimedia
data types concurrently:
•
•
•
•
Pixel Data
Vertex Data
General Purpose Processing
API support for industry standards:
–
–
–
OpenGL - ES 1.1 and 2.0
OpenCL -EP 1.1
Direct3D Feature Level 9.3
•
Single-core GPU architecture:
–
–
1 × SGX544 core
System level cache of 64 KiB
•
•
Tile-based deferred rendering architecture:
Reduces external bandwidth to SDRAM
Universal Scalable Shader Engine (USSE™):
–
–
–
Multithreaded engine incorporating vertex and pixel shader functionality
Automatic load balancing of vertex and pixel processing tasks
•
•
Present and texture load accelerator (PTLA):
–
–
–
–
Enables to move, rotate, twiddle, and scale texture surfaces
Supports RGB, ARGB, YUV4:2:2, and YUV4:2:0 surface formats
Supports bilinear upscale
Supports source color key
Fully virtualized memory addressing for operating system (OS) in a unified memory architecture:
–
–
Memory management unit (MMU)
Up to 4-GiB virtual address space
The 3D-GPU subsystem generates a single (aggregate) interrupt connected to the device Interrupt
Crossbar. This allows for this interrupt to be programmatically mapped to multiple device host interrupt
controllers.
•
Texture support:
–
–
–
Cube map
Projected textures
Non-square textures
•
Texture formats:
–
–
–
–
RGBA 8888, 565, 1555, and 1565
Monochromatic 8, 16, 16f, 32f, and 32int
Dual channel, 8:8, 16:16, and 16f:16f
Compressed textures:
•
•
•
•
•
•
PVRTC-i 2 bpp
PVRTC-i 4 bpp
PVRTC-ii 2 bpp
PVRTC-ii 4 bpp
ETC1
DXT 1-5 and BC 4-5
–
Programmable support for YUV formats:
•
•
Programmable matrix in hardware, coefficients on 12 bits
YUV4:2:2, YUV4:2:0, two planes (NV12 or NV21); YUV4:2:0, three planes
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•
•
•
Resolution support:
–
–
Frame buffer maximum = 4096 × 4096
Texture maximum size = 4096 × 4096
Texture filtering:
–
–
Bilinear, trilinear
Independent minimum and mag control
Anti-aliasing:
–
–
4× multisampling
Programmable sample positions
For more information, see chapter 3D Graphics Accelerator of the device TRM.
6.8 BB2D
The 2D graphics accelerator subsystem accelerates 2D graphics applications. The 2D graphics
accelerator subsystem is based on the GC320 2D GPU core from Vivante Corporation. The hardware
acceleration is brought to numerous 2D applications, including on-screen display and touch screen user
interfaces, graphical user interfaces (GUIs) and menu displays, flash animation, and gaming.
•
API support:
–
–
–
OpenWF™, DirectFB
GDI/DirectDraw™
Flash
•
BB2D architecture:
–
–
–
–
–
–
–
–
–
–
–
BitBlt and StretchBlt
DirectFB hardware acceleration
ROP2, ROP3, ROP4 full alpha blending and transparency
Clipping rectangle support
Alpha blending includes Java® 2 Porter-Duff compositing rules
90-, 180-, 270-degree rotation on every primitive
YUV-to-RGB color space conversion
Programmable display format conversion with 14 source and 7 destination formats
High-quality 9-tap, 32-phase filter for image and video scaling at 1080p
Monochrome expansion for text rendering
32 K × 32 K coordinate system
•
Hardware acceleration for DirectFB:
–
–
–
–
–
–
–
–
–
–
–
–
–
–
High-speed video scaler
ROP2/3/4
Rectangle filling and drawing
Line drawing
Simple blitting
Stretch blitting
Blending with alpha channel (per-pixel alpha)
Blending with alpha factor (alpha modulation)
Nine source and destination blending functions
Porter-Duff rules support
Premultiplied alpha support
Colorized blitting (color modulation)
Source color keying
Destination color keying
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The device BB2D generates a single (aggregate) interrupt request connected to the device Interrupt
Crossbar. This allows for this interrupt to be programmatically mapped to multiple device host interrupt
controllers.
For more information, see chapter 2D Graphics Accelerator of the device TRM.
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6.9 Memory Subsystem
6.9.1 EMIF
The EMIF module provides connectivity between DDR memory types and manages data bus read/write
accesses between external memory and device subsystems which have master access to the L3_MAIN
interconnect and DMA capability.
The EMIF module has the following capabilities:
•
•
Supports JEDEC standard-compliant DDR3/DDR3L-SDRAM memory types
2-GiB SDRAM address range over one chip-select. This range is configurable through the dynamic
memory manager (DMM) module
•
•
•
Supports SDRAM devices with one, two, four or eight internal banks
Supports SDRAM devices with single or dual die packages
Data bus widths:
–
–
–
–
128-bit L3_MAIN (system) interconnect data bus width
128-bit port for direct connection with MPU subsystem
32-bit SDRAM data bus width
16-bit SDRAM data bus width used in narrow mode
•
Supported CAS latencies:
DDR3: 5, 6, 7, 8, 9, 10 and 11
–
•
•
•
•
•
•
•
•
•
•
•
•
Supports 256-, 512-, 1024-, and 2048-word page sizes
Supported burst length: 8
Supports sequential burst type
SDRAM auto initialization from reset or configuration change
Supports self refresh and power-down modes for low power
Partial array self-refresh mode for low power.
Output impedance (ZQ) calibration for DDR3
Supports on-die termination (ODT) DDR3
Supports prioritized refresh
Programmable SDRAM refresh rate and backlog counter
Programmable SDRAM timing parameters
Write and read leveling/calibration and data eye training for DDR3.
The EMIF module does not support:
•
•
•
•
•
Burst chop for DDR3
Interleave burst type
Auto precharge because of better Bank Interleaving performance
DLL disabling from EMIF side
SDRAM devices with more than one die, or topologies which require more than one chip select on a
single EMIF channel
For more information, see section DDR External Memory Interface (EMIF) in chapter Memory Subsystem
of the device TRM.
6.9.2 GPMC
The General Purpose Memory Controller (GPMC) is an external memory controller of the device. Its data
access engine provides a flexible programming model for communication with all standard memories.
The GPMC supports the following various access types:
•
Asynchronous read/write access
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•
•
•
•
•
•
•
Asynchronous read page access (4, 8, and 16 Word16)
Synchronous read/write access
Synchronous read/write burst access without wrap capability (4, 8 and 16 Word16)
Synchronous read/write burst access with wrap capability (4, 8 and 16 Word16)
Address-data-multiplexed (AD) access
Address-address-data (AAD) multiplexed access
Little- and big-endian access
The GPMC can communicate with a wide range of external devices:
•
•
•
•
•
•
External asynchronous or synchronous 8-bit wide memory or device (non burst device)
External asynchronous or synchronous 16-bit wide memory or device
External 16-bit non-multiplexed NOR flash device
External 16-bit address and data multiplexed NOR Flash device
External 8-bit and 16-bit NAND flash device
External 16-bit pseudo-SRAM (pSRAM) device
The main features of the GPMC are:
•
•
8- or 16-bit-wide data path to external memory device
Supports up to eight CS regions of programmable size and programmable base addresses in a total
address space of 1 GiB
•
•
Supports transactions controlled by a firewall
On-the-fly error code detection using the Bose-ChaudhurI-Hocquenghem (BCH) (t = 4, 8, or 16) or
Hamming code to improve the reliability of NAND with a minimum effect on software (NAND flash with
512-byte page size or greater)
•
•
•
•
Fully pipelined operation for optimal memory bandwidth use
The clock to the external memory is provided from GPMC functional clock divided by 1, 2, 3, or 4
Supports programmable autoclock gating when no access is detected
Independent and programmable control signal timing parameters for setup and hold time on a per-chip
basis. Parameters are set according to the memory device timing parameters, with a timing granularity
of one GPMC functional clock cycle.
•
Flexible internal access time control (WAIT state) and flexible handshake mode using external WAIT
pin monitoring
•
•
•
Support bus keeping
Support bus turnaround
Prefetch and write posting engine associated with to achieve full performance from the NAND device
with minimum effect on NOR/SRAM concurrent access
For more information, see section General-Purpose Memory Controller (GPMC) in chapter Memory
Subsystem of the device TRM.
6.9.3 ELM
In the case of NAND modules with no internal correction capability, sometimes referred to as bare NAND,
the correction process can be delegated to the error location module (ELM) used in conjunction with the
GPMC.
The ELM supports the following features:
•
•
•
4, 8, and 16 bits per 512-byte block error location based on BCH algorithm
Eight simultaneous processing contexts
Page-based and continuous modes
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•
Interrupt generation when error location process completes:
–
–
When the full page has been processed in page mode
For each syndrome polynomial (checksum-like information) in continuous mode
For more information, see section Error Location Module (ELM) in chapter Memory Subsystem of the
device TRM.
6.9.4 OCMC
There is one on-chip memory controller (OCMC) in the device.
The OCM Controller supports the following features:
•
•
L3_MAIN data interface:
–
–
–
Used for maximum throughput performance
128-bit data bus width
Burst supported
L4 interface (OCMC_RAM only):
–
–
–
–
Used for access to configuration registers
32-bit data bus width
Only single accesses supported
The L4 associated OCMC clock is two times lower than the L3 associated OCMC clock
•
Error correction and detection:
–
–
Single error correction and dual error detection
9-bit Hamming error correction code (ECC) calculated on 128-bit data word which is concatenated
with memory address bits
–
–
–
–
–
–
Hamming distance of 4
Enable/Disable mode control through a dedicated register
Single bit error correction on a read transaction
Exclusion of repeated addresses from correctable error address trace history
ECC valid for all write transactions to an enabled region
Sub-128-bit writes supported via read modify write
•
•
ECC Error Status Reporting:
–
–
Trace history buffer (FIFO) with depth of 4 for corrected error address
Trace history buffer with depth of 4 for non correctable error address and also including double
error detection
–
Interrupt generation for correctable and uncorrectable detected errors
ECC Diagnostics Configuration:
–
Counters for single error correction (SEC), double error detection (DED) and address error events
(AEE)
–
–
–
Programmable threshold registers for exeptions associated with SEC, DED and AEE counters
Register control for enabling and disabling of diagnostics
Configuration registers and ECC status accessible through L4 interconnect
•
Circular buffer for sliced based VIP frame transfers:
–
–
Up to 12 programmable circular buffers mapped with unique virtual frame addresses
On the fly (with no additional latency) address translation from virtual to OCMC circular buffer
memory space
–
–
–
–
Virtual frame size up to 8 MiB and circular buffer size up to 1 MiB
Error handling and reporting of illegal CBUF addressing
Underflow and Overflow status reporting and error handling
Last access read/write address history
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•
Two Interrupt outputs configured independently to service either ECC or CBUF interrupt events
The OCM controller does not have a memory protection logic and does not support endianism conversion.
For more information, see section On-Chip Memory (OCM) in chapter Memory Subsystem of the device
TRM.
6.10 Interprocessor Communication
6.10.1 MailBox
Communication between the on-chip processors of the device uses a queued mailbox-interrupt
mechanism.
The queued mailbox-interrupt mechanism allows the software to establish a communication channel
between two processors through a set of registers and associated interrupt signals by sending and
receiving messages (mailboxes).
The device implements the following mailbox types:
•
System mailbox:
–
–
–
Number of instances: 13
Used for communication between: MPU, DSP1, IPU1, and IPU2 subsystems
Reference name: MAILBOX(1..13)
•
IVA mailbox:
–
–
Number of instances: 1
Used for communication between: IVA local user (ICONT1, or ICONT2) and three external users
(selected among MPU, DSP1, IPU1, and IPU2 subsystems)
–
Reference name: IVA_MBOX
Each mailbox module supports the following features:
•
Parameters configurable at design time
–
–
–
Number of users
Number of mailbox message queues
Number of messages (FIFO depth) for each message queue
•
•
•
•
32-bit message width
Message reception and queue-not-full notification using interrupts
Support of 16-/32-bit addressing scheme
Power management support
For more information, see chapter MailBox of the device TRM.
6.10.2 Spinlock
The Spinlock module provides hardware assistance for synchronizing the processes running on multiple
processors in the device:
•
•
•
Cortex®-A15 microprocessor unit (MPU) subsystem
Digital signal processor (DSP) subsystem – DSP1
Dual Cortex-M4 image processing unit (IPU) subsystems – IPU1 and IPU2
The Spinlock module implements 256 spinlocks (or hardware semaphores), which provide an efficient
way to perform a lock operation of a device resource using a single read-access, avoiding the need of
a readmodify- write bus transfer that the programmable cores are not capable of.
For more information, see chapter Spinlock Module of the device TRM.
6.11 Interrupt Controller
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The device has a large number of interrupts to service the needs of its many peripherals and subsystems.
The MPU, DSP, and IPU (x2) subsystems are capable of servicing these interrupts via their integrated
interrupt controllers. In addition, each processor's interrupt controller is preceded by an Interrupt Controller
Crossbar (IRQ_CROSSBAR) that provides flexibility in mapping the device interrupts to processor
interrupt inputs. For more information about IRQ crossbar, see chapter Control Module of the Device
TRM.
Cortex®-A15 MPU Subsystem Interrupt Controller (MPU_INTC)
The MPU_INTC module (also called Generalized Interrupt Controller [GIC]) is a single functional unit that
is integrated in the Arm Cortex-A15 multiprocessor core (MPCore) alongside Cortex-A15 processor. It
provides:
•
•
•
•
•
•
160 hardware interrupt inputs
Generation of interrupts by software
Prioritization of interrupts
Masking of any interrupts
Distribution of the interrupts to the target Cortex-A15 processor(s)
Tracking the status of interrupts
The Cortex-A15 processor supports three main groups of interrupt sources, with each interrupt source
having a unique ID:
•
Software Generated Interrupts (SGIs): SGIs are generated by writing to the Cortex-A15 Software
Generated Interrupt Register (GICD_SGIR). A maximum of 16 SGIs (ID0–ID15) can be generated for
the CPU interface. An SGI has edge-triggered properties. The software triggering of the interrupt is
equivalent to the edge transition of the interrupt signal on a peripheral input.
•
•
Private Peripheral Interrupts (PPIs): A PPI is an interrupt generated by a peripheral that is specific to
the processor. Although interrupts ID16–ID31 are dedicated to PPIs in general, only seven PPIs are
actually used for the CPU interface (ID25–ID31). Interrupts ID16–ID24 are reserved (not used).
Shared Peripheral Interrupts (SPIs): SPIs are triggered by events generated on associated interrupt
input lines. In this device, the GIC is configured to support 160 SPIs corresponding to its external
IRQS[159:0] signals.
For detailed information about this module and description of SGIs and PPIs, see the Arm Cortex-A15
MPCore Technical Reference Manual (available at infocenter.arm.com/help/index.jsp).
C66x DSP Subsystem Interrupt Controller (DSP1_INTC)
The DSP1 subsystem integrates an interrupt controller - DSP1_INTC, which interfaces the system events
to the C66x core interrupt and exceptions inputs. It combines up to 128 interrupts into 12 prioritized
interrupts presented to the C66x CPU.
For detailed information about this module, see chapter DSP Subsystem of the Device TRM.
Dual Cortex-M4 IPU Subsystem Interrupt Controller (IPUx_Cx_INTC, where x = 1, 2)
There are two Image Processing Unit (IPU) subsystems in the device - IPU1, and IPU2. Each IPU
subsystem integrates two Arm Cortex-M4 cores.
A Nested Vectored Interrupt Controller (NVIC) is integrated within each Cortex-M4. The interrupt mapping
is the same (per IPU) for the two cores to facilitate parallel processing. The NVIC supports:
•
64 external interrupts (in addition to 16 Cortex-M4 internal interrupts), which are dynamically prioritized
with 16 levels of priority defined for each core
•
•
•
•
Low-latency exception and interrupt handling
Prioritization and handling of exceptions
Control of the local power management
Debug accesses to the processor core
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For detailed information about this module, refer to Arm Cortex-M4 Technical Reference Manual (available
at infocenter.arm.com/help/index.jsp).
6.12 EDMA
The primary purpose of the Enhanced Direct Memory Access (EDMA) controller is to service user-
programmed data transfers between two memory-mapped slave endpoints on the device.
Typical usage of the EDMA controller includes:
•
Servicing software-driven paging transfers (for example, data movement between external memory
[such as SDRAM] and internal memory [such as DSP L2 SRAM])
•
•
•
Servicing event-driven peripherals, such as a serial port
Performing sorting or sub-frame extraction of various data structures
Offloading data transfers from the main device CPUs, such as the C66x DSP CorePac or the Arm
CorePac
The EDMA controller consists of two major principle blocks:
•
•
EDMA Channel Controller
EDMA Transfer Controller(s)
The EDMA Channel Controller (EDMACC) serves as the user interface for the EDMA controller. The
EDMACC includes parameter RAM (PaRAM), channel control registers, and interrupt control registers.
The EDMACC serves to prioritize incoming software requests or events from peripherals and submits
transfer requests (TR) to the EDMA transfer controller.
The EDMA Transfer Controller (EDMATC) is responsible for data movement. The transfer request packets
(TRP) submitted by the EDMACC contain the transfer context, based on which the transfer controller
issues read/write commands to the source and destination addresses programmed for a given transfer.
There are two EDMA controllers present on this device:
•
EDMA_0, integrating:
–
–
1 Channel Controller, referenced as: EDMACC_0
2 Transfer Controllers, referenced as: EDMACC_0_TC_0 (or EDMATC_0) and EDMACC_0_TC_1
(or EDMATC_1)
•
EDMA_1, integrating:
–
–
1 Channel Controller, referenced as: EDMACC_1
2 Transfer Controllers, referenced as: EDMACC_1_TC_0 (or EDMATC_2) and EDMACC_1_TC_1
(or EDMATC_3)
The two EDMA channel controllers (EDMACC_0 and EDMACC_1) are functionally identical. For
simplification, the unified name EDMACC shall be regularly used throughout this chapter when referring to
EDMA Channel Controllers functionality and features.
The four EDMA transfer controllers (EDMACC_0_TC_0, EDMACC_0_TC_1, EDMACC_1_TC_0 and
EDMACC_1_TC_1) are functionally identical. For simplification, the unified name EDMATC shall be
regularly used throughout this chapter when referring to EDMA Transfer Controllers functionality and
features.
Each EDMACC has the following features:
•
Fully orthogonal transfer description
–
3 transfer dimensions:
•
•
•
Array (multiple bytes)
Frame (multiple arrays)
Block (multiple frames)
–
–
Single event can trigger transfer of array, frame, or entire block
Independent indexes on source and destination
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•
•
Flexible transfer definition
–
–
–
Increment or constant addressing modes
Linking mechanism allows automatic PaRAM set update
Chaining allows multiple transfers to execute with one event
64 DMA channels
–
Channels triggered by either:
•
•
•
Event synchronization
Manual synchronization (CPU write to event set register)
Chain synchronization (completion of one transfer triggers another transfer)
–
Support for programmable DMA Channel to PaRAM mapping
•
8 Quick DMA (QDMA) channels
–
–
QDMA channels are triggered automatically upon writing to PaRAM set entry
Support for programmable QDMA channel to PaRAM mapping
•
•
•
512 PaRAM sets
Each PaRAM set can be used for a DMA channel, QDMA channel, or link set
2 transfer controllers/event queues
16 event entries per event queue
Interrupt generation based on:
–
–
–
–
Transfer completion
Error conditions
•
•
Debug visibility
–
–
Queue water marking/threshold
Error and status recording to facilitate debug
Memory protection support
–
–
Proxied memory protection for TR submission
Active memory protection for accesses to PaRAM and registers
Each EDMATC has the following features:
•
Supports 2-dimensional (2D) transfers with independent indexes on source and destination (EDMACC
manages the 3rd dimension)
•
•
•
•
•
•
Up to 4 in-flight transfer requests (TR)
Programmable priority levels
Support for increment or constant addressing mode transfers
Interrupt and error support
Supports only little-endian operation in this device
Memory mapped register (MMR) bit fields are fixed position in 32-bit MMR
For more information chapter EDMA Controller of the device TRM.
6.13 Peripherals
6.13.1 VIP
The VIP module provides video capture functions for the device. VIP incorporates a multi-channel raw
video parser, various video processing blocks, and a flexible Video Port Direct Memory Access (VPDMA)
engine to store incoming video in various formats. The device uses a single instantiation of the VIP
module giving the ability of capturing up to two video streams.
A VIP module includes the following main features:
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•
•
Two independently configurable external video input capture slices (Slice 0 and Slice 1) each of which
has two video input ports, Port A and Port B, where Port A can be configured as a 24/16/8-bit port, and
Port B is a fixed 8-bit port.
Each video Port A can be operated as a port with clock independent input channels (with interleaved or
separated Y/C data input). Embedded sync and external sync modes are supported for all input
configurations.
•
•
Support for a single external asynchronous pixel clock, up to 165MHz per port.
Pixel Clock Input Domain Port A supports up to one 24-bit input data bus, including BT.1120 style
embedded sync for 16-bit and 24-bit data.
•
•
•
Embedded Sync data interface mode supports single or multiplexed sources
Discrete Sync data interface mode supports only single source input
24-bit data input plus discrete syncs can be configured to include:
–
–
–
–
–
–
–
8-bit YUV422 (Y and U/V time interleaved)
16-bit YUV422 (CbY and CrY time interleaved)
24-bit YUV444
16-bit RGB565
24-bit RGB888
12/16-bit RAW Capture
24-bit RAW capture
•
•
•
Discrete sync modes include:
–
–
–
–
VSYNC + HSYNC (FID determined by FID signal pin or HSYNC/VSYNC skew)
VSYNC + ACTVID + FID
VBLANK + ACTVID (ACTVID toggles in VBLANK) + FID
VBLANK + ACTVID (no ACTVID toggles in VBLANK) + FID
Multichannel parser (embedded syncs only)
–
–
–
–
Embedded syncs only
Pixel (2x or 4x) or Line multiplexed modes supported
Performs demultiplexing and basic error checking
Supports maximum of 9 channels in Line Mux (8 normal + 1 split line)
Ancillary data capture support
–
–
For 16-bit or 24-bit input, ancillary data may be extracted from any single channel
For 8-bit time interleaved input, ancillary data can be chosen from the Luma channel, the Chroma
channel, or both channels
–
–
Horizontal blanking interval data capture only supported when using discrete syncs (VSYNC +
HSYNC or VSYNC + HBLANK)
Ancillary data extraction supported on multichannel capture as well as single source streams
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•
Format conversion and scaling
–
–
–
–
–
Programmable color space conversion
YUV422 to YUV444 conversion
YUV444 to YUV422 conversion
YUV422 to YUV420 conversion
YUV444 Source: YUV444 to YUV444, YUV444 to RGB888, YUV444 to YUV422, YUV444 to
YUV420
–
–
RGB888 Source: RGB888 to RGB888, RGB888 to YUV444, RGB888 to YUV422, RGB888 to
YUV420
YUV422 Source: YUV422 to YUV422, YUV422 to YUV420, YUV422 to YUV444, YUV422 to
RGB888
–
–
Supports RAW to RAW (no processing)
Scaling and format conversions do not work for multiplexed input
•
•
Supports up to 2047 pixels wide input - when scaling is engaged
Supports up to 3840 pixels wide input - when only chroma up/down sampling is engaged, without
scaling
•
•
Supports up to 4095 pixels wide input - without scaling and chroma up/down sampling
The maximum supported input resolution is further limited by:
–
–
Pixel clock and feature-dependent constraints
For RGB24-bit format (RAW data), the maximum frame width is limited to 2730 pixels
For more information, see chapter Video Input Port of the device TRM
6.13.2 DSS
Display Port Interfaces (DPI) is available in DSS named DPI Video Output (VOUT).
VOUT interface consists of:
•
•
•
•
•
•
24-bit data bus (data[23:0])
Horizontal synchronization signal (HSYNC)
Vertical synchronization signal (VSYNC)
Data enable (DE)
Field ID (FID)
Pixel clock (CLK)
For more information, see section Display Subsystem (DSS) of the device TRM.
6.13.3 Timers
The device includes several types of timers used by the system software, including 16 general-purpose
(GP) timers, one watchdog timer, and a 32-kHz synchronized timer (COUNTER_32K).
6.13.3.1 General-Purpose Timers
The device has 16 GP timers: TIMER1 through TIMER16.
•
TIMER1(1ms tick): has its event capture pin tied to 32KHz clock and can be used to gauge the system
clock input and detects its frequency among 19.2, 20, or 27 MHz. It includes a specific functions to
generate accurate tick interrupts to the operating system and it belongs to the PD_WKUPAON domain
•
TIMER2 and TIMER10: (1ms tick timers): they include a specific functions to generate accurate tick
interrupts to the operating system, TIMER2 and TIMER10 belong to the PD_L4PER domain
•
•
•
TIMER3/4/9/11/13/14/15/16: they belongs to the PD_L4PER domain
TIMER12 belongs to the PD_WKUPAON power domain
TIMER5 trough TIMER8: belong to the PD_IPU module
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Each timer (except TIMER12) can be clocked from the system clock (19.2, 20, or 27 MHz) or the 32-kHz
clock. The selection of clock source is made at the power, reset, and clock management (PRCM) module
level. TIMER12 can be clocked only from the internal oscillator (on-die oscillator)
The following are the main features of the GP timer controllers:
•
Level 4 (L4) slave interface support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
10-bit address bus width
Burst mode not supported
Write nonposted transaction mode supported
•
•
•
•
•
•
•
•
•
•
Interrupts generated on overflow, compare, and capture
Free-running 32-bit upward counter
Compare and capture modes
Autoreload mode
Start/stop mode
Programmable divider clock source (2n, where n = [0:8])
Dedicated input trigger for capture mode and dedicated output trigger/PWM signal
Dedicated GP output signal for using the TIMERi_GPO_CFG signal
On-the-fly read/write register (while counting)
1-ms tick with 32.768-Hz functional clock generated (only TIMER1, TIMER2, and TIMER10)
For more information, see section Timers of the device TRM.
6.13.3.2 32-kHz Synchronized Timer (COUNTER_32K)
The 32-kHz synchronized timer (COUNTER_32K) is a 32-bit counter clocked by the falling edge of the 32-
kHz system clock.
The main features of the 32-kHz synchronized timer controller are:
•
L4 slave interface (OCP) support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
16-bit address bus width
Burst mode not supported
Write nonposted transaction mode not supported
•
Only read operations are supported on the module registers; no write operation is supported (no
error/no action on write).
•
•
•
•
Free-running 32-bit upward counter
Start and keep counting after power-on reset
Automatic roll over to 0; highest value reached: 0xFFFF FFFF
On-the-fly read (while counting)
For more information, see section Timers of the device TRM.
6.13.3.3 Watchdog Timer
The device includes one instance of the 32-bit watchdog timer: WD_TIMER2.
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The watchdog timer is an upward counter capable of generating a pulse on the reset pin and an interrupt
to the device system modules following an overflow condition. The WD_TIMER2 timer serves resets to the
PRCM module (its interrupt outputs are unused).
WD_TIMER2 is located in the PD_WKUPAON power domain, and can run when the device is in lowest
power state (all power domains are off except always-on (AON) and WKUP).
The watchdog timer can be accessed, loaded, and cleared by registers through the L4_WKUP interface.
The watchdog timer has the 32-kHz clock for its timer clock input. WD_TIMER2 directly generates a warm
reset condition on overflow.
WD_TIMER2 connects to a single target agent port on the L4_WKUP interconnect.
The main features of the watchdog timer controllers are:
•
L4 slave interface support:
–
–
–
–
–
–
32-bit data bus width
32-/16-bit access supported
8-bit access not supported
11-bit address bus width
Burst mode not supported
Write nonposted mode supported
•
•
•
•
•
•
•
Free-running 32-bit upward counter
Programmable divider clock source (2n where n = [0:7])
On-the-fly read/write register (while counting)
Subset programming model of the GP timer
The watchdog timer is reset either on power on or after a warm reset before it starts counting.
Reset or interrupt actions when a timer overflow condition occurs
The watchdog timer generates a reset or an interrupt in its hardware integration.
For more information, see section Timers of the device TRM.
6.13.4 I2C
The device contains five multimaster high-speed (HS) inter-integrated circuit (I2C) controllers (I2Ci
modules, where i = 1, 2 ,3, 4, 5, 6) each of which provides an interface between a local host (LH), such as
a digital signal processor (DSP), and any I2C-bus-compatible device that connects through the I2C serial
bus. External components attached to the I2C bus can serially transmit and receive up to 8 bits of data to
and from the LH device through the 2-wire I2C interface.
Each multimaster HS I2C controller can be configured to act like a slave or master I2C-compatible device.
I2C1 and I2C2 controllers have dedicated I2C compliant open drain buffers, and support Fast mode (up to
400Kbps). I2C3, I2C4, I2C5 and I2C6 controllers are multiplexed with standard LVCMOS IO and connected
to emulate open drain. I2C emulation is achieved by configuring the LVCMOS buffers to output Hi-Z
instead of driving high when transmitting logic 1. These controllers support HS mode (up to 3.4Mbps).
For more information, see section Multimaster High-Speed I2C Controller (I2C) in chapter Serial
Communication Interfaces of the device TRM.
6.13.5 UART
The UART is a simple L4 slave peripheral that utilizes the DMA_SYSTEM or EDMA for data transfer or
IRQ polling via CPU. There are 10 UART modules in the device. Only one UART supports IrDA features.
Each UART can be used for configuration and data exchange with a number of external peripheral
devices or interprocessor communication between devices.
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6.13.5.1 UART Features
The UARTi (where i = 1 to 10) include the following features:
16C750 compatibility
64-byte FIFO buffer for receiver and 64-byte FIFO for transmitter
Programmable interrupt trigger levels for FIFOs
•
•
•
•
Baud generation based on programmable divisors N (where N = 1…16,384) operating from a fixed
functional clock of 48 MHz or 192 MHz
Oversampling is programmed by software as 16 or 13. Thus, the baud rate computation is one of two
options:
•
•
•
Baud rate = (functional clock / 16) / N
Baud rate = (functional clock / 13) / N
This software programming mode enables higher baud rates with the same error amount without
changing the clock source
•
•
Break character detection and generation
Configurable data format:
–
–
–
Data bit: 5, 6, 7, or 8 bits
Parity bit: Even, odd, none
Stop-bit: 1, 1.5, 2 bit(s)
•
•
•
•
•
Flow control: Hardware (RTS/CTS) or software (XON/XOFF)
The 48 MHz functional clock option allows baud rates up to 3.6Mbps
The 192 MHz functional clock option allows baud rates up to 12Mbps
UART1 module has extended modem control signals (DCD, RI, DTR, DSR)
UART3 supports IrDA
6.13.5.2 IrDA Features
UART3 supports the following IrDA key features:
•
Support of IrDA 1.4 slow infrared (SIR), medium infrared (MIR), and fast infrared (FIR)
communications:
–
Frame formatting: Addition of variable beginning-of-frame (xBOF) characters and end-of-frame
(EOF) characters
–
–
–
–
Uplink/downlink cyclic redundancy check (CRC) generation/detection
Asynchronous transparency (automatic insertion of break character)
Eight-entry status FIFO (with selectable trigger levels) to monitor frame length and frame errors
Framing error, CRC error, illegal symbol (FIR), and abort pattern (SIR, MIR) detection
6.13.5.3 CIR Features
The CIR mode uses a variable pulse-width modulation (PWM) technique (based on multiples of a
programmable t period) to encompass the various formats of infrared encoding for remote-control
applications. The CIR logic transmits data packets based on a user-definable frame structure and packet
content.
The CIR (UART3 only) includes the following features to provide CIR support for remote-control
applications:
•
•
•
•
•
Transmit mode only (receive mode is not supported)
Free data format (supports any remote-control private standards)
Selectable bit rate
Configurable carrier frequency
1/2, 5/12, 1/3, or 1/4 carrier duty cycle
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For more information, see section Universal Asynchronous Receiver/Transmitter (UART) in chapter Serial
Communication Interfaces of the device TRM.
6.13.6 McSPI
The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (McSPI1,
McSPI2, McSPI3, and McSPI4) in the device. All these four modules support up to four external devices
(four chip selects) and are able to work as both master and slave.
The McSPI modules include the following main features:
•
•
•
•
Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of McSPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
–
–
–
–
–
Full duplex/half duplex
Transmit-only/receive-only/transmit-and-receive modes
Flexible input/output (I/O) port controls per channel
Programmable clock granularity
McSPI configuration per channel. This means, clock definition, polarity enabling and word width
•
•
•
•
•
•
•
Single interrupt line for multiple interrupt source events
Power management through wake-up capabilities
Enable the addition of a programmable start-bit for McSPI transfer per channel (start-bit mode)
Supports start-bit write command
Supports start-bit pause and break sequence
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel
For more information, see section Serial Peripheral Interface (McSPI) in chapter Serial Communication
Interfaces of the device TRM.
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6.13.7 QSPI
The quad serial peripheral interface (QSPI™) module is a kind of SPI module that allows single, dual, or
quad read access to external SPI devices. This module has a memory mapped register interface, which
provides a direct interface for accessing data from external SPI devices and thus simplifying software
requirements. The QSPI works as a master only.
The QSPI supports the following features:
•
General SPI features:
–
–
–
–
–
–
–
–
–
–
–
–
Programmable clock divider
Six pin interface
Programmable length (from 1 to 128 bits) of the words transferred
Programmable number (from 1 to 4096) of the words transferred
4 external chip-select signals
Support for 3-, 4-, or 6-pin SPI interface
Optional interrupt generation on word or frame (number of words) completion
Programmable delay between chip select activation and output data from 0 to 3 QSPI clock cycles
Programmable signal polarities
Programmable active clock edge
Software-controllable interface allowing for any type of SPI transfer
Control through L3_MAIN configuration port
•
Serial flash interface (SFI) features:
–
–
–
–
Serial flash read/write interface
Additional registers for defining read and write commands to the external serial flash device
1 to 4 address bytes
Fast read support, where fast read requires dummy bytes after address bytes; 0 to 3 dummy bytes
can be configured.
–
–
–
–
Dual read support
Quad read support
Little-endian support only
Linear increment addressing mode only
The QSPI supports only dual and quad reads. Dual or quad writes are not supported. In addition, there is
no "pass through" mode supported where the data present on the QSPI input is sent to its output.
For more information, see section Quad Serial Peripheral Interface (QSPI) in chapter Serial
Communication Interfaces of the device TRM.
6.13.8 McASP
The McASP functions as a general-purpose audio serial port optimized to the requirements of various
audio applications. The McASP module can operate in both transmit and receive modes. The McASP is
useful for time-division multiplexed (TDM) stream, Inter-IC Sound (I2S) protocols reception and
transmission as well as for an intercomponent digital audio interface transmission (DIT). The McASP has
the flexibility to gluelessly connect to a Sony/Philips digital interface (S/PDIF) transmit physical layer
component.
Although intercomponent digital audio interface reception (DIR) mode (i.e. S/PDIF stream receiving) is not
natively supported by the McASP module, a specific TDM mode implementation for the McASP receivers
allows an easy connection to external DIR components (for example, S/PDIF to I2S format converters).
The device have integrated 8 McASP modules (McASP1-McASP8) with:
•
•
McASP1 and McASP2 supporting 16 channels with independent TX/RX clock/sync domain
McASP3 through McASP8 modules supporting 4 channels with independent TX/RX clock/sync domain
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For more information, see section Multi-channel Audio Serial Port (McASP) in chapter Serial
Communication Interfaces of the device TRM.
6.13.9 USB
SuperSpeed USB DRD Subsystem has three instances in the device providing the following functions:
•
USB1: SuperSpeed (SS) USB 3.0 Dual-Role-Device (DRD) subsystem with integrated SS (USB3.0)
PHY and HS/FS (USB2.0) PHY
•
•
USB2: High-Speed (HS) USB 2.0 Dual-Role-Device (DRD) subsystem with integrated HS/FS PHY
USB3: HS USB 2.0 Dual-Role-Device (DRD) subsystem with ULPI (SDR) interface to external HS/FS
PHYs
SuperSpeed USB DRD Subsystem has the following features:
• Dual-role-device (DRD) capability:
–
Supports USB Peripheral (or Device) mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps),
and FS (12 Mbps)
–
Supports USB Host mode at speeds SS (5Gbps)(USB1 only), HS (480 Mbps), FS (12 Mbps), and
LS (1.5 Mbps)
–
–
–
–
–
USB static peripheral operation
USB static host operation
Flexible stream allocation
Stream priority
External Buffer Control
•
Each instance contains single xHCI controller with the following features:
–
–
–
–
–
–
–
Internal DMA controller
Descriptor caching and data prefetching
Interrupt moderation and blocking
Power management USB3.0 states for U0, U1, U2, and U3
Dynamic FIFO memory allocation for all endpoints
Supports all modes of transfers (control, bulk, interrupt, and isochronous)
Supports high bandwidth ISO mode
•
•
Connects to an external charge pump for VBUS 5 V generation
USB-HS PHY (USB2PHY1 and USB2PHY2 for USB1 and USB2, respectively): contain the USB
functions, drivers, receivers, and pads for correct D+/D– signalling
•
USB3PHY. The USB3PHY is embedded in the USB1 subsystem and contains:
–
–
–
USB3RX_PHY deserializer to receive data at SuperSpeed mode
USB3TX_PHY serializer to transmit data at SuperSpeed mode
Power sequencer that contains a power control state machine, generating the sequences to power
up/down the USB3RX_PHY/USB3TX_PHY
–
Dedicated DPLL (DPLL_USB_OTG_SS)
For more information, see section SuperSpeed USB DRD (USB) in chapter Serial Communication
Interfaces of the device TRM.
6.13.10 PCIe
The Peripheral Component Interconnect Express (PCIe) module is a multi-lane I/O interconnect that
provides low pin-count, high reliability, and high-speed data transfer at rates of up to 5.0 Gbps per lane,
per direction, for serial links on backplanes and printed wiring boards. It is a 3-rd Generation I/O
Interconnect technology succeeding PCI and ISA bus that is designed to be used as a general-purpose
serial I/O interconnect. It is also used as a bridge to other interconnects like USB2/3.0, GbE MAC, and so
forth.
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The PCI Express standard predecessor - PCI, is a parallel bus architecture that is increasingly difficult to
scale-up in bandwidth, which is usually performed by increasing the number of data signal lines. The PCIe
architecture was developed to help minimize I/O bus bottlenecks within systems and to provide the
necessary bandwidth for high-speed, chip-to-chip, and board-to-board communications within a system. It
is designed to replace the PCI-based shared, parallel bus signaling technology that is approaching its
practical performance limits while simplifying the interface design.
The device instantiates two PCIe subsystems (PCIe_SS1 and PCIe_SS2). The PCIe controller is capable
to operate either in Root Complex (RC) or in End Point (EP) PCIe mode. The device PCIe_SS1 controller
supports up to two 16-bit data lanes on its PIPE port. The device PCIe_SS2 controller supports only one
16-bit data lane on its PIPE port.
When the PCIe_SS1 controller PIPE port is configured to operate in a single-lane mode, it operates on a
single pair of PCIe PHY serializer and deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX. When PCIe_SS1
PIPE is configured to operate in dual-lane mode, it operates on two pairs of PCIe PHY serializer and
deserializer - PCIe1_PHY_TX/PCIe1_PHY_RX and PCIe2_PHY_TX/PCIe2_PHY_RX, respectively. The
single-lane PCIe_SS2 controller PIPE port (if enabled) can operate only on the
PCIe2_PHY_TX/PCIe2_PHY_RX pair. Hereby, if PCIe_SS2 controller is used, the PCIe_SS1 can operate
only in a single-lane mode on the PCIe1_PHY_TX/PCIe1_PHY_RX. In addition, PCIe PHY subsystem
encompasses a PCIe PCS (physical coding sublayer), a PCIe power management logic, APLL, a DPLL
reference clock generator and an APLL clock low-jitter buffer.
•
•
The PCIe Controller implements the transport and link layers of the PCIe interface protocol.
PCIe PCS (a physical coding sublayer component) converts a 8-bit portion of parallel data over a PCIe
lane to a 10-bit parallel data to adapt the process of serialization and deserialization in the TX/RX
PHYs to various requirements. At the same time it transforms the transmission rate to maintain the
PCIe Gen2 bandwidth (5 Gbps) on both sides (PCIe controller and PHY).
•
•
A multiplexer logic which adds flexibility to connect a PCIe controller hardware mapped PCS logic
output to a single (for the single-lane PCIe_SS2 controller) or to a couple (for the 2-lane PCIe_SS1
controller) of PHY ports at a time
Physical layer (PHY) serializer/deserializer components with associated power control logic, building
the so called PMA (physical media attachment) part of the PCIe_PHY transceiver, as follows:
–
PCIe physical port 0 associated serializer (TX) - PCIe1_PHY_TX and deserializer (RX) -
PCIe1_PHY_RX
–
PCIe physical port 1 associated serializer (TX) - PCIe2_PHY_TX and deserializer (RX) -
PCIe2_PHY_RX
•
•
•
DPLL_PCIe_REF is a DPLL clock source, controlled from the device PRCM, that provides a 100-MHz
clock to the PCIe PHY serializer/deserializer components reference clock inputs.
Both the PCIe_SS1 and PCIe_SS2 share the same APLL (APLLPCIe) which by default multiplies the
DPLL_PCIe_REF (typically 100 MHz or 20 MHz) clock to 2.5 GHz.
The APLLPCIe low-jitter buffer (ACSPCIE) and additional logic takes care to provide the PCIe APLL
reference input clock.
PCIe module supports the following features:
•
•
PCI Local Bus Specification revision 3.0
PCI Express Base 3.0 Specification, revision 1.0.
At system level the device supports PCI express interface in the following configurations:
•
•
•
Each PCIe subsystem controller has support for PCIe Gen2 mode (5.0 Gbps per lane) and Gen1 mode
(2.5 Gbps per lane).
One PCIe (PCIe_SS1) operates as Gen2 2-lanes supporting in either root-complex (RC) or end-point
EP.
Two PCIe (PCIe_SS1 and PCIe_SS2) operates Gen2 1-lane supporting either RC or EP with the
possibility of one operating in Gen1 and one in Gen2.
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•
•
PCIe_SS1 can be configured to operate in either 2-Lane (dual lane) or 1-Lane (single lane) mode, as
follows:
–
–
Single Lane - lane 0 mapped to the PCIe port 0 of the device
Flexible dual lane configuration - lanes 0 and 1 can be swapped on the two PCIe ports
PCIe_SS2 can only operate in 1-Lane mode, as follows:
Single Lane - lane 0 mapped to the device PCIe port 1
–
When PCIe_SS1 is configured to operate in dual-lane mode, PCIe_SS2 is in-operable as both
PCIe1_PHY_RX/TX and PCIe2_PHY_RX/TX are assigned to PCIe_SS1, and thereby NOT available to
PCIe_SS2.
The main features of a device PCIe controller are:
•
•
•
16-bit operation at 250 MHz on PIPE interface (per 16-bit lane)
One master port on the L3_MAIN supporting 32-bit address and 64-bit data bus.
PCIe_SS1 master port dedicated MMU (device MMU2) on L3_MAIN path, to which PCIe traffic can be
optionally mapped.
•
•
One slave port on the L3_MAIN supporting 29-bit address and 64-bit data bus.
Maximum outbound payload size of 64 Bytes (the L3 Interconnect PCIe1/2 target ports split bursts of
size >64 Bytes to the into multiple 64 Byte bursts)
•
•
•
•
•
Maximum inbound payload size of 256 Bytes (internally converted to 128 Byte - bursts)
No remote read request size limit: implicit support for 4 KiB-size and greater
Support of EP legacy mode
Support of inbound I/O accesses in EP legacy mode
PIPE interface features fixed-width (16-bit data per lane) and dynamic frequency to switch between
PCIe Gen1 and Gen2.
•
•
Ultra-low transmit and receive latency
Automatic Lane reversal as specified in the PCI Express Base 3.0 Specification, revision 1.0 (transmit
and receive)
•
•
•
•
•
•
•
•
•
•
•
•
•
Polarity inversion on receive
Single Virtual Channel (VC0) and Single Traffic Class (TC0)
Single Function in End point mode
Automatic credit management
ECRC generation and checking
All PCI Device Power Management D-states with the exception of D3cold/L2 state
PCI Express Active State Power Management (ASPM) state L0s and L1 (with exceptions)
PCI Express Link Power Management states except for L2 state
PCI Express Advanced Error Reporting (AER)
PCI Express messages for both transmit and receive
Filtering for Posted, Non-Posted, and Completion traffic
Configurable BAR filtering, I/O filtering, configuration filtering and completion lookup/timeout
Access to configuration space registers and external application memory mapped registers through
ECAM mechanism.
•
•
Legacy PCI Interrupts reception (RC) and generation (EP)
2 x hardware interrupts per PCIe_SS1and PCIe_SS2 controller mapped via the device Interrupt
Crossbar (IRQ_CROSSBAR) to multiple device host (MPU, DSP, and so forth) interrupt controllers in
the device
•
•
MSIs generation and reception
PCIe_PHY Loopback in RC mode
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For more information, see section PCIe Controller in chapter Serial Communication Interfaces of the
device TRM.
6.13.11 DCAN
The Controller Area Network (CAN) is a serial communications protocol which efficiently supports
distributed real-time applications. CAN has high immunity to electrical interference and the ability to self-
diagnose and repair data errors. In a CAN network, many short messages are broadcast to the entire
network, which provides for data consistency in every node of the system.
The device provides two DCAN interfaces for supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports CAN protocol version 2.0 part A, B
Bit rates up to 1 MBit/s
64 message objects
Individual identifier mask for each message object
Programmable FIFO mode for message objects
Programmable loop-back modes for self-test operation
Suspend mode for debug support
Software module reset
Automatic bus on after Bus-Off state by a programmable 32-bit timer
Direct access to Message RAM during test mode
CAN Rx/Tx pins are configurable as general-purpose IO pins
Two interrupt lines (plus additional parity-error interrupts line)
RAM initialization
DMA support
For more information, see section Controller Area Network Interface (DCAN) in chapter Serial
Communication Interfaces of the device TRM.
6.13.12 GMAC_SW
The three-port gigabit ethernet switch subsystem (GMAC_SW) provides ethernet packet communication
and can be configured as an ethernet switch. It provides the gigabit media independent interface (G/MII) in
MII mode, reduced gigabit media independent interface (RGMII), reduced media independent interface
(RMII), and the management data input output (MDIO) for physical layer device (PHY) management.
The GMAC_SW subsystem provides the following features:
•
Two Ethernet ports (port 1 and port 2) with selectable RGMII, RMII, and G/MII (in MII mode only)
interfaces plus internal Communications Port Programming Interface (CPPI 3.1) on port 0
•
•
•
•
•
•
•
•
Synchronous 10/100/1000 Mbit operation
Wire rate switching (802.1d)
Non-blocking switch fabric
Flexible logical FIFO-based packet buffer structure
Four priority level Quality Of Service (QOS) support (802.1p)
CPPI 3.1 compliant DMA controllers
Support for Audio/Video Bridging (P802.1Qav/D6.0)
Support for IEEE 1588 Clock Synchronization (2008 Annex D and Annex F)
–
Timing FIFO and time stamping logic embedded in the subsystem
•
•
•
Device Level Ring (DLR) Support
Energy Efficient Ethernet (EEE) support (802.3az)
Flow Control Support (802.3x)
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•
Address Lookup Engine (ALE)
–
–
–
–
–
–
–
–
–
–
–
1024 total address entries plus VLANs
Wire rate lookup
Host controlled time-based aging
Multiple spanning tree support (spanning tree per VLAN)
L2 address lock and L2 filtering support
MAC authentication (802.1x)
Receive-based or destination-based multicast and broadcast rate limits
MAC address blocking
Source port locking
OUI (Vendor ID) host accept/deny feature
Remapping of priority level of VLAN or ports
•
•
VLAN support
802.1Q compliant
–
•
•
Auto add port VLAN for untagged frames on ingress
Auto VLAN removal on egress and auto pad to minimum frame size
Ethernet Statistics:
–
–
EtherStats and 802.3Stats Remote network Monitoring (RMON) statistics gathering (shared)
Programmable statistics interrupt mask when a statistic is above one half its 32-bit value
•
•
•
•
•
•
•
•
•
Flow Control Support (802.3x)
Digital loopback and FIFO loopback modes supported
Maximum frame size 2016 bytes (2020 with VLAN)
8k (2048 × 32) internal CPPI buffer descriptor memory
Management Data Input/Output (MDIO) module for PHY Management
Programmable interrupt control with selected interrupt pacing
Emulation support
Programmable Transmit Inter Packet Gap (IPG)
Reset isolation (switch function remains active even in case of all device resets except for POR pin
reset and ICEPICK cold reset)
•
•
Full duplex mode supported in 10/100/1000 Mbps. Half-duplex mode supported only in 10/100 Mbps.
IEEE 802.3 gigabit Ethernet conformant
For more information, see section Gigabit Ethernet Switch (GMAC_SW) in chapter Serial Communication
Interfaces of the device TRM.
6.13.13 eMMC/SD/SDIO
The eMMC/SD/SDIO host controller provides an interface between a local host (LH) such as a
microprocessor unit (MPU) or digital signal processor (DSP) and either eMMC, SD® memory cards, or
SDIO cards and handles eMMC/SD/SDIO transactions with minimal LH intervention.
Optionally, the controller is connected to the L3_MAIN interconnect to have a direct access to system
memory. It also supports two direct memory access (DMA) slave channels or a DMA master access (in
this case, slave DMA channels are deactivated) depending on its integration.
The eMMC/SD/SDIO host controller deals with eMMC/SD/SDIO protocol at transmission level, data
packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical correctness.
The application interface can send every eMMC/SD/SDIO command and poll for the status of the adapter
or wait for an interrupt request, which is sent back in case of exceptions or to warn of end of operation.
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The application interface can read card responses or flag registers. It can also mask individual interrupt
sources. All these operations can be performed by reading and writing control registers. The
eMMC/SD/SDIO host controller also supports two DMA channels.
There are four eMMC/SD/SDIO host controllers inside the device. gives an overview of the
eMMC/SD/SDIOi (i = 1 to 4) controllers.
Each controller has the following data width:
•
•
•
•
eMMC/SD/SDIO1 - 4-bit wide data bus
eMMC/SD/SDIO2 - 8-bit wide data bus
eMMC/SD/SDIO3 - 4-bit wide data bus
eMMC/SD/SDIO4 - 4-bit wide data bus
The eMMC/SD/SDIOi controller is also referred to as MMCi.
Compliance with standards:
•
•
•
•
Full compliance with MMC/eMMC command/response sets as defined in the JC64 MMC/eMMC
standard specification, v4.5.
Full compliance with SD command/response sets as defined in the SD Physical Layer specification
v3.01
Full compliance with SDIO command/response sets and interrupt/read-wait suspend-resume
operations as defined in the SD part E1 specification v3.00
Full compliance with SD Host Controller Standard Specification sets as defined in the SD card
specification Part A2 v3.00
Main features of the eMMC/SD/SDIO host controllers:
•
•
•
•
•
•
•
•
Flexible architecture allowing support for new command structure
32-bit wide access bus to maximize bus throughput
Designed for low power
Programmable clock generation
Dedicated DLL to support SDR104 mode (MMC1 only)
Dedicated DLL to support HS200 mode (MMC2 only)
Card insertion/removal detection and write protect detection
L4 slave interface supports:
–
–
–
–
–
32-bit data bus width
8/16/32 bit access supported
9-bit address bus width
Streaming burst supported only with burst length up to 7
WNP supported
•
L3 initiator interface Supports:
–
–
–
–
32-bit data bus width
8/16/32 bit access supported
32-bit address bus width
Burst supported
•
•
•
•
•
Built-in 1024-byte buffer for read or write
Two DMA channels, one interrupt line
Support JC 64 v4.4.1 boot mode operations
Support SDA 3.00 Part A2 programming model
Support SDA 3.00 Part A2 DMA feature (ADMA2)
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•
Supported data transfer rates:
–
MMCi supports the following SD v3.0 data transfer rates:
•
•
•
•
•
•
•
DS mode (3.3V IOs): up to 12 MBps (24 MHz clock)
HS mode (3.3V IOs): up to 24 MBps (48 MHz clock)
SDR12 (1.8V IOs): up to 12 MBps (24 MHz clock)
SDR25 (1.8V IOs): up to 24 MBps (48 MHz clock)
SDR50 (1.8V IOs): up to 48 MBps (96 MHz clock) - MMC1 and MMC3 only
DDR50 (1.8V IOs): up to 48 MBps (48 MHz clock) - MMC1 only
SDR104 (1.8V IOs) cards can be supported up to 192 MHz clock (96 MBps max) - MMC1 only
–
–
MMCi supports the Default SD mode 1-bit data transfer up to 24Mbps (3MBps)
Only MMC2 supports also the following JC64 v4.5 data transfer rates:
•
•
Up to 192 MBps in eMMC mode, 8-bit SDR mode (192 MHz clock frequency)
Up to 96 MBps in eMMC mode, 8-bit DDR mode (48 MHz clock frequency)
•
All eMMC/SD/SDIO controllers are connected to 1,8V/3.3V compatible I/Os to support 1,8V/3.3V
signaling
注
eMMC functionality is supported fully by MMC2 only. The other MMC modules are capable of
eMMC functionality, but are not timing-optimized for eMMC.
The differences between the eMMC/SD/SDIO host controllers and a standard SD host controller defined
by the SD Card Specification, Part A2, SD Host Controller Standard Specification, v3.00 are:
•
The clock divider in the eMMC/SD/SDIO host controller supports a wider range of frequency than
specified in the SD Memory Card Specifications, v3.0. The eMMC/SD/SDIO host controller supports
odd and even clock ratio.
•
•
•
The eMMC/SD/SDIO host controller supports configurable busy time-out.
ADMA2 64-bit mode is not supported.
There is no external LED control.
注
Only even ratios are supported in DDR mode.
For more information, see chapter eMMC/SD/SDIO of the device TRM.
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6.13.14 GPIO
The general-purpose interface combines eight general-purpose input/output (GPIO) banks.
Each GPIO module provides 32 dedicated general-purpose pins with input and output capabilities; thus,
the general-purpose interface supports up to 186 pins.
These pins can be configured for the following applications:
•
•
•
Data input (capture)/output (drive)
Keyboard interface with a debounce cell
Interrupt generation in active mode upon the detection of external events. Detected events are
processed by two parallel independent interrupt-generation submodules to support biprocessor
operations.
•
Wake-up request generation in idle mode upon the detection of external events
For more information, see section General-Purpose Interface (GPIO) of the device TRM.
6.13.15 ePWM
An effective PWM peripheral must be able to generate complex pulse width waveforms with minimal CPU
overhead or intervention. It needs to be highly programmable and very flexible while being easy to
understand and use. The ePWM unit described here addresses these requirements by allocating all
needed timing and control resources on a per PWM channel basis. Cross coupling or sharing of resources
has been avoided; instead, the ePWM is built up from smaller single channel modules with separate
resources and that can operate together as required to form a system. This modular approach results in
an orthogonal architecture and provides a more transparent view of the peripheral structure, helping users
to understand its operation quickly.
Each ePWM module supports the following features:
•
•
Dedicated 16-bit time-base counter with period and frequency control
Two PWM outputs (EPWMxA and EPWMxB) that can be used in the following configurations:
–
–
–
Two independent PWM outputs with single-edge operation
Two independent PWM outputs with dual-edge symmetric operation
One independent PWM output with dual-edge asymmetric operation
•
•
•
•
•
Asynchronous override control of PWM signals through software.
Programmable phase-control support for lag or lead operation relative to other ePWM modules.
Hardware-locked (synchronized) phase relationship on a cycle-by-cycle basis.
Dead-band generation with independent rising and falling edge delay control.
Programmable trip zone allocation of both cycle-by-cycle trip and one-shot trip on fault
conditions.
•
A trip condition can force either high, low, or high-impedance state logic levels at PWM
outputs.
•
•
Programmable event prescaling minimizes CPU overhead on interrupts.
PWM chopping by high-frequency carrier signal, useful for pulse transformer gate drives.
For more information, see section Enhanced PWM (ePWM) Module in chapter Pulse-Width Modulation
Subsystem of the device TRM.
6.13.16 eCAP
Uses for eCAP include:
•
•
•
•
Sample rate measurements of audio inputs
Speed measurements of rotating machinery (for example, toothed sprockets sensed via Hall sensors)
Elapsed time measurements between position sensor pulses
4 stage sequencer (Mod4 counter) which is synchronized to external events (ECAPx pin edges)
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•
•
Period and duty cycle measurements of pulse train signals
Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors
The eCAP module includes the following features:
•
•
•
•
•
•
•
•
•
•
32-bit time base counter
4-event time-stamp registers (each 32 bits)
Edge polarity selection for up to four sequenced time-stamp capture events
Interrupt on either of the four events
Single shot capture of up to four event time-stamps
Continuous mode capture of time-stamps in a four-deep circular buffer
Absolute time-stamp capture
Difference (Delta) mode time-stamp capture
All above resources dedicated to a single input pin
When not used in capture mode, the ECAP module can be configured as a single channel PWM output
For more information, see section Enhanced Capture (eCAP) Module in chapter Pulse-Width Modulation
Subsystem of the device TRM.
6.13.17 eQEP
A single track of slots patterns the periphery of an incremental encoder disk, as shown in 图 6-2. These
slots create an alternating pattern of dark and light lines. The disk count is defined as the number of
dark/light line pairs that occur per revolution (lines per revolution). As a rule, a second track is added to
generate a signal that occurs once per revolution (index signal: QEPI), which can be used to indicate an
absolute position. Encoder manufacturers identify the index pulse using different terms such as index,
marker, home position, and zero reference.
QEPA
QEPB
QEPI
eqep-001
图 6-2. Optical Encoder Disk
To derive direction information, the lines on the disk are read out by two different photo-elements that
"look" at the disk pattern with a mechanical shift of 1/4 the pitch of a line pair between them. This shift is
realized with a reticle or mask that restricts the view of the photo-element to the desired part of the disk
lines. As the disk rotates, the two photo-elements generate signals that are shifted 90 degrees out of
phase from each other. These are commonly called the quadrature QEPA and QEPB signals. The
clockwise direction for most encoders is defined as the QEPA channel going positive before the QEPB
channel.
The encoder wheel typically makes one revolution for every revolution of the motor or the wheel may be at
a geared rotation ratio with respect to the motor. Therefore, the frequency of the digital signal coming from
the QEPA and QEPB outputs varies proportionally with the velocity of the motor. For example, a 2000-line
encoder directly coupled to a motor running at 5000 revolutions per minute (rpm) results in a frequency of
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can
determine the velocity of the motor.
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For more information, see section Enhanced Quadrature Encoder Pulse (eQEP) Module in chapter Pulse-
Width Modulation Subsystem of the device TRM.
6.14 On-chip Debug
Debugging a system that contains an embedded processor involves an environment that connects high-
level debugging software running on a host computer to a low-level debug interface supported by the
target device. Between these levels, a debug and trace controller (DTC) facilitates communication
between the host debugger and the debug support logic on the target chip.
The DTC is a combination of hardware and software that connects the host debugger to the target system.
The DTC uses one or more hardware interfaces and/or protocols to convert actions dictated by the
debugger user to JTAG® commands and scans that execute the core hardware.
The debug software and hardware components let the user control multiple central processing unit (CPU)
cores embedded in the device in a global or local manner. This environment provides:
•
•
•
Synchronized global starting and stopping of multiple processors
Starting and stopping of an individual processor
Each processor can generate triggers that can be used to alter the execution flow of other processors
System topics include but are not limited to:
•
•
•
System clocking and power-down issues
Interconnection of multiple devices
Trigger channels
For more information, see chapter On-chip Debug of the device TRM.
The device deploys Texas Instrument's CTools debug technology for on-chip debug and trace support. It
provides the following features:
•
External debug interfaces:
–
Primary debug interface - IEEE1149.1 (JTAG) or IEEE1149.7 (complementary superset of JTAG)
•
•
Used for debugger connection
Default mode is IEEE1149.1 but debugger can switch to IEEE1149.7 via an IEEE1149.7
adapter module
•
Controls ICEPick™ (generic test access port [TAP] for dynamic TAP insertion) to allow the
debugger to access several debug resources through its secondary (output) JTAG ports (for
more information, see ICEPick Secondary TAPs section of the Device TRM).
–
Debug (trace) port
•
•
•
Can be used to export processor or system trace off-chip (to an external trace receiver)
Can be used for cross-triggering with an external device
Configured through debug resources manager (DRM) module instantiated in the debug
subsystem
•
For more information about debug (trace) port, see Debug (Trace) Port and Concurrent Debug
Modes sections of the Device TRM.
•
•
JTAG based processor debug on:
–
–
–
–
Cortex-A15 in MPU
C66x in DSP1
Cortex-M4 (x2) in IPU1, IPU2
Arm968 (x2) in IVA
Dynamic TAP insertion
–
–
Controlled by ICEPick
For more information, see , Dynamic TAP Insertion.
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•
Power and clock management
–
–
–
–
Debugger can get the status of the power domain associated to each TAP.
Debugger may prevent the application software switching off the power domain.
Application power management behavior can be preserved during debug across power transitions.
For more information, see Power and Clock Management section of the Device TRM.
•
•
Reset management
–
–
Debugger can configure ICEPick to assert, block, or extend the reset of a given subsystem.
For more information, see Reset Management section of the Device TRM.
Cross-triggering
–
Provides a way to propagate debug (trigger) events from one processor, subsystem, or module to
another:
•
Subsystem A can be programmed to generate a debug event, which can then be exported as a
global trigger across the device.
•
Subsystem B can be programmed to be sensitive to the trigger line input and to generate an
action on trigger detection.
–
–
Two global trigger lines are implemented
Device-level cross-triggering is handled by the XTRIG (TI cross-trigger) module implemented in the
debug subsystem
–
Various Arm® CoreSight™ cross-trigger modules implemented to provide support for CoreSight
triggers distribution
•
•
CoreSight Cross-Trigger Interface (CS_CTI) modules
CoreSight Cross-Trigger Matrix (CS_CTM) modules
–
For more information about cross-triggering, see Cross-Triggering section of the Device TRM.
•
•
Suspend
–
Provides a way to stop a closely coupled hardware process running on a peripheral module when
the host processor enters debug state
–
For more information about suspend, see Suspend section of the Device TRM.
MPU watchpoint
–
–
–
Embedded in MPU subsystem
Provides visibility on MPU to EMIF direct paths
For more information, see MPU Memory Adaptor (MPU_MA) Watchpoint section of the Device
TRM.
•
Processor trace
–
–
–
–
Cortex-A15 (MPU) and C66x (DSP) processor trace is supported
Program trace only for MPU (no data trace)
MPU trace supported by a CoreSight Program Trace Macrocell (CS_PTM) module
Three exclusive trace sinks:
•
•
•
CoreSight Trace Port Interface Unit (CS_TPIU) – trace export to an external trace receiver
CTools Trace Buffer Router (CT_TBR) in system bridge mode – trace export through USB
CT_TBR in buffer mode – trace history store into on-chip trace buffer
–
For more information, see Processor Trace section of the Device TRM.
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•
System instrumentation (trace)
–
Supported by a CTools System Trace Module (CT_STM), implementing MIPI System Trace
Protocol (STP) (rev 2.0)
–
Real-time software trace
•
•
MPU software instrumentation through CoreSight STM (CS_STM) (STP2.0)
System-on-chip (SoC) software instrumentation through CT_STM (STP2.0)
–
–
OCP watchpoint (OCP_WP_NOC)
•
OCP target traffic monitoring: OCP_WP_NOC can be configured to generate a trigger upon
watchpoint match (that is, when target transaction attributes match the user-defined attributes).
•
•
SoC events trace
DMA transfer profiling
Statistics collector (performance probes)
•
Computes traffic statistics within a user-defined window and periodically reports to the user
through the CT_STM interface
•
•
Embedded in the L3_MAIN interconnect
10 instances:
–
–
1 instance dedicated to target (SDRAM) load monitoring
9 instances dedicated to master latency monitoring
–
–
–
IVA instrumentation (hardware accelerator [HWA] profiling)
•
Supported through a software message and system trace event (SMSET) module embedded in
the IVA subsystem
Power-management events profiling (PM instrumentation [PMI])
•
Monitoring major power-management events. The PM state changes are handled as generic
events and encapsulated in STP messages.
Clock-management events profiling (CM instrumentation [CMI])
•
Monitoring major clock management events. The CM state changes are handled as generic
events and encapsulated in STP messages.
•
Two instances, one per CM
–
–
CM1 Instrumentation (CMI1) module mapped in the PD_CORE_AON power domain
CM2 Instrumentation (CMI2) module mapped in the PD_CORE power domain
–
For more information, see System Instrumentation section of the Device TRM.
•
Performance monitoring
–
–
Supported by subsystem counter timer module (SCTM) for IPU
Supported by performance monitoring unit (PMU) for MPU subsystem
For more information, see chapter On-Chip Debug Support of the device TRM.
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7 Applications, Implementation, and Layout
注
Information in the following Applications section is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI's customers are responsible for
determining suitability of components for their purposes. Customers should validate and test
their design implementation to confirm system functionality.
7.1 Introduction
This chapter is intended to communicate, guide and illustrate a PCB design strategy resulting in a PCB
that can support TI’s latest Application Processor. This Processor is a high-performance processor
designed for automotive Infotainment based on enhanced OMAP™ architecture integrated on a 28-nm
CMOS process technology.
These guidelines first focus on designing a robust Power Delivery Network (PDN) which is essential to
achieve the desirable high performance processing available on Device. The general principles and step-
by-step approach for implementing good power integrity (PI) with specific requirements will be described
for the key Device power domains.
TI strongly believes that simulating a PCB’s proposed PDN is required for first pass PCB design success.
Key Device processor high-current power domains need to be evaluated for Power Rail IR Drop,
Decoupling Capacitor Loop-Inductance and Power Rail Target Impedance. Only then can a PCB’s PDN
performance be truly accessed by comparing these model PI parameters vs. TI’s recommended values.
Ultimately for any high-volume product, TI recommends conducting a “Processor PDN Validation” test on
prototype PCBs across processor “split lots” to verify PDN robustness meets desired performance goals
for each customer’s worst-case scenario. Please contact your TI representative to receive guidance on
PDN PI modeling and validation testing.
Likewise, the methodology and requirements needed to route Device high-speed, differential interfaces
(i.e. USB2.0, USB3.0, HDMI, PCI), single-ended interfaces (i.e. DDR3, QSPI) and general purpose
interfaces using LVCMOS drivers that meet timing requirements while minimizing signal integrity (SI)
distortions on the PCB’s signaling traces. Signal trace lengths and flight times are aligned with FR-4
standard specification for PCBs.
Several different PCB layout stack-up examples have been presented to illustrate a typical number of
layers, signal assignments and controlled impedance requirements. Different Device interface signals
demand more or less complexity for routing and controlled impedance stack-ups. Optimizing the PCB’s
PDN stack-up needs with all of these different types of signal interfaces will ultimately determine the final
layer count and layer assignments in each customer’s PCB design.
This guideline must be used as a supplement in complement to TI’s Application Processor, Power
Management IC (PMIC) and Audio Companion components along with other TI component technical
documentation (i.e. Technical Reference Manual, Data Manual, Data Sheets, Silicon Errata, Pin-Out
Spreadsheet, Application Notes, etc.).
注
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or
statutory, including any implied warranty of merchantability of fitness for a specific purpose,
for customer boards. The data described in this appendix are intended as guidelines only.
注
These PCB guidelines are in a draft maturity and consequently, are subject to change
depending on design verification testing conducted during IC development and validation.
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7.1.1 Initial Requirements and Guidelines
Unless otherwise specified, the characteristic impedance for single-ended interfaces is recommended to
be between 35 Ω and 65 Ω to minimize the overshoot or undershoot on far-end loads.
Characteristic impedance for differential interfaces must be routed as differential traces on the same layer.
The trace width and spacing must be chosen to yield the recommended differential impedance. For more
information see 节 7.5.1.
The PDN must be optimized for low trace resistance and low trace inductance for all high-current power
nets from PMIC to the device.
An external interface using a connector must be protected following the IEC61000-4-2 level 4 system
ESD.
7.2 Power Optimizations
This section describes the necessary steps for designing a robust Power Distribution Network (PDN):
•
•
•
•
节 7.2.1, Step 1: PCB Stack-up
节 7.2.2, Step 2: Physical Placement
节 7.2.3, Step 3: Static Analysis
节 7.2.4, Step 4: Frequency Analysis
7.2.1 Step 1: PCB Stack-up
The PCB stack-up (layer assignment) is an important factor in determining the optimal performance of the
power distribution system. An optimized PCB stack-up for higher power integrity performance can be
achieved by following these recommendations:
•
•
•
Power and ground plane pairs must be closely coupled together. The capacitance formed between the
planes can decouple the power supply at high frequencies. Whenever possible, the power and ground
planes must be solid to provide continuous return path for return current.
Use a thin dielectric between the power and ground plane pair. Capacitance is inversely proportional to
the separation of the plane pair. Minimizing the separation distance (the dielectric thickness)
maximizes the capacitance.
Optimize the power and ground plane pair carrying high current supplies to key component power
domains as close as possible to the same surface where these components are placed (see 图 7-1).
This will help to minimize “loop inductance” encountered between supply decoupling capacitors and
component supply inputs and between power and ground plane pairs.
注
1-2oz Cu weight for power / ground plane is preferred to enable better PCB heat spreading,
helping to reduce Processor junction temperatures. In addition, it is preferable to have the
power / ground planes be adjacent to the PCB surface on which the Processor is mounted.
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Capacitor
Trace
DIE
Package
Via
3
1
Power/Ground
Ground/Power
2
Loop inductance
Note: 1. BGA via pair loop inductance
2. Power/Ground net spreading inductance
3. Capacitor trace inductance
SPRS906_PCB_STACKUP_01
图 7-1. Minimize Loop Inductance With Proper Layer Assignment
The placement of power and ground planes in the PCB stackup (determined by layer assignment) has a
significant impact on the parasitic inductances of power current path as shown in 图 7-1. For this reason, it
is recommended to consider layer order in the early stages of the PCB PDN design cycle, putting high-
priority supplies in the top half of the stackup (assuming high load and priority components are mounted
on the top-side of PCB) and low-priority supplies in the bottom half of the stackup as shown in the
examples below (vias have parasitic inductances which impact the bottom layers more, so it is advised to
put the sensitive and high-priority power supplies on the top/same layers).
7.2.2 Step 2: Physical Placement
A critical step in designing an optimized PDN is that proper care must be taken to making sure that the
initial floor planning of the PCB layout is done with good power integrity design guidelines in mind. The
following points are important for optimizing a PCB’s PDN:
•
Minimizing the physical distance between power sources and key high load components is the first
step toward optimization. Placing source and load components on the same side of the PCB is
desirable. This will minimize via inductance impact for high current loads and steps
•
•
External trace routing between components must be as wide as possible. The wider the traces, the
lower the DC resistance and consequently the lower the static IR drop.
Whenever possible for the internal layers (routing and plane), wide traces and copper area fills are
preferred for PDN layout. The routing of power nets in plane provide for more interplane capacitance
and improved high frequency performance of the PDN.
•
Whenever possible, use a via to component pin/pad ratio of 1:1 or better (i.e. especially decoupling
capacitors, power inductors and current sensing resistors). Do not share vias among multiple
capacitors for connecting power supply and ground planes.
•
•
Placement of vias must be as close as possible or even within a component’s solder pad if the PCB
technology you are using provides this capability.
To avoid any “ampacity” issue – maximum current-carrying capacity of each transitional via should be
evaluated to determine the appropriate number of vias required to connect components.
Adding vias to bring the “via-to-pad” ratio to 1:1 will improve PDN performance.
•
For noise sensitive power supplies (i.e. Phase Lock-Loops, analog signals like audio and video), a Gnd
shield can be used to isolate coplanar supplies that may have high step currents or high frequency
switching transitions from coupling into low-noise supplies.
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vdd_mpu
vss
vdd
PCB_PO_8
图 7-2. Coplanar Shielding of Power Net Using Ground Guard-band
7.2.3 Step 3: Static Analysis
Delivering reliable power to circuits is always of critical importance because voltage drops (also known as
IR drops) can happen at every level within an electronic system, on-chip, within a package, and across the
board. Robust system performance can only be ensured by understanding how the system elements will
perform under typical stressful Use Cases. Therefore, it is a good practice to perform a Static or DC
Analysis.
Static or DC analysis and design methodology results in a PDN design that minimizes voltage or IR drops
across power and ground planes, traces and vias. This ensures the application processor’s internal
transistors will be operating within their specified voltage ranges for proper functionality. The amount of IR
drop that will be encounter is based upon amount power drawn for a desired Use Case and PCB trace
(widths, geometry and number of parallel traces) and via (size, type and number) characteristics.
Components that are distant from their power source are particularly susceptible to IR drop. Designs that
rely on battery power must minimize voltage drops to avoid unacceptable power loss that can negatively
impact system performance. Early assessments a PDN’s static (DC) performance helps to determine
basic power distribution parameters such as best system input power point, optimal PCB layer stackup,
and copper area needed for load currents.
The resistance Rs of a plane conductor
for a unit length and unit width is called
the surface resistivity (ohms per square).
r
1
L
Rs =
=
t
σ ×t
l
t
R = Rs ×
W
w
SPRS906_PCB_STATIC_01
图 7-3. Depiction of Sheet Resistivity and Resistance
Ohm’s Law (V = I × R) relates conduction current to voltage drop. At DC, the relation coefficient is a
constant and represents the resistance of the conductor. Even current carrying conductors will dissipate
power at high currents even though their resistance may be very small. Both voltage drop and power
dissipation are proportional to the resistance of the conductor.
图 7-4 shows a PCB-level static IR drop budget defined between the power management device (PMIC)
pins and the application processor’s balls when the PMIC is supplying power.
•
It is highly recommended to physically place the PMIC as close as possible to the processor and on
the same side. The orientation of the PMIC vs. processor should be aligned to minimize distance for
the highest current rail.
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PCB
Static IR drop and Effective Resistance
Source Component
Load Component
BGA pad on PCB
SPRS906_PCB_STATIC_02
图 7-4. Static IR Drop Budget for PCB Only
The system-level IR drop budget is made up of three portions: on-chip, package, and PCB board. Static IR
or DC analysis/design methodology consists of designing the PDN such that the voltage drop (under DC
operating conditions) across power and ground pads of the transistors of the application processor device
is within a specified value of the nominal voltage for proper functionality of the device.
A PCB system-level voltage drop budget for proper device functionality is typically 1.5% of nominal
voltage. For a 1.35-V supply, this would be ≤20 mV.
To accurately analyze PCB static IR drop, the actual geometry of the PDN must be modeled properly and
simulated to accurately characterize long distribution paths, copper weight impacts, electro-migration
violations of current-carrying vias, and “Swiss-cheese” effects via placement has on power rails. It is
recommended to perform the following analyses:
•
•
Lumped resistance/IR drop analysis
Distributed resistance/IR drop analysis
注
The PMIC companion device supporting this processor has been designed with voltage
sensing feedback loop capabilities that enable a remote sense of the SMPS output voltage at
the point of use.
The NOTE above means the SMPS feedback signals and returns must be routed across PCB and
connected to the Device input power ball for which a particular SMPS is supplying power. This feedback
loop provides compensation for some of the voltage drop encountered across the PDN within limits. As
such, the effective resistance of the PDN within this loop should be determined in order to optimize
voltage compensation loop performance. The resistance of two PDN segments are of interest: one from
the power inductor/bulk power filtering capacitor node to the Processor’s input power and second is the
entire PDN route from SMPS output pin/ball to the Processor input power.
In the following sections each methodology is described in detail and an example has been provided of
analysis flow that can be used by the PCB designer to validate compliance to the requirements on their
PCB PDN design.
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7.2.3.1 PDN Resistance and IR Drop
Lumped methodology consists of grouping all of the power pins on both the PMIC (voltage source) and
processor (current sink) devices. Then the PMIC source is set to an expected Use Case voltage level and
the processor load has its Use Case current sink value set as well. Now the lumped/effective resistance
for the power rail trace/plane routes can be determine based upon the actual layout’s power rail etch wide,
shape, length, via count and placement 图 7-5 illustrates the pin-grouping/lumped concept.
The lumped methodology consists of importing the PCB layout database (from Cadence Allegro tool or
any other layout design tool) into the static IR drop modeling and simulation tool of preference for the PCB
designer. This is followed by applying the correct PCB stack-up information (thickness, material
properties) of the PCB dielectric and metallization layers. The material properties of dielectric consist of
permittivity (Dk) and loss tangent (Df).
For the conductor layers, the correct conductivity needs to be programmed into the simulation tool. This is
followed by pin-grouping of the power and ground nets, and applying appropriate voltage/current sources.
The current and voltage information can be obtained from the power and voltage specifications of the
device under different operating conditions / Use Cases.
Sources
Sources
Multiport net
Branch
Grouped Power/Ground
pins to create 1 equivalent
resistive branch
Port/Pin
Sinks
Sinks
SPRS906_PCB_PDN_01
图 7-5. Pin-grouping concept: Lumped and Distributed Methodologies
7.2.4 Step 4: Frequency Analysis
Delivering low noise voltage sources are very important to allowing a system to operate at the lowest
possible Operational Performance Point (OPP) for any one Use Case. An OPP is a combination of the
supply voltage level and clocking rate for key internal processor domains. A SCH and PCB designed to
provide low noise voltage supplies will then enable the processor to enter optimal OPPs for each Use
Case that in turn will minimize power dissipation and junction temperatures on-die. Therefore, it is a good
engineering practice to perform a Frequency Analysis over the key power domains.
Frequency analysis and design methodology results in a PDN design that minimizes transient noise
voltages at the processor’s input power balls. This allows the processor’s internal transistors to operate
near the minimum specified operating supply voltage levels. To accomplish this one must evaluate how a
voltage supply will change due to impedance variations over frequency. This analysis will focus on the
decoupling capacitor network (VDD_xxx and VSS/Gnd rails) at the load. Sufficient capacitance with a
distribution of self-resonant points will provide for an overall lower impedance vs frequency response for
each power domain.
Decoupling components that are distant from their load’s input power are susceptible to encountering
spreading loop inductance from the PCB design. Early analysis of each key power domain’s frequency
response helps to determine basic decoupling capacitor placement, optimal footprint, layer assignment,
and types needed for minimizing supply voltage noise/fluctuations due to switching and load current
transients.
注
Evaluation of loop inductance values for decoupling capacitors placed ~300mils closer to the
load’s input power balls has shown an 18% reduction in loop inductance due to reduced
distance.
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•
Decoupling capacitors must be carefully placed in order to minimize loop inductance impact on supply
voltage transients. A real capacitor has characteristics not only of capacitance but also inductance and
resistance.
图 7-6 shows the parasitic model of a real capacitor. A real capacitor must be treated as an RLC circuit
with effective series resistance (ESR) and effective series inductance (ESL).
C
ESL
ESR
SPRS906_PCB_FREQ_01
图 7-6. Characteristics of a Real Capacitor With ESL and ESR
The magnitude of the impedance of this series model is given as:
1
æ
ö2
2
Z = ESR +
ωESL -
ç
÷
ωC
è
ø
where : w = 2π¦
SPRS906_PCB_FREQ_02
图 7-7. Series Model Impedance Equation
图 7-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of 55
MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance
and inductance as shown in the equation above.
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+01
1.0e+00
1.0e–01
1.0e–02
XC=1/ωC
XL=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
1.00e+006
1.00e+008
Frequency (MHz)
SPRS906_PCB_FREQ_03
图 7-8. Typical Impedance Profile of a Capacitor
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Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in 图 7-1. The capacitor mounting inductance and resistance values
include the inductance and resistance of the pads, trace, and vias. Whenever possible, use footprints that
have the lowest inductance configuration as shown in 图 7-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in 图 7-9. If the PCB manufacturing processes allow it and if cost-
effective, via-in-pad (VIP) geometries are strongly recommended.
In addition to mounting inductance and resistance associated with placing a capacitor on the PCB, the
effectiveness of a decoupling capacitor also depends on the spreading inductance and resistance that the
capacitor sees with respect to the load. The spreading inductance and resistance is strongly dependent on
the layer assignment in the PCB stack-up. Therefore, try to minimize X, Y and Z dimensions where the Z
is due to PCB thickness (as shown in 图 7-9).
From left (highest inductance) to right (lowest inductance) the capacitor footprint types shown in 图 7-9 are
known as:
•
•
•
•
•
2-via, Skinny End Exit (2vSEE)
2-via, Wide End Exit (2vWEE)
2-via, Wide Side Exit (2vWSE)
4-via, Wide Side Exit (4vWSE)
2-via, In-Pad (2vIP)
Via
Via-in-pad
Pad
Trace
Mounting geometry for reduced inductance
SPRS906_PCB_FREQ_04
图 7-9. Capacitor Placement Geometry for Improved Mounting Inductance
注
Evaluation of loop inductance values for decoupling capacitor footprints 2vSEE (worst case)
vs 4vWSE (2nd best) has shown a 30% reduction in inductance when 4vWSE footprint was
used in place of 2vSEE.
Decoupling Capacitor (Dcap) Strategy:
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1. Use lowest inductance footprint and trace connection scheme possible for given PCB technology and
layout area in order to minimize Dcap loop inductance to power pin as much as possible (see 图 7-9).
2. Place Dcaps on “same-side” as component within their power plane outline to minimize “decoupling
loop inductance”. Target distance to power pin should be less than ~500mils depending upon PCB
layout characteristics (plane's layer assignment and solid nature). Use PI modeling CAD tool to verify
minimum inductance for top vs bottom-side placement.
3. Place Dcaps on “opposite-side” as component within their power plane outline if “same-side” is not
feasible or if distance to power pin is greater than ~500mils for top-side location. Use PI modeling CAD
tool to verify minimum inductance for top vs bottom-side placement.
4. Use minimum 10mil trace width for all voltage and gnd planes connections (i.e. Dcap pads, component
power pins, etc.).
5. Place all voltage and gnd plane vias “as close as possible” to point of use (i.e. Dcap pads, component
power pins, etc.).
6. Use a “Power/Gnd pad/pin to via” ratio of 1:1 whenever possible. Do not exceed 2:1 ratio for small
number of vias within restricted PCB areas (i.e. underneath BGA components).
Frequency analysis for the CORE power domain has yielded the vdd Impedance vs Frequency response
shown in 节 7.3.8.2, vdd Example Analysis. As the example shows the overall CORE PDN Reff meets the
maximum recommended PDN resistance of 10mΩ.
7.2.5 System ESD Generic Guidelines
7.2.5.1 System ESD Generic PCB Guideline
Protection devices must be placed close to the ESD source which means close to the connector. This
allows the device to subtract the energy associated with an ESD strike before it reaches the internal
circuitry of the application board.
To help minimize the residual voltage pulse that will be built-up at the protection device due to its nonzero
turn-on impedance, it is mandatory to route the ESD device with minimum stub length so that the low-
resistive, low-inductive path from the signal to the ground is granted and not increasing the impedance
between signal and ground.
For ESD protection array being railed to a power supply when no decoupling capacitor is available in close
vicinity, consider using a decoupling capacitor (≥ 0.1 µF) tight to the VCC pin of the ESD protection. A
positive strike will be partially diverted to this capacitance resulting in a lower residual voltage pulse.
Ensure that there is sufficient metallization for the supply of signals at the interconnect side (VCC and
GND in 图 7-10) from connector to external protection because the interconnect may see between 15-A to
30-A current in a short period of time during the ESD event.
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Bypass
capacitor
0.1 mf
(minimum)
Stub
inductance
Stub
inductance
Interconnection
inductance
vcc
Signal
VCC
VCC
Protected
circuit
Signal
ESD
strike
Stub
inductance
Minimize such
inductance by
optimizing layout
External
protection
Ground
inductance
Keep distance
between protected
circuit and external
protection
Keep external
protection closed by
connector
SPRS906_PCB_ESD_01
图 7-10. Placement Recommendation for an ESD External Protection
注
To ensure normal behavior of the ESD protection (unwanted leakage), it is better to ground
the ESD protection to the board ground rather than any local ground (example isolated shield
or audio ground).
7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
•
Avoid running critical signal traces (clocks, resets, interrupts, control signals, and so forth) near PCB
edges.
•
Add high frequency filtering: Decoupling capacitors close to the receivers rather than close to the
drivers to minimize ESD coupling.
•
•
Put a ground (guard) ring around the entire periphery of the PCB to act as a lightning rod.
Connect the guard ring to the PCB ground plane to provide a low impedance path for ESD-coupled
current on the ring.
•
•
Fill unused portions of the PCB with ground plane.
Minimize circuit loops between power and ground by using multilayer PCB with dedicated power and
ground planes.
•
•
Shield long line length (strip lines) to minimize radiated ESD.
Avoid running traces over split ground planes. It is better to use a bridge connecting the two planes in
one area.
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BAD
BETTER
SPRS906_PCB_EMC_01
图 7-11. Trace Examples
•
Always route signal traces and their associated ground returns as close to one another as possible to
minimize the loop area enclosed by current flow:
–
–
At high frequencies current follows the path of least inductance.
At low frequencies current flows through the path of least resistance.
7.2.5.3 ESD Protection System Design Consideration
ESD protection system design consideration is covered in 节 7.5.2.2 of this document. The following are
additional considerations for ESD protection in a system.
•
•
•
•
•
•
Metallic shielding for both ESD and EMI
Chassis GND isolation from the board GND
Air gap designed on board to absorb ESD energy
Clamping diodes to absorb ESD energy
Capacitors to divert ESD energy
The use of external ESD components on the DP/DM lines may affect signal quality and are not
recommended.
7.2.6 EMI / EMC Issues Prevention
All high-speed digital integrated circuits can be sources of unwanted radiation, which can affect nearby
sensitive circuitry and cause the final product to have radiated emissions levels above the limits allowed
by the EMC regulations if some preventative steps are not taken.
Likewise, analog and digital circuits can be susceptible to interference from the outside world and picked
up by the circuitry interconnections.
To minimize the potential for EMI/EMC issues, the following guidelines are recommended to be followed.
7.2.6.1 Signal Bandwidth
To evaluate the frequency of a digital signal, an estimated rule of thumb is to consider its bandwidth fBW
with respect to its rise time, tR:
fBW ≈ 0.35 / tR
This frequency actually corresponds to the break point in the signal spectrum, where the harmonics start
to decay at 40 dB per decade instead of 20 dB per decade.
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7.2.6.2 Signal Routing
7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
Keep radio frequency (RF) sensitive circuitry (like GPS receivers, GSM/WCDMA, Bluetooth/WLAN
transceivers, frequency modulation (FM) radio) away from high-speed ICs (the device, power and audio
manager, chargers, memories, and so forth) and ideally on the opposite side of the PCB. For improved
protection it is recommended to place these emission sources in a shield can. If the shield can have a
removable lid (two-piece shield), ensure there is low contact impedance between the fence and the lid.
Leave some space between the lid and the components under it to limit the high-frequency currents
induced in the lid. Limit the shield size to put any potential shield resonances above the frequencies of
interest; see 图 7-8, Typical Impedance Profile of a Capacitor.
7.2.6.2.2 Signal Routing—Outer Layer Routing
In case there is a need to use the outer layers for routing outside of shielded areas, it is recommended to
route only static signals and ensure that these static signals do not carry any high-frequency components
(due to parasitic coupling with other signals). In case of long traces, make provision for a bypass capacitor
near the signal source.
Routing of high-frequency clock signals on outer layers, even for a short distance, is discouraged,
because their emissions energy is concentrated at the discrete harmonics and can become significant
even with poor radiators.
Coplanar shielding of traces on outer layers (placing ground near the sides of a track along its length) is
effective only if the distance between the trace sides and the ground is smaller that the trace height above
the ground reference plane. For modern multilayer PCBs this is often not possible, so coplanar shielding
will not be effective. Do not route high-frequency traces near the periphery of the PCB, as the lack of a
ground reference near the trace edges can increase EMI: see 节 7.2.6.3, Ground Guidelines.
7.2.6.3 Ground Guidelines
7.2.6.3.1 PCB Outer Layers
Ideally the areas on the top and bottom layers of the PCB that are not enclosed by a shield should be
filled with ground after the routing is completed and connected with an adequate number of vias to the
ground on the inner ground planes.
7.2.6.3.2 Metallic Frames
Ensure that all metallic parts are well connected to the PCB ground (like LCD screens metallic frames,
antennas reference planes, connector cages, flex cables grounds, and so forth). If using flex PCB ribbon
cables to bring high-frequency signals off the PCB, ensure they are adequately shielded (coaxial cables or
flex ribbons with a solid reference ground).
7.2.6.3.3 Connectors
For high-frequency signals going to connectors choose a fully shielded connector, if possible (for example,
SD card connectors). For signals going to external connectors or which are routed over long distances, it
is recommended to reduce their bandwidth by using low-pass filters (resistor, capacitor (RC) combinations
or lossy ferrite inductors). These filters will help to prevent emissions from the board and can also improve
the immunity from external disturbances.
7.2.6.3.4 Guard Ring on PCB Edges
The major advantage of a multilayer PCB with ground-plane is the ground return path below each and
every signal or power trace.
As shown in 图 7-12 the field lines of the signal return to PCB ground as long as an infinite ground is
available.
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Traces near the PCB-edges do not have this infinite ground and therefore may radiate more than the
others. Thus, signals (clocks) or power traces (core power) identified to be critical must not be routed in
the vicinity of PCB edges, or, if not avoidable, must be accompanied by a guard ring on the PCB edge.
SPRS906_PCB_EMC_02
图 7-12. Field Lines of a Signal Above Ground
Signal
Power
Ground
Signal
SPRS906_PCB_EMC_03
图 7-13. Guard Ring Routing
The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB
edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on
the borders of all layers (including power layer) must be applied as shown in 图 7-13.
As these traces must have the same (HF–) potential as the ground plane they must be connected to the
ground plane at least every 10 mm.
7.2.6.3.5 Analog and Digital Ground
For the optimum solution, the AGND and the DGND planes must be connected together at the power
supply source in a same point. This ensures that both planes are at the same potential, while the transfer
of noise from the digital to the analog domain is minimized.
7.3 Core Power Domains
This section provides boundary conditions and theoretical background to be applied as a guide for
optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give
recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board
designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the
expected PDN performance needed to optimize SoC performance.
7.3.1 General Constraints and Theory
•
•
Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using TI recommended
PMICs without remote sensing as measured from PMIC’s power inductor and filter capacitor node to
Processor input including any ground return losses.
Max PCB static/DC voltage drop (IRd) budget can be relaxed to 7.5% of supply voltage when using
PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor
node to Device’s supply input including any ground return losses.
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•
PMIC component DM and guidelines should be referenced for the following:
–
–
Routing remote feedback sensing to optimize per each SMPS’s implementation
Selecting power filtering capacitor values and PCB placement.
•
•
•
•
Max Effective Resistance (Reff) budget can range from 4 – 100mΩ for key Device power rails not
including ground returns depending upon maximum load currents and maximum DC voltage drop
budget (as discussed above).
Max Device supply input voltage difference budget of 5mV under max current loading shall be
maintained across all balls connected to a common power rail. This represents any voltage difference
that may exist between a remote sense point to any power input.
Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high
frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending
upon maximum transient load currents.
Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device
including ground returns are as follows:
–
+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~
200kHz)
–
+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)
•
Max PCB Impedance (Z) vs Frequency (F) budget between Device’s power inputs and PMIC’s output
power filter node including ground return is determined by applying the Frequency Domain Target
Impedance Method to determine the PCB’s maximum frequency of interest (Fpcb). Ideally a properly
designed and decoupled PDN will exhibit smoothly increasing Z vs. F curve. There are 2 general
regions of interest as can be seen in 图 7-14.
–
1st area is from DC (0Hz) up to Fpmic (typ a few 100 kHz) where a PMIC’s transient response
characteristic (i.e. Switching Freq, Compensation Loop BW) dominate. A PDN’s Z is typically very
low due to power filtering & bulk capacitor values when PDN has very low trace resistance (i.e.
good Reff performance). The goal is to maintain a smoothly increasing Z that is less than Zt1 over
this low frequency range. This will ensure that a max transient current event will not cause a
voltage drop more than the PMIC’s current step response can support (typ 3%).
–
2nd area is from Fpmic up to Fpcb (typ 20-100MHz) where a PCB’s inherent characteristics (i.e.
parasitic capacitance, planar spreading inductances) dominate. A PDN’s Z will naturally increase
with frequency. At frequencies between Fpmic up to Fpcb, the goal is to maintain a smoothly
increasing Z to be less than Zt2. This will ensue that the high frequency content of a max transient
current event will not cause a voltage drop to be more than 5% of the min supply voltage.
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图 7-14. PDN’s Target impedance
1.Voltage Rail Drop includes regulation accuracy, voltage distribution drops, and all dynamic events
such as transient noise, AC ripple, voltage dips etc.
2.Typical max transient current is defined as 50% of max current draw possible.
7.3.2 Voltage Decoupling
Recommended power supply decoupling capacitors main characteristics for commercial products whose
ambient temperature is not to exceed +85C are shown in table below:
表 7-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3)
Value
Voltage [V]
Package
Stability
Dielectric Capacitanc Temp Range
Temp
Sensitivity
[%]
REFERENCE
e
[°C]
Tolerance
22µF
10µF
4.7µF
2.2µF
1µF
6,3
4,0
6,3
6,3
6,3
0603
0402
0402
0402
0201
Class 2
Class 2
Class 2
Class 2
Class 2
X5R
X5R
X5R
X5R
X5R
- / + 20%
- / + 20%
- / + 20%
- / + 20%
- / + 20%
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
-55 to + 85
- / + 15
- / + 15
- / + 15
- / + 15
- / + 15
GRM188R60J226MEA0L
GRM155R60G106ME44
GRM155R60J475ME95
GRM155R60J225ME95
GRM033R60J105MEA2
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表 7-1. Commercial Applications Recommended Decoupling Capacitors Characteristics(1)(2)(3) (continued)
Value
Voltage [V]
Package
Stability
Dielectric Capacitanc Temp Range
Temp
Sensitivity
[%]
REFERENCE
e
[°C]
Tolerance
470nF
220nF
100nF
6,3
6,3
6,3
0201
0201
0201
Class 2
Class 2
Class 2
X5R
X5R
X5R
- / + 20%
- / + 20%
- / + 20%
-55 to + 85
-55 to + 85
-55 to + 85
- / + 15
- / + 15
- / + 15
GRM033R60G474ME90
GRM033R60J224ME90
GRM033R60J104ME19
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) In comparison with the EIA Class 1 dielectrics, Class 2 dielectric capacitors tend to have severe temperature drift, high dependence of
capacitance on applied voltage, high voltage coefficient of dissipation factor, high frequency coefficient of dissipation, and problems with
aging due to gradual change of crystal structure. Aging causes gradual exponential loss of capacitance and decrease of dissipation
factor.
Recommended power supply decoupling capacitors main characteristics for automotive products are
shown in table below:
表 7-2. Automotive Applications Recommended Decoupling Capacitors Characteristics (1)(2)
Value
Voltage [V]
Package
AEC-Q200
Dielectric Capacitanc
Temp
Temp
REFERENCE
e
Range [°C] Sensitivity
[%]
Tolerance
22µF
10µF
10
10
10
6,3
10
10
25
10
6.3
10
10
10
10
1206
0805
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
X7R
X7R
X7S
X7R
X7S
X7S
X7R
X7R
X7S
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 15
GCM31CR71A226KE02
GCM21BR71A106KE22
GCM21BC71A475KA73
GCM188R70J225KE22
GCM155C71A105KE38
GCM155C71A474KE36
GCM155R71A104KA55
GCM155R71C104MA55
GCM033C70J104K
- / + 15
- / + 22
- / + 15
- / + 22
- / + 22
- / + 15
- / + 15
- / + 15
4.7µF
2.2µF
1µF
0805
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 10% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
- / + 20% -55 to + 125
0603
0402
470nF
220nF
100nF
100nF
1.0μF
0.47μF
0.22μF
0.1μF
0402
0603
0402
0201
3T-0805(3)
3T-0805(3)
3T-0805(3)
3T-0805(3)
NFM21HC105R1C3
NFM21HC474R1C3
NFM21HC224R1C3
NFM21HC104R1C3
(1) Minimum value for each PCB capacitor: 100 nF.
(2) Among the different capacitors, 470 nF is recommended (not required) to filter at 5-MHz to 10-MHz frequency range.
(3) 3T designates this as a "3-terminal, low inductance type package”.
7.3.3 Static PDN Analysis
One power net parameter derived from a PCB’s PDN static analysis is the Effective Resistance (Reff).
This is the total PCB power net routing resistance that is the sum of all the individual power net segments
used to deliver a supply voltage to the point of load and includes any series resistive elements (i.e. current
sensing resistor) that may be installed between the PMIC outputs and Processor inputs.
7.3.4 Dynamic PDN Analysis
Three power net parameters derived from a PCB’s PDN dynamic analysis are the Loop Inductance (LL),
Impedance (Z) and PCB Frequency of Interest (Fpcb).
•
LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
•
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
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•
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
表 7-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)
PDN Analysis:
Supply
Static
Dynamic
Number of Recommended Decoupling Capacitors
per Supply
Frequency
range
of Interest
[MHz]
Max Reff
Dec. Cap.
Max LL(6)
[nH]
Max
Impedance
[mΩ]
100
nF
220
nF
470
nF
2.2
μF
4.7
μF
10
μF
22
μF
(5)
1μF
[mΩ]
vdd_dsp
22
2.5
2
54
≤20
≤20
≤100
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
6
8
1
1
3
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
vdd
18
57
1
vdds_ddr1
33
2.5
6
200
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
cap_vbbldo_dsp
cap_vbbldo_gpu
cap_vbbldo_iva
cap_vbbldo_mpu
cap_vddram_core1
cap_vddram_core3
cap_vddram_core4
cap_vddram_dsp
cap_vddram_gpu
cap_vddram_iva
cap_vddram_mpu
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
6
6
6
6
6
6
6
6
6
6
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) Maximum static voltage drop allowed drives the maximum acceptable power net resistance ( Reff) between the PMIC or the external
SMPS and the processor power balls.
(5) Maximum Reff (from SMPS to Processor) allows for max supply voltage drop when both remote voltage sensing very close to processor
power balls and TI recommended PMICs are used.
(6) Maximum Loop Inductance to each high-frequency (30-70MHz) decoupling capacitor.
7.3.5 Power Supply Mapping
TPS65919 or LP8733 are the Power Management ICs (PMICs) that should be used for the Device
designs. TI requires use of these PMICs for the following reasons:
•
•
TI has validated their use with the Device
Board level margins including transient response and output accuracy are analyzed and optimized for
the entire system
•
•
•
Support for power sequencing requirements (refer to Section 5.10.3 Power Supply Sequences)
Support for Adaptive Voltage Scaling (AVS) Class 0 requirements, including TI provided software
Remote sensing at point of load with output voltage compensation allows for the maximum IR drop
budget
Whenever one SMPS supplies multiple SoC voltage domains from a common power rail, the most
stringent PDN guideline across the voltage domains being combined should be applied to the common
power rail.
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It is possible that some voltage domains on the device are unused in some systems. In such cases, to
ensure device reliability, it is still required that the supply pins for the specific voltage domains are
connected to some core power supply output.
These unused supplies though can be combined with any of the core supplies that are used (active) in the
system. e.g. if the DSP domain is not used, it can be combined with the CORE domain, thereby having a
single power supply driving the combined CORE and DSP domains.
For the combined rail, the following relaxations do apply:
•
The AVS voltage of active voltage domain in the combined rail needs to be used to set the power
supply
•
•
The decoupling capacitance should be set according to the active voltage domain in the combined rail
The PDN guideline should be set according to the active voltage domain in the combined rail
表 7-4 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the TPS656919 PMIC.
表 7-4. TPS65919 Power Supply Connections(1)
SMPS
Valid Combination
TPS65919 Current
Limitation(2) (3)
SMPS1
SMPS2
SMPS3
SMPS4
VD_CORE
Free (DDR Memory)
VD_DSP
3.5A
3.5A
3A
VDDS18V
1.5A
(1) Power consumption is highly application-specific. Separate analysis must be performed to ensure output current ratings (average and
peak) is within the limits of the PMIC for all rails of the device.
(2) Refer to the PMIC data manual for the latest TPS65919 specifications.
(3) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power
dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.
表 7-5 illustrates the approved and validated power supply connections to the Device for the SMPS
outputs of the LP8733 PMIC.
表 7-5. LP8733 Power Supply Connections
SMPS
Valid Combination
LP8733 Current Limitation(1)
(2)
SMPS1
SMPS2
VD_CORE
VD_DSP
3A
3A
(1) Refer to the LP8733 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in
this table are for comparison purposes.
(2) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.
7.3.6 DPLL Voltage Requirement
The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage
inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The
TPS65919 PMIC LDOLN output is specifically designed to meet this low noise requirement.
注
For more information about Input Voltage Sources, see Section 5.10.4.3 DPLLs, DLLs
Specifications.
表 7-6 presents the voltage inputs that supply the DPLLs.
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表 7-6. Input Voltage Power Supplies for the DPLLs
POWER SUPPLY
vdda_per
DPLLs
DPLL_PER and PER HSDIVIDER analog power supply
DPLL_DDR and DDR HSDIVIDER analog power supply
DPLL_DEBUG analog power supply
vdda_ddr
vdda_debug
vdda_core_gmac
vdda_gpu
DPLL_CORE and HSDIVIDER analog power supply
DPLL_GPU analog power supply
vdda_video
DPLL_VIDEO1 analog power supply
vdda_mpu_abe
vdda_osc
DPLL_MPU and DPLL_ABE analog power supply
not DPLL input but is required to be supplied by low noise input voltage
DSP PLL and IVA PLL analog power supply
vdda_dsp_iva
7.3.7 Loss of Input Power Event
A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for
a “Loss of Input Power” event are:
•
“Loss of Input Power” early warning
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using the 1st Stage
Converter’s (i.e. LM536033-Q1) Power Good status output to enable and disable the 2nd Stage
PMIC devices (i.e. TPS65917/919, LP8733, and LP8732). If a different 1st Stage Converter is used,
care must be taken to ensure an adequate “PG_Status” or “Vbatt_Status” signal is provided that
can disable 2nd Stage PMIC to begin a controlled and compliant SoC power down sequence. The
total elapsed time from asserting “PG_Status” low until SoC’s PMIC input voltage reaches minimum
level of 2.75 V should be minimum of 1.5ms and 2ms preferred.
•
Maximize discharge time of 1st Stage Vout (VSYS_3V3 power rail = input voltage to SoC PMIC).
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by opening an in-line load
switch immediately upon “PG_Status” low assertion in order to remove the SoC’s 3.3V IO load
current from VSYS_3V3. This will extend the VSYS_3V3 power rail’s discharge time in order to
maximize elapsed time for allowing SoC PMIC to execute a controlled and compliant power down
sequence. Care should be taken to either disable or isolate any additional peripheral components
that may be loading the VSYS_3V3 rail as well.
•
•
Sufficient bulk decoupling capacitance on the 1st Stage Vout (VSYS_3V3 per PDN) that allows for
desired 1.5 – 2 ms elapsed time as described above.
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using 200 µF of total
capacitance on VSYS_3V3. The 1st Stage Converter (i.e. LM536033-Q1) can typically drive a max
of 400 µF to help extend VSYS_3V3 discharge time for a compliant SoC power down sequence.
Optimizing the 2nd Stage SoC PMIC’s OTP settings that determines SoC power up and down
sequences and total elapsed time needed for a controlled sequence.
–
TI EVM and Reference Design Study SCHs and PDNs achieve this by using optimized OTPs per
the SCH and components used. The definition of these OTPs is captured in the detailed timing
diagrams for both power up and down sequences. The PDN diagram typically shows a
recommended PMIC OTP ID based upon the SoC and DDR memory types.
7.3.8 Example PCB Design
The following sections describe an example PCB design and its resulting PDN performance for the vdd
processor power domain.
注
Materials presented in this section are based on generic PDN analysis on PCB boards and
are not specific to systems integrating the Device.
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7.3.8.1 Example Stack-up
Layer Assignments:
•
Layer Top: Signal and Segmented Power Plane
Processor and PMIC components placed on Top-side
–
•
•
•
•
•
•
•
Layer 2: Gnd Plane1
Layer 3: Signals
Layer n: Power Plane1
Layer n+1: Power Plane 2
Layer n+2: Signal
Layer n+3: Gnd Plane2
Layer Bottom: Signal and Segmented Power Planes
–
Decoupling caps, etc.
Via Technology: Through-hole
Copper Weight:
•
•
½ oz for all signal layers.
1-2oz for all power plane for improved PCB heat spreading.
7.3.8.2 vdd Example Analysis
Maximum acceptable PCB resistance (Reff) between the PMIC and Processor input power balls should not
exceed 10mΩ.
Maximum decoupling capacitance loop inductance (LL) between Processor input power balls and
decoupling capacitances should not exceed 2.0nH (ESL NOT included)
Impedance target for key frequency of interest between Processor input power balls and PMIC’s SMPS
output power balls should not exceed 57mΩ at 20MHz.
表 7-7. Example PCB vdd PI Analysis Summary
Parameter
OPP
Recommendation
OPP_NOM
266 MHz
1 V
Example PCB
Clocking Rate
Voltage Level
Max Current Draw
1 V
1 A
1 A
Max Effective Resistance: Power
Inductor Segment Total Reff
10mΩ
9.7 mΩ
Max Loop Inductance
Impedance Target
2.0nH
0.97 –1.75nH
57mΩ F<20Mhz
57mΩ F<20Mhz
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图 7-15 show a PCB layout example and the resulting PI analysis results.
L1002
1.0uH, 4.5A, 1616
PMIC
CORE_VDD
IHLP-1616ABER1R0M11
SMPS2
SoC
SMPS2_SW
C1014
VDD
47uF, 6.3V, X7R, 1210
GCM32ER70J476ME19
C363, 364, 386, 388,
390, 498
0.1uF, 16V, X7R, 0402
GCM155R71C104KA55
C395
0.22uF, 25V, X7R, 0603
GCM188R71E224KA55
C394
0.47uF, 16V, X7R, 0603
GCM188R71C474KA55
C393
1.0uF, 16V, X7R, 0603
GCM188R71C105KA64
C456
2.2uF, 6.3V, X7R, 0603
GCM188R70J225KE22
C487
4.7uF, 16V, X7R, 0805
GCM21BR71C475KA73
图 7-15. vdd Simplified SCH Diagram
注
PCB Etch Resistance Breakdown, PDN Effective Resistance, and vdd routings are UNDER
DEVELOPMENT!
IR Drop: vdd (PCB Rev Oct25, CAD sPSI v13.1.1)
•
•
Source Conditions: 1V @ 1A
Power Plane/Trace Effective Resistances
–
–
–
From PMIC SMPS to SoC load = 9.7mohm
From Power Inductor to SoC load = 6mohm
"Open-Loop" Voltage/IR Drop for 1A = 6mV
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图 7-16. vdd Voltage/IR Drop [All Layers]
Dynamic analysis of this PCB design for the CORE power domain determined the vdd decoupling
capacitor loop inductance and impedance vs frequency analysis shown below. As you can see, the loop
inductance values ranged from 0.97 –1.75nH and were less than maximum 2.0nH recommended.
注
Comparing loop inductances for capacitors at different distances from the SoC’s input power
balls shows an 18% reduction for caps placed closer. This was derived by averaging the
inductances for the 3 caps with distances over 800mils (Avg LL = 1.33nH) vs the 3 caps with
distances less than 600mils (Avg LL = 1.096nH).
表 7-8. Rail - vdd
Cap Ref Model Port
Loop Inductacne
[nH]
Footprint
Types
PCB Side
Distance to
Ball-Field
[mils]
Value [μF]
Size
Des
#
C487
C393
C394
C456
C386
C395
C363
C390
C364
C498
C388
10
6
0.97
1.11
1.12
1.13
1.16
1.18
1.46
1.48
1.74
1.74
1.75
4vWSE
4vWSE
4vWSE
4vWSE
2vWSE
4vWSE
2vWSE
2vWSE
2vWSE
2vWSE
2vWSE
Top
521
358
357
403
40
4.7
1.0
0.47
2.2
0.1
0.22
0.1
0.1
0.1
0.1
0.1
0805
0603
0603
0603
0402
0603
0402
0402
0402
0402
0402
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
Bottom
7
9
3
8
460
40
1
5
40
2
40
11
4
40
40
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Loop Inductance range: 0.97 –1.75nH
图 7-17. vdd Decoupling Cap Loop Inductances
图 7-18 shows vdd Impedance vs Frequency characteristics.
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173mohm @ 100MHz
87mohm @ 50MHz
27mohm @ 20MHz
9.9mohm @ 10MHz
图 7-18. vdd Impedance vs Frequency
7.4 Single-Ended Interfaces
7.4.1 General Routing Guidelines
The following paragraphs detail the routing guidelines that must be observed when routing the various
functional LVCMOS interfaces.
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•
Line spacing:
–
For a line width equal to W, the spacing between two lines must be 2W, at least. This minimizes the
crosstalk between switching signals between the different lines. On the PCB, this is not achievable
everywhere (for example, when breaking signals out from the device package), but it is
recommended to follow this rule as much as possible. When violating this guideline, minimize the
length of the traces running parallel to each other (see 图 7-19).
W
D+
S = 2 W = 200 µm
SPRS906_PCB_SE_GND_01
图 7-19. Ground Guard Illustration
•
Length matching (unless otherwise specified):
–
For bus or traces at frequencies less than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 25 mm.
–
For bus or traces at frequencies greater than 10 MHz, the trace length matching (maximum length
difference between the longest and the shortest lines) must be less than 2.5 mm.
•
•
Characteristic impedance
–
Unless otherwise specified, the characteristic impedance for single-ended interfaces is
recommended to be between 35-Ω and 65-Ω.
Multiple peripheral support
–
For interfaces where multiple peripherals have to be supported in the star topology, the length of
each branch has to be balanced. Before closing the PCB design, it is highly recommended to verify
signal integrity based on simulations including actual PCB extraction.
7.4.2 QSPI Board Design and Layout Guidelines
The following section details the routing guidelines that must be observed when routing the QSPI
interfaces.
•
•
The qspi1_sclk output signal must be looped back into the qspi1_rtclk input.
The signal propagation delay from the qspi1_sclk ball to the QSPI device CLK input pin (A to C) must
be approximately equal to the signal propagation delay from the QSPI device CLK pin to the
qspi1_rtclk ball (C to D).
•
The signal propagation delay from the QSPI device CLK pin to the qspi1_rtclk ball (C to D) must be
approximately equal to the signal propagation delay of the control and data signals between the QSPI
device and the SoC device (E to F, or F to E).
•
•
The signal propagation delay from the qspi1_sclk signal to the series terminators (R2 = 10 Ω) near the
QSPI device must be < 450pS (~7cm as stripline or ~8cm as microstrip)
50 Ω PCB routing is recommended along with series terminations, as shown in 图 7-20.
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•
Propagation delays and matching:
–
–
–
–
A to C = C to D = E to F.
Matching skew: < 60pS
A to B < 450pS
B to C = as small as possible (<60pS)
Locate both R2 resistors
close together near the QSPI device
A
B
C
R1
R2
0 Ω*
10 Ω
R2
10 Ω
qspi1_sclk
QSPI device
clock input
D
qspi1_rtclk
E
F
QSPI device
IOx, CS#
qspi1_d[x], qspi1_cs[y]
SPRS906_PCB_QSPI_01
图 7-20. QSPI Interface High Level Schematic
注
*0 Ω resistor (R1), located as close as possible to the qspi1_sclk pin, is placeholder for fine-
tuning if needed.
7.5 Differential Interfaces
7.5.1 General Routing Guidelines
To maximize signal integrity, proper routing techniques for differential signals are important for high-speed
designs. The following general routing guidelines describe the routing guidelines for differential lanes and
differential signals.
•
As much as possible, no other high-frequency signals must be routed in close proximity to the
differential pair.
•
Must be routed as differential traces on the same layer. The trace width and spacing must be chosen
to yield the differential impedance value recommended.
•
•
•
•
Minimize external components on differential lanes (like external ESD, probe points).
Through-hole pins are not recommended.
Differential lanes mustn’t cross image planes (ground planes).
No sharp bend on differential lanes.
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•
•
Number of vias on the differential pairs must be minimized, and identical on each line of the differential
pair. In case of multiple differential lanes in the same interface, all lines should have the same number
of vias.
Shielded routing is to be promoted as much as possible (for instance, signals must be routed on
internal layers that are inside power and/or ground planes).
7.5.2 USB 2.0 Board Design and Layout Guidelines
This section discusses schematic guidelines when designing a universal serial bus (USB) system.
7.5.2.1 Background
Clock frequencies generate the main source of energy in a USB design. The USB differential DP/DM pairs
operate in high-speed mode at 480 Mbps. System clocks can operate at 12 MHz, 48 MHz, and 60 MHz.
The USB cable can behave as a monopole antenna; take care to prevent RF currents from coupling onto
the cable.
When designing a USB board, the signals of most interest are:
•
•
Device interface signals: Clocks and other signal/data lines that run between devices on the PCB.
Power going into and out of the cable: The USB connector socket pin 1 (VBUS ) may be heavily
filtered and need only pass low frequency signals of less than ~100 KHz. The USB socket pin 4
(analog ground) must be able to return the current during data transmission, and must be filtered
sparingly.
•
•
Differential twisted pair signals going out on cable, DP and DM: Depending upon the data transfer rate,
these device terminals can have signals with fundamental frequencies of 240 MHz (high speed), 6
MHz (full speed), and 750 kHz (low speed).
External crystal circuit (device terminals XI and X0): 12 MHz, 19.2 MHz, 24 MHz, and 48 MHz
fundamental. When using an external crystal as a reference clock, a 24 MHz and higher crystal is
highly recommended.
7.5.2.2 USB PHY Layout Guide
The following sections describe in detail the specific guidelines for USB PHY Layout.
7.5.2.2.1 General Routing and Placement
Use the following routing and placement guidelines when laying out a new design for the USB physical
layer (PHY). These guidelines help minimize signal quality and electromagnetic interference (EMI)
problems on a four-or-more layer evaluation module (EVM).
•
Place the USB PHY and major components on the un-routed board first. For more details, see 节
7.5.2.2.2.3.
•
•
•
Route the high-speed clock and high-speed USB differential signals with minimum trace lengths.
Route the high-speed USB signals on the plane closest to the ground plane, whenever possible.
Route the high-speed USB signals using a minimum of vias and corners. This reduces signal
reflections and impedance changes.
•
•
•
•
When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal traces by minimizing impedance discontinuities.
Do not route USB traces under or near crystals, oscillators, clock signal generators, switching
regulators, mounting holes, magnetic devices or IC’s that use or duplicate clock signals.
Avoid stubs on the high-speed USB signals because they cause signal reflections. If a stub is
unavoidable, then the stub should be less than 200 mils.
Route all high-speed USB signal traces over continuous planes (VCC or GND), with no interruptions.
Avoid crossing over anti-etch, commonly found with plane splits.
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7.5.2.2.2 Specific Guidelines for USB PHY Layout
The following sections describe in detail the specific guidelines for USB PHY Layout.
7.5.2.2.2.1 Analog, PLL, and Digital Power Supply Filtering
To minimize EMI emissions, add decoupling capacitors with a ferrite bead at power supply terminals for
the analog, phase-locked loop (PLL), and digital portions of the chip. Place this array as close to the chip
as possible to minimize the inductance of the line and noise contributions to the system. An analog and
digital supply example is shown in 图 7-21. In case of multiple power supply pins with the same function,
tie them up to a single low-impedance point in the board and then add the decoupling capacitors, in
addition to the ferrite bead. This array of caps and ferrite bead improve EMI and jitter performance. Take
both EMI and jitter into account before altering the configuration.
Analog
Power Supply
Ferrite Bead
0.1 µF
0.01 µF
0.001 µF
1 µF
SoC Board
AGND
Digital
Power Supply
Ferrite Bead
0.1 µF
0.01 µF
0.001 µF
1 µF
DGND
SPRS906_PCB_USB20_01
图 7-21. Suggested Array Capacitors and a Ferrite Bead to Minimize EMI
Consider the recommendations listed below to achieve proper ESD/EMI performance:
•
•
•
Use a 0.01 μF cap on each cable power VBUS line to chassis GND close to the USB connector pin.
Use a 0.01 μF cap on each cable ground line to chassis GND next to the USB connector pin.
If voltage regulators are used, place a 0.01 μF cap on both input and output. This is to increase the
immunity to ESD and reduce EMI. For other requirements, see the device-specific datasheet.
7.5.2.2.2.2 Analog, Digital, and PLL Partitioning
If separate power planes are used, they must be tied together at one point through a low-impedance
bridge or preferably through a ferrite bead. Care must be taken to capacitively decouple each power rail
close to the device. The analog ground, digital ground, and PLL ground must be tied together to the low-
impedance circuit board ground plane.
7.5.2.2.2.3 Board Stackup
Because of the high frequencies associated with the USB, a printed circuit board with at least four layers
is recommended; two signal layers separated by a ground and power layer as shown in 图 7-22.
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Signal 1
GND Plane
Power Plane
Signal 2
SPRS906_PCB_USB20_02
图 7-22. Four-Layer Board Stack-Up
The majority of signal traces should run on a single layer, preferably SIGNAL1. Immediately next to this
layer should be the GND plane, which is solid with no cuts. Avoid running signal traces across a split in
the ground or power plane. When running across split planes is unavoidable, sufficient decoupling must
be used. Minimizing the number of signal vias reduces EMI by reducing inductance at high frequencies.
7.5.2.2.2.4 Cable Connector Socket
Short the cable connector sockets directly to a small chassis ground plane (GND strap) that exists
immediately underneath the connector sockets. This shorts EMI (and ESD) directly to the chassis ground
before it gets onto the USB cable. This etch plane should be as large as possible, but all the conductors
coming off connector pins 1 through 6 must have the board signal GND plane run under. If needed, scoop
out the chassis GND strap etch to allow for the signal ground to extend under the connector pins. Note
that the etches coming from pins 1 and 4 (VBUS power and GND) should be wide and via-ed to their
respective planes as soon as possible, respecting the filtering that may be in place between the connector
pin and the plane. See 图 7-23 for a schematic example.
Place a ferrite in series with the cable shield pins near the USB connector socket to keep EMI from getting
onto the cable shield. The ferrite bead between the cable shield and ground may be valued between 10 Ω
and 50 Ω at 100 MHz; it should be resistive to approximately 1 GHz. To keep EMI from getting onto the
cable bus power wire (a very large antenna) a ferrite may be placed in series with cable bus power,
VBUS, near the USB connector pin 1. The ferrite bead between connector pin 1 and bus power may be
valued between 47 Ω and approximately 1000 Ω at 100 MHz. It should continue being resistive out to
approximately 1 GHz, as shown in 图 7-23.
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5
SHIELD_GND
4
GND
3
DP
2
DM
1
+5 V
Ferrite Bead
VBUS
U2
6
SHIELD_GND
USB Socket
U1
Ferrite Bead
SPRS906_PCB_USB20_03
图 7-23. USB Connector
7.5.2.2.2.5 Clock Routings
To address the system clock emissions between devices, place a ~10 to 130 Ω resistor in series with the
clock signal. Use a trial and error method of looking at the shape of the clock waveform on a high-speed
oscilloscope and of tuning the value of the resistance to minimize waveform distortion. The value on this
resistor should be as small as possible to get the desired effect. Place the resistor close to the device
generating the clock signal. If an external crystal is used, follow the guidelines detailed in the Selection
and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
When routing the clock traces from one device to another, try to use the 3W spacing rule. The distance
from the center of the clock trace to the center of any adjacent signal trace should be at least three times
the width of the clock trace. Many clocks, including slow frequency clocks, can have fast rise and fall
times. Using the 3W rule cuts down on crosstalk between traces. In general, leave space between each of
the traces running parallel between the devices. Avoid using right angles when routing traces to minimize
the routing distance and impedance discontinuities. For further protection from crosstalk, run guard traces
beside the clock signals (GND pin to GND pin), if possible. This lessens clock signal coupling, as shown in
图 7-24.
3W
3W
W
Trace
SPRS906_PCB_USB20_04
图 7-24. 3W Spacing Rule
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7.5.2.2.2.6 Crystals/Oscillator
Keep the crystal and its load capacitors close to the USB PHY pins, XI and XO (see 图 7-25). Note that
frequencies from power sources or large capacitors can cause modulations within the clock and should
not be placed near the crystal. In these instances, errors such as dropped packets occur. A placeholder
for a resistor, in parallel with the crystal, can be incorporated in the design to assist oscillator startup.
Power is proportional to the current squared. The current is I = C × dv/dt, because dv/dt is a function of
the PHY, current is proportional to the capacitive load. Cutting the load to 1/2 decreases the current by 1/2
and the power to 1/4 of the original value. For more details on crystal selection, see the Selection and
Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122).
X1
0.1 µF
Power Pins
XTAL
X0
0.001 µF
USB PHY
SPRS906_PCB_USB20_05
图 7-25. Power Supply and Clock Connection to the USB PHY
7.5.2.2.2.7 DP/DM Trace
Place the USB PHY as close as possible to the USB 2.0 connector. The signal swing during high-speed
operation on the DP/DM lines is relatively small (400 mV ± 10%), so any differential noise picked up on
the twisted pair can affect the received signal. When the DP/DM traces do not have any shielding, the
traces tend to behave like an antenna and picks up noise generated by the surrounding components in
the environment. To minimize the effect of this behavior:
•
DP/DM traces should always be matched lengths and must be no more than 4 inches in length;
otherwise, the eye opening may be degraded (see 图 7-26).
•
Route DP/DM traces close together for noise rejection on differential signals, parallel to each other and
within two mils in length of each other. The measurement for trace length must be started from
device's balls.
•
•
A high-speed USB connection is made through a shielded, twisted pair cable with a differential
characteristic impedance of 90 Ω ±15%. In layout, the impedance of DP and DM should each be 45 Ω
± 10%.
DP/DM traces should not have any extra components to maintain signal integrity. For example, traces
cannot be routed to two USB connectors.
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Minimize
This Distance
VBUS
GND
D+
Cable
Connector
D+
D-
USB PHY
Connector
D-
SPRS906_PCB_USB20_06
图 7-26. USB PHY Connector and Cable Connector
7.5.2.2.2.8 DP/DM Vias
When a via must be used, increase the clearance size around it to minimize its capacitance. Each via
introduces discontinuities in the signal’s transmission line and increases the chance of picking up
interference from the other layers of the board. Be careful when designing test points on twisted pair lines;
through-hole pins are not recommended.
7.5.2.2.2.9 Image Planes
An image plane is a layer of copper (voltage plane or ground plane), physically adjacent to a signal routing
plane. Use of image planes provides a low impedance, shortest possible return path for RF currents. For a
USB board, the best image plane is the ground plane because it can be used for both analog and digital
circuits.
•
Do not route traces so they cross from one plane to the other. This can cause a broken RF return path
resulting in an EMI radiating loop as shown in 图 7-27. This is important for higher frequency or
repetitive signals. Therefore, on a multi-layer board, it is best to run all clock signals on the signal
plane above a solid ground plane.
•
Avoid crossing the image power or ground plane boundaries with high-speed clock signal traces
immediately above or below the separated planes. This also holds true for the twisted pair signals (DP,
DM). Any unused area of the top and bottom signal layers of the PCB can be filled with copper that is
connected to the ground plane through vias.
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Do
Don't
SPRS906_PCB_USB20_07
图 7-27. Do Not Cross Plane Boundaries
•
Do not overlap planes that do not reference each other. For example, do not overlap a digital power
plane with an analog power plane as this produces a capacitance between the overlapping areas that
could pass RF emissions from one plane to the other, as shown in 图 7-28.
Analog Power Plane
Unwanted Capacitance
Digital Power Plane
SPRS906_PCB_USB20_08
图 7-28. Do Not Overlap Planes
•
Avoid image plane violations. Traces that route over a slot in an image plane results in a possible RF
return loop, as shown in 图 7-29.
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RF Return
Current
RF Return
Current
Slot in Image Plane
Slot in Image Plane
Bad
Better
SPRS906_PCB_USB20_09
图 7-29. Do Not Violate Image Planes
7.5.2.2.2.10 Power Regulators
Switching power regulators are a source of noise and can cause noise coupling if placed close to sensitive
areas on a circuit board. Therefore, the switching power regulator should be kept away from the DP/DM
signals, the external clock crystal (or clock oscillator), and the USB PHY.
7.5.2.3 References
USB 2.0 Specification, Intel, 2000, http://www.usb.org/developers/docs/
High Speed USB Platform Design Guidelines,
http://www.intel.com/technology/usb/download/usb2dg_R1_0.pdf
Selection and Specification of Crystals for Texas Instruments USB 2.0 Devices (SLLA122)
•
•
Intel,
2000,
•
7.5.3 USB 3.0 Board Design and Layout Guidelines
This section provides the timing specification for the USB3.0 (USB1 in the device) interface as a PCB
design and manufacturing specification. The design rules constrain PCB trace length, PCB trace skew,
signal integrity, cross-talk, and signal timing. TI has performed the simulation and system design work to
ensure the USB3.0 interface requirements are met. The design rules stated within this document are
targeted at DEVICE mode electrical compliance. HOST mode and/or systems that do not include the 3m
USB cable and far-end 11-inch PCB trace required by DEVICE mode compliance testing may not need
the complete list of optimizations shown in this document; however, applying these optimizations to HOST
mode systems will lead to optimal DEVICE mode performance.
7.5.3.1 USB 3.0 interface introduction
The USB 3.0 has two unidirectional differential pairs: TXp/TXn pair and RXp/RXn pair. AC coupling caps
are needed on the board for TX traces.
图 7-30 present high level schematic diagram for USB 3.0 interface.
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Device
AC Caps
usb_txp0
usb_txn0
CMF
Vias (if necessary)
Vias (if necessary)
usb_rxp0
usb_rxn0
CMF
Vias (if necessary)
Vias (if necessary)
Place near connector, and keep routing short
SPRS85x_PCB_USB30_1
图 7-30. USB 3.0 Interface High Level Schematic
注
ESD components should be on a PCB layer next to a system GND plane layer so the
inductance of the via to GND will be minimal.
If vias are used, place the vias near the AC Caps or CMFs and under the SoC BGA, if
necessary.
图 7-31 present placement diagram for USB 3.0 interface.
AC Cap
SoC TX
SoC RX
CMF
CMF
AC Cap
SPRS85x_PCB_USB30_2
图 7-31. USB 3.0 placement diagram
表 7-9. USB1 Component Reference
INTERFACE
COMPONENT
ESD
SUPPLIER
PART NUMBER
TI
Murata
-
TPD1E05U06
DLW21SN900HQ2
USB3 PHY
CMF
C
100nF (typical size: 0201)
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7.5.3.2 USB 3.0 General routing rules
Some general routing guidelines regarding USB 3.0:
•
•
•
•
•
•
Avoid crossing splits reference plane(s).
Shorter trace length is preferred.
Minimize the via usage and layer transition
Keep large spacing between TX and RX pairs.
Intra-lane delay mismatch between DP and DM less than 1ps. Same for RXp and RXn.
Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
•
•
•
Distance between ESD protection device and USB connector should be as short as possible.
Distance between AC capacitors (TX only) and CMF should be as short as possible.
USB 3.0 signals should always be routed over an adjacent ground plane.
表 7-10 and 表 7-11 present routing specification and recommendations for USB1 in the device.
表 7-10. USB1 Routing Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Device balls to USB 3.0 connector trace
length
3500
Mils
Skew within a differential pair
Number of stubs allowed on TX/RX traces
TX/RX pair differential impedance
3
6
0
Mils
Stubs
Ω
83
90
97
2
Number of vias on each TX/RX trace
Differential pair to any other trace spacing
Vias
2xDS
3xDS
Number of ground plane cuts allowed within
USB3 routing region (except for specific
ground carving as explained in this
document)
0
0
Cuts
Number of layers between USB3.0 routing
region and reference ground plane
Layers
PCB trace width
6
Mils
Mils
Mils
PCB BGA escape via pad size
PCB BGA escape via hole size
18
10
1. Vias must be used in pairs and spaced equally along a signal path.
2. DS = differential spacing of the traces.
3. Exceptions may be necessary in the SoC package BGA area.
4. GND guard-bands on the same layer may be closer, but should not be allowed to affect the impedance
of the differential pair routing. GND guard-bands to isolate USB3.0 differential pairs from all other
signals are recommended.
表 7-11. USB1 Routing Recommendations
Item
Description
Reason
Place ESD component on same layer as connector (no via or stub to Eliminate reflection loss from via
ESD location
ESD component)
TPD1E05U06
& stub to ESD
ESD part number
CMF part number
Minimize capacitance (0.42pF)
Manufacturer’s recommended
device
DLW21SN900HQ2
Enable full signal chain
simulation
Connector
Use USB3.0 connector with supporting s-parameter model
Carve GND underneath AC Caps, ESD, CMF, and connector
Minimize capacitance under ESD
and CMF
Carve Ground
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表 7-11. USB1 Routing Recommendations (continued)
Item
Description
Reason
Minimize pad size and round the corners of the pads for the ESD
and CMF components
Round pads
Minimize capacitance
Max 2 vias per signal trace. If vias are required, place vias close to
the AC Caps and CMFs. Vias under the SoC grid array may be used
if necessary to route signals away from BGA pattern.
Vias significantly degrade signal
integrity at 2.5GHz
Vias
图 7-32 presents an example layout, demonstrating the “carve GND” concept.
AC Cap
CMF
AC Cap
CMF
Layer2, GND: Gaps carved in GND underneath
AC Caps, CMF, ESD, and connector.
Top Layer: Routing from SoC through
AC Caps, CMF, and ESD to connector.
Layer3, Signal: Implement as keep-out
zone underneath carved GND areas.
Layer4, GND Plane underneath AC Caps,
CMF, ESD, and connector.
SPRS85x_PCB_USB30_3
图 7-32. USB 3.0 Example “carve GND” layout
7.5.4 HDMI Board Design and Layout Guidelines
This section provides the timing specification for the HDMI interface as a PCB design and manufacturing
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. TI has performed the simulation and system design work to ensure the HDMI interface
requirements are met. The design rules stated within this document are targeted at resolutions less than
or equal to 1080p60 with 8-bit color; deep color (10-bit) requires further signal integrity optimization.
7.5.4.1 HDMI Interface Schematic
The HDMI bus is separated into three main sections (HDMI Ethernet and the optional Audio Return
Channel are not specifically supported by this Device):
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1. Transition Minimized Differential Signaling (TMDS) high speed digital video interface
2. Display Data Channel (I2C bus for configuration and status exchange between two devices)
3. Consumer Electronics Control (optional) for remote control of connected devices.
The DDC and CEC are low speed interfaces, so nothing special is required for PCB layout of these
signals.
The TMDS channels are high speed differential pairs and therefore require the most care in layout.
Specifications for TMDS layout are below.
图 7-33 shows the HDMI interface schematic.
Device
hdmi_tx*-
CMF
hdmi_tx*+
Place near connector, and keep routing short
SPRS85x_PCB_HDMI_1
图 7-33. HDMI Interface High Level Schematic
图 7-34 presents placement diagram for HDMI interface.
CMF
CMF
CMF
CMF
SPRS85x_PCB_HDMI_2
图 7-34. HDMI Placement Diagram
表 7-12. HDMI Component Reference
INTERFACE
DEVICE
ESD
SUPPLIER
TI
PART NUMBER
TPD1E05U06
HDMI
CMF
Murata
DLW21SN900HQ2
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7.5.4.2 TMDS General Routing Guidelines
The TMDS signals are high speed differential pairs. Care must be taken in the PCB layout of these signals
to ensure good signal integrity.
The TMDS differential signal traces must be routed to achieve 100 Ohms (+/- 10%) differential impedance
and 60 ohms (+/-10%) single ended impedance. Single ended impedance control is required because
differential signals can’t be closely coupled on PCBs and therefore single ended impedance becomes
important.
These impedances are impacted by trace width, trace spacing, distance to reference planes, and dielectric
material. Verify with a PCB design tool that the trace geometry for both data signal pairs results in as
close to 60 ohms impedance traces as possible. For best accuracy, work with your PCB fabricator to
ensure this impedance is met.
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier, and trace width variations don’t affect impedance as much, therefore it’s
easier to maintain accurate impedance over the length of the signal. The wider traces also show reduced
skin effect and therefore often result in better signal integrity.
Some general routing guidelines regarding TMDS:
•
•
•
Avoid crossing splits reference plane(s).
Shorter trace length is preferred.
Distance between common mode filter (CMF) and ESD protection device should be as short as
possible
•
Distance between ESD protection device and HDMI connector should be as short as possible.
表 7-13 shows the routing specifications for the TMDS signals.
表 7-13. TMDS Routing Specifications
PARAMETER
Device balls to HDMI header trace length
MIN
TYP
MAX
4000
5
UNIT
Mils
Mils
stubs
Ω
Skew within a differential pair
3
Number of stubs allowed on TMDS traces
TMDS pair differential impedance
TMDS single-ended impedance
0
90
54
100
60
110
66
Ω
Number of vias on each TMDS trace
TMDS differential pair to any other trace spacing
0
Vias
Mils
(1) (2) (3)
2×DS
3xDS
Number of ground plane cuts allowed within HDMI routing region (except for specific
ground carving as explained in this document)
0
0
Cuts
Number of layers between HDMI routing region and reference ground plane
PCB trace width
Layers
Mils
4.4
(1) DS = differential spacing of the traces.
(2) Exceptions may be necessary in the SoC package BGA area.
(3) GND guard-bands may be closer, but should not be allowed to affect the impedance of the differential pair routing. GND guard-bands to
isolate HDMI differential pairs from all other signals is recommended.
表 7-14. TDMS Routing Recommendations
Item
Description
Reason
ESD part number
TPD1E05U06
Minimize capacitance (0.42pF)
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表 7-14. TDMS Routing Recommendations (continued)
Item
Description
Reason
Minimize capacitance under ESD
and CMF
Carve Ground
Carve GND underneath ESD and CMF
Reduce pad size and round the corners of the pads for the ESD and
CMF components
Round pads
Routing layer
Minimize capacitance
Minimize reflection loss
Route all signals only on the same layer as SoC
图 7-35presents an example layout, demonstrating the “carve GND” concept.
CMF
CMF
CMF
CMF
Top Layer: Routing from SoC through CMF,
and ESD to connector.
Layer2, GND: Gaps carved in GND underneath,
CMF, ESD, and connector.
SPRS85x_PCB_HDMI_3
图 7-35. HDMI Example “carve GND” layout
7.5.4.3 TPD5S115
The TPD5S115 is an integrated HDMI companion chip solution. The device provides a regulated 5 V
output (5VOUT) for sourcing the HDMI power line. The TPD5S115 exceeds the IEC61000-4-2 (Level 4)
ESD protection level.
7.5.4.4 HDMI ESD Protection Device (Required)
Interfaces that connect to a cable such as HDMI generally require more ESD protection than can be built
into the processor’s outputs. Therefore this HDMI interface requires the use of an ESD protection chip to
provide adequate ESD.
When selecting an ESD protection chip, choose the lowest capacitance ESD protection available to
minimize signal degradation. In no case should be ESD protection circuit capacitance be more than 5pF.
TI manufactures these devices that provide ESD protection for HDMI signals such as the TPDxE05U06.
For more information see the www.ti.com website.
7.5.4.5 PCB Stackup Specifications
表 7-15 shows the stackup and feature sizes required for HDMI.
表 7-15. HDMI PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
PCB Routing/Plane Layers
4
6
-
Layers
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表 7-15. HDMI PCB Stackup Specifications (continued)
PARAMETER
MIN
TYP
MAX
UNIT
Signal Routing Layers
2
3
-
Layers
Number of ground plane cuts allowed within HDMI routing
region
-
-
-
0
0
Cuts
Number of layers between HDMI routing region and
reference ground plane
-
Layers
Mils
PCB Trace width
4
7.5.4.6 Grounding
Each TMDS channel has its own shield pin and they should be grounded to provide a return current path
for the TMDS signal.
7.5.5 PCIe Board Design and Layout Guidelines
The PCIe interface on the device provides support for a 5.0 Gbps lane with polarity inversion.
7.5.5.1 PCIe Connections and Interface Compliance
The PCIe interface on the device is compliant with the PCIe revision 3.0 specification. Please refer to the
PCIe specifications for all connections that are described in it. Those recommendations are more
descriptive and exhaustive than what is possible here.
The use of PCIe compatible bridges and switches is allowed for interfacing with more than one other
processor or PCIe device.
7.5.5.1.1 Coupling Capacitors
AC coupling capacitors are required on the transmit data pair. 表 7-16 shows the requirements for these
capacitors.
表 7-16. PCIe AC Coupling Capacitors Requirements
PARAMETER
MIN
TYP
100
MAX
110
UNIT
nF
EIA(1)(2)
PCIe AC coupling capacitor value
PCIe AC coupling capacitor package size
90
0402
0603
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
7.5.5.1.2 Polarity Inversion
The PCIe specification requires polarity inversion support. This means for layout purposes, polarity is
unimportant because each signal can change its polarity on die inside the chip. This means polarity within
a lane is unimportant for layout.
7.5.5.2 Non-standard PCIe connections
The following sections contain suggestions for any PCIe connection that is NOT described in the official
PCIe specification, such as an on-board Device to Device or Device to other PCIe compliant processor
connection.
7.5.5.2.1 PCB Stackup Specifications
表 7-17 shows the stackup and feature sizes required for these types of PCIe connections.
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表 7-17. PCIe PCB Stackup Specifications
PARAMETER
MIN
TYP
MAX
UNIT
Number of ground plane cuts allowed within PCIe routing
region
-
-
0
Cuts
Number of layers between PCIe routing area and reference
-
-
0
Layers
(1)
plane
PCB Routing clearance
PCB Trace width
4
4
Mils
Mils
(1) A reference plane may be a ground plane or the power plane referencing the PCIe signals.
7.5.5.2.2 Routing Specifications
7.5.5.2.2.1 Impedance
The PCIe data signal traces must be routed to achieve 100-Ω (±10%) differential impedance and 60-Ω
(±10%) single-ended impedance. The single-ended impedance is required because differential signals are
extremely difficult to closely couple on PCBs and, therefore, single-ended impedance becomes important.
These requirements are the same as those recommended in the PCIe Motherboard Checklist 1.0
document, available from PCI-SIG (www.pcisig.com).
These impedances are impacted by trace width, trace spacing, distance between signals and referencing
planes, and dielectric material. Verify with a PCB design tool that the trace geometry for both data signal
pairs result in as close to 100-Ω differential impedance and 60-Ω single-ended impedance as possible. For
best accuracy, work with your PCB fabricator to ensure this impedance is met. See 表 7-18 below.
7.5.5.2.2.2 Differential Coupling
In general, closely coupled differential signal traces are not an advantage on PCBs. When differential
signals are closely coupled, tight spacing and width control is necessary. Very small width and spacing
variations affect impedance dramatically, so tight impedance control can be more problematic to maintain
in production. For PCBs with very tight space limitations (which are usually small) this can work, but for
most PCBs, the loosely coupled option is probably best.
Loosely coupled PCB differential signals make impedance control much easier. Wider traces and spacing
make obstacle avoidance easier (because each trace is not so fixed in position relative to the other), and
trace width variations don’t affect impedance as much, therefore it’s easier to maintain an accurate
impedance over the length of the signal. For longer routes, the wider traces also show reduced skin effect
and therefore often result in better signal integrity with a larger eye diagram opening.
表 7-18 shows the routing specifications for the PCIe data signals.
表 7-18. PCI-E Routing Specifications
PARAMETER
PCIe signal trace length (device balls to PCIe connector)
Differential pair trace matching
MIN
TYP
MAX
UNIT
Mils
Mils
stubs
Ω
(1)
4700
(2)
5
(3)
Number of stubs allowed on PCIe traces
0
TX/RX pair differential impedance
TX/RX single-ended impedance
Pad size of vias on PCIe trace
90
54
100
60
110
66
Ω
(4)
25
Mils
Mils
Vias
Hole size of vias on PCIe trace
14
0
Number of vias on each PCIe trace
PCIe differential pair to any other trace spacing
(5)
2×DS
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(1) Beyond this, signal integrity may suffer.
(2) For example, RXP0 within 5 Mils of RXN0.
(3) Inline pads may be used for probing.
(4) 35-Mil antipad maximum recommended.
(5) DS = differential spacing of the PCIe traces.
表 7-19. PCI-E Routing Recommendations
Item
Description
Reason
ESD suppression generally not
used on PCIe
ESD part number
None
7.5.5.2.2.3 Pair Length Matching
Each signal in the differential pair should be matched to within 5 mils of its matching differential signal.
Length matching should be done as close to the mismatch as possible.
7.5.5.3 LJCB_REFN/P Connections
A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two
modes of Common Refclk Rx Architecture are supported:
•
External REFCLK Mode: An common external 100MHz clock source is distributed to both the Device
and the link partner
•
Output REFCLK Mode: A 100MHz HCSL clock source is output by the device and used by the link
partner
In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100MHz clock source compliant to
the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs.
Alternatively, an LVDS clock source can be used with the following additional requirements:
•
External AC coupling capacitors described in 表 7-20 should be populated at the ljcb_clkn / ljcb_clkp
inputs.
•
All termination requirements (ex. parallel 100ohm termination) from the clock source manufacturer
should be followed.
In Output REFCLK Mode, the 100MHz clock from the Device’s DPLL_PCIE_REF should be output on
the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-
side termination to ground described in 表 7-21 is required on both of the ljcb_clkn / ljcb_clkp outputs in
this mode.
表 7-20. LJCB_REFN/P Requirements in External LVDS REFCLK Mode
PARAMETER
MIN
TYP
100
MAX
UNIT
nF
EIA(1)(2)
ljcb_clkn / ljcb_clkp AC coupling capacitor value
ljcb_clkn / ljcb_clkp AC coupling capacitor package size
0402
0603
(1) EIA LxW units, i.e., a 0402 is a 40x20 mils surface mount capacitor.
(2) The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.
表 7-21. LJCB_REFN/P Requirements in Output REFCLK Mode
PARAMETER
MIN
TYP
MAX
UNIT
ljcb_clkn / ljcb_clkp near-side termination to ground value
47.5
50
52.5
Ohms
7.5.6 CSI2 Board Design and Routing Guidelines
The MIPI D-PHY signals include the CSI2_0 camera serial interfaces to or from the Device.
For more information regarding the MIPI-PHY signals and corresponding balls, see 表 4-5, CSI2 Signal
Descriptions.
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For more information, you can also see the MIPI D-PHY specification v1-01-00_r0-03 (specifically the
Interconnect and Lane Configuration and Annex B Interconnect Design Guidelines chapters).
In the next section, the PCB guidelines of the following differential interfaces are presented:
•
CSI2_0 CSI-2 at 1.5 Gbps
表 7-22 lists the MIPI D-PHY interface signals in the Device.
表 7-22. MIPI D-PHY Interface Signals in the Device
SIGNAL NAME
csi2_0_dx0
csi2_0_dx1
csi2_0_dx2
BOTTOM BALL
SIGNAL NAME
csi2_0_dy0
csi2_0_dy1
csi2_0_dy2
BOTTOM BALL
AC1
AD1
AE2
AB2
AC2
AD2
7.5.6.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
7.5.6.1.1 General Guidelines
The general guidelines for the PCB differential lines are:
•
•
Differential trace impedance Z0 = 100 Ω (minimum = 85 Ω, maximum = 115 Ω)
Total conductor length from the Device package pins to the peripheral device package pins is 25 to 30
cm with common FR4 PCB and flex materials.
注
Longer interconnect length can be supported at the expense of detailed simulations of the
complete link including driver and receiver models.
The general rule of thumb for the space S = 2 × W is not designated (see 图 7-19, Guard Illustration). It is
because although the S = 2 × W rule is a good rule of thumb, it is not always the best solution. The
electrical performance will be checked with the frequency-domain specification. Even though the designer
does not follow the S = 2 × W rule, the differential lines are ok if the lines satisfy the frequency-domain
specification.
Because the MIPI signals are used for low-power, single-ended signaling in addition to their high-speed
differential implementation, the pairs must be loosely coupled.
7.5.6.1.2 Length Mismatch Guidelines
7.5.6.1.2.1 CSI2_0 MIPI CSI-2 (1.5 Gbps)
The guidelines of the length mismatch for CSI-2 are presented in 表 7-23.
表 7-23. Length Mismatch Guidelines for CSI-2 (1.5 Gbps)
PARAMETER
TYPICAL VALUE
UNIT
Mbps
ps
Operating speed
1500
667
UI (bit time)
(1)
Intralane skew
Have to satisfy mode-conversion S parameters
Interlane skew (UI / 50)
PCB lane-to-lane skew (0.1 UI)
13.34
66.7
ps
ps
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(1) sdc12, scd21, scd12, sdc21, scd11, sdc11, scd22, and sdc22
7.5.6.1.3 Frequency-domain Specification Guidelines
After the PCB design is finished, the S-parameters of the PCB differential lines will be extracted with a 3D
Maxwell Equation Solver such as the high-frequency structure simulator (HFSS) or equivalent, and
compared to the frequency-domain specification as defined in the section 7 of the MIPI Alliance
Specification for D-PHY Version v1-01-00_r0-03.
If the PCB lines satisfy the frequency-domain specification, the design is finished. Otherwise, the design
needs to be improved.
7.6 Clock Routing Guidelines
7.6.1 Oscillator Ground Connection
Although the impedance of a ground plane is low it is, of course, not zero. Therefore, any noise current in
the ground plane causes a voltage drop in the ground.
图 7-36 shows the grounding scheme for high-frequency clock.
Device
xi_oscj
xo_oscj
vssa_oscj
Rd
(Optional)
Crystal
Cf2
Cf1
SPRS906_PCB_CLK_OSC_03
(1) j in *_osc = 0 or 1
图 7-36. Grounding Scheme for High-Frequency Clock
7.7 DDR3 Board Design and Layout Guidelines
7.7.1 DDR3 General Board Layout Guidelines
To help ensure good signaling performance, consider the following board design guidelines:
•
•
•
•
•
•
•
•
•
•
•
Avoid crossing splits in the power plane.
Minimize Vref noise.
Use the widest trace that is practical between decoupling capacitors and memory module.
Maintain a single reference.
Minimize ISI by keeping impedances matched.
Minimize crosstalk by isolating sensitive bits, such as strobes, and avoiding return path discontinuities.
Use proper low-pass filtering on the Vref pins.
Keep the stub length as short as possible.
Add additional spacing for on-clock and strobe nets to eliminate crosstalk.
Maintain a common ground reference for all bypass and decoupling capacitors.
Take into account the differences in propagation delays between microstrip and stripline nets when
evaluating timing constraints.
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7.7.2 DDR3 Board Design and Layout Guidelines
7.7.2.1 Board Designs
TI only supports board designs using DDR3 memory that follow the guidelines in this document. The
switching characteristics and timing diagram for the DDR3 memory controller are shown in 表 7-24 and 图
7-37.
表 7-24. Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory
Controller
NO.
PARAMETER
MIN
MAX
UNIT
1
tc(DDR_CLK)
Cycle time, DDR_CLK
1.5
2.5(1)
ns
(1) This is the absolute maximum the clock period can be. Actual maximum clock period may be limited by DDR3 speed grade and
operating frequency (see the DDR3 memory device data sheet).
1
DDR_CLK
SPRS906_PCB_DDR3_01
图 7-37. DDR3 Memory Controller Clock Timing
7.7.2.2 DDR3 EMIF
The processor contains one DDR3 EMIF with one chip select.
7.7.2.3 DDR3 Device Combinations
Because there are several possible combinations of device counts and single- or dual-side mounting, 表
7-25 summarizes the supported device configurations.
表 7-25. Supported DDR3 Device Combinations
NUMBER OF DDR3 DEVICES
DDR3 DEVICE WIDTH (BITS)
MIRRORED?
DDR3 EMIF WIDTH (BITS)
1
2
2
2
3
4
4
5
16
8
N
Y(1)
N
Y(1)
N(3)
N
16
16
32
32
32
32
32
32
16
16
16
8
8
Y(2)
(3)
8
N
(1) Two DDR3 devices are mirrored when one device is placed on the top of the board and the second device is placed on the bottom of
the board.
(2) This is two mirrored pairs of DDR3 devices.
(3) Three or five DDR3 device combination is not available on this device, but combination types are retained for consistency with the
DRA7xx family of devices.
7.7.2.4 DDR3 Interface Schematic
7.7.2.4.1 32-Bit DDR3 Interface
The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width
of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR
devices look like two 8-bit devices. 图 7-38 and 图 7-39 show the schematic connections for 32-bit
interfaces using x16 devices.
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7.7.2.4.2 16-Bit DDR3 Interface
Note that the 16-bit wide interface schematic is practically identical to the 32-bit interface (see 图 7-38 and
图 7-39); only the high-word DDR memories are removed and the unused DQS inputs are tied off.
When not using all or part of a DDR interface, the proper method of handling the unused pins is to tie off
the ddrx_dqsi pins to ground via a 1k-Ω resistor and to tie off the ddrx_dqsni pins to the corresponding
vdds_ddrx supply via a 1k-Ω resistor. This needs to be done for each byte not used. Although these
signals have internal pullups and pulldowns, external pullups and pulldowns provide additional protection
against external electrical noise causing activity on the signals.
The vdds_ddrx and ddrx_vref0 power supply pins need to be connected to their respective power supplies
even if ddrx is not being used. All other DDR interface pins can be left unconnected. Note that the
supported modes for use of the DDR EMIF are 32-bits wide, 16-bits wide, or not used.
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32-bit DDR3 EMIF
16-Bit DDR3
Devices
ddr1_d31
ddr1_d24
DQ15
DQ8
8
ddr1_dqm3
ddr1_dqs3
ddr1_dqsn3
UDM
UDQS
UDQS
ddr1_d23
DQ7
8
ddr1_d16
ddr1_dqm2
ddr1_dqs2
ddr1_dqsn2
D08
LDM
LDQS
LDQS
ddr1_d15
DQ15
DQ8
8
8
ddr1_d8
ddr1_dqm1
ddr1_dqs1
ddr1_dqsn1
ddr1_d7
UDM
UDQS
UDQS
DQ7
ddr1_d0
ddr1_dqm0
ddr1_dqs0
ddr1_dqsn0
ddr1_ck
DQ0
LDM
LDQS
LDQS
CK
0.1 µF
Zo
CK
CK
DDR_1V5
ddr1_nck
CK
Zo
ddr1_odt0
ddr1_csn0
ddr1_odt1
ddr1_csn1
ODT
CS
ODT
CS
ddr1_ba0
ddr1_ba1
ddr1_ba2
ddr1_a0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
Zo
Zo
16
ddr1_a15
ddr1_casn
ddr1_rasn
ddr1_wen
ddr1_cke
ddr1_rst
A15
A15
CAS
RAS
WE
CAS
RAS
WE
CKE
CKE
RST
DDR_VREF
RST
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
ddr1_vref0
0.1 µF
0.1 µF
0.1 µF
Zo
ZQ
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
SPRS906_PCB_DDR3_02
图 7-38. 32-Bit, One-Bank DDR3 Interface Schematic Using Two 16-Bit DDR3 Devices
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32-bit DDR3 EMIF
8-Bit DDR3
Devices
8-Bit DDR3
Devices
ddrx_d31
8
DQ7
DQ0
ddrx_d24
ddrx_dqm3
DM/TQS
TDQS
DQS
NC
ddrx_dqs3
ddrx_dqsn3
DQS
ddrx_d23
8
DQ7
DQ0
ddrx_d16
ddrx_dqm2
DM/TQS
TDQS
NC
ddrx_dqs2
DQS
DQS
ddrx_dqsn2
ddrx_d15
8
DQ7
ddrx_d8
DQ0
ddrx_dqm1
DM/TQS
TDQS
DQS
NC
ddrx_dqs1
ddrx_dqsn1
DQS
ddrx_d7
ddrx_d0
DQ7
DQ0
8
NC
TDQS
DM/TQS
ddrx_dqm0
ddrx_dqs0
ddrx_dqsn0
ddrx_ck
DQS
DQS
CK
0.1 µF
Zo
Zo
CK
CK
CK
CK
CK
CK
DDR_1V5
ddrx_nck
CK
ddrx_odt0
ddrx_csn0
ddrx_odt1
ddrx_csn1
ddrx_ba0
ddrx_ba1
ddrx_ba2
ddrx_a0
ODT
CS
ODT
CS
ODT
CS
ODT
CS
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
BA0
BA1
BA2
A0
DDR_VTT
Zo
Zo
16
ddrx_a15
ddrx_casn
ddrx_rasn
ddrx_wen
ddrx_cke
ddrx_rst
A15
A15
CAS
RAS
WE
A15
A15
CAS
RAS
WE
CAS
CAS
RAS
RAS
WE
WE
CKE
CKE
RST
CKE
CKE
RST
RST
RST
DDR_VREF
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
ZQ
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
VREFDQ
VREFCA
ddrx_vref0
0.1 µF
0.1 µF
0.1 µF
0.1 µF
0.1 µF
Zo
Termination is required. See terminator comments.
Value determined according to the DDR memory device data sheet.
ZQ
SPRS906_PCB_DDR3_03
图 7-39. 32-Bit, One-Bank DDR3 Interface Schematic Using Four 8-Bit DDR3 Devices
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7.7.2.5 Compatible JEDEC DDR3 Devices
表 7-26 shows the parameters of the JEDEC DDR3 devices that are compatible with this interface.
Generally, the DDR3 interface is compatible with DDR3-1333 devices in the x8 or x16 widths.
表 7-26. Compatible JEDEC DDR3 Devices (Per Interface)
N
PARAMETER
CONDITION
MIN
MAX
UNIT
O.
1
JEDEC DDR3 device speed grade(1)
DDR clock rate = 400MHz
DDR3-800
DDR3-1066
DDR3-1333
x8
DDR3-1600
DDR3-1600
DDR3-1600
x16
400MHz< DDR clock rate ≤ 533MHz
533MHz< DDR clock rate ≤ 667MHz
2
3
JEDEC DDR3 device bit width
JEDEC DDR3 device count(2)
Bits
2
4
Devices
(1) Refer to 表 7-24 Switching Characteristics Over Recommended Operating Conditions for DDR3 Memory Controller for the range of
supported DDR clock rates.
(2) For valid DDR3 device configurations and device counts, see 节 7.7.2.4, 图 7-38, and 图 7-39.
7.7.2.6 PCB Stackup
The minimum stackup for routing the DDR3 interface is a six-layer stack up as shown in 表 7-27.
Additional layers may be added to the PCB stackup to accommodate other circuitry, enhance SI/EMI
performance, or to reduce the size of the PCB footprint. Complete stackup specifications are provided in
表 7-28.
表 7-27. Six-Layer PCB Stackup Suggestion
LAYER
TYPE
Signal
Plane
Plane
Plane
Plane
Signal
DESCRIPTION
1
2
3
4
5
6
Top routing mostly vertical
Ground
Split power plane
Split power plane or Internal routing
Ground
Bottom routing mostly horizontal
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表 7-28. PCB Stackup Specifications
NO.
PARAMETER
MIN
TYP
MAX
UNIT
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PCB routing/plane layers
Signal routing layers
6
3
1
1
Full ground reference layers under DDR3 routing region(1)
Full 1.5-V power reference layers under the DDR3 routing region(1)
Number of reference plane cuts allowed within DDR routing region(2)
Number of layers between DDR3 routing layer and reference plane(3)
PCB routing feature size
0
0
4
4
Mils
Mils
Ω
PCB trace width, w
Single-ended impedance, Zo
Impedance control(5)
50
75
Z-5
Z
Z+5
Ω
(1) Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer
return current as the trace routes switch routing layers.
(2) No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts
create large return current paths which can lead to excessive crosstalk and EMI radiation.
(3) Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.
(4) An 18-mil pad assumes Via Channel is the most economical BGA escape. A 20-mil pad may be used if additional layers are available
for power routing. An 18-mil pad is required for minimum layer count escape.
(5) Z is the nominal singled-ended impedance selected for the PCB specified by PS9.
7.7.2.7 Placement
图 7-40 shows the required placement for the processor as well as the DDR3 devices. The dimensions for
this figure are defined in 表 7-29. The placement does not restrict the side of the PCB on which the
devices are mounted. The ultimate purpose of the placement is to limit the maximum trace lengths and
allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3 devices are
omitted from the placement.
图 7-40. Placement Specifications
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表 7-29. Placement Specifications DDR3
NO.
PARAMETER
MIN
MAX
500
UNIT
Mils
Mils
Mils
Mils
Mils
KOD31 X1
KOD32 X2
KOD33 X3
KOD34 Y1
KOD35 Y2
600
600
1800
600
KOD36 DDR3 keepout region (1)
KOD37 Clearance from non-DDR3 signal
to DDR3 keepout region (2) (3)
4
W
(1) DDR3 keepout region to encompass entire DDR3 routing area.
(2) Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.
(3) If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be
separated by this specification.
7.7.2.8 DDR3 Keepout Region
The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout
region is defined for this purpose and is shown in 图 7-41. The size of this region varies with the
placement and DDR routing. Additional clearances required for the keepout region are shown in 表 7-29.
Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region. Non-
DDR3 signals may be routed in the region, provided they are routed on layers separated from the DDR
signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this region.
In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that the two
signals from the DDR3 controller should be separated from each other by the specification in 表 7-29 (see
KOD37).
图 7-41. DDR3 Keepout Region
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7.7.2.9 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry. 表 7-
30 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this
table only covers the bypass needs of the DDR3 controllers and DDR3 devices. Additional bulk bypass
capacitance may be needed for other circuitry.
表 7-30. Bulk Bypass Capacitors
NO.
1
PARAMETER
vdds_ddrx bulk bypass capacitor count(1)
vdds_ddrx bulk bypass total capacitance
MIN
1
MAX
UNIT
Devices
μF
2
22
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR3 signal routing.
7.7.2.10 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. 表 7-31 contains the specification for the HS bypass capacitors
as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in 表 7-31.
表 7-31. High-Speed Bypass Capacitors
NO.
1
PARAMETER
HS bypass capacitor package size(1)
MIN
TYP
MAX
0402
400
UNIT
10 Mils
Mils
0201
2
Distance, HS bypass capacitor to processor being bypassed(2)(3)(4)
Processor HS bypass capacitor count per vdds_ddrx rail(12)
Processor HS bypass capacitor total capacitance per vdds_ddrx rail(12)
Number of connection vias for each device power/ground ball(5)
Trace length from device power/ground ball to connection via(2)
Distance, HS bypass capacitor to DDR device being bypassed(6)
DDR3 device HS bypass capacitor count(7)
3
See 表 7-3 and (11)
See 表 7-3 and (11)
Devices
μF
4
5
Vias
6
35
70
Mils
7
150
Mils
8
12
0.85
2
Devices
μF
9
DDR3 device HS bypass capacitor total capacitance(7)
10 Number of connection vias for each HS capacitor(8)(9)
11 Trace length from bypass capacitor connect to connection via(2)(9)
12 Number of connection vias for each DDR3 device power/ground ball(10)
13 Trace length from DDR3 device power/ground ball to connection via(2)(8)
(1) LxW, 10-mil units, that is, a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
Vias
35
35
100
60
Mils
1
Vias
Mils
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
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(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
(11) The capacitor recommendations in this data manual reflect only the needs of this processor. Please see the memory vendor’s
guidelines for determining the appropriate decoupling capacitor arrangement for the memory device itself.
(12) For more information, see 节 7.3, Core Power Domains.
7.7.2.10.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Because these are returns for signal current, the signal via size may be used for these
capacitors.
7.7.2.11 Net Classes
表 7-32 lists the clock net classes for the DDR3 interface. 表 7-33 lists the signal net classes, and
associated clock net classes, for signals in the DDR3 interface. These net classes are used for the
termination and routing rules that follow.
表 7-32. Clock Net Class Definitions
CLOCK NET CLASS processor PIN NAMES
CK
ddrx_ck/ddrx_nck
DQS0
ddrx_dqs0 / ddrx_dqsn0
ddrx_dqs1 / ddrx_dqsn1
ddrx_dqs2 / ddrx_dqsn2
ddrx_dqs3 / ddrx_dqsn3
DQS1
DQS2(1)
DQS3(1)
(1) Only used on 32-bit wide DDR3 memory systems.
表 7-33. Signal Net Class Definitions
ASSOCIATED CLOCK
SIGNAL NET CLASS
processor PIN NAMES
NET CLASS
ADDR_CTRL
CK
ddrx_ba[2:0], ddrx_a[14:0], ddrx_csnj, ddrx_casn, ddrx_rasn, ddrx_wen,
ddrx_cke, ddrx_odti
DQ0
DQ1
DQ2(1)
DQ3(1)
DQS0
DQS1
DQS2
DQS3
ddrx_d[7:0], ddrx_dqm0
ddrx_d[15:8], ddrx_dqm1
ddrx_d[23:16], ddrx_dqm2
ddrx_d[31:24], ddrx_dqm3
(1) Only used on 32-bit wide DDR3 memory systems.
7.7.2.12 DDR3 Signal Termination
Signal terminators are required for the CK and ADDR_CTRL net classes. The data lines are terminated by
ODT and, thus, the PCB traces should be unterminated. Detailed termination specifications are covered in
the routing rules in the following sections.
7.7.2.13 VREF_DDR Routing
ddrx_vref0 (VREF) is used as a reference by the input buffers of the DDR3 memories as well as the
processor. VREF is intended to be half the DDR3 power supply voltage and is typically generated with the
DDR3 VDDS and VTT power supply. It should be routed as a nominal 20-mil wide trace with 0.1 µF
bypass capacitors near each device connection. Narrowing of VREF is allowed to accommodate routing
congestion.
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7.7.2.14 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
7.7.2.15 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. The figures in the following subsections define the terms for the routing specification
detailed in 表 7-34.
7.7.2.15.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
7.7.2.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
图 7-42 shows the topology of the CK net classes and 图 7-43 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
–
–
+
+
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_06
图 7-42. CK Topology for Four x8 DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
A4
A3
AT
VTT
SPRS906_PCB_DDR3_07
图 7-43. ADDR_CTRL Topology for Four x8 DDR3 Devices
7.7.2.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
图 7-44 shows the CK routing for four DDR3 devices placed on the same side of the PCB. 图 7-45 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_08
图 7-44. CK Routing for Four Single-Side DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_09
图 7-45. ADDR_CTRL Routing for Four Single-Side DDR3 Devices
To save PCB space, the four DDR3 memories may be mounted as two mirrored pairs at a cost of
increased routing and assembly complexity. 图 7-46 and 图 7-47 show the routing for CK and
ADDR_CTRL, respectively, for four DDR3 devices mirrored in a two-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
A4
A4
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_10
图 7-46. CK Routing for Four Mirrored DDR3 Devices
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Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_11
图 7-47. ADDR_CTRL Routing for Four Mirrored DDR3 Devices
7.7.2.15.2 Two DDR3 Devices
Two DDR3 devices are supported on the DDR EMIF consisting of two x8 DDR3 devices arranged as one
bank (CS), 16 bits wide, or two x16 DDR3 devices arranged as one bank (CS), 32 bits wide. These two
devices may be mounted on a single side of the PCB, or may be mirrored in a pair to save board space at
a cost of increased routing complexity and parts on the backside of the PCB.
7.7.2.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
图 7-48 shows the topology of the CK net classes and 图 7-49 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffers
–
–
+
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
A3
A3
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_12
图 7-48. CK Topology for Two DDR3 Devices
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
A3
AT
VTT
SPRS906_PCB_DDR3_13
图 7-49. ADDR_CTRL Topology for Two DDR3 Devices
7.7.2.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
图 7-50 shows the CK routing for two DDR3 devices placed on the same side of the PCB. 图 7-51 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_14
图 7-50. CK Routing for Two Single-Side DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_15
图 7-51. ADDR_CTRL Routing for Two Single-Side DDR3 Devices
To save PCB space, the two DDR3 memories may be mounted as a mirrored pair at a cost of increased
routing and assembly complexity. 图 7-52 and 图 7-53 show the routing for CK and ADDR_CTRL,
respectively, for two DDR3 devices mirrored in a single-pair configuration.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
A3
A3
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_16
图 7-52. CK Routing for Two Mirrored DDR3 Devices
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Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_17
图 7-53. ADDR_CTRL Routing for Two Mirrored DDR3 Devices
7.7.2.15.3 One DDR3 Device
A single DDR3 device is supported on the DDR EMIF consisting of one x16 DDR3 device arranged as
one bank (CS), 16 bits wide.
7.7.2.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
图 7-54 shows the topology of the CK net classes and 图 7-55 shows the topology for the corresponding
ADDR_CTRL net classes.
DDR Differential CK Input Buffer
–
+
Clock Parallel
Terminator
DDR_1V5
Rcp
A1
A1
A2
A2
AT
AT
Cac
Processor
Differential Clock
Output Buffer
+
–
0.1 µF
Rcp
Routed as Differential Pair
SPRS906_PCB_DDR3_18
图 7-54. CK Topology for One DDR3 Device
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DDR Address and Control Input Buffers
Address and Control
Terminator
Rtt
Processor
Address and Control
Output Buffer
A1
A2
AT
VTT
SPRS906_PCB_DDR3_19
图 7-55. ADDR_CTRL Topology for One DDR3 Device
7.7.2.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
图 7-56 shows the CK routing for one DDR3 device placed on the same side of the PCB. 图 7-57 shows
the corresponding ADDR_CTRL routing.
DDR_1V5
Cac
Rcp
Rcp
A2
A2
AT
AT
0.1 µF
=
SPRS906_PCB_DDR3_20
图 7-56. CK Routing for One DDR3 Device
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Rtt
A2
AT
VTT
=
SPRS906_PCB_DDR3_21
图 7-57. ADDR_CTRL Routing for One DDR3 Device
7.7.2.16 Data Topologies and Routing Definition
No matter the number of DDR3 devices used, the data line topology is always point to point, so its
definition is simple.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or vdds_ddr. Ensure there are nearby bypass capacitors to allow the return
currents to transition between reference planes if one of the reference planes is ground. The goal is to
minimize the size of the return current loops.
7.7.2.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
DQS lines are point-to-point differential, and DQ/DM lines are point-to-point singled ended. 图 7-58 and 图
7-59 show these topologies.
Processor
DQS
DDR
DQSn+
DQSn-
DQS
IO Buffer
IO Buffer
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_22
图 7-58. DQS Topology
Processor
DQ and DM
IO Buffer
DDR
Dn
DQ and DM
IO Buffer
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_23
图 7-59. DQ/DM Topology
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7.7.2.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
图 7-60 and 图 7-61 show the DQS and DQ/DM routing.
DQS
DQSn+
DQSn-
Routed Differentially
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_24
图 7-60. DQS Routing With Any Number of Allowed DDR3 Devices
DQ and DM
Dn
n = 0, 1, 2, 3
SPRS906_PCB_DDR3_25
图 7-61. DQ/DM Routing With Any Number of Allowed DDR3 Devices
7.7.2.17 Routing Specification
7.7.2.17.1 CK and ADDR_CTRL Routing Specification
Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this
skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter
traces up to the length of the longest net in the net class and its associated clock. A metric to establish
this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the
length between the points when connecting them only with horizontal or vertical segments. A reasonable
trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address
Control Longest Manhattan distance.
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Given the clock and address pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-62 and 图 7-63 show this
distance for four loads and two loads, respectively. It is from this distance that the specifications on the
lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for
other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class.
For CK and ADDR_CTRL routing, these specifications are contained in 表 7-34.
A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
A8(A)
A8(A)
Rtt
A2
A3
A4
A3
AT
VTT
=
SPRS906_PCB_DDR3_26
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-62. CACLM for Four Address Loads on One Side of PCB
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A8(A)
CACLMY
CACLMX
A8(A)
A8(A)
Rtt
A2
A3
AT
VTT
=
SPRS906_PCB_DDR3_27
A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3
memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that
satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.
The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this
length calculation. Non-included lengths are grayed out in the figure.
Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.
图 7-63. CACLM for Two Address Loads on One Side of PCB
表 7-34. CK and ADDR_CTRL Routing Specification(2)(3)
NO.
PARAMETER
MIN
TYP
MAX
500(1)
29
UNIT
ps
CARS31
CARS32
CARS33
CARS34
CARS35
CARS36
CARS37
CARS38
CARS39
CARS310
CARS311
CARS312
CARS313
CARS314
CARS315
CARS316
CARS317
CARS318
CARS319
CARS320
A1+A2 length
A1+A2 skew
A3 length
A3 skew(4)
A3 skew(5)
A4 length
ps
125
6
ps
ps
6
ps
125
6
17(1)
14(1)
12
ps
A4 skew
ps
AS length
5
1.3
5
ps
AS skew
ps
AS+/AS- length
AS+/AS- skew
AT length(6)
AT skew(7)
AT skew(8)
ps
1
ps
75
14
ps
ps
1
ps
CK/ADDR_CTRL trace length
1020
3(1)
1(15)
ps
Vias per trace
vias
vias
Via count difference
Center-to-center CK to other DDR3 trace spacing(9)
Center-to-center ADDR_CTRL to other DDR3 trace spacing(9)(10)
4w
4w
3w
Center-to-center ADDR_CTRL to other ADDR_CTRL trace
spacing(9)
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表 7-34. CK and ADDR_CTRL Routing Specification(2)(3) (continued)
NO.
PARAMETER
CK center-to-center spacing(11)(12)
CK spacing to other net(9)
Rcp(13)
MIN
TYP
MAX
UNIT
CARS321
CARS322
CARS323
CARS324
4w
Zo-1
Zo-5
Zo
Zo
Zo+1
Zo+5
Ω
Ω
Rtt(13)(14)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) The use of vias should be minimized.
(3) Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump
between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
(4) Non-mirrored configuration (all DDR3 memories on same side of PCB).
(5) Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
(6) While this length can be increased for convenience, its length should be minimized.
(7) ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
(8) CK net class only.
(9) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(10) The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
(11) CK spacing set to ensure proper differential impedance.
(12) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(13) Source termination (series resistor at driver) is specifically not allowed.
(14) Termination values should be uniform across the net class.
(15) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.
7.7.2.17.2 DQS and DQ Routing Specification
Skew within the DQS and DQ/DM net classes directly reduces setup and hold margin and thus this skew
must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces
up to the length of the longest net in the net class and its associated clock. As with CK and ADDR_CTRL,
a reasonable trace route length is to within a percentage of its Manhattan distance. DQLMn is defined as
DQ Longest Manhattan distance n, where n is the byte number. For a 32-bit interface, there are four
DQLMs, DQLM0-DQLM3. Likewise, for a 16-bit interface, there are two DQLMs, DQLM0-DQLM1.
注
It is not required, nor is it recommended, to match the lengths across all bytes. Length
matching is only required within each byte.
Given the DQS and DQ/DM pin locations on the processor and the DDR3 memories, the maximum
possible Manhattan distance can be determined given the placement. 图 7-64 shows this distance for four
loads. It is from this distance that the specifications on the lengths of the transmission lines for the data
bus are determined. For DQS and DQ/DM routing, these specifications are contained in 表 7-35.
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DQLMX0
DB0
DQ[0:7]/DM0/DQS0
DQ[8:15]/DM1/DQS1
DB1
DQLMX1
DQ[16:23]/DM2/DQS2
DB2
DQLMX2
DQ[23:31]/DM3/DQS3
DQLMY0
DQLMY1
DQLMY3 DQLMY2
DB3
DQLMX3
3
2
1
0
DB0 - DB3 represent data bytes 0 - 3.
SPRS906_PCB_DDR3_28
There are four DQLMs, one for each byte (32-bit interface). Each DQLM is the longest Manhattan distance of the
byte; therefore:
DQLM0 = DQLMX0 + DQLMY0
DQLM1 = DQLMX1 + DQLMY1
DQLM2 = DQLMX2 + DQLMY2
DQLM3 = DQLMX3 + DQLMY3
图 7-64. DQLM for Any Number of Allowed DDR3 Devices
表 7-35. Data Routing Specification(2)
NO.
PARAMETER
MIN
TYP
MAX
340
340
340
340
5
UNIT
ps
DRS31
DRS32
DRS33
DRS34
DRS35
DRS36
DRS37
DRS38
DRS39
DRS310
DRS311
DRS312
DRS313
DB0 length
DB1 length
ps
DB2 length
ps
DB3 length
DBn skew(3)
ps
ps
DQSn+ to DQSn- skew
DQSn to DBn skew(3)(4)
Vias per trace
Via count difference
1
ps
5(10)
2(1)
0(10)
ps
vias
vias
w(5)
w(5)
Center-to-center DBn to other DDR3 trace spacing(6)
Center-to-center DBn to other DBn trace spacing(7)
DQSn center-to-center spacing(8)(9)
4
3
DQSn center-to-center spacing to other net
4
w(5)
(1) Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of
rise time and fall time confirms desired operation.
(2) External termination disallowed. Data termination should use built-in ODT functionality.
(3) Length matching is only done within a byte. Length matching across bytes is neither required nor recommended.
(4) Each DQS pair is length matched to its associated byte.
(5) Center-to-center spacing is allowed to fall to minimum 2w for up to 1250 mils of routed length.
(6) Other DDR3 trace spacing means other DDR3 net classes not within the byte.
(7) This applies to spacing within the net classes of a byte.
(8) DQS pair spacing is set to ensure proper differential impedance.
(9) The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking,
center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended
impedance, Zo.
(10) Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal
propagation through vias – has been applied to ensure DBn skew and DQSn to DBn skew maximums are not exceeded.
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8 Device and Documentation Support
TI offers an extensive line of development tools, including methods to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules as listed below.
8.1 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
microprocessors (MPUs) and support tools. Each device has one of three prefixes: X, P, or null (no prefix)
(for example, TDA2Ex). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMDX) through fully qualified production devices and tools (TMDS).
Device development evolutionary flow:
X
Experimental device that is not necessarily representative of the final device's electrical
specifications and may not use production assembly flow.
P
Prototype device that is not necessarily the final silicon die and may not necessarily meet
final electrical specifications.
null
Production version of the silicon die that is fully qualified.
Support tool development evolutionary flow:
TMDX
Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS
Fully-qualified development-support product.
X and P devices and TMDX development-support tools are shipped against the following disclaimer:
"Developmental product is intended for internal evaluation purposes."
Production devices and TMDS development-support tools have been characterized fully, and the quality
and reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (X or P) have a greater failure rate than the standard production
devices. Texas Instruments recommends that these devices not be used in any production system
because their expected end-use failure rate still is undefined. Only qualified production devices are to be
used.
For orderable part numbers of TDA2Ex devices in the CBD package type, see the Package Option
Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative.
For additional description of the device nomenclature markings on the die, see the Silicon Errata (literature
number SPRZ428).
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8.1.1 Standard Package Symbolization
TDA
aBBBBBIrzYTPPPQ1
XXXXXXX
PIN ONE INDICATOR
G1
ZZZ
YYY
O
SWPS859_PACK_01
图 8-1. Printed Device Reference
注
Some devices may have a cosmetic circular marking visible on the top of the device package
which results from the production test process. In addition, some devices may also show a
color variation in the package substrate which results from the substrate manufacturer.
These differences are cosmetic only with no reliability impact.
8.1.2 Device Naming Convention
表 8-1. Nomenclature Description
FIELD
FIELD DESCRIPTION
VALUES
DESCRIPTION
PARAMETER
SYMBOLIZATION
ORDERABLE
a
Device evolution stage
X
Contact TI
Prototype
P
Preproduction (production test flow, no
reliability data)
BLANK
Production
BBBBB
I
Base production part number
Device Identity
TDA2E
ADAS 2nd Generation Entry Tier
Scene Viewing
GFX enabled
SR 1.0
V
G
r
Device revision
BLANK
A
B
D
H
SR 2.0
SR 2.1
z
Device Speed
Device type
Indicates the speed grade for each of the
cores in the device. For more information see
表 3-1, Device Comparison.
Y
BLANK
General purpose (Prototype and Production)
Emulation (E) devices
E
D
High security prototype devices with TI
Development keys (D)
S
High-Security device, Secure Boot Supported
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表 8-1. Nomenclature Description (continued)
FIELD
PARAMETER
FIELD DESCRIPTION
VALUES
SYMBOLIZATION
DESCRIPTION
ORDERABLE
T
PPP
c
Temperature
Q
Full temp range: -40°C to 125°C
Package designator
Carrier designator
CBD
S-PBGA-N538 (17mm × 17mm) Package
N/A
N/A
BLANK
R
Tray
Tape & Reel
Q1
Automotive Designator
BLANK
Q1
Not meeting automotive qualification
Meeting Q100 equal requirements, with
exceptions as specified in DM.
XXXXXXX
YYY
Lot Trace Code
As marked
As marked
N/A
N/A
Production Code, For TI use
only
ZZZ
Production Code, For TI use
onl
As marked
N/A
O
Pin one designator
As marked
As marked
N/A
N/A
G1
ECAT—Green package
designator
(1) To designate the stages in the product development cycle, TI assigns prefixes to the part numbers. These prefixes represent
evolutionary stages of product development from engineering prototypes through fully qualified production devices.
Prototype devices are shipped against the following disclaimer:
“This product is still under development and is intended for internal evaluation purposes.”
Notwithstanding any provision to the contrary, TI makes no warranty expressed, implied, or statutory, including any implied warranty of
merchantability of fitness for a specific purpose, of this device.
(2) Applies to device max junction temperature.
注
BLANK in the symbol or part number is collapsed so there are no gaps between characters.
8.2 Tools and Software
The following products support development for TDA2Ex platforms:
Development Tools
TDA2Ex Clock Tree Tool is interactive clock tree configuration software that allows the user to
visualize the device clock tree, interact with clock tree elements and view the effect on PRCM
registers, interact with the PRCM registers and view the effect on the device clock tree, and view a
trace of all the device registers affected by the user interaction with the clock tree.
TDA2Ex Register Descriptor Tool is an interactive device register configuration tool that allows users
to visualize the register state on power-on reset, and then customize the configuration of the device for
the specific use-case.
TDA2Ex Pad Configuration Tool is an interactive pad-configuration tool that allows the user to
visualize the device pad configuration state on power-on reset and then customize the configuration of
the pads for the specific use-case and identify the device register settings associated to that
configuration.
For a complete listing of development-support tools for the processor platform, visit the Texas Instruments
website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office
or authorized distributor.
8.3 Documentation Support
The following documents describe the TDA2Ex devices.
TRM
TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS) 23mm (ABC) Package
(SR2.0, SR1.0) 17mm (CBD) Package (SR2.1, SR2.0) Technical Reference Manual
Details the integration, the environment, the functional description, and the programming
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models for each peripheral and subsystem in the TDA2Ex family of devices.
Errata
TDA2Ex SoC for Advanced Driver Assistance Systems (ADAS) Silicon Revision
(SR2.1, SR2.0, SR1.0) Silicon Errata Describes known advisories on silicon and provides
workarounds.
8.4 Receiving Notification of Documentation Updates
To receive notification of documentation updates — including silicon errata — go to the product folder for
your device on www.ti.com. In the upper right-hand corner, click the "Alert me" button. This registers you
to receive a weekly digest of product information that has changed (if any). For change details, check the
revision history of any revised document.
8.5 Community Resources
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术
规范，并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI Embedded Processors WikiTexas Instruments Embedded Processors Wiki.
Established to help developers get started with Embedded Processors from Texas
Instruments and to foster innovation and growth of general knowledge about the hardware
and software surrounding these devices.
8.6 商标
ICEPick is a trademark of Texas Instruments Inc.
Arm, Cortex, Thumb are registered trademarks of Arm Limited.
Neon is a trademark of Arm Ltd.
HDMI is a trademark of HDMI Licensing, LLC.
PowerVR is a registered trademark of Imagination Technologies Ltd.
JTAG is a registered trademark of JTAG Technologies, Inc.
MIPI is a registered trademark of Mobile Industry Processor Interface (MIPI) Alliance.
MMC, eMMC are trademarks of MultiMediaCard Association.
带有两个 5Gbps 通道的 PCI Express is a registered trademark of PCI-SIG.
SD is a registered trademark of Toshiba Corporation.
Vivante is a registered trademark of Vivante Corporation.
All other trademarks are the property of their respective owners.
8.7 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
8.8 出口管制提示
接收方同意：如果美国或其他适用法律限制或禁止将通过非披露义务的披露方获得的任何产品或技术数据
（其中包括软件）（见美国、欧盟和其他出口管理条例之定义）、或者其他适用国家条例限制的任何受管制
产品或此项技术的任何直接产品出口或再出口至任何目的地，那么在没有事先获得美国商务部和其他相关政
府机构授权的情况下，接收方不得在知情的情况下，以直接或间接的方式将其出口。
8.9 术语表
TI 术语表
这份术语表列出并解释术语、缩写和定义。
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9 Mechanical Packaging and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Mechanical Data
The device package has been specially engineered with a technology called Via Channel. The Via
Channel Array technology allows larger than normal PCB via sizes, reduces the number of PCB signal
layers required in a PCB design with this package, and will substantially reduce PCB costs compared to a
full array 0.65mm pitch package.
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TDA2EGBDQCBDQ1
ACTIVE
FCCSP
FCCSP
FCCSP
CBD
538
538
538
84
RoHS & Green
RoHS & Green
RoHS & Green
Call TI
Level-3-260C-168 HR
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 125
TDA2EGBDQCBDQ1
TDA
784
784 CBD G1
Samples
TDA2EGBHQCBDQ1
TDA2EGBHQCBDRQ1
ACTIVE
ACTIVE
CBD
CBD
84
SNAGCU
Call TI
-40 to 125
-40 to 125
TDA2EGBHQCBDQ1
TDA
784
784 CBD G1
Samples
Samples
750
TDA2EGBHQCBDQ1
TDA
784
784 CBD G1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
20-Oct-2022
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OUTLINE
CBD0538A
FCBGA - 1.298 mm max height
SCALE 0.800
BALL GRID ARRAY
17.1
16.9
B
A
BALL A1 CORNER
17.1
16.9
(
14)
4X (R1)
(0.378)
C
SEATING PLANE
BALL TYP
NOTE 4
0.1 C
1.298 MAX
0.36
TYP
0.26
15.6 TYP
SYMM
(0.7) TYP
(0.7) TYP
0.65 TYP
AE
AC
AA
W
U
AD
AB
Y
V
T
R
SYMM
15.6
TYP
P
N
M
K
L
J
H
F
G
E
D
B
0.47
0.37
C
538X
0.15
0.08
A
C A B
1
3
5
7
9
11 13 15 17
19 21
23 25
24
14
16 18
20 22
2
4
6
8
10 12
0.65 TYP
C
NOTE 3
4222967/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
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EXAMPLE BOARD LAYOUT
CBD0538A
FCBGA - 1.298 mm max height
BALL GRID ARRAY
(0.65) TYP
1
2
3
4
5
6
7
9
10 11
8
12
13
14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
(0.65) TYP
538X ( 0.35)
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
LAND PATTERN EXAMPLE
SCALE:6X
(
0.35)
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
METAL
(
0.35)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4222967/A 04/2016
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
CBD0538A
FCBGA - 1.298 mm max height
BALL GRID ARRAY
538X ( 0.35)
(0.65) TYP
1
2
3
4
5
6
7
9
10 11
8
12
13
14 15 16 17 18 19 20 21 22 23 24 25
A
B
C
D
(0.65)
TYP
E
F
G
H
J
K
L
M
N
SYMM
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:6X
4222967/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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