TFP410PAPG4_技术文档

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

1

D

Digital Visual Interface (DVI) Compliant

D

Enhanced Jitter Performance

– No HSYNC Jitter Anomaly

– Negligible Data-Dependent Jitter

Supports Resolutions From VGA to UXGA

(25 MHz – 165 MHz Pixel Rates)

2

D

Programmable Using I C Serial Interface

Universal Graphics Controller Interface

– 12-Bit, Dual-Edge and 24-Bit,

Single-Edge Input Modes

Monitor Detection Through Hot-Plug and

Receiver Detection

– Adjustable 1.1 V to 1.8 V and Standard

3.3 V CMOS Input Signal Levels

– Fully Differential and Single-Ended Input

Clocking Modes

– Standard Intel 12-Bit Digital Video Port

Compatible as on Intel 81x Chipsets

D

Single 3.3-V Supply Operation

D

64-Pin TQFP Using TI’s PowerPAD

Package

D

TI’s Advanced 0.18 µm EPIC-5 CMOS

Process Technology

Pin Compatible With SiI164 DVI Transmitter

D

Enhanced PLL Noise Immunity

– On-Chip Regulators and Bypass

Capacitors for Reducing System Costs

description

The TFP410 is a Texas Instruments PanelBus flat panel display product, part of a comprehensive family of

end-to-end DVI 1.0-compliant solutions, targeted at the PC and consumer electronics industry.

The TFP410 provides a universal interface to allow a glue-less connection to most commonly available graphics

controllers. Some of the advantages of this universal interface include selectable bus widths, adjustable signal

levels, and differential and single-ended clocking. The adjustable 1.1-V to 1.8-V digital interface provides a

low-EMI, high-speed bus that connects seamlessly with 12-bit or 24-bit interfaces. The DVI interface supports

flat panel display resolutions up to UXGA at 165 MHz in 24-bit true color pixel format.

The TFP410 combines PanelBus circuit innovation with TI’s advanced 0.18 µm EPIC-5 CMOS process

technology and TI’s ultralow ground inductance PowerPAD package. The result is a compact 64-pin TQFP

package providing a reliable, low-current, low-noise, high-speed digital interface solution.

This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These

circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,

Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated

voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device

should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,

preferably either V

or ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for

CC

Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Footnote:

1. The digital visual interface (DVI) specification is an industry standard developed by the digital display working group (DDWG) for high-speed

digital connection to digital displays and has been adopted by industry-leading PC and consumer electronics manufacturers. The TFP410

is compliant to the DVI Revision 1.0 specification.

PanelBus, PowerPAD, and EPIC-5 are trademarks of Texas Instruments.

VESA is a trademark of Video Electronics Standards Association.

Intel is a trademark of Intel Corporation.

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1

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

pin assignments

PAP PACKAGE

(TOP VIEW)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

49

32

31

30

29

28

27

26

25

24

23

NC

DATA11

DATA10

DATA9

DATA8

DATA7

DATA6

IDCK–

IDCK+

TGND

TX2+

TX2–

50

51

52

53

54

55

56

57

TV

DD

TX1+

TX1–

TGND

TX0+

TX0–

DATA5 58

DATA4 59

DATA3 60

DATA2 61

TV

DD

22 TXC+

21 TXC–

20 TGND

19 TFADJ

DATA1

DATA0

DGND

62

63

64

PV

18

17

DD

PGND

1 2

3

4

5

6 7 8 9 10 11 12 13 14 15 16

2

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

functional block diagram

Universal Input

T.M.D.S. Transmitter

IDCK±

DATA[23:0]

DE

12/24 Bit

I/F

Data

Format

Serializer

Control

TX2±

TX1±

VSYNC

HSYNC

Encoder

V

REF

EDGE/HTPLG

DKEN

TX0±

TXC±

MSEN

PD

ISEL/RST

CTL/A/DK[3:1]

TFADJ

2

BSEL/SCL

DSEL/SDA

I C Slave I/F

For DDC

1.8-V Regulators

With Bypass

Capacitors

PLL

Terminal Functions

TERMINAL

NAME

I/O

DESCRIPTION

NO.

Input

DATA[23:12]

36–47

I

The upper 12 bits of the 24-bit pixel bus

In 24-bit, single-edge input mode (BSEL = high), this bus inputs the top half of the 24-bit pixel bus.

In 12-bit, dual-edge input mode (BSEL = low), these bits are not used to input pixel data. In this mode,

2

the state of DATA[23:16] is input to the I C register CFG. This allows 8 bits of user configuration data to

2

be read by the graphics controller through the I C interface (see the I C register descriptions section).

Note: All unused data inputs should be tied to GND or V

.

DD

DATA[11:0]

50–55,

58–63

I

The lower 12 bits of the 24-bit pixel bus/12-bit pixel bus input

In 24-bit, single-edge input mode (BSEL = high), this bus inputs the bottom half of the 24-bit pixel bus.

In 12-bit, dual-edge input mode (BSEL = low), this bus inputs 1/2 a pixel (12 bits) at every latch edge

(both rising and falling) of the clock.

IDCK–

IDCK+

56

57

Differential clock input. The TFP410 supports both single-ended and fully differential clock input

modes. In the single-ended clock input mode, the IDCK+ input (pin 57) should be connected to the

single-ended clock source and the IDCK– input (pin 56) should be tied to GND. In the differential clock

input mode, the TFP410 uses the crossover point between the IDCK+ and IDCK– signals as the timing

reference for latching incoming data DATA[23:0], DE, HSYNC, & VSYNC. The differential clock input

mode is only available in the low signal swing mode.

DE

2

I

Data enable. As defined in DVI 1.0 specification, the DE signal allows the transmitter to encode pixel

data or control data on any given input clock cycle. During active video (DE = high), the transmitter

encodes pixel data, DATA[23:0]. During the blanking interval (DE = low), the transmitter encodes

HSYNC, VSYNC and CTL[3:1].

HSYNC

VSYNC

4

5

I

Horizontal sync input

Vertical sync input

3

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

Terminal Functions (Continued)

TERMINAL

NAME

I/O

DESCRIPTION

NO.

CTL3/A3/DK3

CTL2/A2/DK2

CTL1/A1/DK1

6

7

8

I

The operation of these three multifunction inputs depends on the settings of the ISEL (pin 13) and

DKEN (pin 35) inputs. All three inputs support 3.3-V CMOS signal levels and contain weak pulldown

resistors so that if left unconnected they default to all low.

2

When the I C bus is disabled (ISEL = low) and the de-skew mode is disabled (DKEN = low), these three

inputs become the control inputs, CTL[3:1], which can be used to send additional information across

the DVI link during the blanking interval (DE = low). The CTL3 input is reserved for HDCP compliant DVI

TXs (TFP510) and the CTL[2:1] inputs are reserved for future use.

2

When the I C bus is disabled (ISEL = low) and the de-skew mode is enabled (DKEN = high), these

three inputs become the de-skew inputs DK[3:1], used to adjust the setup and hold times of the pixel

data inputs DATA[23:0], relative to the clock input IDCK±.

2

When the I C bus is enabled (ISEL = high), these three inputs become the 3 LSBs of the I C slave

address, A[3:1].

Configuration/Programming

MSEN/PO1 11

2

O

Monitor sense/programmable output 1. The operation of this pin depends on whether the I C interface

is enabled or disabled. This pin has an open-drain output and is only 3.3-V tolerant. An external 5-kΩ

pullup resistor connected to V

is required on this pin.

DD

2

When I C is disabled (ISEL = low), a low level indicates a powered on receiver is detected at the

differential outputs. A high level indicates a powered on receiver is not detected. This function is only

valid in dc-coupled systems.

2

When I C is enabled (ISEL = high), this output is programmable through the I C interface (see the I C

register descriptions section).

2 2

I C interface select/I C RESET (active low, asynchronous)

ISEL/RST

13

I

2

If ISEL is high, then the I C interface is active. Default values for the I C registers can be found in the

2

I C register descriptions section.

2

If ISEL is low, then I C is disabled and the chip configuration is specified by the configuration pins

(BSEL, DSEL, EDGE, V ) and state pins (PD, DKEN).

REF

2

If ISEL is brought low and then back high, the I C state machine is reset. The register values are

changed to their default values and are not preserved from before the reset.

2

BSEL/SCL

15

14

9

I

I/O

I

Input bus select/I C clock input. The operation of this pin depends on whether the I C interface is

enabled or disabled. This pin is only 3.3-V tolerant.

2

When I C is disabled (ISEL = low), a high level selects 24-bit input, single-edge input mode. A low level

selects 12-bit input, dual-edge input mode.

2

When I C is enabled (ISEL = high), this pin functions as the I C clock input (see the I C register

descriptions section). In this configuration, this pin has an open-drain output that requires an external

5-kΩ pullup resistor connected to V

DD

.

2

DSEL/SDA

DSEL/I C data. The operation of this pin depends on whether the I C interface is enabled or disabled.

This pin is only 3.3-V tolerant.

2

When I C is disabled (ISEL = low), this pin is used with BSEL and V to select the single-ended or

differential input clock mode (see the universal graphics controller interface modes section).

REF

2

When I C is enabled (ISEL = high), this pin functions as the I C bidirectional data line. In this

configuration, this pin has an open-drain output that requires an external 5-kΩ pullup resistor

connected to V

.

DD

2

EDGE/HTPLG

Edge select/hot plug input. The operation of this pin depends on whether the I C interface is enabled or

disabled. This input is 3.3-V tolerant only.

2

When I C is disabled (ISEL = low), a high level selects the primary latch to occur on the rising edge of

the input clock IDCK+. A low level selects the primary latch to occur on the falling edge of the input clock

IDCK+. This is the case for both single-ended and differential input clock modes.

2

When I C is enabled (ISEL = high), this pin is used to monitor the hot plug detect signal (see the DVI or

VESA P&D and DFP standards). When used for hot-plug detection, this pin requires a series 1-KΩ

resistor.

4

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

Terminal Functions (Continued)

TERMINAL

NAME

DKEN

I/O

DESCRIPTION

NO.

2

35

I

Data de-skew enable. The de-skew function can be enabled either through I C or by this pin when I C

is disabled. When de-skew is enabled, the input clock to data setup/hold time can be adjusted in

discrete trim increments. The amount of trim per increment is defined by t

.

(STEP)

2

When I C is disabled (ISEL = low), a high level enables de-skew with the trim increment determined by

pins DK[3:1] (see the data de-skew section). A low level disables de-skew and the default trim setting is

used.

2

When I C is enabled (ISEL = high), the value of DKEN and the trim increment are selected through I C.

In this configuration, the DKEN pin should be tied to either GND or V to avoid a floating input.

DD

V

3

I

Input reference voltage. Selects the swing range of the digital data inputs (DATA[23:0], DE, HSYNC,

VSYNC, and IDCK±).

REF

For high-swing 3.3-V input signal levels, V

REF

should be tied to V .

DD

For low-swing input signal levels, V

REF

should be set to half of the maximum input voltage level. See

the recommended operating conditions section for the allowable range for V

.

REF

The desired V

REF

voltage level is typically derived using a simple voltage-divider circuit.

2

PD

10

Power down (active low). In the powerdown state, only the digital I/O buffers and I C interface remain

active.

2

When I C is disabled (ISEL = low), a high level selects the normal operating mode. A low level selects

the powerdown mode.

2

When I C is enabled (ISEL = high), the power-down state is selected through I C. In this configuration,

the PD pin should be tied to GND.

2

Note: The default register value for PD is low, so the device is in powerdown mode when I C is first

enabled or after an I C RESET.

2

Reserved

RESERVED

34

In

This pin is reserved and must be tied to GND for normal operation.

DVI Differential Signal Output Pins

TX0+

TX0–

25

24

O

I

Channel 0 DVI differential output pair. TX0± transmits the 8-bit blue pixel data during active video and

HSYNC and VSYNC during the blanking interval.

TX1+

TX1–

28

27

Channel 1 DVI differential output pair. TX1± transmits the 8-bit green pixel data during active video and

CTL[1] during the blanking interval.

TX2+

TX2–

31

30

Channel 2 DVI differential output pair. TX2± transmits the 8-bit red pixel data during active video and

CTL[3:2] during the blanking interval.

TXC+

TXC–

22

21

DVI differential output clock.

TFADJ

19

Full-scale adjust. This pin controls the amplitude of the DVI output voltage swing, determined by the

value of the pullup resistor R

TFADJ

connected to TV .

DD

Power and Ground Pins

DV

PV

1, 12, 33

18

Power Digital power supply. Must be set to 3.3 V nominal.

Power PLL power supply. Must be set to 3.3 V nominal.

DD

TV

23, 29

Power Transmitter differential output driver power supply. Must be set to 3.3 V nominal.

DGND

PGND

TGND

NC

16, 48, 64 Ground Digital ground

17 Ground PLL ground

20, 26, 32 Ground Transmitter differential output driver ground

49

NC

No connection required. If connected, tie high.

5

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage range, DV , PV , TV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V

DD

Input voltage, logic/analog signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V

External DVI single-ended termination resistance, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 Ω to open circuit

T

External TFADJ resistance, R

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 Ω to open circuit

TFADJ

STG

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

Case temperature for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

ESD protection, DVI pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kV Human body model

ESD protection, all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kV Human body model

JEDEC latch-up (EIA/JESD78) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

recommended operating conditions

MIN

3.0

NOM

MAX

3.6

UNIT

V

Supply voltage, V

DD

(DV , PV , TV

DD DD DD

)

3.3

‡

Low-swing mode

High-swing mode

DVI receiver

0.55

V

DDQ

/2

0.9

V

Input reference voltage, V

REF

DV

V

DD

DVI termination supply voltage, AV

(see Note 1)

DVI Single-ended termination resistance, R (see Note 2)

3.14

45

3.3

50

3.46

V

DD

DVI receiver

55

515

70

Ω

T

TFADJ resistor for DVI-compliant V

(SWING)

range, R

(TFADJ)

400 mV = V

(SWING)

= 600 mV

505

0

510

25

Ω

Operating free-air temperature range, T

°C

A

‡

V

defines the maximum low-level input voltage, it is not an actual input voltage.

DDQ

NOTES: 1. AV

is the termination supply voltage of the DVI link.

is the single-ended termination resistance at the receiver end of the DVI link.

DD

T

2.

R

6

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

dc specifications

PARAMETERS

TEST CONDITIONS

MIN

TYP

MAX

UNIT

V

= DV

0.7 V

DD

REF

0.5 V ꢀ V

DD

V

High-level input voltage (CMOS input)

V

IH

ꢀ 0.95 V

V

+ 0.2

REF

V

= DV

0.3V

DD

REF

0.5 V ꢀ V

DD

Low-level input voltage (CMOS input)

V

IL

V

– 0.2

REF

V

High-level digital output voltage (open-drain output)

Low-level digital output voltage (open-drain output)

High-level input current

V

= 3 V, I

OH

= 20 µA

= 4 mA

2.4

V

OH

DD

= 3.6 V, I

OL

0.4

±25

OL

DD

I

V = 3.6 V

I

µA

V

IH

Low-level input current

V = 0

I

±25

IL

V

DVI single-ended high-level output voltage

DVI single-ended low-level output voltage

AV

– 0.01

AV

DD

+ 0.01

H

DD

AV

R

= 3.3 V ± 5%,

= 50 Ω ± 10%,

DD

AV

– 0.6

AV

– 0.4

V

L

DD

†

T

V_SWINGDVI single-ended output swing voltage

400

600 mV

P-P

= 510 Ω ± 1%

TFADJ

V

OFF

DVI single-ended standby/off output voltage

Power-down current (see Note 3)

Normal power supply current

AV

– 0.01

AV

+ 0.01

V

DD

I

200

500

250

µA

PD

‡

I

Worst case pattern

mA

IDD

†

‡

R

is the single-ended termination resistance at the receiver end of the DVI link.

T

Black and white checkerboard pattern, each checker is one pixel wide.

NOTE 3: Assumes all inputs to the transmitter are not toggling.

ac specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

165

40

UNIT

MHz

ns

f

t

IDCK frequency

25

6.06

30%

(IDCK)

(pixel)

(IDCK)

(ijit)

Pixel time period (see Note 4)

IDCK duty cycle

70%

IDCK clock jitter tolerance

2

ns

ps

ns

ps

DVI output rise time (20-80%) (see Note5)

DVI output fall time (20-80%) (see Note 5)

DVI output intra-pair + to – differential skew (see Note 6)

DVI output inter-pair or channel-to-channel skew (see Note 6)

DVI output clock jitter, max. (see Note 7)

75

240

r

f

50

f

= 165 MHz

sk(D)

sk(CC)

ojit

(IDCK)

1.2

150

Single edge

(BSEL=1, DSEL=0,

DKEN=0, EDGE=0)

t

Data, DE, VSYNC, HSYNC setup time to IDCK+ falling edge

Data, DE, VSYNC, HSYNC hold time to IDCK+ falling edge

Data, DE, VSYNC, HSYNC setup time to IDCK+ rising edge

Data, DE, VSYNC, HSYNC hold time to IDCK+ rising edge

1.2

1.3

1.2

1.3

ns

su(IDF)

h(IDF)

Single edge

(BSEL=1, DSEL=0,

DKEN=0, EDGE=1)

su(IDR)

h(IDR)

Dual edge

(BSEL=0, DSEL=1,

DKEN=0)

Data, DE, VSYNC, HSYNC setup time to IDCK+ falling/rising

edge

t

0.9

1

ns

su(ID)

Data, DE, VSYNC, HSYNC hold time to IDCK+ falling/rising

edge

Dual edge (BSEL=0,

DSEL=1, DKEN=0)

t

ns

ps

h(ID)

De-skew trim increment

DKEN = 1

350

(STEP)

NOTES: 4. t

is the pixel time defined as the period of the TXC output clock. The period of IDCK is equal to t

.

(pixel)

5. Rise and fall times are measured as the time between 20% and 80% of signal amplitude.

6. Measured differentially at the 50% crossing point using the IDCK+ input clock as a trigger.

7. Relative to input clock (IDCK).

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

timing diagrams

t

f

r

DVI

Outputs

80% V

20% V

OD

Figure 1. Rise and Fall Time for DVI Outputs

t

h(IDF)

IDCK–

IDCK+

t

h(IDR)

su(IDF)

t

su(IDR)

V

IH

V

IL

DATA[23:0], DE,

HSYNC, VSYNC

Figure 2. Control and Single-Edge-Data Setup/Hold Time to IDCK±

IDCK+

t

h(ID)

su(ID)

h(ID)

t

su(ID)

DATA[23:0], DE,

HSYNC, VSYNC

V

IH

IL

Figure 3. Dual Edge Data Setup/Hold Times to IDCK+

t

sk(D)

TX+

50%

TX–

Figure 4. Analog Output Intra-Pair ± Differential Skew

TXN

50%

t

sk(CC)

50%

TXM

Figure 5. Analog Output Channel-to-Channel Skew

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functional description

The TFP410 is a DVI-compliant digital transmitter that is used in digital host monitor systems to T.M.D.S. encode

and serialize RGB pixel data streams. TFP410 supports resolutions from VGA to UXGA and can be controlled

2

in two ways: 1) configuration and state pins or 2) the programmable I C serial interface (see the terminal

functions section).

The host in a digital display system, usually a PC or consumer electronics device, contains a DVI-compatible

transmitter such as the TI TFP410 that receives 24-bit pixel data along with appropriate control signals. The

TFP410 encodes the signals into a high speed, low voltage, differential serial bit stream optimized for

transmission over a twisted-pair cable to a display device. The display device, usually a flat-panel monitor,

requires a DVI compatible receiver like the TI TFP401 to decode the serial bit stream back to the same 24-bit

pixel data and control signals that originated at the host. This decoded data can then be applied directly to the

flat panel drive circuitry to produce an image on the display. Since the host and display can be separated by

distances up to 5 meters or more, serial transmission of the pixel data is preferred (see the T.M.D.S. pixel data

and control signal encoding, pixel data and control signal encoding, universal graphics contoller interface

voltage signal levels, and universal graphics controller interface clock inputs sections).

The TFP410 integrates a high-speed digital interface, a T.M.D.S. encoder, and three differential T.M.D.S.

drivers. Data is driven to the TFP410 encoder across 12 or 24 data lines, along with differential clock pair and

sync signals. The flexibility of the TFP410 allows for multiple clock and data formats that enhance system

performance.

The TFP410 also has enhanced PLL noise immunity, an enhancement accomplished with on-chip regulators

and bypass capacitors.

2

The TFP410 is versatile and highly programmable to provide maximum flexibility for the user. An I C host

interface is provided to allow enhanced configurations in addition to power-on default settings programmed by

pin-strapping resistors.

2

The TFP410 offers monitor detection through receiver detection, or hot-plug detection when I C is enabled. The

monitor detection feature allows the user enhanced flexibility when attaching to digital displays or receivers (see

terminal functions, hot-plug/unplug, and register descriptions sections).

The TFP410 has a data de-skew feature allowing the users to de-skew the input data with respect to the IDCK±

(see the data de-skew feature section).

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

T.M.D.S. pixel data and control signal encoding

For transition minimized differential signaling (T.M.D.S.), only one of two possible T.M.D.S. characters for a

given pixel is transmitted at a given time. The transmitter keeps a running count of the number of ones and zeros

previously sent and transmits the character that minimizes the number of transitions and approximates a dc

balance of the transmission line. Three T.M.D.S. channels are used to transmit RGB pixel data during the active

video interval (DE = High). These same three channels are also used to transmit HSYNC, VSYNC, and three

user definable control signals, CTL[3:1], during the inactive display or blanking interval (DE = Low). The

following table maps the transmitted output data to the appropriate T.M.D.S. output channel in a DVI-compliant

system.

INPUT PINS

(VALID FOR DE = High)

TRANSMITTED PIXEL DATA

ACTIVE DISPLAY (DE = High)

T.M.D.S. OUTPUT CHANNEL

Channel 2 (TX2 ±)

DATA[23:16]

Red[7:0]

DATA[15:8]

DATA[7:0]

Channel 1 (TX1 ±)

Channel 0 (TX0 ±)

Green[7:0]

Blue[7:0]

INPUT PINS

(VALID FOR DE = Low)

TRANSMITTED CONTROL DATA

BLANKING INTERVAL (DE = Low)

T.M.D.S. OUTPUT CHANNEL

CTL3, CTL2 (see Note 8)

Channel 2 (TX2 ±)

Channel 1 (TX1 ±)

Channel 0 (TX0 ±)

CTL[3:2]

CTL1 (See Note 8)

HSYNC, VSYNC

CTL[1]

HSYNC, VSYNC

NOTE 8: The TFP410 encodes and transfers the CTL[3:1] inputs during the vertical blanking interval. The CTL3 input is reserved for HDCP

compliant DVI TXs and the CTL[2:1] inputs are reserved for future use. When DE = high, CTL and SYNC pins must be held

constant.

universal graphics controller interface voltage signal levels

The universal graphics controller interface can operate in the following two distinct voltage modes:

D

The high-swing mode where standard 3.3-V CMOS signaling levels are used.

The low-swing mode where adjustable 1.1-V to 1.8-V signaling levels are used.

D

To select the high-swing mode, the V

To select the low-swing mode, the V

input pin must be tied to the 3.3-V power supply.

must be 0.55 to 0.95 V.

REF

In the low-swing mode, V

is used to set the midpoint of the adjustable signaling levels. The allowable range

REF

of values for V

is from 0.55 V to 0.9 V. The typical approach is to provide this from off chip by using a simple

REF

voltage-divider circuit. The minimum allowable input signal swing in the low-swing mode is V

±0.2 V. In

REF

low-swing mode, the V

input is common to all differential input receivers.

REF

universal graphics controller interface clock inputs

The universal graphics controller interface of the TFP410 supports both fully differential and single-ended clock

input modes. In the differential clock input mode, the universal graphics controller interface uses the crossover

point between the IDCK+ and IDCK– signals as the timing reference for latching incoming data (DATA[23:0],

DE, HSYNC, and VSYNC). Differential clock inputs provide greater common-mode noise rejection. The

differential clock input mode is only available in the low-swing mode. In the single-ended clock input mode, the

IDCK+ input (Pin 57) should be connected to the single-ended clock source and the IDCK– input (Pin 56) should

be tied to GND.

The universal graphics controller interface of the TFP410 provides selectable 12-bit dual-edge, and 24-bit

single-edge, input clocking modes. In the 12-bit dual-edge , the 12-bit data is latched on each edge of the input

clock. In the 24-bit single-edge mode, the 24-bit data is latched on the rising edge of the input clock when

EDGE = 1 and the falling edge of the input clock when EDGE = 0.

DKEN and DK[3:1] allow the user to compensate the skew between IDCK± and the pixel data and control

signals. See the description of the CTL_3_MODE register for details.

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universal graphics controller interface modes

Table 1 is a tabular representation of the different modes for the universal graphics controller interface. The

12-bit mode is selected when BSEL=0 and the 24-bit mode when BSEL=1. The 12-bit mode uses dual-edge

clocking and the 24-bit mode uses single-edge clocking. The EDGE input is used to control the latching edge

in 24-bit mode, or the primary latching edge in 12-bit mode. When EDGE=1, the data input is latched on the rising

edge of the input clock; and when EDGE=0, the data input is latched on the falling edge of the input clock. A

fully differential input clock is available only in the low-swing mode. Single-ended clocking is not recommended

in the low-swing mode as this decreases common-mode noise rejection.

2

Note that BSEL, DSEL, and EDGE are determined by register CTL_1_MODE when I C is enabled (ISEL=1)

2

and by input pins when I C is disabled (ISEL=0).

Table 1. Universal Graphics Controller Interface Options (Tabular Representation)

V

BSEL

EDGE

DSEL

BUS WIDTH

12-bit

24-bit

12-bit

24-bit

LATCH MODE CLOCK EDGE

CLOCK MODE

Differential (see Note 9 and 10)

Single-ended

REF

0.55 V – 0.9 V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

Dual-edge

Single-edge

Dual-edge

Single-edge

Falling

Rising

Falling

Rising

Falling

Rising

Falling

Rising

Differential (see Note 9 and 10)

Single-ended

Differential (see Note 9 and 11)

Single-ended

Differential (see Note 9 and 11)

Single-ended (see Note 12)

DV

DD

NOTES: 9. The differential clock input mode is only available in the low signal swing mode (i.e., V

10. The TFP410 does not support a 12-bit dual-clock, single-edge input clocking mode.

11. The TFP410 does not support a 24-bit single-clock, dual-edge input clocking mode.

p 0.9 V).

REF

12. In the high-swing mode (V

REF

= DV ), DSEL is a don’t care; therefore, the device is always in the single-ended latch mode.

DD

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universal graphics controller interface modes (continued)

12-Bit, Dual-Edge Input Mode (BSEL = 0)

DE

L = Low Half Pixel

H = High Half Pixel

P

L

P

L

P

H

P

L

P H

1

P

H

P

L

D[11:0]

P L

N

N+1

0

1

N

N–1

DSEL=1

EDGE=0

IDCK+

Single-Ended

Clock Input

Mode

DSEL=1

EDGE=1

DSEL=0

EDGE=0

Differential

Clock Input

Mode (Low

Swing Only)

{(IDCK+) – (IDCK–)}

DSEL=0

EDGE=1

First Latch Edge

Figure 6. Universal Graphics Controller Interface Options for 12-Bit Mode (Graphical Representation)

24-Bit, Single-Edge Input Mode (BSEL = 1)

DE

P

0

P

1

P

N-1

P

N

D[23:0]

DSEL=0

EDGE=0

IDCK+

Single-Ended

Clock Input

Mode

DSEL=0

EDGE=1

IDCK+

DSEL=1

EDGE=0

Differential

Clock Input

Mode (Low

Swing Only)

{(IDCK+) – (IDCK–)}

DSEL=1

EDGE=1

First Latch Edge

Figure 7. Universal Graphics Controller Interface Options for 24-Bit Mode (Graphical Representation)

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12-bit mode data mapping

P0

P1

P2

NAME

P0L

LOW

G0[3]

G0[2]

G0[1]

G0[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

P0H

HIGH

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[7]

G0[6]

G0[5]

G0[4]

P1L

LOW

G1[3]

G1[2]

G1[1]

G1[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

P1H

P2L

LOW

G2[3]

G2[2]

G2[1]

G2[0]

B2[7]

B2[6]

B2[5]

B2[4]

B2[3]

B2[2]

B2[1]

B2[0]

P2H

HIGH

R2[7]

R2[6]

R2[5]

R2[4]

R2[3]

R2[2]

R2[1]

R2[0]

G2[7]

G2[6]

G2[5]

G2[4]

HIGH

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[7]

G1[6]

G1[5]

G1[4]

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

24-bit mode data mapping

PIN NAME

D23

P0

P1

P2

PIN NAME

D11

D10

D9

P0

P1

P2

R0[7]

R0[6]

R0[5]

R0[4]

R0[3]

R0[2]

R0[1]

R0[0]

G0[7]

G0[6]

G0[5]

G0[4]

R1[7]

R1[6]

R1[5]

R1[4]

R1[3]

R1[2]

R1[1]

R1[0]

G1[7]

G1[6]

G1[5]

G1[4]

R2[7]

R2[6]

R2[5]

R2[4]

R2[3]

R2[2]

R2[1]

R2[0]

G2[7]

G2[6]

G2[5]

G2[4]

G0[3]

G0[2]

G0[1]

G0[0]

B0[7]

B0[6]

B0[5]

B0[4]

B0[3]

B0[2]

B0[1]

B0[0]

G1[3]

G1[2]

G1[1]

G1[0]

B1[7]

B1[6]

B1[5]

B1[4]

B1[3]

B1[2]

B1[1]

B1[0]

G2[3]

G2[2]

G2[1]

G2[0]

B2[7]

B2[6]

B2[5]

B2[4]

B2[3]

B2[2]

B2[1]

B2[0]

D22

D21

D20

D8

D19

D7

D18

D6

D17

D5

D16

D4

D15

D3

D14

D2

D13

D1

D12

D0

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data de-skew feature

The de-skew feature allows adjustment of the input setup/hold time. Specifically, the input data DATA[23:0] can

be latched slightly before or after the latching edge of the clock IDCK± depending on the amount of de-skew

desired. When de-skew enable (DKEN) is enabled, the amount of de-skew is programmable by setting the three

bits DK[3:1]. When disabled, a default de-skew setting is used. To allow maximum flexibility and ease of use,

2

DKEN and DK[3:1] are accessed directly through configuration pins when I C is disabled, or through registers

2

of the same name when I C is enabled. When using I C mode, the DKEN pin should be tied to ground to avoid

a floating input.

The input setup/hold time can be varied with respect to the input clock by an amount t

given by the formula:

(CD)

t

= (DK[3:1] – 4) × t

(STEP)

(CD)

Where:

t

is the adjustment increment amount

(STEP)

DK[3:1] is a number from 0 to 7 represented as a 3-bit binary number

is the cumulative de-skew amount

t

(CD)

(DK[3:1]-4) is simply a multiplier in the range {-4,-3,-2,-1, 0, 1, 2, 3} for t

. Therefore, data can be latched

(STEP)

in increments from 4 times the value of t

before the latching edge of the clock to 3 times the value of t

(STEP)

after the latching edge. Note that the input clock is not changed, only the time when data is latched with respect

to the clock.

DATA[23:0]

IDCK±

–t

(CD)

t

–t

(CD)

t

(CD)

DK[3:1]

000

–4 × t

100

0

111

3 × t

000

100

0

111

3 × t

(STEP)

t

–4 × t

(STEP) (STEP)

(CD)

(STEP)

Default Falling

Default Rising

Figure 8. A Graphical Representation of the De-Skew Function

hot plug/unplug (auto connect/disconnect detection)

TFP410 supports hot plug/unplug (auto connect/disconnect detection) for the DVI link. The receiver sense input

(RSEN) bit indicates if a DVI receiver is connected to TXC+ and TXC-. The HTPLG bit reflects the current state

2

of the HTPLG pin connected to the monitor via the DVI connector. When I C is disabled (ISEL=0), the RSEN

2

value is available on the MSEN pin. When I C is enabled, the connection status of the DVI link and HTPLG sense

pins are provided by the CTL_2_MODE register. The MSEL bits of the CTL_2_MODE register can be used to

program the MSEN to output the HTPLG value, the RSEN value, an interrupt, or be disabled.

The source of the interrupt event is selected by TSEL in the CTL_2_MODE register. An interrupt is generated

by a change in status of the selected signal. The interrupt status is indicated in the MDI bit of CTL_2_MODE

and can be output via the MSEN pin. The interrupt continues to be asserted until a 1 is written to the MDI bit,

resetting the bit back to 0. Writing 0 to the MDI bit has no effect.

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2

device configuration and I C RESET description

The TFP410 device configuration can be programmed by several different methods to allow maximum flexibility

for the user’s application. Device configuration is controlled depending on the state of the ISEL/RST pin,

2

configuration pins (BSEL, DSEL, EDGE, V

) and state pins (PD, DKEN). I C bus select and I C RESET

REF

(active low) are shared functions on the ISEL/RST pin, which operates asynchronously.

Holding ISEL/RST low causes the device configuration to be set by the configuration pins (BSEL, DSEL, EDGE,

2

and V

) and state pins (PD, DKEN). The I C bus is disabled.

REF

Holding ISEL/RST high causes the chip configuration to be set based on the configuration bits (BSEL, DSEL,

2

EDGE) and state bits (PD, DKEN) in the I C registers. The I C bus is enabled.

Momentarily bringing ISEL/RST low and then back high while the device is operating in normal or power-down

2

mode will RESET the I C registers to their default values. The device configuration will be changed to the default

power-up state with I C enabled. After power up, the device must be reset. It is suggested that this pin be tied

to the system reset signal, which is low during power up and is then asserted high after all the power supplies

are fully functional.

DE generator

The TFP410 contains a DE generator that can be used to generate an internal DE signal when the original data

2

source does not provide one. There are several I C programmable values that control the DE generator (see

Figure 9). DE_GEN in the DE_CTL register enables this function. When enabled, the DE pin is ignored.

DE_TOP and DE_LIN are line counts used to control the number of lines after VSYNC goes active that DE is

enabled, and the total number of lines that DE remains active, respectively. The polarity of VSYNC must be set

by VS_POL in the DE_CTL register.

DE_DLY and DE_CNT are pixel counts used to control the number of pixels after HSYNC goes active that DE

is enabled, and the total number of pixels that DE remains active, respectively. The polarity of HSYNC must be

set by HS_POL in the DE_CTL register.

The TFP410 also counts the total number of HSYNC pulses between VSYNC pulses, and the total number of

pixels between HSYNC pulses. These values, the total vertical and horizontal resolutions, are available in

V_RES and H_RES, respectively. These values are available at all times, whether or not the DE generator is

enabled.

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DE generator (continued)

Full Vertical Frame

DE_TOP

DE_DLY

DE_CNT

V_RES

DE_LIN

Actual Display Area

H_RES

Figure 9. DE Generator Register Functions

register map

2

The TFP410 is a standard I C slave device. All the registers can be written and read through the I C interface

(unless otherwise specified). The TFP410 slave machine supports only byte read and write cycles. Page mode

2

is not supported. The 8-bit binary address of the I C machine is 0111 A A A X, where A[3:1] are pin

3 2 1

2

programmable or set to 000 by default. The I C base address of the TFP410 is dependent on A[3:1] (pins 6,

7 and 8 respectively) as shown below.

WRITE ADDRESS

(Hex)

READ ADDRESS

(Hex)

A[3:1]

000

001

010

011

100

101

110

111

70

72

74

76

78

7A

7C

7E

71

73

75

77

79

7B

7D

7F

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

register map (continued)

SUB-

ADDRESS

REGISTER

RW

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

VEN_ID

R

00

VEN_ID[7:0]

01

VEN_ID[15:8]

DEV_ID[7:0]

DEV_ID[15:8]

REV_ID[7:0]

Reserved

DEV_ID

R

02

R

03

REV_ID

R

04

RESERVED

CTL_1_MODE

CTL_2_MODE

CTL_3_MODE

CFG

R

05-07

08

RW

R

RSVD

VLOW

TDIS

DK

VEN

HEN

DSEL

TSEL

BSEL

RSEN

CTL

EDGE

PD

MDI

09

MSEL

HTPLG

0A

DKEN

RSVD

0B

CFG

RESERVED

DE_DLY

0C-31

32

Reserved

DE_DLY[7:0]

DE_CTL

33

RSVD

DE_GEN

VS_POL

HS_POL

RSVD

DE_DLY[8]

DE_TOP

34

DE_DLY[6:0]

RESERVED

DE_CNT

35

Reserved

36

DE_CNT[7:0]

37

Reserved

DE_CNT[10:8]

DE_LIN[10:8]

H_RES[10:8]

V_RES[10:8]

DE_LIN

38

DE_LIN[7:0]

H_RES[7:0]

V_RES[7:0]

39

H_RES

3A

R

3B

V_RES

R

3C

R

3D

RESERVED

R

3E–FF

register descriptions

VEN_ID

Sub-Address = 01–00

Read Only

Default = 0x014C

7

6

5

4

3

2

1

0

VEN_ID[7:0]

VEN_ID[15:8]

These read-only registers contain the 16-bit Texas Instruments vendor ID. VEN_ID is hardwired to 0x014C.

DEV_ID

7

Sub-Address = 03–02

Read Only

Default = 0x0410

6

5

4

3

2

1

0

DEV_ID[7:0]

DEV_ID[15:8]

These read-only registers contain the 16-bit device ID for the TFP410. DEV_ID is hardwired to 0x0410.

REV_ID

7

Sub-Address = 04

5

Read Only

Default = 0x00

6

4

3

2

1

0

REV_ID[7:0]

This read-only register contains the revision ID.

17

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

register descriptions (continued)

RESERVED

7

Sub-Address = 07–05

Read Only

Default = 0x641400

6

5

4

3

2

1

0

RESERVED[7:0]

RESERVED[15:8]

CTL_1_MODE

Sub-Address = 08

Read/Write

Default = 0xFE

7

6

5

4

3

1

0

RSVD

TDIS

VEN

HEN

DSEL

BSEL

EDGE

PD

PD: This read/write register contains the power-down mode.

0: Power down (default after RESET)

1: Normal operation

EDGE: This read/write register contains the edge select mode.

0: Input data latches to the falling edge of IDCK+

1: Input data latches to the rising edge of IDCK+

BSEL: This read/write register contains the input bus select mode.

0: 12-bit operation with dual-edge clock

1: 24-bit operation with single-edge clock

DSEL:This read/write register is used in combination with BSEL and V

to select the single-ended or differential

REF

input clock mode. In the high-swing mode, DSEL is a don’t care since IDCK is always single-ended.

HEN: This read/write register contains the horizontal sync enable mode.

0: HSYNC input is transmitted as a fixed low

1: HSYNC input is transmitted in its original state

VEN: This read/write register contains the vertical sync enable mode.

0: VSYNC input is transmitted as a fixed low

1: VSYNC input is transmitted in its original state

TDIS: This read/write register contains the T.M.D.S. disable mode.

0: T.M.D.S. circuitry enable state is determined by PD.

1: T.M.D.S. circuitry is disabled.

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

register descriptions (continued)

CTL_2_MODE

Sub-Address = 09

Read/Write

Default = 0x00

7

6

5

4

3

2

1

0

VLOW

MSEL[3:1]

TSEL

RSEN

HTPLG

MDI

MDI: This read/write register contains the monitor detect interrupt mode.

0: Detected logic level change in detection signal (to clear, write one to this bit)

1: Logic level remains the same

HTPLG: This read only register contains the hot plug detection input logic state.

0: Logic level detected on the EDGE/HTPLG pin (pin 9)

1: High level detected on the EDGE/HTPLG pin (pin 9)

RSEN: This read only register contains the receiver sense input logic state, which is valid only for dc-coupled systems.

0: A powered-on receiver is not detected

1: A powered-on receiver is detected (i.e. connected to the DVI transmitter outputs)

TSEL: This read/write register contains the interrupt generation source select.

0: Interrupt bit (MDI) is generated by monitoring RSEN

1: Interrupt bit (MDI) is generated by monitoring HTPLG

MSEL: This read/write register contains the source select of the monitor sense output pin.

000: Disabled. MSEN output high

001: Outputs the MDI bit (interrupt)

010: Outputs the RSEN bit (receiver detect)

011: Outputs the HTPLG bit (hot plug detect)

VLOW: This read only register indicates the V

input level.

REF

0: This bit is a logic level (0) if the V

1: This bit is a logic level (1) if the V

analog input selects high-swing inputs

analog input selects low-swing inputs

REF

CTL_3_MODE

7

Sub-Address = 0A

5

Read/Write

Default = 0x80

6

4

3

2

1

0

DK[3:1]

DKEN

CTL[3:1]

RSVD

CTL[3:1]:This read/write register contains the values of the three CTL[3:1] bits that are output on the DVI port during

the blanking interval.

DKEN: This read/write register controls the data de-skew enable.

0: Data de-skew is disabled, the values in DK[3:1] are not used

1: Data de-skew is enabled, the de-skew setting is controlled through DK[3:1]

DK[3:1]: This read/write register contains the de-skew setting, each increment adjusts the skew by t

(STEP).

000: Step 1 (minimum setup/maximum hold)

001: Step 2

010: Step 3

011: Step 4

100: Step 5 (default)

101: Step 6

110: Step 7

111: Step 8 (maximum setup/minimum hold)

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ꢀ

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ꢉ

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ꢍ

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

register descriptions (continued)

CFG

Sub-Address = 0B

5

Read Only

7

6

4

3

2

1

0

CFG[7:0] (D[23:16])

This read-only register contains the state of the inputs D[23:16]. These pins can be used to provide the user with

2

selectable configuration data through the I C bus.

RESERVED

7

Sub-Address = 0E–0C

Read/Write

Default = 0x97D0A9

1 0

6

5

4

3

2

RESERVED

These read/write registers have no effect on TFP410 operation.

DE_DLY

7

Sub-Address = 32

5

Read/Write

Default = 0x00

1 0

6

4

3

2

DE_DLY[7:0]

This read/write register defines the number of pixels after HSYNC goes active that DE is generated, when the DE

generator is enabled.

DE_CTL

7

Sub-Address = 33

Read/Write

Default = 0x00

6

5

4

3

2

1

0

Reserved

DE_GEN

VS_POL

HS_POL

Reserved

DE_DLY[8]

DE_DLY[8]: This read/write register contains the top bit of DE_DLY.

HS_POL: This read/write register sets the HSYNC polarity.

0: HSYNC is considered active low.

1: HSYNC is considered active high.

Pixel counts are reset on the HSYNC active edge.

VS_POL: This read/write register sets the VSYNC polarity.

0: VSYNC is considered active low.

1: VSYNC is considered active high.

Line counts are reset on the VSYNC active edge.

DE_GEN: This read/write register enables the internal DE generator.

0: DE generator is disabled. Signal required on DE pin

1: DE generator is enabled. DE pin is ignored.

DE_TOP

7

Sub-Address = 34

5

Read/Write

Default = 0x00

6

4

3

2

1

0

DE_TOP[7:0]

This read/write register defines the number of pixels after VSYNC goes active that DE is generated, when the DE

generator is enabled.

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

register descriptions (continued)

DE_CNT

7

Sub-Address = 37–36

Read/Write

Default = 0x0000

6

5

4

3

2

1

0

DE_CNT[7:0]

Reserved

DE_CNT[10:8]

These read/write registers define the width of the active display, in pixels, when the DE generator is enabled.

DE_LIN

Sub-Address = 39–38

Read/Write

Default = 0x0000

7

6

5

4

3

2

1

0

DE_LIN[7:0]

Reserved

DE_LIN[10:8]

These read/write registers define the height of the active display, in lines, when the DE generator is enabled.

H_RES

Sub-Address = 3B–3A

Read Only

7

6

5

4

3

2

1

0

H_RES[7:0]

Reserved

H_RES[10:8]

These read-only registers return the number of pixels between consecutive HSYNC pulses.

V_RES

Sub-Address = 3D–3C

Read Only

7

6

5

4

3

2

1

0

V_RES[7:0]

Reserved

V_RES[10:8]

These read-only registers return the number of lines between consecutive VSYNC pulses.

2

I C interface

2

The I C interface is used to access the internal TFP410 registers. This two-pin interface consists of the SCL

2

clock line and the SDA serial data line. The basic I C access cycles are shown in Figure 10 and Figure 11.

SDA

SCL

Start Condition (S)

Stop Condition (P)

2

Figure 10. I C Start and Stop Conditions

The basic access write cycle consists of the following:

1. A start condition

2. A slave address cycle

3. A sub-address cycle

4. Any number of data cycles

5. A stop condition

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

2

I C interface (continued)

The basic access read cycle consists of the following:

1. A start condition

2. A slave write address cycle

3. A sub-address cycle

4. A restart condition

5. A slave read address cycle

6. Any number of data cycles

7. A stop condition

The start and stop conditions are shown in Figure 10. The high to low transition of SDA while SCL is high defines

the start condition. The low to high transition of SDA while SCL is high defines the stop condition. Each cycle,

data or address, consists of 8 bits of serial data followed by one acknowledge bit generated by the receiving

device. Thus, each data/address cycle contains 9 bits as shown in Figure 11.

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

1

2

3

4

5

6

7

8

9

SCL

SDA

Slave Address

Sub-Address

2

Data

Stop

Figure 11. I C Access Cycles

2

Following a start condition, each I C device decodes the slave address. The TFP410 responds with an

acknowledge by pulling the SDA line low during the ninth clock cycle if it decodes the address as its address.

During subsequent sub-address and data cycles, the TFP410 responds with acknowledge as shown in

Figure 12. The sub-address is auto-incremented after each data cycle.

The transmitting device must not drive the SDA signal during the acknowledge cycle so that the receiving device

may drive the SDA signal low. The master indicates a not acknowledge condition (/A) by keeping the SDA signal

high just before it asserts the stop condition (P). This sequence terminates a read cycle as shown in Figure 13.

The slave address consists of 7 bits of address along with 1 bit of read/write information (read = 1, write = 0)

as shown below in Figures 11 and 12. For the TFP410, the selectable slave addresses (including the R/W bit)

using A[3:1]are 0x70, 0x72, 0x74, 0x76, 0x78, 0x7A, 0x7C, and 0x7E for write cycles and 0x71, 0x73, 0x75,

0x77, 0x79, 0x7B, 0x7D, and 0x7F for read cycles.

S

Slave Address

W

A

Sub-Address

A

Data

A

Data

A

P

Where:

From Master

From Slave

A

S

Acknowledge

Start condition

P

Stop Condition

2

Figure 12. I C Write Cycle

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

2

I C interface (continued)

S

Slave Address

W

A

Sub-Address

A

Sr

Slave Address

R

A

Data

A

Data

/A

P

Where:

From Master

From Slave

A

S

Acknowledge

Start condition

/A Not acknowledge (SDA high)

P

Stop Condition

R

Read Condition = 1

Write Condition = 0

Sr Restart Condition

W

2

Figure 13. I C Read Cycle

TI PowerPAD 64-pin TQFP package

The TFP410 is available in TI’s thermally enhanced 64-pin TQFP PowerPAD package. The PowerPAD package

is a 10mm × 10mm × 1,0 mm TQFP outline with 0,5 mm lead-pitch. The PowerPAD package has a specially

designed die mount pad that offers improved thermal capability over typical TQFP packages of the same outline.

The TI 64-pin TQFP PowerPAD package offers a backside solder plane that connects directly to the die mount

pad for enhanced thermal conduction. For thermal considerations, soldering the backside of the TFP410 to the

application board is not required since the device power dissipation is well within the package capability when

not soldered.

Soldering the backside of the device to the PCB ground plane is recommended for electrical considerations.

Because the die pad is electrically connected to the chip substrate and hence chip ground, connecting the back

side of the PowerPAD package to a PCG ground plane provides a low-inductance, low-impedance connection

to help improve EMI, ground bounce, and power supply noise performance.

Table 2 contains the thermal properties of the TI 64-pin TQFP PowerPAD package. The 64-pin TQFP

non-PowerPAD package is included only for reference.

Table 2. TI 64-Pin TQFP (10 × 10 × 1,0 mm)/0,5 mm Lead-Pitch

PowerPAD

NOT CONNECTED TO

PCB THERMAL PLANE

WITHOUT

PowerPAD

CONNECTED TO PCB

THERMAL PLANE

(see Note 13)

PARAMETER

Thermal resistance, junction-to-ambient

(see Notes 13 and 14)

R

75.83°C/W

7.80°/W

0.92 W

42.20°C/W

0.38°C/W

1.66 W

21.47°C/W

0.38°C/W

3.26 W

θJA

θJC

D

Thermal resistance, junction-to-case (see Notes 13 and 14)

Power handling capabilities of package (see Notes 13, 14,

and 15)

P

NOTES: 13. Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz. Cu plate PCB thermal plane.

14. Airflow is at 0 LFM (no airflow)

15. Specified at 150°C junction temperature and 80°C ambient temperature.

23

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THERMAL PAD MECHANICAL DATA

PowerPAD™ PLASTIC QUAD FLATPACK

PAP (S-PQFP-G64)

www.ti.com

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SLDS145A – OCTOBER 2001 – REVISED JANUARY 2002

MECHANICAL DATA

PAP (S-PQFP-G64)

PowerPAD PLASTIC QUAD FLATPACK

0,27

M

0,50

48

0,08

0,17

33

49

32

Thermal Pad

(See Note D)

64

17

0,13 NOM

1

16

7,50 TYP

Gage Plane

10,20

SQ

9,80

12,20

SQ

0,25

11,80

0,15

0,05

0°–ā7°

1,05

0,95

0,75

0,45

Seating Plane

0,08

1,20 MAX

4147702/A 01/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.

This pad is electrically and thermally connected to the backside of the die and possibly selected leads.

E. Falls within JEDEC MS-026

PowerPAD is a trademark of Texas Instruments.

24

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IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess

in which TI products or services are used. Information published by TI regarding third–party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

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Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

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Mailing Address:

Texas Instruments

Post Office Box 655303

Dallas, Texas 75265


型号：	TFP410PAPG4
厂家：	TEXAS INSTRUMENTS
描述：	165MHz TMDS DVI 变送器/串行器和 Panelbus™ 集成电路 \| PAP \| 64 \| 0 to 70 驱动接口集成电路显示驱动器驱动程序和接口
文件：	总26页 (文件大小：375K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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