TFP7423PZP [TI]
IC,LCD CONTROLLER,TQFP,100PIN;
| 型号： | TFP7423PZP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC,LCD CONTROLLER,TQFP,100PIN CD |
| 文件： | 总45页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
D
D
D
Support for 6-Bit as Well as 8-Bit Video
Inputs, With On-Chip Dithering
D
D
Support for 2-Level and 3-Level Gate
Drivers
FlatLink Input Interface for Low EMI and
Power
Optional Serial EEPROM for Fine Tuning
Timing During Development
mini-LVDS Intra-Panel Interface Towards
Column Drivers
D
Four Default Timing Sets Provided On-Chip
D
Fail-Safe Circuit Detects Off-Spec
Conditions and Generates Timing Signals
Internally
D
DE-Only Mode of Operation
D
Tolerates Spread Spectrum Clock at the
Input, With SSC Pass-Thru to the Outputs
D
D
PowerPADt TQFP Package
D
D
Support for SSC at the Outputs by Using
External SSC Generation
Operating Voltage Range: 2.7 V to 3.6 V
Flexible Control Outputs With
User-Programmable Timings
–
description
The TFP74X3 is a family of programmable timing controllers for TFT LCD panels supporting resolutions from
XGA up to QXGA. The timing controllers reside on the panel and provide the interface between graphics
controllers and the TFT-LCD system, routing video data and generating timing signals for the panel.
The host interface is FlatLink, which is a proven, low-power, and low-EMI serial interface. mini-LVDS, an
advanced serial intra-panel interface, is used between the TFP74X3 and the column drivers, resulting in
improved EMI performance and lower power consumption.
Control outputs with user-programmable timings are available to control source and gate drivers. Additional
control outputs are available to sequence the panel power supplies. The TFP74X3 can be configured from an
optional external serial EEPROM.
PACKAGE INFORMATION
DEVICE
TFP7423
TFP7433
TFP7443
TFP7453
RESOLUTIONS SUPPORTED
PACKAGE
100-pin TQFP
100-pin TQFP
100-pin TQFP
100-pin TQFP
XGA
SXGA, SXGA+
UXGA
QXGA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
FlatLink and PowerPAD are trademarks of Texas Instruments.
Copyright 2002, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
pin assignment for TFP7423
TQFP PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DVDD
TP1
POL
DGND
T1
FPO1
DGND
DIGCAP
CPV
STVB
STVA
DGND
DIGCAP
RESET
OE
LGND
LLV0+
LLV0–
LCAP
NC
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
NC
LCAP
LLV2+
LLV2–
LVDD
LLV3+
LLV3–
DGND
NC
NC
FPO2
SCL
SDA
LVDD
LLV5+
LLV5–
LGND
NC
CLKIN
DVDD
CLKOUT
DGND
TEST
AGING
DGND
NC
AGND
AVDD
DIGCAP
R-MLVDS
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
pin assignment for TFP7433, TPF7443, and TFP7453
TQFP PACKAGE
(TOP VIEW)
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DVDD
TP1
POL
DGND
T1
FPO1
DGND
DIGCAP
CPV
STVB
STVA
DGND
DIGCAP
RESET
OE
LGND
LLV0+
LLV0–
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
LCAP
LLV1+
LLV1–
LCAP
LLV2+
LLV2–
LVDD
LLV3+
LLV3–
DGND
LLV4+
LLV4–
LVDD
LLV5+
LLV5–
LGND
LLV6+
LLV6–
AGND
AVDD
DIGCAP
R-MLVDS
FPO2
SCL
SDA
CLKIN
DVDD
CLKOUT
DGND
TEST
AGING
DGND
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
block diagram
Data Path
Line
LLV0-6
RLV0-6
LVDS Rx
ERX0-3
mini-LVDS
Transmitters
Merge
and
Align
Buffer
RAM
Dither
Format
Rx PLL
ERXCLK
Output PLL
ORX0-3
LVDS Rx
Rx PLL
TP1, POL
Off-Spec Detect
ORXCLK
STVA, STVB
Timing
Failsafe Generator
Generator
CPV, OE
FPO1, FPO2, T1
AGING Generator
Power-On
Reset
EEPROM
I/F
Clock
Oscillator
Miscellaneous
Control Logic
TEST, AGING
SCL, SDA
system diagram
ERXn, ERXCLK
T1, FPOn
ORXn, ORXCLK
SCL, SDA
Panel
Power Supply
EEPROM
TFP74X3
STVA/B, CPV, FPOn, OE
TP1, POL
RLVn
LLVn
mini-LVDS
Source Driver
mini-LVDS
Source Driver
mini-LVDS
Source Driver
mini-LVDS
Source Driver
Gate
Driver
TFT-LCD Array
Gate
Driver
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Terminal Functions
†
FlatLink inputs
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
TFP7423
TFP74x3
ERX0±...ERX3±
1, 2, 3, 4, 6, 1, 2, 3, 4, 6, Differential inputs Even pixel FlatLink (LVDS) data inputs. This is the port used in
7, 10, 11
7, 10, 11
single-port mode. In dual-port mode, the first pixel is input to this port.
ERXCLK±
8, 9
8, 9
Differential input Clock pair for even-pixel port
ORX0±...ORX3±
13-16, 18,
19, 22, 23
Differential inputs Odd pixel FlatLink (LVDS) data inputs. This port is unused in single-port
mode.
ORXCLK±
21, 20
Differential input Clock pair for odd-pixel port
Not connected
NC
13-16, 18-23
†
All the FlatLink signals have to be terminated with external resistors. See Figure 1 for the data format on the FlatLink ports.
mini-LVDS outputs
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
TFP7423
TFP74x3
LLV0±…LLV6±
49, 48, 43, 42, 49, 48, 46, 45,
40, 39, 34, 33 43, 42, 40, 39,
37, 36, 34, 33,
mini-LVDS outputs. mini-LVDS clock pairs are assigned out of these pins
depending on the mode/resolution.
Drive levels for data pins are set by a resistor on R-MLVDS.
Drive levels for clock pins are set proportional to the data pin drive levels
by a register. Pre-emphasis levels are programmable by registers.
31, 30
Differential
outputs
RLV0±…RLV6±
68, 67, 62, 61, 71, 70, 68, 67,
59, 58, 53, 52 65, 64, 62, 61,
59, 58, 56, 55,
53, 52
NC
30, 31, 36, 37,
45, 46, 55, 56,
64, 65. 70, 71
Not connected
source driver control signals
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
TFP7423 TFP74x3
POL
TP1
78
78
Polaritycontrol. OutputwithreferencetoTIP1.Programmablefordot-inversion
or 2-line inversion by register.
Output
CMOS 4 mA
77
77
Rising edge generated after all the line data is fed out on mini-LVDS pairs.
Width programmable by register.
EEPROM interface
TERMINAL
NO.
TFP7423 TFP74x3
92, 93 92, 93
TYPE
DESCRIPTION
NAME
2
SCL, SDA
Open-drain
I/O
I C interface pins for connecting to external EEPROM. If an EEPROM is not present,
then these pins are used as inputs to select from one of four built-in timing sets.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Terminal Functions (Continued)
power pins
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
TFP7423
12, 24, 29
5, 17, 28
TFP74x3
12, 24, 29
5, 17, 28
AGND
AVDD
DGND
Analog ground
Power supply for the analog circuitry (PLLs).
Digital ground
38, 74, 79, 82,
87, 97, 100
38, 74, 79, 82,
87, 97, 100
DIGCAP
27, 83, 88
27, 83, 88
External capacitor for on-chip 1.8-V regulator for the digital logic. Each
DIGCAP pin requires their own capacitor to DGND.
DVDD
LCAP
72, 73, 75, 76, 95 72, 73, 75, 76, 95
44, 47, 57 44, 47, 57
Power supply for the digital circuitry.
External capacitor for on-chip 1.8-V regulator for the mini-LVDS transmitters.
Each LCAP pin requires their own capacitor to LGND.
LGND
LVDD
32, 50, 51, 63, 69 32, 50, 51, 63, 69
35, 41, 54, 60, 66 35, 41, 54, 60, 66
Ground connection for the mini-LVDS outputs.
Power supply for the mini-LVDS outputs.
gate driver control signals
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
TFP7423 TFP74x3
CPV
84
84
Output
CMOS 4 mA
Shiftclock for gate driver. RisingandfallingedgesprogrammablearoundTP1rising
edge by registers. CPV starting time (after power-on) is programmable by register.
FPO1
FPO2
OE
81
91
90
81
91
90
Output
CMOS 4 mA
Fully programmable general-purpose output. Can be used for OE2, frame pulse, or
dc-dc control. Programmable using registers.
Output
CMOS 4 mA
Output enable for gate driver. Rising and falling edges programmable around TP1
rising edge by registers. Polarity of OE after power on is programmable.
STVA
STVB
86
85
86
85
Output
CMOS 4 mA
Gate strobe. Pulse width, duration, and position with respect to the first line is
programmable using registers.
Figure 2 is an example of typical waveforms that can be generated on the gate driver control outputs. For details
on programming the timings of these signals, see the EEPROM register assignment and definition section.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Terminal Functions (Continued)
miscellaneous
TERMINAL
NO.
TYPE
DESCRIPTION
NAME
AGING
TFP7423 TFP74x3
99
99
Input
In AGING mode, built-in video patterns are fed out on the mini-LVDS outputs.
L = Auto-graying patterns are output
H = Normal operation
Internally pulled up
AGING mode requires external clock to be fed in at the FlatLink ports.
Note: The status of AGING is sensed only at power on.
CLKIN
94
94
Input
Dot-clock fed in after spreading.
If external SSC is not being done, then CLKOUT can be connected to CLKIN
internally by register programming. In that case, CLKOUT buffer is powered
down.
CLKOUT
R-CLK
R-MLVDS
RESET
TEST
96
25
26
89
98
80
96
25
26
89
98
80
Output
CMOS 8 mA
Recovered dot-clock brought out, to feed to external SSC chip.
Analog output
Analog output
External resistor to GND sets internal clock oscillator frequency.
The frequency can be set between 6 MHz and 12 MHz.
External resistor to GND sets drive level (steady state) on mini-LVDS data
pairs. The drive level can be set up to 8 mA.
Schmitt trigger
input
Used for power-on reset with external resistor and capacitor.
Input
Controls whether the TFP74X3 is in normal operation mode. H = test mode, L =
normal operation.
T1
Output
CMOS 4 mA
Can be used to control panel dc-dc converter. Starting time after power on is
programmable with register.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
detailed description
LVDS receiver
The FlatLink receiver has two input ports. ERX0– through ERX3– and ERX0+ through ERX3+ are for the even
(0, 2, 4…) pixels, ORX0– through ORX3– and ORX0+ through ORX3+ are for the odd (1, 3, 5…) pixels. In the
single input port mode, ERX0– through ERX3– and ERX0+ through ERX3+ must be used. Both 18-bit color and
24-bit color are supported.
The FlatLink inputs are SSC tolerant and input SSC is passed on to the outputs to enable a low-EMI total
solution.
NOTE:
The TFP7423 has only one input port.
data path
In the data path, video data from the two input ports are aligned and merged to form a single data stream.
On-chip dithering is available to convert 24-bit color to 18-bit color. The dithering can be turned on or off by the
user through the use of suitable register programming. The formatting sectionaddscontrol bitstothemini-LVDS
data stream and distributes data to different mini-LVDS outputs depending on resolution and mounting options.
For normally-black panels, the video data can be inverted by register programming.
mini-LVDS transmitter
There are 14 pairs of mini-LVDS outputs, arranged as seven pairs for the left half-bus (LLV0– through LLV6–
and LLV0+ through LLV6+) and seven pairs for the right half-bus (RLV0– through RLV6– and RLV0+ through
RLV6+). Data and clock pairs are assigned out of these pins depending on the mode/resolution. Drive levels
for data pairs are set by a resistor on R-MLVDS. The drive levels on the clock pairs can be set proportional to
the data-pair drive levels by register programming. Pre-emphasis with register-programmable levels may be
used on the mini-LVDS signals.
timing generator
The timing generator produces signals for controlling the gate drivers, source drivers, and the panel power
supply. The timing signals can be programmed by configuring the internal registers from an external EEPROM.
Two versatile general-purpose outputs, FPO1 and FPO2, are also available.
fail-safe circuit and clock oscillator
The TFP74X3 detects if the input signal is out of specification. In such a case, the fail-safe circuit generates
timing signals and feeds black data to the panel. This prevents any damage to the panel. The fail-safe circuit
works off an internal clock. The frequency of the internal oscillator is set by a single external resistor.
EEPROM interface
2
This block controls the reading of an external I C EEPROM. If an EEPROM is not connected, the TFP74X3
configuresitselffromoneoffourinternalROMs, dependingonhowtheSCLandSDApinsareconnected(pulled
high/pulled low). In case an external EEPROM is connected, but the read operation is not successful, the
TFP74X3 remains in the reset condition.
miscellaneous control logic
This block configures the internal registers from the EEPROM (if present) and sets up the internal control
depending on the contents of the EEPROM, the status of SCL, SDA, TEST, and AGING.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
power-on reset
A laser-trimmed band-gap voltage sets accurate thresholds for the power-on reset. An external resistor and
capacitor set the reset duration. Internal circuitry in this block also detects glitches in the power supply and
initiates a reset sequence if a glitch in the power supply reduces voltage below safe levels, preventing damage
to the panel.
ERXCLK+
ERXCLK–
ERX0
ER1
EG2
EB3
ER7
ER0
EG1
EB2
ER6
EG0
EB1
DE
ER5
EB0
ER4
EG5
ER3
EG4
EB5
EG7
ER2
EG3
EB4
EG6
ER1
EG2
EB3
ER7
ER0
EG1
EB2
ER6
EG0
EB1
DE
ERX1
ERX2
ERX3
Vsync
EB7
Hsync
EB6
th
th
Present(n ) Cycle
th
(n+1) Cycle
(n–1) Cycle
ORXCLK+
ORXCLK–
ORX0
ORX1
ORX2
ORX3
OR1
OG2
OB3
OR7
OR0
OG1
OB2
OR6
OG0
OB1
OR5
OB0
OR4
OG5
OR3
OG4
OB5
OG7
OR2
OR1
OG2
OB3
OR7
OR0
OG1
OB2
OR6
OG0
OG3
OB4
OG6
OB1
OB7
OB6
Figure 1. FlatLink Data Mapping
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Input DE
First Line
Read In
First Line
Read Out,
TP1 Generated
TP1
OE
CPV
Line Position–1
for STVA/STVB
Line Position 0
for STVA/STVB
Line Position 1
for STVA/STVB
STVA
STVB
In this example, STVA 1 = 00000001, STVA 2 = 01000000
STVB 1 = 00000001, STVB 2 = 10000000
Figure 2. Timing of Normal Operation
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage DVDD, AVDD, LVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4 V
Input voltage: FlatLink pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 2.6 V
mini-LVDS outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.1 V to 2.6 V
DIGCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8 V to 2.6 V
All other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD + 0.5 V
Storage temperature range, T
Lead temperature 1,5 mm from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to the GND terminals unless otherwise noted.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
recommended operating conditions
MIN
TYP
MAX
UNIT
V
Supply voltage, V
DD
DVDD, AVDD, LVDD
Digital inputs, SDA
Digital inputs, SDA
FlatLink inputs
2.7
3.3
3.6
High-level input voltage, V
IH
0.7V
V
DD
Low-level input voltage, V
0.3V
V
IL
Differential input voltage, |V
DD
|
50
600
mV
ID
Common-mode input voltage, V
0.6 + |V
2
|
2 – |V
|
ID
ID
FlatLink inputs
1.2
10
V
IC
mini-LVDS drive level (steady state), I
2
LLV0–7, RLV0–7
8
mA
MHz
MHz
kHz
SS
Internal clock frequency, f
OSC
6
12
Input clock frequency, f
ERXCLK, ORXCLK
ERXCLK, ORXCLK
ERXCLK, ORXCLK
40
112
200
(clk)
Modulating frequency of input clock during SSC, f
MOD
Maximum deviation of input clock frequency during SSC, f
±2%
DEV
Reset duration, t
10
ms
(RST)
TP1 width, T TP
H
1
0
t
(R)
Pullup resistors, R
SCL, SDA
4.7
kΩ
_C
P
Ambient temperature, T
70
A
NOTE: For values of t
and t , see the mini-LVDS outputs and the gate and source driver control outputs sections.
(M)
(R)
electrical characteristics over recommended operating conditions (unless otherwise specified)
TP1, POL, CPV, OE, FPO1, FPO2, STVA, STVB, T1, SCL
PARAMETER
High-level output voltage
Low-level output voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
I
= 4 mA
= 4 mA
2.3
OH
OH
OL
I
0.4
V
OL
CLKOUT
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
= 8 mA
= 8 mA
2.3
OH
OH
0.4
V
OL
OL
CLKIN, TEST
PARAMETER
PARAMETER
PARAMETER
TEST CONDITIONS
= 0 V to V
MIN
MIN
TYP
TYP
TYP
MAX
UNIT
I
Input current
V
IN
10
µA
IN
DD
AGING
TEST CONDITIONS
= 0 V
MAX
UNIT
I
IL
Input current
V
IL
800
µA
RESET (see Figure 3)
TEST CONDITIONS
V = 0 V to V
IN
MIN
MAX
1
UNIT
µA
I
IN
Input current
DD
V
Reset threshold voltage
Hysteresis voltage
2.3
2.4
50
2.5
V
(TH)
hys
V
mV
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
electrical characteristics over recommended operating conditions (unless otherwise specified)
(continued)
V
hys
V
(TH)
DVDD
0 V
Internal Reset
t
t
(RST)
(RST)
Figure 3. Power-On Reset and Glitch Detect
FlatLink ports
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
mV
mV
µA
V
V
Positive-going input threshold voltage
Negative-going input threshold voltage
Input current
V
= 1.2 V
= 1.2 V
50
IT+
IC
IC
V
–50
IT–
I
IN
10
mini-LVDS outputs (see Figure 4)
PARAMETER
Common-mode output voltage
TEST CONDITIONS
MIN
TYP
MAX
1.3
8
UNIT
V
V
1.1
1.2
OCM
I
I
Drive level (steady state)
Peak drive level
mA
SS
(PK)
1
1.6
150
I
SS
R
mini-LVDS termination resistance
50
Ω
(TERM)
NOTE: I
× R
(TERM)
should not exceed 800 mV
(PK)
t
(PE)
I
SS
I
(PK)
I
(PE)
Figure 4. mini-LVDS Outputs
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
ac electrical characteristics over recommended operating conditions (unless otherwise specified)
FlatLink inputs (see Figure 5)
PARAMETER
Sampling window
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ps
t
t
t
650
(SW)
Receiver skew margin
Skew - even to odd port
f
= 82 MHz
540
ps
sk(RSKM)
sk(EO)
(CLK)
–3/7
3/7
t
C
mini-LVDS outputs (see Figure 6)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
t
t
t
Clock high time
Clock low time
t
t
t
t
t
/2
/2
/4
/4
/4
(MH)
(ML)
su
(M)
(M)
(M)
(M)
(M)
Data setup time
Data hold time
h
pre-emphasis duration
Transition time
(PE)
t
500
ps
source driver control outputs (TP1, POL) (see Figure 7)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
Last mini-LVDS data to TP1 delay
TP1 high time
11.5
t
(M)
d(TP)
1
63
t
(HTP)
(R)
(M)
POL setup time to TP1
1
t
su(POL)
gate driver control outputs (CPV, STVA, STVB, OE) (see Figure 9)
PARAMETER
TP1 to CPV rising
TEST CONDITIONS
MIN
–127
–127
–127
–127
TYP
MAX
127
127
127
127
UNIT
t
t
t
t
t
t
t
t
t
r(CPV)
f(CPV)
r(OE)
(R)
(R)
(R)
(R)
TP1 to CPV falling
TP1 to OE rising
TP1 to OE falling
CPV to STVA/B delay
f(OE)
0
d(STV)
T1, CPV, OE at power-on (see Figure 10)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
t
t
t
Reset duration
0.55RC
5.2
(RST)
EEPROM read duration
T1 activation delay time
CPV activation delay time
f
f
f
= 10 MHz
= 10 MHz
= 10 MHz
ms
ms
ms
(READ)
d(T1)
osc
osc
osc
0
0
155
155
d(CPV)
EEPROM interface (see Figure 11)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
µs
f
t
t
t
t
t
t
t
t
t
t
SCL clock frequency
Clock high time
46.5
(SCL)
4.0
4.7
(SCL_H)
(SCL_L)
r(EE)
Clock low time
µs
SCL, SDA rise time
SCL, SDA fall time
Start condition setup time
Start condition hold time
Stop condition setup time
Data setup time
1000
300
ns
ns
f(EE)
4.7
4.0
4.0
250
300
4.7
µs
f
= 7.5 MHz, R = 4.7 kΩ, C = 50 pF
P L
su(STA)
h(STA)
su(STP)
su(DAT)
h(DAT)
(BUF)
osc
µs
µs
ns
Data hold time
ns
Bus free time
µs
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
EEPROM interface (continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
kHz
µs
f
t
t
t
t
t
t
t
t
t
t
SCL clock frequency
Clock high time
62
(SCL)
4.0
4.7
(SCL_H)
(SCL_L)
r(EE)
Clock low time
µs
SCL, SDA rise time
SCL, SDA fall time
Start condition setup time
Start condition hold time
Stop condition setup time
Data setup time
1000
300
ns
ns
f(EE)
3.5
3.7
4.0
250
300
4.7
µs
f
= 10 MHz, R = 4.7 kΩ, C = 50 pF
P L
su(STA)
h(STA)
su(STP)
su(DAT)
h(DAT)
(BUF)
osc
µs
µs
ns
Data hold time
ns
Bus free time
µs
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
ORXCLK+
V
DIFF
= 0 V
t
sk(EO)
t
C
ERXCLK+
ERXn
V
DIFF
= 0 V
V
DIFF
= 0 V
t /7
C
t
t
sk(RSKM)
sk(RSKM)
t
(SW)
Ideal Strobe Position
Figure 5. Input Timing
t
(M)
t
t
(ML)
(MH)
CLK–
80%
20%
mini-LVDS
Clock
CLK+
t
t
t
t
h
su
h
su
t
t
mini-LVDS
Data
t
(PE)
Figure 6. mini-LVDS Output Timing
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
LVCLK+
Last
Data
mini-LVDS Data
Low
t
t
(HTP)
d(TP)
TP1
t
su(POL)
POL
Figure 7. TP1, POL Timings
LVCLK+
First
Data
mini-LVDS Data
Low
High
High
High
Low
Low
10 Clocks High
Figure 8. Reset Pulse Generation on mini-LVDS Data Pair
TPI
t
t
r(CPV)
f(CPV)
CPV
t
d(STV)
t
d(STV)
STVA, STVB
t
f(OE)
t
r(OE)
OE
Figure 9. Gate Driver Control Timings
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
V
TH
DVDD
t
(RST)
RESET
(Internal)
SCL, SDA
OE
t
(READ)
OE Polarity Set From Register 02h Bit
0
t
d(T1)
T1
t
d(CPV)
CPV
Figure 10. Signal Timings at Power On
t
(SCL_ L)
t
(SCL_ H)
t
f(EE)
t
r(EE)
t
h(STA)
t
(BUF)
t
su(STA)
t
su(STP)
Stop
Start
Condition
Condition
t
su(DAT)
t
h(DAT)
Figure 11. EEPROM Interface Timings
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
off-spec conditions
During normal display operation, the fail-safe circuitry in the TFP74X3 constantly checks for a valid input signal
aswellasinputclock. Ifeithertheclockfailsorifthesignalbecomesabnormal, theTFP74X3entersauto-refresh
mode and generates control signals for the source and gate drivers, at the same time feeding all black data on
the mini-LVDS data pairs.
Any input signal not complying with the conditions listed in Table 1 and Table 2 forces the TFP74X3 into the
auto-refresh mode.
Table 1. Specifications of Valid Input Signal in DE-Only Mode
TOTAL NUMBER OF
CLOCKS/LINE
TOTAL NUMBER OF
LINES/FRAME
TOTAL NUMBER OF
LINES/VBLANK
MIN
1088
1344
1464
1664
1664
2128
MAX
MIN
512
MAX
MIN
4
MAX
XGA
2048
2048
4096
4096
4096
4096
1536
1536
2046
2046
2046
2046
SXGA
512
4
SXGA+
UXGA
1024
1024
1024
1024
4
4
UXGA-FPT
QXGA
4
6
Table 2. Specifications of Valid Input Signal in H-Sync, V-Sync Mode
TOTAL CLOCKS/LINE TOTAL Hs/FRAME
TOTAL Hs/VB-bp
TOTAL Hs in VB
MIN
1088
1344
1464
1664
1664
2128
MAX
2048
2048
4096
4096
4096
4096
MIN
512
MAX
1536
1536
2046
2046
2046
2046
MIN
4
MAX
MIN
MAX
XGA
126
126
126
126
SXGA
512
4
SXGA+
UXGA
1024
1024
1024
1024
4
5
UXGA-FPT
QXGA
4
6
126
126
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
EEPROM register assignment and definition
Table 3. EEPROM Register Assignment and Definition
ADDRESS (Hex)
NAME
Auto detect
FUNCTION
00
01
02
03
If 10101010, EEPROM present. Else default mode
Sets resolutions, modes, etc.
Format control 1
Format control 2
Drive levels
Sets 6/8-bit mode, dithering, OE polarity, etc.
Sets pre-emphasis and mini-LVDS clock drive
levels
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
T1 timing
Defines timing on T1 pin
CPV start
CPV start timer value
TP1 width
Programs TP1 width
CPV rising edge
CPV falling edge
OE timing 1
Sets CPV timing with respect to TP1
Sets CPV timing with respect to TP1
Sets OE timing with respect to TP1
Sets OE timing with respect to TP1
Sets STVA width and position in terms of line count
Sets STVA width and position in terms of line count
Sets STVB width and position in terms of line count
Sets STVB width and position in terms of line count
Enables/disables various off-spec checks
Sets FPO1 mode
OE timing 2
STVA control 1
STVA control 2
STVB control 1
STVB control 2
Off-spec checks
FPO1 control
FPO1 start
Sets FPO1 first transition
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
FPO1 stop
Sets FPO1 second transition
FPO2 control
FPO2 start
Sets FPO2 mode
Sets FPO2 first transition
FPO2 stop
Sets FPO2 second transition
Auto-refresh TP1
Auto-refresh CPV low
Auto-refresh CPV high
Auto-refresh OE timing 1
Auto-refresh OE timing 2
Reserved
Sets TP1 width during auto-refresh
Sets duration of CPV low during auto-refresh
Sets duration of CPV high during auto-refresh
Sets OE timing with respect to CPV in auto-refresh
Sets OE timing with respect to CPV in auto-refresh
Reserved
Reserved
Reserved
Check-sum
Check-sum of EEPROM contents from 00h to 1Eh
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Table 4. Format Control 1
[2–0]
000 = XGA
001 = SXGA
010 = SXGA+
011 = UXGA
100 = UXGA FPT
110 = QXGA
[3]
[4]
[5]
0 = single input port, 1 = dual input ports
Should be 0
Video signal inversion.
0 = signal not inverted, 1 = signal inverted
[6]
2-line POL control. 0 = Dot inversion, 1 = 2-line inversion
[7]
TCON position. 0 = top mount, 1 = bottom mount (see Figure 23)
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
10101110
10001010
10001011
10000000
Table 5. Format Control 2
[0]
OE polarity after EEPROM read
[2–1]
Gate driver initialization at power on
00 = 0 frame initialization
01 = 1 frame initialization
10 = 2 frames initialization
11 = 3 frames initialization
[3]
Determines the method of the timing signal generation in Vblank
0 = H-sync is used to generate signals (should be used if the input has a spread spectrum)
1 = Signals are generated internally, using the stored value of the line length
[4]
[5]
[6]
0 = 6-bit input, 1 = 8-bit input
0 = 6-bit output, 1 = 8-bit output
0 = Disable dithering, 1 = enable dithering
If dithering is disabled and input is 8 bits and output is 6 bits, then truncate.
[7]
0 = Short CLKIN to CLKOUT, 1 = CLKIN and CLKOUT not connected
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000001
00000001
00000001
00000011
Table 6. Drive Levels
[2–0]
Sets clock drive levels in terms of data drive levels.
From 1x to 4x in steps of 0.5x
000....Clock drive level = 1 times data drive level
001....Clock drive level = 1.5 times data drive level
......
110....Clock drive level = 4 times data drive level
111....Reserved
[3]
Determines the minimum operating frequency of the input PLL.
0 = Minimum frequency is 4 x f
OSC
1 = Minimum frequency is 2.8 x f
(Recommended value = 1)
OSC
[5–4]
Sets data pre-emphasis drive levels in terms of data steady-state level.
00....No pre-emphasis
01....20% pre-emphasis
10....40% pre-emphasis
11....60% pre-emphasis
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Table 6. Drive Levels (Continued)
[7–6]
Sets clock pre-emphasis drive levels in terms of clock steady-state level.
00....No pre-emphasis
01....20% pre-emphasis
10....40% pre-emphasis
11....60% pre-emphasis
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000000
00000000
00000000
00000000
Table 7. T1 Timing
[4–0]
[7–5]
Sets timing of transition from 0 ms to 155 ms in 5-ms increments
Reserved
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000001
00000001
00000001
00001010
Table 8. CPV Start
[4–0]
[7–5]
Sets start timing of CPV pulses from 0 ms to 155 ms in 5-ms increments
Reserved
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000010
00000011
00000011
00001111
Table 9. TP1 Width
[5–0]
[7–6]
Controls TP1 width from 1 t
to 63 t
(R) (R)
Reserved
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000101
00001000
00001100
00010011
Table 10. CPV Rising Edge
[6–0]
[7]
Sets CPV rising edge with reference to TP1 rising edge from 0 t
0 = transition after TP1 edge, 1 = transition before TP1 edge
to 127 t
.
(R)
(R)
Built-in Default Values
ROM0
ROM1
ROM2
10111000
ROM3
10100101
00000000
00010011
Table 11. CPV Falling Edge
[6–0]
[7]
Sets CPV falling edge with reference to TP1 rising edge from 0 t
to 127 t
(R) (R)
0 = transition after TP1 edge, 1 = transition before TP1 edge
Built-in Default Values
ROM0
ROM1
ROM2
00111101
ROM3
00101111
00101000
10111001
Table 12. OE Timing 1
If OE power-on polarity is high (bit 0 of register 02h = 1), then this register defines the OE falling edge timing.
If OE power-on polarity is low (bit 0 of register 02h = 0), then this register defines the OE rising edge timing.
[6–0]
Sets OE edge with reference to TP1 rising edge from 0 t to 127 t
(R) (R)
[7]
0 = transition after TP1 edge, 1 = transition before TP1 edge
Built-in Default Values
ROM0
ROM1
00001000
ROM2
00000000
ROM3
00000101
00010111
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Table 13. OE Timing 2
If OE power-on polarity is high (bit 0 of register 02h = 1), then this register defines the OE rising edge timing.
If OE power-on polarity is low (bit 0 of register 02h = 0), then this register defines the OE falling edge timing.
[6–0]
Sets OE edge with reference to TP1 rising edge from 0 t to 127 t
(R) (R)
[7]
0 = transition after TP1 edge, 1 = transition before TP1 edge
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
10110100
10101000
10111101
00000110
NOTE: If OE timing 1 and OE timing 2 are programmed to the same value, the OE remains at the value set by register bit 02[0].
Table 14. STVA Control 1 and Control 2
Together, STVA control 1 and STVA control 2 determine the generation of the STVA pulses. The range is from –7 to 8. A 1 in the bit position
enables the generation of a pulse in the corresponding line.
STVA 1 [7–0]
Bit 7 = line number –7, Bit 0 = line number 0
STVA 2 [7–0]
Bit 7 = line number 1, Bit 0 = line number 8
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
1
2
00000111
00000000
00000111
00000000
00000111
00000000
00000001
00000000
Table 15. STVB Control 1 and Control 2
Together, STVB control 1 and STVB control 2 determine the generation of the STVB pulses. The range is from –7 to 8. A 1 in the bit position
enables the generation of a pulse in the corresponding line.
STVB 1 [7–0]
Bit 7 = line number –7, Bit 0 = line number 0
STVB 2 [7–0]
Bit 7 = line number 1, Bit 0 = line number 8
Built-in Default Value
ROM0
ROM1
ROM2
ROM3
1
2
00000001
00000000
00000011
10000000
00000011
10000000
00000000
10000000
Table 16. Off-Spec Check
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Dot clock
0 = ignore loss of dot-clock, 1 = check
0 = ignore H-sync frequency, 1 = check
0 = ignore V-sync frequency, 1 = check
Clocks / line
H-sync / frame
H-sync / VB back porch
H-sync / Vblank
0 = ignore # H-sync in VB back-porch, 1 = check
0 = ignore # H-sync in Vblank , 1 = check
0 = ignore clocks / line, 1 = check
Clocks / line (DE only)
Lines / frame (DE only)
Lines / Vblank (DE only)
0 = ignore lines / frame, 1 = check
0 = ignore lines / Vblank, 1 = check
Built-in Default Values
ROM0
ROM1
00001111
ROM2
ROM3
00010111
00000111
11100001
Table 17. FPO1 Control
[7]
Pulse polarity
[6–5]
00 = Pulse is dc
01 = Pulse per frame
10 = Pulse per line
[4–0]
Starting time of pulse activation after power on, from 0 ms to 155 ms in 5-ms steps.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000010
00000010
00000010
11000000
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Table 18. FPO1 Start
[7–0]
Ignored in dc mode.
In the once per frame mode, starting position of pulse = [7–0] = –127 to 127 with reference to the
first line. ([7] = 1 indicates before first line)
In the once per line mode, similar to OE start programming.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000000
00000000
00000000
00010111
Table 19. FPO1 Stop
[7–0]
Ignored in dc mode
In the once per frame mode, stop position of pulse = [7–0] = –127 to 127 with reference to the last line.
([7] = 1 indicates before last line)
In the once per line mode, similar to OE stop programming.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000000
00000000
00000000
10000011
Table 20. FPO2 Control
[7]
Pulse polarity
[6–5]
00 = Pulse is dc
01 = Pulse per frame
10 = Pulse per line
[4–0]
Starting time of pulse activation after power-on, from 0 ms to 155 ms in 5-ms steps.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000011
00000011
00000011
11000000
Table 21. FPO2 Start
[7–0]
Ignored in dc mode
In the once per frame mode, starting position of pulse = [7–0] = –127 to 127 with reference to the first
line. ([7] = 1 indicates before first line)
In the once per line mode, similar to OE start programming.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000000
00000000
00000000
00010111
Table 22. FPO2 Stop
[7–0]
Ignored in dc mode
In the once per frame mode, stop position of pulse = [7–0] = –127 to 127 with reference to the last line.
([7] = 1 indicates before last line)
In the once per line mode, similar to OE stop programming.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00000000
00000000
00000000
10000011
Table 23. Auto-Refresh TPI Width
[5–0]
[7–6]
Controls TP1 width during auto-refresh from 1 t
to 63 t
osc osc
Reserved
Built-in Default Values
ROM0
ROM1
ROM2
00010000
ROM3
00010000
00010000
00011001
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
Table 24. Auto-Refresh CPV Low
[7–0]
Sets CPV low duration during auto refresh from 5 t
to 255 t
osc osc
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
01011111
01011111
01011111
10010011
Table 25. Auto-Refresh CPV High
[7–0]
Sets CPV high duration during auto-refresh from 2 t
Note: CPV high duration has to be greater than TP1 width
to 255 t
osc osc
Built-in Default Values
ROM0
ROM1
ROM2
00100111
ROM3
00100111
00100111
00111100
Table 26. Auto-Refresh OE Timing 1
If OE power-on polarity is high (bit 0 of register 02h = 1), then this register defines the OE falling edge timing.
If OE power-on polarity is low (bit 0 of register 02h = 0), then this register defines the OE rising edge timing.
[6–0]
[7]
Sets OE edge with reference to CPV rising edge from 0 t to 127 t
osc osc
0 = transition after CPV rising edge, 1 = transition before CPV rising edge.
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
00010100
00010100
00010100
00011111
NOTE: If [7] = 0, then the value in [6–0] should be ≤ the value programmed for CPV auto-refresh high duration (register 18h).
If [7] = 1, then the value in [6–0] should be ≤ value programmed for CPV auto-refresh low duration (register 17h).
Table 27. Auto-Refresh OE Timing 2
If OE power-on polarity is high (bit 0 of register 02h = 1), then this register defines the OE rising edge timing.
If OE power-on polarity is low (bit 0 of register 02h = 0), then this register defines the OE falling edge timing.
[6–0]
Sets OE edge with reference to CPV rising edge from 0 t to 127 t
osc osc
0 = transition after CPV rising edge, 1 = transition before CPV rising edge.
[7]
Built-in Default Values
ROM0
ROM1
ROM2
ROM3
10001000
10001000
10001000
10001100
NOTE: If [7] = 0, then the value in [6–0] should be ≤ the value programmed for CPV auto-refresh high duration (register 18h).
If [7] = 1, then the value in [6–0] should be ≤ value programmed for CPV auto-refresh low duration (register 17h).
If auto-refresh OE timing 1 and auto-refresh timing 2 are programmed to the same value, the OE remains at the value set by register bit
02[0] during auto-refresh.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
register configuration from EEPROM/internal ROMs
The EEPROM should be configured at slave address 1010001.
On power up, the TFP74X3 examines the status of the SCL and SDA pins. If either of these are low, the
TFP74X3 configures itself from the internal ROMs as shown below. If SCL and SDA are both high, the TFP74x3
attempts to configure itself from the external EEPROM. If there is no acknowledgement signal from the
EEPROM, the values from ROM3 are used for configuring the registers.
If there is an acknowledgement signal, but the first byte read is not 10101010, the TFP74X3 pulls all outputs
low and remains in a reset state. If the first byte is 10101010, the TFP74X3 loads its internal registers from the
next 31 bytes of the EEPROM. If the check-sum verification is successful, the TFP74X3 starts operation;
otherwise it turns all outputs off.
SCL
SDA
ROM #
ROM0
ROM1
ROM2
ROM3
0
0
1
1
0
1
0
1
In addition to the internal ROMs, an extra customizable area can be programmed at device manufacture time
based on end-user requirements. Once timings have been optimized using the EEPROM, they can be burnt
in into the device.
NOTE:
Once the device has been customized, the internal ROMs cannot be used.
Conceptually, the scheme looks like:
SCL/SDA
Customized
ROM0
EEPROM Present
ROM1
Configuration Data
ROM2
to Registers
ROM3
Customizable
Area
(External)
EEPROM
Figure 12. EEPROM Scheme
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
EEPROM address configuration
The EEPROM should be configured at slave address 1010001.
V
DD
A
A
A
SCL
SDA
0
1
2
2
I C
To TFP74X3
EEPROM
V
SS
Figure 13. EEPROM Address Configuration
The EEPROM used for configuring the TFP74X3 cannot be shared for any other purpose (e.g. EDID).
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
checksum algorithm
The algorithm used for generating the checksum is:
1. Add the contents of all locations from 00h to 1Eh (binary addition with carry).
2. Invert (complement) the result.
3. Add binary 1 to the result (with carry).
4. Use the lower 8 bits of this as checksum and program it into location 1Fh.
FlatLink inputs
Each of the FlatLink pairs has to be terminated in an external resistor, mounted as close as possible to the
TFP74X3.
The port usage and nominal operating frequencies are specified inTable 28.
Table 28. Port Usage and Nominal Operating Frequencies
SINGLE INPUT PORT
DUAL INPUT PORTS
NA
XGA 60 Hz
SXGA 60 Hz
SXGA+ 60 Hz
UXGA 60 Hz
QXGA 50 Hz
65 MHz
108 MHz
108 MHz
NA
54 MHz
54 MHz
81 MHz
NA
82 MHz
mini-LVDS outputs
Clock and data pairs are internally assigned out of the pool of mini-LVDS outputs based on the resolution and
mode programmed. The assignment for all the modes are shown in mini-LVDS pin assignments in different
modes section.
The nominal frequencies (f ) on the mini-LVDS clock pairs are shown in Table 29.
(M)
Table 29. Nominal Frequencies of the mini-LVDS Clock Pairs
BUS WIDTH
Three pairs
Three pairs
Five pairs
Six pairs
f
: f
f
t
(M)
(M) (CLK)
(M)
XGA 6 bit
XGA 8 bit
3 : 2
2 : 1
9:10
1 : 1
9 : 8
3 : 2
9 : 10
1 : 1
3 : 4
1 : 1
97 MHz
130 MHz
97 MHz
10.26 ns
7.69 ns
10.28 ns
9.26 ns
8.23 ns
6.17 ns
6.86 ns
6.17 ns
8.13 ns
6.10 ns
SXGA 6 bit
SXGA 8 bit
108 MHz
121 MHz
162 MHz
146 MHz
162 MHz
124 MHz
165 MHz
SXGA+ 6 bit
SXGA+ 8 bit
UXGA 6 bit
Four pairs
Four pairs
Five pairs
Six pairs
UXGA 8 bit
QXGA 6 bit (50 Hz)
QXGA 8 bit (50 Hz)
Six pairs
Six pairs
An external resistor connected from R-MLVDS to GND sets the steady-state drive strength on data pairs of the
mini-LVDS outputs. The drive strength as a function of the resistance is shown in Figure 14. The drive strength
on the clock pairs is set by register 03h. This register also sets the pre-emphasis on the data and clock pairs.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
I
SS
vs
R-MLVDS
10
9
8
7
6
5
4
3
2
1
5
10
15
20
25
30
35
40
45
50
R-MLVDS – kΩ
Figure 14. Drive Strength
gate and source driver control outputs
The timing resolution and range for various signals with programmable timings is described in Table 30
(absolute values are at nominal operating frequency).
Table 30. Timing Resolution and Range
MODE
XGA 6
RESOLUTION t
t
(nominal)
(R)
TP1 MAX WIDTH
7.75 µs
CPV, OE EDGES
±15.6 µs
±15.6 µs
±10.44 µs
±9.41 µs
±9.41 µs
±9.41 µs
±6.97 µs
±6.27 µs
±6.2 µs
(R)
12 t
16 t
123.1 ns
123.1 ns
82.2 ns
74.1 ns
74.1 ns
74.1 ns
54.9 ns
49.4 ns
48.8 ns
48.8 ns
(M)
(M)
(M)
(M)
(M)
XGA 8
7.75 µs
SXGA 6
SXGA 8
SXGA+ 6
SXGA+ 8
UXGA 6
UXGA 8
QXGA 6
QXGA 8
8 t
8 t
9 t
5.18 µs
4.67 µs
4.67 µs
12 t
4.67 µs
(M)
(M)
(M)
(M)
(M)
8 t
8 t
6 t
8 t
3.46 µs
3.11 µs
3.07 µs
3.07 µs
±6.2 µs
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
internal oscillator frequency
A resistor connected from the R-CLK pin to GND sets the frequency of the internal oscillator. The frequency
variation with resistance is shown in Figure 15.
OSCILLATION FREQUENCY
vs
R-CLK
13
12
11
10
9
8
7
6
5
20
25
30
35
40
45
R-CLK – kΩ
Figure 15. Frequency Variation With Resistance
FPO1 and FPO2
FPO1 and FPO2 are general-purpose outputs, which can be programmed by the user in a number of different
ways:
D
If programmed in dc mode, FPOn transitions once after power on. For example, if the polarity is
programmed as H, then FPOn goes from low to high after a programmable delay after power-on reset. In
this mode, FPOn can be used to sequence supply rails of the panel’s dc/dc converter.
D
D
When programmed in the once-per-line mode, the programming and behavior is identical to that of the
OE pin.
In the once-per-frame mode, FPOn generates a pulse every frame. The polarity of the pulse is
programmable. The start position of the pulse is programmable around the first line, and the stop position
is programmable with reference to the last line.
Figure 16 shows FPOn programmed with low polarity, start position at –2, and stop position at +1. The exact
definition of position is similar to that of STVA/STVB and the transitions are aligned with the falling edge of CPV.
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
First Active Line
Last Active Line
DE
FPOn
Figure 16. FPOn Programmed With Low Polarity
operation at power on
After powering up, as already described, the device initializes itself, either from the external EEPROM or from
the internal ROM. The device then generates one or more frames for initializing the gate drivers and then locks
on to the incoming frame structure. While the device is attempting to lock, it remains in auto refresh.
This sequence of events depicted in Figure 17.
V
DD
t
(RST)
High or Low
Reset
Set by [02h:B0]
OE
T1
t
t
(READ)
d(1)
Minimum Two Frames
Input DE
(Only Vblank Shown
0/1/2/3 Frames Gate-
Driver Initialization
Normal Frames
Auto-Refresh Frames
t
d(CPV)
CPV
TP1
POL
STVA / STVB
mLVDS CLK
Normal Clock
Oscillator Clock
Reset Signal
mLVDS DATA
Figure 17. Power-Up Sequence
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
auto-refresh operation
The TFP74X3 checks the input signal during operation. If it detects that the input signal is abnormal, it goes into
auto-refresh, duringwhichthedeviceoperatesfromtheinternaloscillator, andwritesall-blackdatatothesource
drivers. Because the internal clock frequency (f
) is low compared to the normal operating frequency, the
OSC
operation during auto-refresh is quite different from normal display operation and the timing signals are
generated in a different way. During auto-refresh, TP1 is generated once in a frame. The frame duration is
governed by f
timing programmability set by t
. The control signals are generated using a separate set of registers, with the resolution of the
OSC
(= 1 / f
).
OSC
OSC
Figure 18 shows what happens when the device enters auto-refresh due to off-spec detection and Figure 19
describes what happens once the input signal is back to normal and the device leaves the auto-refresh mode
of operation and comes back to normal operation. Figure 20 describes the auto-refresh operation in detail.
All-black data is all zeros if B5 of register 01h is programmed as 0, and is all ones if it is programmed as 1.
Off-Spec Condition Detected
OE
Gate-Driver Reset
CPV
Auto-Refresh Frames
TP1
POL
STVA / STVB
mLVDS CLK
All-Black Data
Reset Signal
mLVDS DATA
Figure 18. Normal Operation to Auto-Refresh
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
Input DE
(Only Vblank Shown)
Normal Detected Within This Period
OE
CPV
Auto-Refresh Frame
Normal Frame
Normal Frame
Auto-Refresh Frame
TP1
POL
STVA / STVB
mLVDS CLK
All-Black Data
Reset Signal
mLVDS DATA
Figure 19. Auto-Refresh to Normal Operation
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
OE
CPV
One Auto-Refresh Frame
TP1
POL
STVA / STVB
mLVDS CLK
Reset Signal
All-Black Data
mLVDS DATA
OE
CPV
TP1
POL
In This Example, Programmed for –2, –1, 0
STVA
In this Example, programmed to –1, 0, 1
STVB
mLVDS CLK
Reset Signal
mLVDS DATA
Figure 20. Auto-Refresh Operation Details
aging mode
IftheAGINGpinisheldlowduringpoweron, thedeviceenterstheagingmodeofoperation. ItneedstheFlatLink
clock for operation, but otherwise generates patterns internally. The sequence of patterns is shown in Figure 21.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
Device Powered Up
in Aging Mode
Pattern 1
Pattern 2
Pattern 3
Pattern 4
Pattern 5
240 (200)
Frames
240 (200)
Frames
240 (200)
Frames
240 (200)
Frames
240 (200)
Frames
Pattern 7
Pattern 6
Pattern 1:
Pattern 2:
Pattern 3:
Pattern 4:
Pattern 5:
Pattern 6:
Pattern 7:
Checker Board
Gray Ramp
Red Ramp
Green Ramp
Blue Ramp
All White
60 (50)
60 (50)
Frames
Frames
All Black
Pattern 6
Pattern 7
60 (50)
60 (50)
Numbers in ( ) Are For QXGA Only
Frames
Frames
Pattern 7
Pattern 6
Pattern 7
Pattern 6
60 (50)
60 (50)
60 (50)
60 (50)
Frames
Frames
Frames
Frames
Figure 21. Aging Mode Patterns
normal operation
The way the signals behave during normal operation is shown in Figure 22.
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
st
nd
Line
1
Line
2
Input DE
st
All-Black
1
Line Data
mLVDS
DATA
TP1
POL
Source Driver
Outputs
st
1
Line
–2
–1
0
1
2
3
CPV
STVA
OE
OUT1
OUT2
OUT3
Single on Pulse
OUT = Gate Driver Output
Double on Pulse
Figure 22. Timing of Normal Operation
typical power consumption
Table 31 shows the typical power consumption for devices of the TFP74X3 family, operating at nominal
conditions (room temperature, V = 3 V, mini-LVDS current = 3 mA, no pre-emphasis).
DD
Table 31. Typical Power Consumption
CURRENT IN
DVDD (mA)
CURRENT IN
AVDD (mA)
CURRENT IN
LVDD (mA)
TOTAL
CURRENT (mA)
DEVICE
TFP7423
TFP7433
TFP7443
TFP7453
RESOLUTION
XGA 60 Hz
29.9
56.9
79.3
74.5
10.5
18.5
19.9
19.8
24
30
36
42
64.4
105.4
135.2
136.3
SXGA+ 60 Hz
UXGA 60 Hz
QXGA 50 Hz
definition of top / bottom mounting
Figure 23 shows a TFT–LCD panel assembly in un-folded form with the timing controller top mounted and
bottom mounted.
35
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
APPLICATION INFORMATION
TCON Top Mounted
PCB Panel
Assembly
Source Driver
On COF / TCP
TFT Assembly
TCON Bottom Mounted
Figure 23. Definition of Top / Bottom Mounting
36
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
6-bit and 8-bit XGA
TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
Power down
Power down
000R
001R
Power down
Power down
000G
001G
Power down
Power down
000B
001B
Power down
511R
Power down
511G
Power down
511B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
512R
513R
Power down
Power down
512G
513G
Power down
Power down
512B
513B
Power down
Power down
1023R
Power down
1023G
Power down
1023B
Power down
TCON top
RLV0
RLV1
RLV2
RLV3
RLV4
Clock
RLV5
RLV6
Power down
Power down
512B
513B
Power down
Power down
512G
513G
Power down
Power down
512R
513R
Power down
1023B
Power down
1023G
Power down
1023R
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
000B
001B
Power down
Power down
000G
001G
Power down
Power down
000R
001R
Power down
Power down
511B
Power down
511G
Power down
511R
Power down
37
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
6-bit SXGA
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
001B
000G
002R
Power down
Power down
000B
002G
001R
002B
001G
003R
638G
638B
Power down
639R
639G
639B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
640R
641B
640G
642R
Power down
Power down
640B
642G
641R
642B
641G
643R
1278G
1278B
Power down
1279R
1279G
1279B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
641G
643R
641R
642B
640B
642G
Power down
Power down
640G
642R
640R
641B
1279B
1279G
1279R
Power down
1278B
1278G
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001G
003R
001R
002B
000B
002G
Power down
Power down
000G
002R
000R
001B
639B
639G
639R
Power down
638B
638G
38
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
8-bit SXGA
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
002R
000G
002R
000B
002B
001R
003R
001G
003G
001B
003B
638R
638G
638B
639R
639G
639B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
640R
642R
640G
642G
640B
642B
641R
643R
641G
643G
641G
643G
1278R
1278G
1278B
1279R
1279G
1279B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
641B
643B
641G
643G
641R
643R
640B
642B
640G
642G
640R
642R
1279B
1279G
1279R
1278B
1278G
1278R
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001B
003B
001G
003G
001R
003R
000B
002B
000G
002G
000R
002R
639B
639G
639R
638B
638G
638R
39
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
6-bit and 8-bit SXGA+
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
001G
000G
001B
Power down
Power down
Power down
Power down
000B
002R
001R
002G
698B
699R
Power down
Power down
699G
699B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
700R
701G
700G
701B
Power down
Power down
Power down
Power down
700B
702R
701R
702G
1398B
1399R
Power down
Power down
1399G
1399B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
701R
702G
700B
702R
Power down
Power down
Power down
Power down
700G
701B
700R
701G
1399B
1399G
Power down
Power down
1399R
1398B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001R
002G
000B
002R
Power down
Power down
Power down
Power down
000G
001B
000R
001G
699B
699G
Power down
Power down
699R
698B
40
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
6-bit UXGA
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
001B
000G
002R
Power down
Power down
000B
002G
001R
002B
001G
003R
798B
798B
Power down
799R
799G
799B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
800R
801B
800G
802R
Power down
Power down
800B
802G
801R
802B
801G
803R
1598G
1598B
Power down
1599R
1599G
1599B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
801G
803R
801R
802B
800B
802G
Power down
Power down
800G
802R
800R
801B
1599B
1599G
1599R
Power down
1598B
1598G
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001G
003R
001R
002B
000B
002G
Power down
Power down
000G
002R
000R
001B
799B
799G
799R
Power down
798B
798G
41
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
8-bit UXGA
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
002R
000G
002G
000B
002B
001R
003R
001G
003G
001B
003B
798R
798G
798B
799R
799G
799B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
800R
802R
800G
802G
800B
802B
801R
803R
801G
803G
801B
803B
1598R
1598G
1598B
1599R
1599G
1599B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
801B
803B
801G
803G
801R
803R
800B
802B
800G
802G
800R
802R
1599B
1599G
1599R
1598B
1598G
1598R
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001B
003B
001G
003G
001R
003R
000B
002B
000G
002G
000R
002R
799B
799G
799R
798B
798G
798R
42
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
mini-LVDS PIN ASSIGNMENTS IN DIFFERENT MODES
6-bit and 8-bit QXGA
PCB top, TCON bottom
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
000R
002R
000G
002G
000B
002B
001R
003R
001G
003G
001B
003B
1022R
1022G
1022B
1023R
1023G
1023B
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
1024R
1026R
1024G
1026G
1024B
1026B
1025R
1027R
1025G
1027G
1025B
1027B
2046R
2046G
2046B
2047R
2047G
2047B
PCB top, TCON top
RLV0
RLV1
RLV2
RLV3
Clock
RLV4
RLV5
RLV6
1025B
1027B
1025G
1027G
1025R
1027R
1024B
1026B
1024G
1026G
1024R
1026R
2047B
2047G
2047R
2046B
2046G
2046R
LLV0
LLV1
LLV2
LLV3
LLV4
LLV5
LLV6
Clock
001B
003B
001G
003G
001R
003R
000B
002B
000G
002G
000R
002R
1023B
1023G
1023R
1022B
1022G
1022R
43
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TFP7423, TFP7433, TFP7443, TFP7453
TFT LCD PANEL TIMING CONTROLLER
WITH mini-LVDS AND FlatLink
SLDS140B – APRIL 2001 – REVISED SEPTEMBER 2002
MECHANICAL DATA
PZP (S-PQFP-G100)
PowerPAD PLASTIC QUAD FLATPACK
0,27
0,17
M
0,50
75
0,08
51
50
76
Thermal Pad
(see Note D)
26
100
0,13 NOM
1
25
12,00 TYP
Gage Plane
14,20
SQ
13,80
16,20
SQ
0,25
0,15
15,80
0°–ā7°
0,05
1,05
0,95
0,75
0,45
Seating Plane
0,08
1,20 MAX
4146929/A 04/99
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. The package thermal performance may be enhanced by bonding the thermal pad to an external thermal plane.
This pad is electrically and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MS-026
PowerPAD is a trademark of Texas Instruments.
44
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, maskworkright, orotherTIintellectualpropertyrightrelatingtoanycombination, machine, orprocess
in which TI products or services are used. Information published by TI regarding third–party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Mailing Address:
Texas Instruments
Post Office Box 655303
Dallas, Texas 75265
Copyright 2002, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明