THS1007IDARG4_技术文档

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

ꢃꢄ ꢆ ꢇ ꢈꢀꢉ ꢊ ꢋ ꢌ ꢋ ꢍꢎ ꢏ ꢈꢌ ꢐꢑ ꢀꢉ ꢒꢆ ꢓ ꢂꢐ ꢂ ꢉ ꢂ ꢈꢓ ꢑꢍꢀꢋ ꢌꢔ ꢎꢑ ꢂ ꢂ ꢋꢓ ꢐꢍ ꢈꢌ ꢏ

ꢋ ꢌ ꢋ ꢍ ꢎꢏꢆ ꢀ ꢎ ꢆ ꢕꢈ ꢏ ꢈꢀꢋꢍ ꢖꢎ ꢌ ꢗꢔ ꢘꢀꢔ ꢘ

mode. The THS1007 consists of four analog inputs, which

are sampled simultaneously. These inputs can be selected

individually and configured to single-ended or differential

inputs. Internal reference voltages for the ADC (1.5 V and

3.5 V) are provided. An external reference can also be

chosen to suit the dc accuracy and temperature drift

requirements of the application.

FEATURES

D

Simultaneous Sampling of 4 Single-Ended

Signals or 2 Differential Signals or

Combination of Both

D

Signal-to-Noise and Distortion Ratio: 59 dB

at f = 2 MHz

I

D

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1 LSB

Auto-Scan Mode for 2, 3, or 4 Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 216 mW Max at 5 V

Power Down: 1 mW Max

The THS1007C is characterized for operation from 0°C to

70°C, and the THS1007I is characterized for operation

from –40°C to 85°C.

DA (TSSOP) PACKAGE

(TOP VIEW)

D0

D1

D2

D3

D4

D5

AINP

1

32

31

30

29

28

27

26

25

24

23

22

21

5-V Analog Single Supply Operation

AINM

BINP

2

Internal Voltage References . . . 50 PPM/°C

and ±5% Accuracy

3

BINM

4

D

Glueless DSP Interface

REFIN

REFOUT

REFP

REFM

AGND

5

6

D

Parallel µC/DSP Interface

BV

7

DD

BGND

D6

8

APPLICATIONS

9

D

Radar Applications

D7

AV

10

11

12

13

14

15

16

DD

Communications

D8

D9

CS0

CS1

Control Applications

High-Speed DSP Front-End

Automotive Applications

RA0

20 WR (R/W)

19

18

17

RA1

CONV_CLK

SYNC

RD

DV

DD

DGND

DESCRIPTION

The THS1007 is a CMOS, low-power, 10-bit, 6 MSPS

analog-to-digital converter (ADC). The speed, resolution,

bandwidth, and single-supply operation are suited for

applications in radar, imaging, high-speed acquisition, and

communications. A multistage pipelined architecture with

output error correction logic provides for no missing codes

over the full operating temperature range. Internal control

registers are used to program the ADC into the desired

ORDERING INFORMATION

PACKAGED DEVICE

T

A

TSSOP

(DA)

0°C to 70°C

THS1007CDA

THS1007IDA

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

ꢐꢘ ꢎ ꢕꢑ ꢖ ꢀꢈ ꢎꢌ ꢕ ꢋꢀꢋ ꢙꢚ ꢛꢜ ꢝ ꢞꢟ ꢠꢙꢜꢚ ꢙꢡ ꢢꢣ ꢝ ꢝ ꢤꢚꢠ ꢟꢡ ꢜꢛ ꢥꢣꢦ ꢧꢙꢢ ꢟꢠꢙ ꢜꢚ ꢨꢟ ꢠꢤꢩ ꢐꢝ ꢜꢨꢣ ꢢꢠꢡ

ꢢ ꢜꢚ ꢛꢜꢝ ꢞ ꢠꢜ ꢡ ꢥꢤ ꢢ ꢙ ꢛꢙ ꢢ ꢟ ꢠꢙ ꢜꢚꢡ ꢥ ꢤꢝ ꢠꢪꢤ ꢠꢤ ꢝ ꢞꢡ ꢜꢛ ꢀꢤꢫ ꢟꢡ ꢈꢚꢡ ꢠꢝ ꢣꢞ ꢤꢚꢠ ꢡ ꢡꢠ ꢟꢚꢨ ꢟꢝ ꢨ ꢬ ꢟꢝ ꢝ ꢟ ꢚꢠꢭꢩ

ꢐꢝ ꢜ ꢨꢣꢢ ꢠ ꢙꢜ ꢚ ꢥꢝ ꢜ ꢢ ꢤ ꢡ ꢡ ꢙꢚ ꢮ ꢨꢜ ꢤ ꢡ ꢚꢜꢠ ꢚꢤ ꢢꢤ ꢡꢡ ꢟꢝ ꢙꢧ ꢭ ꢙꢚꢢ ꢧꢣꢨ ꢤ ꢠꢤ ꢡꢠꢙ ꢚꢮ ꢜꢛ ꢟꢧ ꢧ ꢥꢟ ꢝ ꢟꢞ ꢤꢠꢤ ꢝ ꢡꢩ

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

UNITS

DGND to DV

BGND to BV

–0.3 V to 6.5 V

DD

Supply voltage range

DD

AGND to AV

Analog input voltage range

Reference input voltage

Digital input voltage range

AGND –0.3 V to AV

DD

+ 1.5 V

+ 0.3 V

–0.3 V + AGND to AV

DD

–0.3 V to BV /DV

DD DD

Operating virtual junction temperature range, T

–40°C to 150°C

0°C to 70°C

–30°C to 85°C

–65°C to 150°C

260°C

J

THS1007C

THS1007I

Operating free-air temperature range, T

A

Storage temperature range, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

POWER SUPPLY

MIN NOM

MAX

5.25

UNIT

AV

DD

4.75

3

5

Supply voltage

DV

V

DD

BV

ANALOG AND REFERENCE INPUTS

MIN NOM

MAX

UNIT

Analog input voltage in single-ended configuration

V

REFM

REFP

4

Common-mode input voltage V

in differential configuration

(optional)

1

2.5

CM

External reference voltage,V

3.5 AV –1.2

REFP

DD

External reference voltage, V

REFM

(optional)

1.4

1.5

2

Input voltage difference, REFP – REFM

DIGITAL INPUTS

MIN NOM

MAX

UNIT

V

BV

DV

= 3.3 V

2

DD

High-level input voltage, V

IH

= 5.25 V

2.6

V

= 3.3 V

0.6

V

Low-level input voltage, V

IL

= 5.25 V

V

Input CONV_CLK frequency

= 4.75 V to 5.25 V

0.1

80

0

6

MHz

ns

CONV_CLK pulse duration, clock high, t

83

5000

70

w(CONV_CLKH)

CONV_CLK pulse duration, clock low, t

w(CONV_CLKL)

THS1007CDA

THS1007IDA

Operating free-air temperature, T

°C

A

–40

85

2

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, AV

DIGITAL SPECIFICATIONS

PARAMETER

= DV

DD

= 5 V, BV

DD

= 3.3 V, V

REF

= internal (unless otherwise noted)

DD

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital inputs

I

High-level input current

Low-level input current

Input capacitance

DV

DD

= digital inputs

–50

50

µA

pF

IH

Digital input = 0 V

IL

C

5

i

Digital outputs

V

High-level output voltage

Low-level output voltage

I

= –50 µA, BV

= 3.3 V, 5 V

BV –0.5

V

OH

DD

= 50 µA,

BV

0.4

10

V

OL

DD

I

High-impedance-state output current

Output capacitance

CS1 = DGND, CS0 = DV

DD

–10

µA

pF

OZ

C

5

O

L

C

Load capacitance at databus D0 – D9

30

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, AV

DC SPECIFICATIONS

PARAMETER

= DV

DD

= 5 V, BV

DD

= 3.3 V, f = 6 MSPS, V = internal (unless otherwise noted)

REF

DD

s

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

10

Bits

Accuracy

Integral nonlinearity, INL

Differential nonlinearity, DNL

Offset error

±1

LSB

After calibration in single-ended mode

After calibration in differential mode

±5

Offset error

–10

10

Gain error

Analog input

Input capacitance

Input leakage current

Internal voltage reference

15

pF

V

AIN

= V

REFM

to V

REFP

±10

µA

Accuracy, V

3.3

1.4

3.5

1.5

3.7

1.6

V

REFP

REFM

PPM/°

C

Temperature coefficient

50

Reference noise

100

µV

Accuracy, REFOUT

2.475

2.5 2.525

V

Power supply

I

Analog supply current

Digital supply current

Buffer supply current

Power dissipation

AV

= DV

= 5 V, BV

=3.3 V

= 3.3 V

36

0.5

1.5

186

40

3

mA

mW

DDA

DDD

DDB

DD

= DV

DD

4

216

Power dissipation in power down with conversion

clock inactive

AV

= DV

= 5 V, BV

= 3.3 V

0.25

mW

DD

3

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, V

= internal, f = 6 MSPS, f = 2 MHz at –1 dBFS (unless otherwise noted)

s I

REF

AC SPECIFICATIONS, AV

DD

= DV

DD

= 5 V, BV = 3.3 V, C < 30 pF

DD L

PARAMETER

TEST CONDITIONS

Differential mode

MIN

56

TYP

59

MAX

UNIT

dB

Bits

dB

SINAD Signal-to-noise ratio + distortion

Single-ended mode

Differential mode

55

58

59

61

SNR

THD

Signal-to-noise ratio

Single-ended mode

Differential mode

58

60

–64

–63

9.5

9.35

65

–61

–60

Total harmonic distortion

Effective number of bits

Spurious free dynamic range

Single-ended mode

Differential mode

9

8.85

61

ENOB

(SNR)

Single-ended mode

Differential mode

SFDR

Single-ended mode

60

64

Analog Input

Full-power bandwidth with a source impedance of 150 Ω in

differential configuration.

Full scale sinewave, –3 dB

100 mVpp sinewave, –3 dB

96

54

96

54

MHz

Full-power bandwidth with a source impedance of 150 Ω in

single-ended configuration.

Small-signal bandwidth with a source impedance of 150 Ω in

differential configuration.

Small-signal bandwidth with a source impedance of 150 Ω in

single-ended configuration.

TIMING REQUIREMENTS

AV

= DV

DD

= 5 V, BV

DD

= 3.3 V, V = internal, C < 30 pF

REF L

DD

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONV

CLK

t

Latency

5

pipe

t

Setup time, CONV_CLK low before CS valid

Setup time, CS invalid to CONV_CLK low

Delay time, CONV_CLK low to SYNC low

Delay time, CONV_CLK low to SYNC high

10

20

ns

su(CONV_CLKL-READL)

su(READH-CONV_CLKL)

d(CONV_CLKL-SYNCL)

d(CONV_CLKL-SYNCH)

10

4

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TERMINAL

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

Terminal Functions

I/O

DESCRIPTION

NAME

NO.

32

AINP

AINM

BINP

BINM

I

Analog input, single-ended or positive input of differential channel A

Analog input, single-ended or negative input of differential channel A

Analog input, single-ended or positive input of differential channel B

Analog input, single-ended or negative input of differential channel B

Analog supply voltage

31

30

I

29

I

AV

DD

23

24

7

I

AGND

BV

I

Analog ground

I

Digital supply voltage for buffer

DD

BGND

CONV_CLK

CS0

8

I

Digital ground for buffer

15

22

21

16

I

Digital input. This input is the conversion clock input.

Chip select input (active low)

I

CS1

I

Chip select input (active high)

SYNC

O

Synchronizationoutput. This signal indicates in a multichannel operation that data of channel A is brought to

the digital output and can therefore be used for synchronization.

DGND

17

18

I

Digital ground. Ground reference for digital circuitry.

Digital supply voltage

DV

DD

D0 – D9

1–6,

I/O/Z

Digital input, output; D0 = LSB

9–12

RA0

13

14

28

26

I

Digital input. RA0 is used as an address line for the control register. This is required for writing to the control

register 0 and control register 1. See Table 7.

RA1

Digital input. RA1 is used as an address line for the control register. This is required for writing to control

register 0 and control register 1. See Table 7.

REFIN

REFP

Common-modereference input for the analog input channels. It is recommended that this pin be connected to

the reference output REFOUT.

Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed through

control register 0. See Table 8.

REFM

25

I

Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference

voltage. An external reference voltage at this input can be applied. This option can be programmed through

control register 0. See Table 8.

REFOUT

27

19

20

O

I

Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output

requires a capacitor of 10 µF to AGND for filtering and stability.

(1)

RD

The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input,

active low as a data read select from the processor. See timing section.

(1)

WR (R/W)

I

This input is programmable. It functions as a read-write input R/W and can also be configured as a write-only

input WR, which is active low and used as data write select from the processor. In this case, the RD input is

used as a read input from the processor. See timing section.

(1)

The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

5

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

DD

2.5 V

3.5 V

1.5 V

REFP

1.225 V

REF

REFOUT

REFM

REFIN

V

S/H

REFM

AINP

V

REFP

BV

DD

Single

Ended

and/or

Differential

MUX

S/H

+

–

AINM

10 Bit

Pipeline

ADC

10

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

S/H

BINP

BINM

Buffers

RA0

RA1

CONV_CLK

CS0

Logic

and

Control

CS1

Control

Register

BGND

SYNC

RD

WR (R/W)

AGND

DGND

6

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

SIGNAL-TO-NOISE AND DISTORTION

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 1

Figure 2

SIGNAL-TO-NOISE

vs

SPURIOUS FREE DYNAMIC RANGE

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

80

70

60

50

40

30

20

90

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

80

70

60

50

40

30

20

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 3

Figure 4

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

SIGNAL-TO-NOISE AND DISTORTION

vs

SAMPLING FREQUENCY (DIFFERENTIAL)

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

IN

DD

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 5

Figure 6

SIGNAL-TO-NOISE

vs

SPURIOUS FREE DYNAMIC RANGE

vs

SAMPLING FREQUENCY (DIFFERENTIAL)

80

70

60

50

40

30

20

100

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

AV

f

IN

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

IN

90

80

70

60

50

40

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 7

Figure 8

8

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

INPUT FREQUENCY (SINGLE-ENDED)

SIGNAL-TO-NOISE AND DISTORTION

vs

INPUT FREQUENCY (SINGLE-ENDED)

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –1 dB FS

DD

s

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –1 dB FS

DD

s

DD

0

1

2

3

4

0

1

2

3

4

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 9

Figure 10

SIGNAL-TO-NOISE

vs

SPURIOUS FREE DYNAMIC RANGE

vs

INPUT FREQUENCY (SINGLE-ENDED)

80

75

70

65

60

55

50

45

40

35

30

25

20

90

80

70

60

50

40

30

20

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –1 dB FS

DD

s

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –1 dB FS

DD

s

DD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 11

Figure 12

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

SIGNAL-TO-NOISE AND DISTORTION

TOTAL HARMONIC DISTORTION

vs

INPUT FREQUENCY (DIFFERENTIAL)

vs

INPUT FREQUENCY (DIFFERENTIAL)

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

AV

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

DD

AV

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

DD

f

s

f

s

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 14

Figure 13

SPURIOUS FREE DYNAMIC RANGE

vs

SIGNAL-TO-NOISE

vs

INPUT FREQUENCY (DIFFERENTIAL)

90

80

70

60

50

40

30

20

80

70

60

50

40

30

20

AV

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

DD

f

s

AV

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

DD

f

s

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 16

Figure 15

10

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

SAMPLING FREQUENCY (DIFFERENTIAL)

12

11

10

9

12

11

10

9

AV

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

AV

f

in

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –0.5 dB FS

DD

f

in

8

7

6

0

1

2

3

4

5

6

7

0

1

2

3

4

5

6

7

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 18

Figure 17

EFFECTIVE NUMBER OF BITS

vs

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY (SINGLE-ENDED)

INPUT FREQUENCY (DIFFERENTIAL)

12

11

10

9

12

11

10

9

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

s

AV

f

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –1 dB FS

DD

s

DD

8

7

6

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 20

Figure 19

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

INTEGRAL NONLINEARITY

vs

TEMPERATURE

0.70

0.68

0.66

0.64

0.62

0.60

0.58

0.56

0.54

0.52

0.50

0.70

0.68

0.66

0.64

0.62

0.60

0.58

0.56

0.54

0.52

0.50

AV

BV

= 5 V,

= DV

DD

= 3.3 V,

Differential Mode,

Internal Reference,

Internal Oscillator

AV

BV

= 5 V,

= DV

DD

= 3.3 V,

Differential Mode,

Internal Reference,

Internal Oscillator

–40

–15

10

35

60

85

–40

–15

10

35

60

85

T

A

– Temperature – °C

T

A

– Temperature – °C

Figure 21

Figure 22

GAIN

vs

INPUT FREQUENCY (SINGLE-ENDED)

5

0

AV

= 5 V, DV

= BV

= 3 V,

= 6 MSPS, AIN = –0.5 dB FS

DD

f

s

–5

–10

–15

–20

–25

–30

0

10 20 30 40 50 60 70 80 90 100 110 120

f – Input Frequency – MHz

i

Figure 23

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM (4096 POINTS)

(SINGLE-ENDED)

vs

FREQUENCY

0

–20

–40

–60

–80

AV

DD

= 5 V, DV

DD

= BV = 3 V,

DD

f

s

= 6 MSPS, AIN = –0.5 dB FS, f = 1 MHz

in

–100

–120

–140

0.0

0.5

1.0

1.5

2.0

2.5

3.0

f – Frequency – MHz

Figure 24

FAST FOURIER TRANSFORM (4096 POINTS)

(DIFFERENTIAL)

vs

FREQUENCY

0

AV

DD

= 5 V, DV

DD

= BV = 3 V,

DD

–20

–40

f

s

= 6 MSPS, AIN = –0.5 dB FS, f = 1 MHz

in

–60

–80

–100

–120

–140

0.0

0.5

1.0

1.5

2.0

2.5

3.0

f – Frequency – MHz

Figure 25

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

ADC CODE

1.0

0.8

AV

= 5 V,

= 3 V,

= 8 MSPS

DD

DV

= BV

DD

f

DD

0.6

s

0.4

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

256

512

768

1024

ADC Code

Figure 26

INTEGRAL NONLINEARITY

vs

ADC CODE

1.0

0.8

0.6

AV

= 5 V,

= 3 V,

= 8 MSPS

DD

DV

= BV

DD

f

DD

0.4

s

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

256

512

768

1024

ADC Code

Figure 27

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

DETAILED DESCRIPTION

Reference Voltage

The THS1007 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V

and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP

and REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish

the upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

Analog Inputs

The THS1007 consists of 4 analog inputs, which are sampled simultaneously. These inputs can be selected

individually and configured as single-ended or differential inputs. The desired analog input channel can be

programmed.

Converter

The THS1007 uses a 10-bit pipelined multistaged architecture, which achieves a high sample rate with low

power consumption. The THS1007 distributes the conversion over several smaller ADC sub-blocks, refining

the conversion with progressively higher accuracy as the device passes the results from stage to stage. This

distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.

A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input

sample while the second through the eighth stages operate on the seven preceding samples.

Conversion Clock

An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new

conversion is started with every falling edge of the applied clock signal. The conversion values are available

at the output with a latency of 5 clock cycles.

SYNC

In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK

after a SYNC reset. This is due to the latency of the pipeline architecture of the THS1007.

Sampling Rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels.

Table 1 shows the maximum conversion rate for different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

CHANNEL CONFIGURATION

1 single-ended channel

1

2

3

4

1

2

3

6 MSPS

3 MSPS

2 MSPS

1.5 MSPS

6 MSPS

3 MSPS

2 MSPS

2 single-ended channels

3 single-ended channels

4 single-ended channels

1 differential channel

2 differential channels

1 single-ended and 1 differential channel

2 single-ended and 1 differential channels

The maximum conversion rate per channel, fc, is given by:

6 MSPS

# channels

fc +

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Conversion

During conversion, the ADC operates with a free running external clock applied to the input CONV_CLK. With

every falling edge of the CONV_CLK signal a new converted value is available to the data bus with the

corresponding read signal. The THS1007 allows up to four analog inputs to be selected. The inputs can be

configured as two differential channels, four single-ended channels or a combination of differential and

signle-ended.

To provide the system with channel information, the THS1007 utilizes an active low SYNC signal. When

operated in a multichannel configuration, the SYNC signal is active low when data from channel 1 is available

to the databus. When operated in signle-channel mode (single-ended or differential operation) the SYNC signal

is disabled.

Figure 28 shows the timing of the conversion, when one analog input channel is selected. The maximum

throughput rate is 6 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since

this information is not necessary. There is a certain timing relationship required for the read signal with respect

to the conversion clock. This can be seen in Figure 28 and the timing specifications. A more detailed description

of the timing is given in the timing section and signal description of the THS1007.

Sample N+1

Channel 1

Sample N

Channel 1

Sample N+2

Channel 1

Sample N+3

Channel 1

Sample N+4

Channel 1

Sample N+5

Channel 1

Sample N+6

Channel 1

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(READH-CONV_CLKL)

su(CONV_CLKL-READL)

†

READ

Data N–4

Channel 1

Data N–3

Channel 1

Data N+1

Channel 1

Data N–2

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+2

Channel 1

†

READ is the logical combination from CS0, CS1 and RD

Figure 28. Conversion Timing in 1-Channel Operation

Figure 29 shows the conversion timing when two analog input channels are selected. The maximum throughput

rate per channel is 3 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted

data is available to the data bus. The SYNC pulse is active low when the data of channel one is available to

the databus. The data of channel one is followed by the data of channel two before the SYNC signal is active

low again.

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

Sample N+1

Channel 1, 2

Sample N

Channel 1, 2

Sample N+3

Channel 1, 2

Sample N+2

Channel 1, 2

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(CONV_CLKL-READL)

t

su(READH-CONV_CLKL)

†

READ

t

d(CONV_CLKL-SYNCL)

d(CONV_CLKL-SYNCH)

SYNC

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

Data N–1

Channel 2

Data N

Channel 1

Data N+1

Channel 1

Data N

Channel 2

†

READ is the logical combination from CS0, CS1 and RD

Figure 29. Conversion Timing in 2-Channel Operation

Figure 30 shows the conversion timing when three analog input channels are selected. The maximum

throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which

order the converted data is available to the data bus. The SYNC signal is active low when the data of channel

one is available to the data bus. The data of channel one is followed by the data of channel two and channel

three before channel one is again available and the SYNC signal is active low.

Sample N

Sample N+1

Sample N+2

Channel 1, 2, 3

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(READH-CONV_CLKL)

t

su(CONV_CLKL-READL)

†

READ

t

d(CONV_CLKL-SYNCH)

t

d(CONV_CLKL-SYNCL)

SYNC

Data N

Channel 2

Data N–2

Channel 3

Data N–1

Channel 1

Data N–1

Channel 2

Data N–1

Channel 3

Data N

Channel 1

Data N

Channel 3

†

READ is the logical combination from CS0, CS1 and RD

Figure 30. Conversion Timing in 3-Channel Operation

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

Figure 31 shows the conversion timing when four analog input channels are selected. The maximum throughput

rate per channel is 1.5 MSPS in this mode. The data flow in the bottom of the figure shows in which order the

converted data is available to the databus. The SYNC signal is active low when the data of channel one is

available to the data bus. The data of channel one is followed by the data of channel two, the data of channel

three and the data of channel four before channel one is again available to the databus and SYNC is active low.

Sample N

Sample N+1

Channel 1, 2, 3, 4

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(READH-CONV_CLKL)

t

su(CONV_CLKL-READL)

†

READ

t

su(CONV_CLKL-SYNCH)

t

su(CONV_CLKL-SYNCL)

SYNC

Data N

Channel 2

Data N–1

Channel 1

Data N–1

Channel 2

Data N–1

Channel 3

Data N–1

Channel 4

Data N

Channel 1

Data N

Channel 3

†

READ is the logical combination from CS0, CS1 and RD

Figure 31. Timing of Continuous Conversion Mode (4-channel operation)

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

DIGITAL OUTPUT DATA FORMAT

The digital output data format of the THS1007 can either be in binary format or in twos complement format. The

following tables list the digital outputs for the analog input voltages.

Table 2. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE

AIN = V

DIGITAL OUTPUT CODE

3FFh

200h

000h

REFP

AIN = (V

+ V )/2

REFM

REFP

AIN = V

REFM

Table 3. Two’s Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE

AIN = V

DIGITAL OUTPUT CODE

1FFh

000h

200h

REFP

AIN = (V

+ V )/2

REFM

REFP

AIN = V

REFM

Table 4. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE

= AINP – AINM

DIGITAL OUTPUT CODE

V

in

= V

V

REF

– V

REFP REFM

V

= V

3FFh

200h

000h

in

REF

V

in

= 0

V

in

= –V

REF

Table 5. Two’s Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

V

= AINP – AINM

– V

REFP REFM

in

= V

V

REF

V

= V

1FFh

000h

200h

in

REF

V

in

= 0

V

in

= –V

REF

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

ADC CONTROL REGISTER

The THS1007 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the

desired mode. The bit definitions of both control registers are shown in 6.

Table 6. Bit Definitions of Control Register CR0 and CR1

REG

CR0

CR1

BIT 9

TEST1

BIT 8

TEST0

OFFSET

BIT 7

SCAN

BIN/2’s

BIT 6

DIFF1

R/W

BIT 5

DIFF0

RES

BIT 4

CHSEL1 CHSEL0

RES RES

BIT 3

BIT 2

PD

BIT 1

RES

BIT 0

VREF

RESERVED

RES

SRST

RESET

Writing to Control Register 0 and Control Register 1

The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control

register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and

RA1. During this write process, the data bits D0 to D9 contain the desired control register value. Table 7 shows

the addressing of each control register.

Table 7. Control Register Addressing

D0 – D9

RA0

RA1

Addressed Control Register

Control register 0

Desired register value

0

1

0

1

0

1

Control register 1

Reserved for future

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

INITIALIZATION OF THE THS1007

The initialization of the THS1007 should be done according to the configuration flow shown in Figure 32.

Start

No

Use Default

Values?

Yes

Write 0x401 to

THS1007

Write 0x401 to

THS1007

(Set Reset Bit in CR1)

Clear RESET By

Writing 0x400 to

CR1

Clear RESET By

Writing 0x400 to

CR1

Write the User

Configuration to

CR0

Write the User

Configuration to

CR1 ( Must Exclude

RESET)

Continue

Figure 32. THS1007 Configuration Flow

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ADC CONTROL REGISTERS

Control Register 0, Write Only (see Table 7)

BIT 11 BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

TEST1

TEST0

SCAN

DIFF1

DIFF0

CHSEL1

CHSEL0

PD

RES

VREF

Table 8. Control Register 0 Bit Functions

RESET

VALUE

BITS

NAME

FUNCTION

0

VREF

Vref select:

Bit 0 = 0 → The internal reference is selected

Bit 0 = 1 → The external reference voltage is used for the ADC

1

2

0

RES

PD

RESERVED

Power down.

Bit 2 = 0 → The ADC is active

Bit 2 = 1 → Power down

The reading and writing to and from the digital outputs is possible during power down.

3, 4

5,6

7

0,0

1,0

0

CHSEL0,

CHSEL1

Channel select

Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9.

DIFF0, DIFF1 Number of differential channels

Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9.

SCAN

Autoscan enable

Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9.

8,9

0,0

TEST0,

TEST1

Test input enable

Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This

feedback allows the check of all hardware connections and the ADC operation.

Refer to Table 10 for selection of the three different test voltages.

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

ANALOG INPUT CHANNEL SELECTION

The analog input channels of the THS1007 can be selected via bits 3 to 7 of control register 0. One single

channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the

selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more

than one input channel is selected. Table 10 shows the possible selections.

Table 9. Analog Input Channel Configurations

BIT 7

SCAN

BIT 6

DIFF1

BIT 5

BIT 4

BIT 3

DESCRIPTION OF THE SELECTED INPUTS

Analog input AINP (single ended)

DIFF0 CHSEL1 CHSEL0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Analog input AINM (single ended)

Analog input BINP (single ended)

Analog input BINM (single ended)

Differential channel (AINP–AINM)

Differential channel (BINP–BINM)

Autoscan two single ended channels: AINP, AINM, AINP, …

Autoscan three single ended channels: AINP, AINM, BINP, AINP, …

Autoscan four single ended channels: AINP, AINM, BINP, BINM, AINP, …

Autoscan one differential channel and one single ended channel AINP,

(BINP–BINM), AINP, (BINP–BINM), …

1

0

1

0

1

0

1

0

1

Autoscan one differential channel and two single ended channel AINP,

AINM, (BINP–BINM), AINP, …

Autoscan two differential channels (AINP–AINM), (BINP–BINM),

(AINP–AINM), …

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Reserved

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Test Mode

The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown

in Table 10.

Table 10. Test Mode

BIT 9

TEST1 TEST0

BIT 8

OUTPUT RESULT

0

1

0

1

0

1

Normal mode

V

REFP

)+(V

((V

))/2

REFP

REFM

V

REFM

Three different options can be selected. This feature allows support testing of hardware connections between

the ADC and the processor.

Control Register 1, Write Only (see Table 7)

BIT 11 BIT10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

1

RESERVED

OFFSET

BIN/2s

R/W

RES

SRST

RESET

Table 11. Control Register 1 Bit Functions

RESET

VALUE

BITS

NAME

FUNCTION

0

RESET

Reset

Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.

To bring the device out of RESET, a 0 has to be written into this bit.

1

0

SRST

Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the

configurationcycle.

2, 3

4

0,0

1

RES

R/W

Reserved

5

1

Reserved

6

0

R/W, RD/WR selection

Bit 6 of control register 1 controls the function of the inputs RD and WR. Whenbit 6 in control register 1 is set to

1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with

R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR

becomes a write input.

7

8

0

BIN/2s

Complement select

If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of

control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.

OFFSET

Offset cancellation mode

Bit 8 = 0 → normal conversion mode

Bit 8 = 1 → offset calibration mode

If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-

sion. The conversion result is stored in an offset register and subtracted from all conversions in order to

reduce the offset error.

9

0

RESERVED Always write 0.

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

TIMING AND SIGNAL DESCRIPTION OF THE THS1007

The reading from the THS1007 and writing to the THS1007 is performed by using the chip select inputs (CS0,

CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input

(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal

(R/W). The two chip select inputs can be used to interface easily to a processor.

Reading from the THS1007 takes place by an internal RD signal, which is generated from the logical

int

combination of the external signals CS0, CS1 and RD (see Figure 33). This signal is then used to strobe the

words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes

RD active while the write input (WR) is inactive. The first of those external signals switching to its inactive state

int

deactivates RD again.

int

Writing to the THS1007 takes place by an internal WR signal, which is generated from the logical combination

int

of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and

1. The last external signal (either CS0, CS1 or WR) to become valid switches WR active while the read input

int

(RD) is inactive. The first of those external signals going to its inactive state deactivates WR again.

int

RD

CS0

CS1

RD

WR

Control/Data

Registers

Data Bits

Figure 33. Logical Combination of CS0, CS1, RD, and WR

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Read Timing (using RD, RD-controlled)

Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input

RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external

signal of CS0, CS1, and RD which becomes valid.

CS0

CS1

t

su(CS)

h(CS)

WR

RD

t

w(RD)

10%

t

a

t

h

90%

D(0–9)

t

d(CSDAV)

90%

DATA_AV

Figure 34. Read Timing Diagram Using RD (RD-controlled)

Read Timing Parameter (RD-controlled)

PARAMETER

Setup time, RD low to last CS valid

MIN

0

TYP

MAX

10

UNIT

ns

t

su(CS)

Access time, last CS valid to data valid

Delay time, last CS valid to DATA_AV inactive

Hold time, first CS invalid to data invalid

Hold time, RD change to first CS invalid

Pulse duration, RD active

0

ns

a

12

ns

d(CSDAV)

h

0

5

ns

h(CS)

w(RD)

10

ns

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

Write Timing (using WR, WR-controlled)

Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The

input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last

external signal of CS0, CS1, and WR which becomes valid.

CS0

CS1

t

h(CS)

su(CS)

t

w(WR)

WR

RD

10%

t

su

t

h

90%

D(0–9)

DATA_AV

Figure 35. Write Timing Diagram Using WR (WR-controlled)

Write Timing Parameter Using WR (WR-controlled)

PARAMETER

MIN

0

TYP

MAX

UNIT

ns

t

Setup time, CS stable to last WR valid

Setup time, data valid to first WR invalid

Hold time, WR invalid to data invalid

Hold time, WR invalid to CS change

Pulse duration, WR active

su(CS)

5

ns

su

2

ns

h

5

ns

h(CS)

w(WR)

10

ns

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Read Timing (using R/W, CS0-controlled)

Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write

input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled

because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data

should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 36.

t

su(CS0H–CONV_CLKL)

t

su(CONV_CLKL–CS0L)

CONV_CLK

10%

t

90%

w(CS)

CS0

CS1

10%

t

h(R/W)

t

su(R/W)

90%

R/W

RD

t

a

h

90%

D(O–11)

Figure 36. Read Timing Diagram Using R/W (CS0-controlled)

†

Read Timing Parameter (CS0-controlled)

PARAMETER

MIN

10

20

0

TYP

MAX

UNIT

ns

t

Setup time, CONV_CLK low before CS valid

Setup time, CS invalid to CONV_CLK low

Setup time, R/W high to last CS valid

Access time, last CS valid to data valid

Hold time, first CS invalid to data invalid

Hold time, first external CS invalid to R/W change

Pulse duration, CS active

su(CONV_CLKL–CSOL)

ns

su(CSOH–CONV_CLKL)

ns

su(R/W)

a

0

10

5

ns

0

ns

h

5

ns

h(R/W)

w(CS)

10

ns

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

Write Timing (using R/W, CS0-controlled)

Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write

input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled

because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1007

can be performed irrespective of the conversion clock signal CONV_CLK.

t

w(CS)

90%

CS0

CS1

10%

t

su(R/W)

t

h(R/W)

R/W

RD

10%

t

su

t

h

90%

D(0–11)

Figure 37. Write Timing Diagram Using R/W (CS0-controlled)

†

Read Timing Parameter (CS0-controlled)

PARAMETER

Setup time, R/W stable to last CS valid

MIN

0

TYP

MAX

UNIT

ns

t

su(R/W)

Setup time, data valid to first CS invalid

Hold time, first CS invalid to data invalid

Hold time, first CS invalid to R/W change

Pulse duration, CS active

5

ns

su

2

ns

h

5

ns

h(R/W)

w(CS)

10

ns

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ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE

The THS1007 features four analog input channels. These can be configured for either single-ended or

differential operation. Figure 38 shows a simplified model, where a single-ended configuration for channel AINP

is selected. The reference voltages for the ADC itself are V

and V

(either internal or external reference

REFP

REFM

voltage). The analog input voltage range is between V

to V

. This means that V

defines the

REFM

REFP

REFM

minimum voltage, and V

defines the maximum voltage, which can be applied to the ADC. The internal

REFP

reference source provides the voltage V

of 1.5 V and the voltage V

of 3.5 V (see also section

REFM

REFP

reference voltage). The resulting analog input voltage swing of 2 V can be expressed by:

V

v AINP v V

(1)

REFM

REFP

V

REFP

10-Bit

ADC

AINP

V

REFM

Figure 38. Single-Ended Input Stage

A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 39 shows

a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The

differential operation mode provides in terms of performance benefits over the single-ended mode and is

therefore recommended for best performance. The THS1007 offers 2 differential analog inputs and in the

single-ended mode4 analog inputs. If the analog input architecture is different, common-mode voltages can be

rejected. Additional details for both modes are given below.

V

REFP

AINP

+

V

ADC

10-Bit

ADC

Σ

–

AINM

V

REFM

Figure 39. Differential Input Stage

In comparison to the single-ended configuration it can be seen that the voltage V

, which is applied at the

ADC

input of the ADC, is the difference between the input AINP and AINM. The voltage V

follows:

can be calculated as

ADC

(

)

V

+ ABS AINP–AINM

(2)

ADC

An advantage to single-ended operation is that the common-mode voltage

AINM ) AINP

V

+

(3)

CM

2

can be rejected in the differential configuration, if the following condition for the analog input voltages is true:

AGND v AINM, AINP v AV

(4)

DD

1 V v V

v 4 V

(5)

CM

SINGLE-ENDED MODE OF OPERATION

The THS1007 can be configured for single-ended operation using dc or ac coupling. In either case, the input

of the THS1007 must be driven from an operational amplifier that does not degrade the ADC performance.

Because the THS1007 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar

signals to comply with its input requirements. This can be achieved with dc and ac-coupling.

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

DC COUPLING

An operational amplifier can be configured to shift the signal level according to the analog input voltage range

of the THS1007. The analog input voltage range of the THS1007 goes from 1.5 V to 3.5 V. An operational

amplifier can be used as shown in Figure 40.

Figure 40 shows an example with the analog input signal in the range between –1 V up to 1 V. This signal is

shifted by an operational amplifier to the analog input range of the THS1007 (1.5 V to 3.5 V). The operational

amplifier is configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the

noninverting input is derived from the 2.5-V output reference REFOUT of the THS1007 by using a resistor

divider. Therefore, the operational amplifier output voltage is centered at 2.5 V. The 10 µF tantalum capacitor

is required for bypassing REFOUT. REFIN of the THS1007 must be connected directly to REFOUT in

single-ended mode. The use of ratio matched, thin-film resistor networks minimizes gain and offset errors.

R

3.5 V

2.5 V

1.5 V

1

5 V

1 V

0 V

R

1

THS1007

AINP

_

R

S

–1 V

+

C

1.25 V

REFIN

REFOUT

+

R

10 µF

2

Figure 40. Level-Shift for DC-Coupled Input

DIFFERENTIAL MODE OF OPERATION

For the differential mode of operation, a conversion from single-ended to differential is required. A conversion

to differential signals can be achieved by using an RF-transformer, which provides a center tap. Best

performance is achieved in differential mode.

Mini Circuits

T4–1

THS1007

49.9 Ω

R

AINP

C

200 Ω

R

AINM

REFOUT

+

10 µF

Figure 41. Transformer Coupled Input

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DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY

Integral Nonlinearity

Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale.

The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level

1/2 LSB beyond the last code transition. The deviation is measured from the center of each particular code to

the true straight line between these two points.

Differential Nonlinearity

An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value.

A differential nonlinearity error of less than ±1 LSB ensures no missing codes.

Zero Offset

The major carry transition should occur when the analog input is at zero volts. Zero error is defined as the

deviation of the actual transition from that point.

Gain Error

The first code transition should occur at an analog value 1/2 LSB above negative full scale. The last transition

should occur at an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual

difference between first and last code transitions and the ideal difference between first and last code transitions.

Signal-to-noise Ratio + Distortion (SINAD)

SINAD is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components

below the Nyquist frequency, including harmonics but excluding dc. The value for SINAD is expressed in

decibels.

Effective Number of Bits (ENOB)

For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,

(

)

SINAD * 1.76

N +

6.02

it is possible to get a measure of performance expressed as N, the effective number of bits. Thus, the effective

number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its

measured SINAD.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input

signal and is expressed as a percentage or in decibels.

Spurious Free Dynamic Range (SFDR)

SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal.

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SLAS286A – AUGUST 2000– REVISED DECEMBER 2002

MECHANICAL DATA

DA (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,30

0,19

M

0,13

0,65

38

20

6,20

8,40

NOM 7,80

0,15 NOM

Gage Plane

1

19

0,25

A

0°–8°

ā

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

28

30

32

38

DIM

9,80

9,60

11,10

10,90

11,10

10,90

12,60

12,40

A MAX

A MIN

4040066/D 11/98

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-153

33

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

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Post Office Box 655303

Dallas, Texas 75265


型号：	THS1007IDARG4
厂家：	TEXAS INSTRUMENTS
描述：	IC,DATA ACQ SYSTEM,4-CHANNEL,10-BIT,TSSOP,32PIN,PLASTIC
文件：	总34页 (文件大小：272K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS1007IDARG4 [TI]

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