THS1009CDAR_技术文档

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

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programming the ADC into the desired mode. The

THS1009 consists of two analog inputs, which are

sampled simultaneously. These inputs can be selected

individually and configured to single-ended or

differential inputs. Internal reference voltages for the

ADC (1.5 V and 3.5 V) are provided. An external

reference can also be chosen to suit the dc accuracy

and temperature drift requirements of the application.

FEATURES

D

Simultaneous Sampling of Two Single-Ended

Signals or One Differential Signals or

Combination of Both

D

Signal-to-Noise and Distortion Ratio: 59 dB

at f = 2 MHz

I

D

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1 LSB

Auto-Scan Mode for Two Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 216 mW Max at 5 V

Power Down: 1 mW Max

The THS1009C is characterized for operation from 0°C

to 70°C, and the THS1009I is characterized for

operation from –40°C to 85°C.

DA PACKAGE

(TOP VIEW)

D0

D1

D2

D3

D4

D5

NC

5-V Analog Single Supply Operation

1

32

31

30

29

28

27

26

25

24

23

22

21

RESET

AINP

2

Internal Voltage References . . . 50 PPM/°C

and ±5% Accuracy

3

AINM

4

D

Glueless DSP Interface

REFIN

REFOUT

REFP

REFM

AGND

5

D

Parallel µC/DSP Interface

6

BV

7

DD

APPLICATIONS

BGND

D6

8

9

D

Radar Applications

D7

AV

10

11

12

13

14

15

16

DD

Communications

D8

D9

CS0

CS1

Control Applications

High-Speed DSP Front-End

Automotive Applications

RA0

20 WR (R/W)

19

18

17

RA1

CONV_CLK

SYNC

RD

DV

DD

DGND

DESCRIPTION

The THS1009 is a CMOS, low-power, 10-bit, 8 MSPS

analog-to-digital converter (ADC). The speed,

resolution, bandwidth, and single-supply operation are

suited for applications in radar, imaging, high-speed

ORDERING INFORMATION

PACKAGED DEVICE

T

A

TSSOP

(DA)

acquisition, and communications.

A

multistage

pipelined architecture with output error correction logic

provides for no missing codes over the full operating

temperature range. Internal control registers allow for

0°C to 70°C

THS1009CDA

THS1009IDA

–40°C to 85°C

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during

storage or handling to prevent electrostatic damage to the MOS gates.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range unless otherwise noted

UNITS

DGND to DV

BGND to BV

–0.3 V to 6.5 V

DD

Supply voltage range

DD

AGND to AV

Analog input voltage range

Reference input voltage

Digital input voltage range

AGND –0.3 V to AV

DD

+ 1.5 V

+ 0.3 V

–0.3 V + AGND to AV

DD

–0.3 V to BV /DV

DD DD

Operating virtual junction temperature range, T

–40°C to 150°C

0 to 70°C

J

THS1009C

THS1009I

Operating free-air temperature range, T

A

–40°C to 85°C

–65°C to 150°C

260°C

Storage temperature range, T

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

POWER SUPPLY

MIN NOM

MAX

5.25

UNIT

AV

DD

4.75

3

5

Supply voltage

DV

V

DD

BV

ANALOG AND REFERENCE INPUTS

MIN NOM

MAX

UNIT

Analog input voltage in single-ended configuration

V

REFM

REFP

4

Common-mode input voltage V

in differential configuration

(optional)

1

2.5

CM

External reference voltage,V

3.5 AV –1.2

REFP

DD

External reference voltage, V

REFM

(optional)

1.4

1.5

2

Input voltage difference, REFP – REFM

DIGITAL INPUTS

MIN NOM

MAX

UNIT

V

BV

DV

= 3.3 V

2

DD

High-level input voltage, V

IH

= 5.25 V

2.6

V

= 3.3 V

0.6

V

Low-level input voltage, V

IL

= 5.25 V

V

Input CONV_CLK frequency

= 4.75 V to 5.25 V

0.1

62

0

8

MHz

ns

CONV_CLK pulse duration, clock high, t

62

5000

70

w(CONV_CLKH)

CONV_CLK pulse duration, clock low, t

w(CONV_CLKL)

THS1009CDA

THS1009IDA

Operating free-air temperature, T

°C

A

–40

85

2

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, AV

DIGITAL SPECIFICATIONS

PARAMETER

= DV

DD

= 5 V, BV

DD

= 3.3 V, V

REF

= internal voltage (unless otherwise noted)

DD

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Digital inputs

I

High-level input current

Low-level input current

Input capacitance

DV

DD

= digital inputs

–50

50

µA

pF

IH

Digital input = 0 V

IL

C

5

i

Digital outputs

V

High-level output voltage

Low-level output voltage

I

= –50 µA, BV

= 3.3 V, 5 V

BV –0.5

V

OH

DD

= 50 µA,

BV

0.4

10

V

OL

DD

I

High-impedance-state output current

Output capacitance

CS1 = DGND, CS0 = DV

DD

–10

µA

pF

OZ

C

5

O

L

C

Load capacitance at databus D0 – D9

30

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, AV

DC SPECIFICATIONS

PARAMETER

= DV

DD

= 5 V, BV

DD

= 3.3 V, f = 8 MSPS, V = internal voltage (unless otherwise noted)

REF

DD

s

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Resolution

10

Bits

Accuracy

Integral nonlinearity, INL

Differential nonlinearity, DNL

±1

LSB

After calibration in single-ended mode

After calibration in differential mode

±5

Offset error

–10

10

Gain error

Analog input

Input capacitance

15

pF

Input leakage current

Internal voltage reference

V

AIN

= V

REFM

to V

REFP

±10

µA

Accuracy, V

3.3

1.4

3.5

1.5

50

3.7

1.6

V

REFP

V

PPM/°C

µV

REFM

Temperature coefficient

Reference noise

100

Accuracy, REFOUT

2.475

2.5 2.525

V

Power supply

I

Analog supply current

Digital supply current

Buffer supply current

Power dissipation

AV

= DV

= 5 V, BV

=3.3 V

= 3.3 V

36

0.5

1.5

186

40

3

mA

mW

DDA

DDD

DDB

DD

= DV

DD

4

216

Power dissipation in power down with conversion

clock inactive

AV

= DV

= 5 V, BV

= 3.3 V

0.25

mW

DD

3

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

ELECTRICAL CHARACTERISTICS

over recommended operating conditions, V

= internal voltage, f = 8 MSPS, f = 2 MSPS at –1 dB (unless otherwise noted)

s I

REF

AC SPECIFICATIONS, AV

DD

= DV

DD

= 5 V, BV = 3.3 V, C < 30 pF

DD L

PARAMETER

TEST CONDITIONS

MIN

56

TYP

59

MAX

UNIT

Differential mode

Single-ended mode

Differential mode

Single-ended mode

Differential mode

Single-ended mode

Differential mode

Single-ended mode

Differential mode

Single-ended mode

SINAD Signal-to-noise ratio + distortion

dB

55

58

59

61

SNR

Signal-to-noise ratio

58

60

–64

–63

9.5

9.35

65

THD

Total harmonic distortion

Effective number of bits

Spurious free dynamic range

dB

9

8.85

61

ENOB

SFDR

Bits

dB

60

64

Analog Input

Full-power bandwidth with a source impedance of 150 Ω in

differential configuration.

Full scale sinewave, –3 dB

100 mVpp sinewave, –3 dB

96

54

96

54

MHz

Full-power bandwidth with a source impedance of 150 Ω in

single-ended configuration.

Small-signal bandwidth with a source impedance of 150 Ω in

differential configuration.

Small-signal bandwidth with a source impedance of 150 Ω in

single-ended configuration.

TIMING REQUIREMENTS

AV

= DV

DD

= 5 V, BV

DD

= 3.3 V, V = internal voltage, C < 30 pF

REF L

DD

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

CONV

CLK

t

Latency

5

pipe

t

Setup time, CONV_CLK low before CS valid

Setup time, CS invalid to CONV_CLK low

Delay time, CONV_CLK low to SYNC low

Delay time, CONV_CLK low to SYNC high

10

20

ns

su(CONV_CLKL-READL)

su(READH-CONV_CLKL)

d(CONV_CLKL-SYNCL)

d(CONV_CLKL-SYNCH)

10

4

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TERMINAL

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

Terminal Functions

I/O

DESCRIPTION

NAME

NO.

30

29

23

24

7

AINP

AINM

I

Analog input, single-ended or positive input of differential channel A

Analog input, single-ended or negative input of differential channel A

Analog supply voltage

AV

DD

I

AGND

BV

I

Analog ground

I

Digital supply voltage for buffer

DD

BGND

CONV_CLK

CS0

8

I

Digital ground for buffer

15

22

21

16

I

Digital input. This input is the conversion clock input.

Chip select input (active low)

I

CS1

I

Chip select input (active high)

SYNC

O

Synchronizationoutput. This signal indicates in a multichannel operation that data of channel A is brought to the

digital output and can therefore be used for synchronization.

DGND

17

18

I

Digital ground. Ground reference for digital circuitry.

Digital supply voltage

DV

DD

D0 – D9

1–6,

I/

Digital input, output; D0 = LSB

9–12

O/Z

RA0

13

I

Digital input. RA0 is used as an address line (RA0) for the control register. This is required for writing to control

register 0 and control register 1. See Table 7.

RA1

14

I

Digital input. RA1 is used as an address line (RA1) for the control register. This is required for writing to control

register 0 and control register 1. See Table 7.

NC

32

28

O

I

Not connected

REFIN

Common-modereference input for the analog input channels. It is recommended that this pin be connected to the

reference output REFOUT.

REFP

REFM

26

25

I

Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.

An external reference voltage at this input can be applied. This option can be programmed through control

register 0. See Table 8.

Reference input, requires a bypass capacitor of 10 µF to AGND in order to bypass the internal reference voltage.

An external reference voltage at this input can be applied. This option can be programmed through control

register 0. See Table 8.

RESET

31

27

I

Hardware reset of the THS1009. Sets the control register to default values.

REFOUT

O

Analog fixed reference output voltage of 2.5 V. Sink and source capability of 250 µA. The reference output requires

a capacitor of 10 µF to AGND for filtering and stability.

(1)

RD

19

20

I

The RD input is used only if the WR input is configured as a write only input. In this case, it is a digital input, active

low as a data read select from the processor. See timing section.

(1)

WR (R/W)

This input is programmable. It functions as a read-write input (R/W) and can also be configured as a write-only input

(WR), which is active low and used as data write select from the processor. In this case, the RD input is used as a

read input from the processor. See timing section.

(1)

The start-conditions of RD and WR (R/W) are unknown. The first access to the ADC has to be a write access to initialize the ADC.

5

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

FUNCTIONAL BLOCK DIAGRAM

AV

DD

DV

DD

3.5 V

1.5 V

2.5 V

REFP

1.225 V

REF

REFOUT

REFM

REFIN

REFP

REFM

10

BV

DD

Single-Ended

+

–

10-Bit

Pipeline

ADC

and/or

Differential

MUX

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

S/H

AINP

AINM

S/H

Buffers

CONV_CLK

CS0

RA0

RA1

Logic

and

Control

Register

CS1

BGND

RD

WR (R/W)

RESET

SYNC

AGND

DGND

6

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

SIGNAL-TO-NOISE AND DISTORTION

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

80

75

70

65

60

55

50

45

40

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

IN

DD

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 1

Figure 2

SIGNAL-TO-NOISE

vs

SPURIOUS FREE DYNAMIC RANGE

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 3

Figure 4

7

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

SIGNAL-TO-NOISE AND DISTORTION

vs

SAMPLING FREQUENCY (DIFFERENTIAL)

85

80

75

70

65

60

55

50

45

40

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

IN

DD

0

1

2

3

4

5

6

7

8

9

0

1

2

3

4

5

6

7

8

9

f

s

– Sampling Frequency – MHz

f

s

– Sampling Frequency – MHz

Figure 5

Figure 6

SIGNAL-TO-NOISE

vs

SPURIOUS FREE DYNAMIC RANGE

vs

SAMPLING FREQUENCY (DIFFERENTIAL)

65

60

55

50

45

40

90

85

80

75

70

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

0

1

2

f

3

4

5

6

7

8

9

0

1

2

s

3

4

5

6

7

8

9

– Sampling Frequency – MHz

f

– Sampling Frequency – MHz

s

Figure 7

Figure 8

8

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

TOTAL HARMONIC DISTORTION

vs

SIGNAL-TO-NOISE AND DISTORTION

vs

INPUT FREQUENCY (SINGLE-ENDED)

80

75

70

65

60

55

50

45

40

65

60

55

50

45

40

AV

= 5 V, DV

= BV

= 3 V,

f = 8 MSPS, AIN = –1 dB FS

DD

s

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 9

Figure 10

SIGNAL-TO-NOISE

vs

INPUT FREQUENCY (SINGLE-ENDED)

SPURIOUS FREE DYNAMIC RANGE

vs

INPUT FREQUENCY (SINGLE-ENDED)

80

90

AV

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dBFS

DD

s

DD

f

85

80

75

70

65

60

55

50

45

40

75

70

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 12

Figure 11

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

SIGNAL-TO-NOISE AND DISTORTION

TOTAL HARMONIC DISTORTION

vs

INPUT FREQUENCY (DIFFERENTIAL)

80

75

70

65

60

55

50

45

40

65

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 800 MSPS, AIN = –1 dB FS

DD

s

DD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 13

Figure 14

SIGNAL-TO-NOISE

vs

INPUT FREQUENCY (DIFFERENTIAL)

SPURIOUS FREE DYNAMIC RANGE

vs

INPUT FREQUENCY (DIFFERENTIAL)

65

90

85

80

75

70

65

60

55

50

45

40

60

55

50

45

40

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 16

Figure 15

10

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

EFFECTIVE NUMBER OF BITS

vs

SAMPLING RATE (DIFFERENTIAL)

EFFECTIVE NUMBER OF BITS

vs

SAMPLING FREQUENCY (SINGLE-ENDED)

11.0

10.5

10.0

9.5

11.0

10.5

10.0

9.5

9.0

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

DD

IN

DD

8.5

AV

f

= 5 V, DV

= BV

= 3 V,

= 500 kHz, AIN = –1 dB FS

8.5

DD

IN

DD

8.0

7.5

7.0

6.5

6.0

0

1

2

3

4

5

6

7

8

9

6.0

f

– Sampling Frequency – MHz

0

1

2

3

4

5

6

7

8

9

s

f

s

– Sampling Frequency – MHz

Figure 18

Figure 17

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY (DIFFERENTIAL)

EFFECTIVE NUMBER OF BITS

vs

INPUT FREQUENCY (SINGLE-ENDED)

11.0

10.5

10.0

9.5

11.0

10.5

10.0

9.5

9.0

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

s

AV

f

= 5 V, DV

= BV

= 3 V,

= 8 MSPS, AIN = –1 dB FS

DD

s

DD

8.5

8.0

7.5

7.0

6.5

6.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

f – Input Frequency – MHz

i

f – Input Frequency – MHz

i

Figure 20

Figure 19

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

DIFFERENTIAL NONLINEARITY

vs

ADC CODE

1.0

0.8

AV

= 5 V,

= 3 V,

= 8 MSPS

DD

DV

= BV

DD

f

DD

0.6

s

0.4

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

256

512

768

1024

ADC Code

Figure 21

INTEGRAL NONLINEARITY

vs

ADC CODE

1.0

0.8

0.6

AV

= 5 V,

= 3 V,

= 8 MSPS

DD

DV

= BV

DD

f

DD

0.4

s

0.2

–0.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

256

512

768

1024

ADC Code

Figure 22

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TYPICAL CHARACTERISTICS

FAST FOURIER TRANSFORM (4096 Points)

(SINGLE-ENDED)

vs

FREQUENCY

0

–20

–40

–60

–80

AV

DD

= 5 V, DV

DD

= BV = 3 V,

DD

f

s

= 8 MHz, AIN = –1 dB FS, f = 1.25 MHz

IN

–100

–120

–140

0

500000

1000000 1500000 2000000 2500000 3000000 3500000 4000000

f – Frequency – Hz

Figure 23

FAST FOURIER TRANSFORM (4096 Points)

(DIFFERENTIAL)

vs

FREQUENCY

0

–20

AV

DD

= 5 V, DV

DD

= BV = 3 V,

DD

f

s

= 8 MHz, AIN = –0.5 dB FS, f = 1.25 MHz

IN

–40

–60

–80

–100

–120

–140

0

500000

1000000 1500000 2000000 2500000 3000000 3500000 4000000

f – Frequency – Hz

Figure 24

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

DETAILED DESCRIPTION

Reference Voltage

The THS1009 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V

and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and

REFM, if the reference source is programmed as external. The voltage levels applied to these pins establish the

upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively.

Analog Inputs

The THS1009 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected

individually and configured as single-ended or differential inputs. The desired analog input channel can be

programmed.

Converter

The THS1009 uses a 10-bit pipelined multistaged architecture which achieves a high sample rate with low power

consumption. The THS1009 distributes the conversion over several smaller ADC sub-blocks, refining the conversion

with progressively higher accuracy as the device passes the results from stage to stage. This distributed conversion

requires a small fraction of the number of comparators used in a traditional flash ADC. A sample-and-hold amplifier

(SHA) within each of the stages permits the first stage to operate on a new input sample while the second through

the eighth stages operate on the seven preceding samples.

Conversion

An external clock signal with a duty cycle of 50% has to be applied to the clock input (CONV_CLK). A new conversion

is started with every falling edge of the applied clock signal. The conversion values are available at the output with

a latency of 5 clock cycles.

SYNC

In multichannel mode, the first SYNC signal is delayed by [7+ (# Channels Sampled)] cycles of the CONV_CLK after

a SYNC reset. This is due to the latency of the pipeline architecture of the THS1009.

Sampling Rate

The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1

shows the maximum conversion rate for the different combinations.

Table 1. Maximum Conversion Rate in Continuous Conversion Mode

NUMBER OF

CHANNELS

MAXIMUM CONVERSION

RATE PER CHANNEL

CHANNEL CONFIGURATION

1 single-ended channel

1

2

1

8 MSPS

4 MSPS

8 MSPS

2 single-ended channels

1 differential channel

The maximum conversion rate per channel, fc, is given by:

8 MSPS

# channels

fc +

Continuous Conversion Mode

During conversion the ADC operates with a free running external clock signal applied to the input CONV_CLK. With

every falling edge of the CONV_CLK signal a new converted value is available to the databus with the corresponding

read signal. The THS1009 offers up to two analog inputs to be selected. It is important to provide the channel

information to the system; this means knowing which channel is available to the databus. To maintain this channel

integrity, the THS1009 has an output signal SYNC, which is always active low if the data of channel 1 is applied to

the databus.

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Figure 25 shows the timing of the conversion when one analog input channel is selected. The maximum throughput

rate is 8 MSPS in this mode. The signal SYNC is disabled for the selection of one analog input since this information

is not required for one analog input. There is a certain timing relationship required for the read signal with respect

to the conversion clock. This can be seen in Figure 26 and the timing specification. A more detailed description of

the timing is given in the section timing and signal description of the THS1009.

Sample N+1

Channel 1

Sample N

Channel 1

Sample N+2

Channel 1

Sample N+3 Sample N+4

Sample N+5

Channel 1

Sample N+6

Channel 1

Sample N+7 Sample N+8

Channel 1

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(CONV_CLKL-READL)

su(READH-CONV_CLKL)

†

READ

Data N–4

Channel 1

Data N–3

Channel 1

Data N+1

Channel 1

Data N–2

Channel 1

Data N–1

Channel 1

Data N

Channel 1

Data N+2

Channel 1

†

READ is the logical combination from CS0, CS1 and RD

Figure 25. Conversion Timing in 1-Channel Operation

Figure 27 shows the conversion timing when two analog input channels are selected. The maximum throughput rate

per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data

is available to the data bus. This can be seen in Figure 26 and Table 2. A more detailed description of the timing is

given in the section timing and signal description of the THS1009.

Sample N

Channel 1, 2

Sample N+1

Channel 1, 2

Sample N+2

Channel 1, 2

Sample N+3

Channel 1, 2

Sample N+4

Channel 1, 2

AIN

t

d(A)

t

d(pipe)

t

w(CONV_CLKH)

t

w(CONV_CLKL)

CONV_CLK

t

c

t

su(CONV_CLKL-READL)

t

su(READH-CONV_CLKL)

†

READ

t

su(CONV_CLKL-SYNCH)

t

su(CONV_CLKL-SYNCL)

SYNC

Data N

Channel 2

Data N–2

Channel 1

Data N–2

Channel 2

Data N–1

Channel 1

Data N–1

Channel 2

Data N

Channel 1

Data N+1

Channel 1

†

READ is the logical combination from CS0, CS1 and RD

Figure 26. Conversion Timing in 2-Channel Operation

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DIGITAL OUTPUT DATA FORMAT

The digital output data format of the THS1009 can either be in binary format or in twos complement format. The

following tables list the digital outputs for the analog input voltages.

Table 2. Binary Output Format for Single-Ended Configuration

SINGLE-ENDED, BINARY OUTPUT

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

AIN = V

3FFh

200h

000h

REFP

+ V

AIN = (V

)/2

REFP

REFM

AIN = V

REFM

Table 3. Twos Complement Output Format for Single-Ended Configuration

SINGLE-ENDED, TWOS COMPLEMENT

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

AIN = V

1FFh

000h

200h

REFP

+ V

AIN = (V

)/2

REFP

REFM

AIN = V

REFM

Table 4. Binary Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE

DIGITAL OUTPUT CODE

V

= AINP – AINM

in

= V

V

– V

REFM

REF

REFP

V

= V

3FFh

200h

000h

in

REF

V

= 0

in

= –V

V

in

REF

Table 5. Twos Complement Output Format for Differential Configuration

DIFFERENTIAL, BINARY OUTPUT

ANALOG INPUT VOLTAGE

= AINP – AINM

DIGITAL OUTPUT CODE

V

in

= V

V

REF

– V

REFM

REFP

V

= V

1FFh

000h

200h

in

REF

V

= 0

in

= –V

V

in

REF

ADC CONTROL REGISTER

The THS1009 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired

mode. The bit definitions of both control registers are shown in Table 6.

Table 6. Bit Definitions of Control Register CR0 and CR1

REG

CR0

CR1

BIT 9

TEST1

BIT 8

TEST0

OFFSET

BIT 7

SCAN

BIN/2’s

BIT 6

DIFF1

R/W

BIT 5

DIFF0

RES

BIT 4

CHSEL1

RES

BIT 3

CHSEL0

RES

BIT 2

PD

BIT 1

RES

BIT 0

VREF

RESERVED

RES

SRST

RESET

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Writing to Control Register 0 and Control Register 1

The 10-bit wide control register 0 and control register 1 can be programmed by addressing the desired control

register and writing the register value to the ADC. The addressing is performed with the upper bits RA0 and RA1.

During this write process, the data bits D0 to D9 contain the desired control register value. Table 7 shows the

addressing of each control register.

Table 7. Control Register Addressing

D0 – D9

RA0

RA1

Addressed Control Register

Control register 0

Desired register value

0

1

0

1

0

1

Control register 1

Reserved for future

INITIALIZATION OF THE THS1009

The initialization of the THS1009 should be done according to the configuration flow shown in Figure 27.

Start

No

Use Default

Values?

Yes

Write 0x401 to

THS1009

(Set Reset Bit in CR1)

Clear RESET By

Writing 0x400 to

CR1

Clear RESET By

Writing 0x400 to

CR1

Write the User

Configuration to

CR0

Write The User

Configuration to

CR1 ( Must

Exclude RESET)

Continue

Figure 27. THS1009 Configuration Flow

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ADC CONTROL REGISTERS

Control Register 0, Write Only (see Table 8)

BIT 11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

0

TEST1

TEST0

SCAN

DIFF1

DIFF0

CHSEL1 CHSEL0

PD

RES

VREF

Table 8. Control Register 0 Bit Functions

RESET

VALUE

BITS

NAME

FUNCTION

0

VREF

Vref select:

Bit 0 = 0 → The internal reference is used

Bit 0 = 1 → The external reference voltage is used for the ADC

1

2

0

RES

PD

Reserved

Power down.

Bit 2 = 0 → The ADC is active

Bit 2 = 1 → Power down

The reading and writing to and from the digital outputs is possible during power down.

3, 4

5,6

7

0,0

1,0

0

CHSEL0,

CHSEL1

Channel select

Bit 3 and bit 4 select the analog input channel of the ADC. Refer to Table 9.

DIFF0, DIFF1 Number of differential channels

Bit 5 and bit 6 contain information about the number of selected differential channels. Refer to Table 9.

SCAN

Autoscan enable

Bit 7 enables or disables the autoscan function of the ADC. Refer to Table 9.

8,9

0,0

TEST0,

TEST1

Test input enable

Bit 8 and bit 9 control the test function of the ADC. Three different test voltages can be measured. This

feedback allows the check of all hardware connections and the ADC operation.

Refer to Table 10 for selection of the three different test voltages.

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

ANALOG INPUT CHANNEL SELECTION

The analog input channels of the THS1009 can be selected via bits 3 to 7 of control register 0. One single channel

(single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between

single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel

is selected. Table 9 shows the possible selections.

Table 9. Analog Input Channel Configurations

BIT 7

SCAN

BIT 6

DIFF1

BIT 5

DIFF0

BIT 4

CHSEL1 CHSEL0

BIT 3

DESCRIPTION OF THE SELECTED INPUTS

Analog input AINP (single ended)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Analog input AINM (single ended)

Reserved

Differential channel (AINP–AINM)

Reserved

Autoscan two single ended channels: AINP, AINM, AINP, …

Reserved

Test Mode

The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in

Table 10.

Table 10. Test Mode

BIT 9

TEST1 TEST0

BIT 8

OUTPUT RESULT

0

1

0

1

0

1

Normal mode

V

REFP

)+(V

((V

))/2

REFP

REFM

V

REFM

Three different options can be selected. This feature allows support testing of hardware connections between the

ADC and the processor.

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

Control Register 1, Write Only (see Table 11)

BIT11

BIT 10

BIT 9

BIT 8

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

SRST

BIT 0

0

1

RESERVED OFFSET

BIN/2s

R/W

RES

RESET

Table 11. Control Register 1 Bit Functions

RESET

VALUE

BITS

NAME

FUNCTION

0

RESET

Reset

Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.

To bring the device out of RESET, a 0 has to be written into this bit.

1

0

SRST

Writing a 1 into this bit resets the sync generator. When running in multichannel mode, this must be set during the

configurationcycle.

2, 3

4

0,0

1

RES

R/W

Reserved

5

1

Reserved

6

0

R/W, RD/WR selection

Bit 6 of control register 1 controls the function of the inputs RD and WR. Whenbit 6 in control register 1 is set to

1, WR becomes a R/W input and RD is disabled. From now on a read is signalled with R/W high and a write with

R/W as a low signal. If bit 6 in control register 1 is set to 0, the input RD becomes a read input and the input WR

becomes a write input.

7

8

0

BIN/2s

Complement select

If bit 7 of control register 1 is set to 0, the output value of the ADC is in twos complement. If bit 7 of

control register 1 is set to 1, the output value of the ADC is in binary format. Refer to Table 2 through Table 5.

OFFSET

Offset cancellation mode

Bit 8 = 0 → normal conversion mode

Bit 8 = 1 → offset calibration mode

If a 1 is written into bit 8 of control register 1, the device internally sets the inputs to zero and does a conver-

sion. The conversion result is stored in an offset register and subtracted from all conversions in order to

reduce the offset error.

9

0

RESERVED Always write 0.

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

TIMING AND SIGNAL DESCRIPTION OF THE THS1009

The reading from the THS1009 and writing to the THS1009 is performed by using the chip select inputs (CS0, CS1),

the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This

is desired in cases where the connected processor consists of a combined read/write output signal (R/W). The two

chip select inputs can be used to interface easily to a processor.

Reading from the THS1009 takes place by an internal RD signal, which is generated from the logical combination

int

of the external signals CS0, CS1 and RD (see Figure 28). This signal is then used to strobe out the words and to

enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes RD active while

int

the write input (WR) is inactive. The first of those external signals switching to its inactive state deactivates RD

again.

int

Writing to the THS1009 takes place by an internal WR signal, which is generated from the logical combination of

int

the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and 1. The

last external signal (either CS0, CS1 or WR) to become valid switches WR active while the read input (RD) is

int

inactive. The first of those external signals going to its inactive state deactivates WR again.

int

RD

int

CS0

CS1

RD

WR

int

WR

Control/Data

Registers

Data Bits

Figure 28. Logical Combination of CS0, CS1, RD, and WR

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Read Timing (using RD, RD-controlled)

Figure 29 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input

RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external

signal of CS0, CS1, and RD which becomes valid.

CS0

CS1

t

su(CS)

h(CS)

WR

RD

t

w(RD)

10%

t

a

t

h

90%

D(0–9)

t

d(CSDAV)

90%

DATA_AV

Figure 29. Read Timing Diagram Using RD (RD-controlled)

Read Timing Parameter (RD-controlled)

PARAMETER

Setup time, RD low to last CS valid

MIN

0

TYP

MAX

10

UNIT

ns

t

su(CS)

Access time, last CS valid to data valid

Delay time, last CS valid to DATA_AV inactive

Hold time, first CS invalid to data invalid

Hold time, RD change to first CS invalid

Pulse duration, RD active

0

ns

a

12

ns

d(CSDAV)

h

0

5

ns

h(CS)

w(RD)

10

ns

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

Write Timing (using WR, WR-controlled)

Figure 30 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The

input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last

external signal of CS0, CS1, and WR which becomes valid.

CS0

CS1

t

h(CS)

su(CS)

t

w(WR)

WR

RD

10%

t

su

t

h

90%

D(0–9)

DATA_AV

Figure 30. Write Timing Diagram Using WR (WR-controlled)

Write Timing Parameter Using WR (WR-controlled)

PARAMETER

MIN

0

TYP

MAX

UNIT

ns

t

Setup time, CS stable to last WR valid

Setup time, data valid to first WR invalid

Hold time, WR invalid to data invalid

Hold time, WR invalid to CS change

Pulse duration, WR active

su(CS)

5

ns

su

2

ns

h

5

ns

h(CS)

w(WR)

10

ns

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Read Timing (using R/W, CS0-controlled)

Figure 31 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input

R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0

is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data should be done with

a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 31.

t

su(CSOH–CONV_CLKL)

t

su(CONV_CLKL–CSOL)

CONV_CLK

10%

90%

t

w(CS)

CS0

CS1

10%

t

h(R/W)

su(R/W)

90%

R/W

RD

t

a

t

h

90%

D(0–11)

Figure 31. Read Timing Diagram Using R/W (CS0-controlled)

Read Timing Parameter (CS0-controlled)

PARAMETER

MIN

10

20

0

TYP

MAX

UNIT

t

Setup time, CONV_CLK low before CS valid

Setup time, CS invalid to CONV_CLK low

Setup time, R/W high to last CS valid

Access time, last CS valid to data valid

Hold time, first CS invalid to data invalid

Hold time, first external CS invalid to R/W change

Pulse duration, CS active

ns

su(CONV_CLKL–CSOL)

su(CSOH–CONV_CLKL)

su(R/W)

a

0

10

5

0

h

5

h(R/W)

w(CS)

10

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SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

Write Timing (using R/W, CS0-controlled)

Figure 32 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input

R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0

is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1009 can be performed

irrespective of the conversion clock signal CONV_CLK.

t

90%

w(CS)

CS0

CS1

10%

t

h(R/W)

su(R/W)

R/W

RD

10%

t

su

t

h

90%

D(0–11)

Figure 32. Write Timing Diagram Using R/W (CS0-controlled)

Write Timing Parameter (CS0-controlled)

PARAMETER

Setup time, R/W stable to last CS valid

MIN

0

TYP

MAX

UNIT

ns

t

su(R/W)

Setup time, data valid to first CS invalid

Hold time, first CS invalid to data invalid

Hold time, first CS invalid to R/W change

Pulse duration, CS active

5

ns

su

2

ns

h

5

ns

h(R/W)

w(CS)

10

ns

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ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE

The THS1009 features two analog input channels. These can be configured for either single-ended or differential

operation. Figure 33 shows a simplified model, where a single-ended configuration for channel AINP is selected. The

reference voltages for the ADC itself are V

and V

(either internal or external reference voltage). The analog

REFP

REFM

input voltage range is between V

to V

. This means that V

defines the minimum voltage and V

REFM

REFP

REFM REFP

defines the maximum voltage, which can be applied to the ADC. The internal reference source provides the voltage

of 1.5 V and the voltage V of 3.5 V (see also section Reference Voltage). The resulting analog input

V

REFM

REFP

voltage swing of 2 V can be expressed by:

V

v AINP v V

REFM

REFP

(1)

V

REFP

10-Bit

ADC

AINP

V

REFM

Figure 33. Single-Ended Input Stage

A differential operation is desired for many applications due to better signal-to-noise ration. Figure 34 shows a

simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The differential

operation mode provides in terms of performance benefits over the single-ended mode and is therefore

recommended for best performance. The THS1009 offers 1 differential analog input and in the single-ended mode

2 analog inputs. If the analog input architecture is differential, common-mode noise and common-mode voltages can

be rejected. Additional details for both modes are given below.

V

REFP

AINP

+

V

ADC

10-Bit

ADC

Σ

–

AINM

V

REFM

Figure 34. Differential Input Stage

In comparison to the single-ended configuration it can be seen that the voltage, V

, which is applied at the input

can be calculated as follows:

ADC

of the ADC is the difference between the input AINP and AINM. The voltage V

ADC

(

)

V

+ ABS AINP–AINM

ADC

(2)

An advantage to single-ended operation is that the common-mode voltage

AINM ) AINP

V

+

CM

2

(3)

can be rejected in the differential configuration, if the following condition for the analog input voltages is true:

AGND v AINM, AINP v AV

DD

(4)

(5)

1 V v V

v 4 V

CM

26

www.ti.com

ꢀꢁ ꢂ ꢃꢄ ꢄꢅ

SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

SINGLE-ENDED MODE OF OPERATION

The THS1009 can be configured for single-ended operation using dc or ac coupling. In either case, the input of the

THS1009 should be driven from an operational amplifier that does not degrade the ADC performance. Because the

THS1009 operates from a 5-V single supply, it is necessary to level-shift ground-based bipolar signals to comply with

its input requirements. This can be achieved with dc- and ac-coupling.

DC COUPLING

An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the

THS1009. The analog input voltage range of the THS1009 goes from 1.5 V to 3.5 V. An operational amplifier can

be used as shown in Figure 35.

Figure 35 shows an example with the analog input signal in the range between –1 V and 1 V. The signal is shifted

by an operational amplifier to the analog input range of the THS1009 (1.5 V to 3.5 V). The operational amplifier is

configured as an inverting amplifier with a gain of –1. The required dc voltage of 1.25 V at the noninverting input is

derived from the 2.5-V output reference REFOUT of the THS1009 by using a resistor divider. Therefore, the

operational amplifier output voltage is centered at 2.5 V. The 10 µF tantalum capacitor is required for bypassing

REFOUT. REFIN of the THS1009 must be connected directly to REFOUT in single-ended mode. The use of ratio

matched, thin-film resistor networks minimizes gain and offset errors.

3.5 V

2.5 V

1.5 V

R

1

5 V

1 V

0 V

R

1

THS1009

AINP

_

R

S

–1 V

+

C

1.25 V

REFIN

REFOUT

+

R

10 µF

2

Figure 35. Level-Shift for DC-Coupled Input

DIFFERENTIAL MODE OF OPERATION

For the differential mode of operation, a conversion from single-ended to differential is required. A conversion to

differential signals can be achieved by using an RF-transformer, which provides a center tap. Best performance is

achieved in differential mode.

Mini Circuits

T4–1

THS1009

49.9 Ω

R

AINP

C

200 Ω

R

AINM

REFOUT

+

10 µF

Figure 36. Transformer Coupled Input

27

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢅ

www.ti.com

SLAS287A – AUGUST 2000 – REVISED DECEMBER 2002

MECHANICAL DATA

DA (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

38 PINS SHOWN

0,30

0,19

M

0,13

0,65

38

20

6,20

8,40

NOM 7,80

0,15 NOM

Gage Plane

1

19

0,25

A

0°–8°

ā

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

28

30

32

38

DIM

9,80

9,60

11,10

10,90

11,10

10,90

12,60

12,40

A MAX

A MIN

4040066/D 11/98

NOTES:A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-153

28

PACKAGE OPTION ADDENDUM

www.ti.com

11-Oct-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

THS1009CDA

THS1009CDAG4

THS1009CDAR

THS1009CDARG4

THS1009IDA

ACTIVE

TSSOP

DA

32

TBD

Call TI

DA

46 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR

no Sb/Br)

THS1009IDAR

ACTIVE

TSSOP

DA

32

TBD

Call TI

THS1009IDARG4

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MTSS002C – JANUARY 1995 – REVISED DECEMBER 1998

DA (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

38 PINS SHOWN

0,30

0,19

M

0,13

0,65

38

20

6,20

8,40

NOM 7,80

0,15 NOM

Gage Plane

1

19

0,25

A

0°–8°

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

30

32

38

DIM

11,10

10,90

11,10

10,90

12,60

12,40

A MAX

A MIN

4040066/D 11/98

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion.

D. Falls within JEDEC MO-153

1

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型号：	THS1009CDAR
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT, 2 ANALOG INPUT, 8 MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER 10位， 2个模拟输入， 8 MSPS同步采样模拟数字转换器转换器输入元件
文件：	总31页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS1009CDAR [TI]

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