THS1040CDW [TI]
3-V, 10-BIT , 40-MSPS CMOS ANALOG TO DIGITAL CONVERTER; 3 -V , 10位, 40 - MSPS CMOS模数转换器型号: | THS1040CDW |
厂家: | TEXAS INSTRUMENTS |
描述: | 3-V, 10-BIT , 40-MSPS CMOS ANALOG TO DIGITAL CONVERTER |
文件: | 总32页 (文件大小:541K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
ꢆ ꢇꢈꢉ ꢃ ꢄ ꢇꢊꢋ ꢌꢉ ꢅ ꢄ ꢇꢍꢂ ꢎꢂ
ꢏꢍ ꢐꢂ ꢑꢒ ꢑꢓ ꢐ ꢔꢇꢀꢐ ꢇꢕꢖꢔ ꢖ ꢀꢑꢓ ꢏꢐ ꢒꢈꢗ ꢘꢀ ꢗꢘ
bypassed to use an external reference to suit the dc
accuracy and temperature drift requirements of the
application. The out-of-range output indicates any
out-of-range condition in THS1040’s input signal.
FEATURES
D
D
D
Analog Supply 3 V
Digital Supply 3 V
Configurable Input Functions:
− Single Ended
− Differential
The speed, resolution, and single-supply operation of
the THS1040 are suited to applications in set-top-box
(STB), video, multimedia, imaging, high-speed
acquisition, and communications. The speed and
resolution ideally suit charge-couple device (CCD) input
systems such as color scanners, digital copiers, digital
cameras, and camcorders. A wide input voltage range
allows the THS1040 to be applied in both imaging and
communications systems.
D
D
D
D
D
D
D
D
Differential Nonlinearity: 0.45 LSB
Signal-to-Noise: 60 dB Typ f at 4.8 MHz
(IN)
Spurious Free Dynamic Range: 72 dB
Adjustable Internal Voltage Reference
On-Chip Voltage Reference Generator
Unsigned Binary Data Output
Out-of-Range Indicator
The THS1040C is characterized for operation from 0°C
to 70°C, while the THS1040I is characterized for
operation from −40°C to 85°C.
Power-Down Mode
APPLICATIONS
28-PIN TSSOP/SOIC PACKAGE
(TOP VIEW)
D
D
D
D
Video/CCD Imaging
Communications
Set-Top Box
AGND
AV
DD
AIN+
1
28
27
26
25
24
23
22
21
20
19
18
DV
2
DD
Medical
D0
D1
D2
D3
D4
D5
D6
D7
D8
VREF
3
AIN−
4
DESCRIPTION
REFB
5
MODE
REFT
6
The THS1040 is a CMOS, low power, 10-bit, 40-MSPS
analog-to-digital converter (ADC) that operates from a
single 3-V supply. The THS1040 has been designed to
give circuit developers flexibility. The analog input to the
THS1040 can be either single-ended or differential. The
THS1040 provides a wide selection of voltage
references to match the user’s design requirements.
For more design flexibility, the internal reference can be
7
BIASREF
TEST
8
9
AGND
REFSENSE
10
11
D9 12
OVR 13
17 STBY
16 OE
DGND 14
15 CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢎ
ꢎ
ꢘ
ꢐ
ꢧ
ꢕ
ꢢ
ꢙ
ꢏ
ꢠ
ꢀ
ꢡ
ꢖ
ꢜ
ꢐ
ꢚ
ꢒ
ꢛ
ꢕ
ꢑ
ꢀ
ꢑ
ꢋ
ꢚ
ꢣ
ꢛ
ꢜ
ꢡ
ꢝ
ꢞ
ꢟ
ꢟ
ꢌ
ꢌ
ꢋ
ꢋ
ꢜ
ꢜ
ꢚ
ꢚ
ꢋ
ꢠ
ꢠ
ꢤ
ꢡ
ꢢ
ꢝ
ꢝ
ꢣ
ꢣ
ꢚ
ꢌ
ꢟ
ꢞ
ꢠ
ꢠ
ꢜ
ꢛ
ꢤ
ꢀꢣ
ꢢ
ꢥ
ꢠ
ꢦ
ꢋ
ꢡ
ꢟ
ꢠ
ꢌ
ꢋ
ꢌ
ꢜ
ꢝ
ꢚ
ꢢ
ꢧ
ꢟ
ꢚ
ꢌ
ꢌ
ꢣ
ꢠ
ꢨ
Copyright 2001 − 2004, Texas Instruments Incorporated
ꢝ
ꢜ
ꢡ
ꢌ
ꢜ
ꢝ
ꢞ
ꢌ
ꢜ
ꢠ
ꢤ
ꢋ
ꢛ
ꢋ
ꢡ
ꢣ
ꢝ
ꢌ
ꢩ
ꢌ
ꢣ
ꢝ
ꢜ
ꢛ
ꢪ
ꢟ
ꢖ
ꢚ
ꢞ
ꢣ
ꢠ
ꢌ
ꢟ
ꢚ
ꢧ
ꢟ
ꢝ
ꢧ
ꢫ
ꢟ
ꢌ ꢣ ꢠ ꢌꢋ ꢚꢭ ꢜꢛ ꢟ ꢦꢦ ꢤꢟ ꢝ ꢟ ꢞ ꢣ ꢌ ꢣ ꢝ ꢠ ꢨ
ꢝ
ꢝ
ꢟ
ꢚ
ꢌ
ꢬ
ꢨ
ꢎ
ꢝ
ꢜ
ꢧ
ꢢ
ꢡ
ꢌ
ꢋ
ꢜ
ꢚ
ꢤ
ꢝ
ꢜ
ꢡ
ꢣ
ꢠ
ꢠ
ꢋ
ꢚ
ꢭ
ꢧ
ꢜ
ꢣ
ꢠ
ꢚ
ꢜ
ꢌ
ꢚ
ꢣ
ꢡ
ꢣ
ꢠ
ꢠ
ꢟ
ꢝ
ꢋ
ꢦ
ꢬ
ꢋ
ꢚ
ꢡ
ꢦ
ꢢ
ꢧ
ꢣ
1
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
AVAILABLE OPTIONS
SPECIFIED
TEMPERATURE
RANGE
PACKAGE
LEAD
PACKAGE
DESGIGNATOR
PACKAGE
MARKINGS
ORDERING
NUMBER
TRANSPORT MEDIA,
QUANTITY
PRODUCT
†
THS1040CPW
THS1040CPWR
THS1040IPW
Tube, 50
Tube and Reel, 2000
Tube, 50
THS1040C
THS1040I
THS1040C
THS1040I
0°C to 70°C
−40°C to 85°C
0°C to 70°C
TH1040
TJ1040
TH1040
TJ1040
TSSOP−28
SOP−28
PW
DW
THS1040IPWR
THS1040CDW
THS1040CDWR
THS1040IDW
THS1040IDWR
Tube and Reel, 2000
Tube, 20
Tube and Reel, 1000
Tube, 20
−40°C to 85°C
Tube and Reel, 1000
†
For the most current specification and package information, refer to the TI web site at www.ti.com.
functional block diagram
Digital
Control
STBY
BIASREF
AIN+
AIN−
3-State
Output
Buffers
10-Bit
ADC
SHA
D (0−9)
OVR
OE
ADC
DV
DD
Mode
MODE
Reference
Resistor
DGND
CLK
Detection
Timing
Circuit
VREF
+
A2
A1
0.5 V
−
AV
DD
AGND
VREF
REFB REFT
REFSENSE
NOTE: A1 − Internal bandgap reference
A2 − Internal ADC reference generator
2
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
Terminal Functions
TERMINAL
NAME
AGND
I/O
DESCRIPTION
NO.
1, 19
27
I
I
I
I
Analog ground
AIN+
AIN−
Positive analog input
Negative analog input
Analog supply
25
AV
DD
28
When the MODE pin is at AV , a buffered AV /2 is present at this pin that can be used by external input
DD
DD
BIASREF
21
O
biasing circuits. The output is high impedance when MODE is AGND or AV /2.
DD
CLK
15
14
2
I
I
I
Clock input
DGND
Digital ground
Digital supply
DV
DD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
3
4
5
6
7
8
9
10
11
12
Digital data bit 0 (LSB)
Digital data bit 1
Digital data bit 2
Digital data bit 3
Digital data bit 4
Digital data bit 5
Digital data bit 6
Digital data bit 7
Digital data bit 8
Digital data bit 9 (MSB)
O
MODE
OE
23
16
13
24
18
22
17
20
26
I
I
Operating mode select (AGND, AV /2, or AV )
DD DD
High to 3-state the data bus, low to enable the data bus
Out-of-range indicator
OVR
O
REFB
REFSENSE
REFT
STBY
TEST
VREF
I/O Bottom ADC reference voltage
VREF mode control
I/O Top ADC reference voltage
I
I
I
Drive high to power-down the THS1040
Production test pin. Tie to DV or DGND
DD
I/O Internal or external reference
3
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range: AV
to AGND, DV
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4 V
DD
DD
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 0.3 V
AV to DV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4 V to 4 V
DD
DD
MODE input voltage range, MODE to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Reference voltage input range, REFT, REFB, to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Analog input voltage range, AIN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Reference input voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Reference output voltage range, VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Clock input voltage range, CLK to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to AV
Digital input voltage range, digital input to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
Digital output voltage range, digital output to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to DV
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
+ 0.3 V
DD
DD
DD
DD
DD
DD
DD
DD
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 150°C
J
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 in) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
over operating free-air temperature range T , (unless otherwise noted)
A
PARAMETER
Power Supply
CONDITION
MIN
NOM
MAX
UNIT
Supply voltage
AV , DV
DD DD
3
3
3.6
V
Analog and Reference Inputs
VREF input voltage
V
V
V
V
(V
REFSENSE = AV
MODE = AGND
MODE = AGND
MODE = AGND
0.5
1.75
1
1
2
V
V
I(VREF)
I(REFT)
I(REFB)
DD
REFT input voltage
REFB input voltage
1.25
1
V
Reference input voltage
Reference common mode voltage
V
0.5
V
I(REFT) − I(REFB)
V
)/2 MODE = AGND
(AV /2) − 0.05 (AV /2) + 0.05
DD DD
V
I(REFT+) I(REFB)
REFSENSE = AGND
REFSENSE = VREF
−1
1
0.5
10
V
Analog input voltage differential (see Note 1)
V
I(AIN)
−0.5
0
V
Analog input capacitance, C
Clock input (see Note 2)
Digital Outputs
pF
V
I
AV
DD
Maximum digital output load resistance
Maximum digital output load capacitance
Digital Inputs
R
C
100
kΩ
L
L
10
pF
High-level input voltage, V
IH
2.4
DV
V
V
DD
0.8
Low-level input voltage, V
IL
DGND
Clock frequency (see Note 3)
Clock pulse duration
t
t
f
f
= 5 MHz to 40 MHz 25
200
13.75
70
nS
nS
c
(CLK)
t
= 40 MHz
11.25
0
12.5
w(CKL), w(CKH)
(CLK)
THS1040C
Operating free-air temperature, T
°C
A
THS1040I
−40
85
NOTE 1:
V
is AIN+ − AIN− range, based on V
V
=1V.Varies proportional to the V
V
value. Input common mode
I(AIN)
I(REFT)− I(REFB)
I(REFT)− I(REFB)
voltage is recommended to be AV /2.
DD
NOTE 2: The clock pin is referenced to AV
NOTE 3: Clock frequency can be extended to this range without degradation of performance.
and powered by AV
.
SS
DD
4
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AV
= 3 V, DV
= 3 V, f = 40 MSPS/50% duty cycle, MODE = AV
(internal reference),
DD
A
DD
s
DD
differential input range = 1 V
and 2 V , T = T
PP min
to T (unless otherwise noted)
max
PP
power supply
PARAMETER
TEST CONDITIONS
MIN
3
TYP
MAX
3.6
UNIT
AV
DD
Supply voltage
V
DV
3
3.6
DD
I
Operating supply current
Power dissipation
Standby power
See Note 4
See Note 4
33
100
75
40
mA
mW
µW
CC
P
P
120
D
D(STBY)
Power up time for all references from standby, t
Wake-up time
10 µF bypass
770
45
µs
µs
(PU)
t
See Note 5
(WU)
REFT, REFB internal ADC reference voltages outputs (MODE = AV
or AV /2) (See Note 6)
DD
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
1.75
2
MAX
UNIT
VREF = 0.5 V
VREF = 1 V
VREF = 0.5 V
VREF = 1 V
Reference voltage top, REFT
AV
= 3 V
= 3 V
V
DD
DD
1.25
1
Reference voltage bottom, REFB
AV
V
Input resistance between REFT and REFB
1.4
1.9
2.5
kΩ
VREF (on-chip voltage reference generator)
PARAMETER
MIN
0.45
0.95
7
TYP
0.5
1
MAX
0.55
1.05
21
UNIT
V
Internal 0.5-V reference voltage (REFSENSE = VREF)
Internal 1-V reference voltage (REFSENSE = AGND)
V
Reference input resistance (REFSENSE = AV , MODE = AV /2 or AV )
DD
14
kΩ
DD
DD
dc accuracy
PARAMETER
MIN
TYP
10
MAX
UNIT
Bits
Resolution
Integral nonlinearity (see definitions)
INL
−1.5
−0.9
−1.5
−3
0.75
0.45
0.7
1.5
0.9
LSB
LSB
DNL
Differential nonlinearity (see definitions)
Zero error (see definitions)
Full-scale error (see definitions)
Missing code
1.5 %FSR
%FSR
2.2
3
No missing code assured
NOTE 4: Apply a −1 dBFS 10-KHz triangle wave at AIN+ and AIN− with an internal bandgap reference and ADC reference enabled, and BIASREF
enabled at AV /2. Any additional load at BIASREF or VREF may require additional current.
DD
NOTE 5: Wake-up time is from the power-down state to accurate ADC samples being taken and is specified for MODE = AGND with external
reference sources applied to the device at the time of release of power-down, and an applied 40-MHz clock. Circuits that need to power
up are the bandgap, bias generator, ADC, and SHA.
NOTE 6: External reference values are listed in the Recommended Operating Conditions Table.
5
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
electrical characteristics
over recommended operating conditions, AV
= 3 V, DV
= 3 V, f = 40 MSPS/50% duty cycle, MODE = AV
(unless otherwise noted) (continued)
(internal reference),
DD
and 2 V , T = T
DD
s
DD
differential input range = 1 V
PP
to T
max
PP
A
min
dynamic performance (ADC)
PARAMETER
TEST CONDITIONS
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
f = 4.8 MHz, −0.5 dBFS
f = 20 MHz, −0.5 dBFS
MIN
TYP
9.6
9.5
72
MAX
UNIT
8.8
ENOB
SFDR
THD
Effective number of bits
Bits
60.5
Spurious free dynamic range
Total harmonic distortion
Signal-to-noise ratio
dB
dB
dB
70
−72.5 −61.3
−71.6
60
55.7
55.6
SNR
57
59.7
59.6
900
SINAD Signal-to-noise and distortion
BW Full power bandwidth (−3 dB)
dB
MHz
digital specifications
PARAMETER
MIN
NOM
MAX
UNIT
Digital Inputs
Clock input
0.8 × AV
0.8 × DV
DD
V
High-level input voltage
Low-level input voltage
V
V
IH
IL
All other inputs
Clock input
DD
0.2 × AV
0.2 × DV
DD
V
All other inputs
DD
1
I
I
High-level input current
Low-level input current
Input capacitance
µA
µA
pF
IH
|−1|
IL
C
5
i
Digital Outputs
V
High-level output voltage
Low-level output voltage
I
I
= 50 µA
DV −0.4
DD
V
V
OH
OL
load
V
= −50 µA
0.4
1
load
High-impedance output current
Rise/fall time
µA
ns
C
= 15 pF
3.5
load
Clock Input
t
t
t
Clock cycle time
25
11.25
11.25
45%
200
110
110
55%
16
ns
ns
ns
c
Pulse duration, clock high
Pulse duration, clock low
Clock duty cycle
w(CKH)
w(CKL)
50%
9.5
4
t
Clock to data valid, delay time
Pipeline latency
ns
Cycles
ns
d(o)
t
Aperture delay time
0.1
1
d(AP)
Aperture uncertainty (jitter)
ps
timing
PARAMETER
MIN
0
TYP
MAX
10
UNIT
ns
t
t
Output disable to Hi-Z output, delay time
Output enable to output valid, delay time
d(DZ)
0
10
ns
d(DEN)
V
Output voltage
MODE = AV
(AV /2) − 0.1
DD
(AV /2) + 0.1
DD
V
O(BIASREF)
DD
6
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PARAMETER MEASUREMENT INFORMATION
Sample 2
Sample 3
Sample 6
Sample 7
Sample 1
Sample 5
Sample 4
Analog
Input
t
c
t
w(CKL)
t
w(CKH)
Input Clock
See
Note A
t
d(o)
(I/O Pad Delay or
Pipeline Latency
Propagation Delay)
Digital
Output
Sample 1
Sample 2
t
t
d(DZ)
d(DEN)
OE
NOTE A: All timing measurements are based on 50% of edge transition.
Figure 1. Digital Output Timing Diagram
7
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
DIFFERENTIAL NONLINEARITY
vs
INPUT CODE
1.0
0.5
AV
DD
= 3 V
= 3 V
DV
DD
f
V
= 40 MSPS
s
= 1 V
ref
0.0
−0.5
−1.0
0
128
256
384
512
640
768
768
768
896
896
896
1024
1024
1024
Input Code
Figure 2
INTEGRAL NONLINEARITY
vs
INPUT CODE
1.0
0.5
0.0
AV
DD
= 3 V
= 3 V
= 40 MSPS
= 1 V
128
−0.5
−1.0
DV
DD
f
V
s
ref
0
256
384
512
640
Input Code
Figure 3
INTEGRAL NONLINEARITY
vs
INPUT CODE
1.0
0.5
AV
DD
DD
= 40 MSPS
= 3 V
= 3 V
DV
f
V
s
= 0.5 V
ref
0.0
−0.5
−1.0
0
128
256
384
512
640
Input Code
Figure 4
8
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
−80
−75
−70
−85
−80
1-V FS Differential Input Range
2-V FS Differential Input Range
−0.5 dBFS
−75
−70
−65
−0.5 dBFS
−6 dBFS
−65
−6 dBFS
−60
−55
−60
−55
−20 dBFS
−20 dBFS
−50
−45
−40
−50
−45
−40
See Note
See Note
0
10 20 30 40 50 60 70 80 90 100110 120
0
10 20 30 40 50 60 70 80 90 100 110 120
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 5
Figure 6
SIGNAL-TO-NOISE RATIO
vs
SPURIOUS FREE DYNAMIC RANGE
vs
INPUT FREQUENCY
INPUT FREQUENCY
61
59
57
55
53
51
Diff Input = 2 V
SE Input = 2 V
82
72
62
52
42
32
Diff Input = 2 V
Diff Input = 1 V
Diff Input = 1 V
SE Input = 1 V
49
47
SE Input = 1 V
See Note
See Note
SE Input = 2 V
0
10 20 30 40 50 60 70 80 90 100 110 120
0
10 20 30 40 50 60 70 80 90 100 110 120
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 7
Figure 8
NOTE: AV
= DV
DD
= 3 V,
f = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
S
DD
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
9
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
SIGNAL-TO-NOISE PLUS DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
INPUT FREQUENCY
INPUT FREQUENCY
Diff Input = 2 V
Diff Input = 1 V
−82
−72
−62
−52
−42
−32
Diff Input = 2 V
Diff Input = 1 V
57
52
47
42
37
32
SE Input = 1 V
SE Input = 2 V
SE Input = 1 V
SE Input = 2 V
See Note
See Note
0
10 20 30 40 50 60 70 80 90 100 110 120
0
10 20 30 40 50 60 70 80 90 100 110 120
f − Input Frequency − MHz
i
f − Input Frequency − MHz
i
Figure 9
Figure 10
NOTE: AV
= DV = 3 V, f = 40 MSPS, 20-pF capacitors AIN+ to AGND and AIN− to AGND,
DD
DD S
Input series resistor = 25 Ω,
2-V Input: Ext Ref, REFT = 2 V, REFB = 1 V, −0.5 dBFS
1-V Input: Ext Ref, REFT = 1.75 V, REFB = 1.25 V, −0.5 dBFS
TOTAL HARMONIC DISTORTION
SIGNAL-TO-NOISE RATIO
vs
vs
SAMPLE RATE
SAMPLE RATE
−75
75
70
65
60
55
50
−70
−65
−60
−55
−50
−45
−40
45
40
Diff Input = 2 V
f = 20 MHz, −0.5 dBFS
i
Diff Input = 2 V
f = 20 MHz, −0.5 dBFS
i
0
5
10 15 20 25 30 35 40 45 50 55
Sample Rate − MSPS
0
5
10 15 20 25 30 35 40 45 50 55
Sample Rate − MSPS
Figure 12
Figure 11
10
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
TOTAL CURRENT
vs
CLOCK FREQUENCY
POWER DISSIPATION
vs
SAMPLE RATE
AV
= 3 V
= 1 V
DD
AV
= 3 V,
= 1 V
DD
36
V
ref
V
ref
34
32
110
90
Int. Ref
Int. Ref
T
= 25°C
A
T
= 25°C
A
Ext. Ref
= 25°C
30
28
T
A
Ext. Ref
= 25°C
T
A
26
24
70
4
8
12 16 20 24 28 32 36 40 44
0
5
10 15 20 25 30 35 40 45
f
− Sample Rate − MSPS
f
− Clock Frequency − MHz
s
clk
Figure 13
Figure 14
INPUT BANDWIDTH
4
AV
DD
= 3 V
= 3 V
DV
DD
= 40 MSPS
f
2
s
0
−2
−4
−6
−8
See Note
100
10
300
500
700
900
1100
f − Input Frequency − MHz
i
Figure 15
NOTE: No series resistors and no bypass capacitors at AIN+ and AIN− inputs.
11
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
ADC CODES
vs
WAKE-UP SETTLING TIME
POWER-UP TIME FOR INTERNAL
REFERENCE VOLTAGE FROM STANDBY
125
120
115
110
105
100
2.4
V
= 1 V, Reft = 10 µF,
ref
Refb = 10 µF, AV
MODE = AGND,
= 3 V
DD
f
= 40 MSPS,
S
Ext. REF = 1 V and 2 V,
AV = 3 V
2
DD
V
reft
1.6
1.2
0.8
0.4
0
V
refb
95
90
See Note
80 95
−10
5
20
35
50
65
110
Wake-Up Settling Time − µs
Power-Up Time − µs
Figure 16
Figure 17
12
www.ti.com
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
TYPICAL CHARACTERISTICS
FFT
20
f = 10 MHz, −0.5 dBFS
i
0
f
= 40 MSPS,
S
−20
Diff Input = 2 V
−40
−60
−80
−100
−120
−140
5
10
15
20
0
f − Frequency − MHz
Figure 18
FFT
20
f = 4.5 MHz, −0.5 dBFS
i
0
−20
−40
f
= 40 MSPS,
S
Diff Inpt = 2 V
−60
−80
−100
−120
−140
5
10
15
20
0
f − Frequency − MHz
Figure 19
13
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
functional overview
See the functional block diagram. A single-ended, sample rate clock is required at pin CLK for device operation.
Analog inputs AIN+ and AIN− are sampled on each rising edge of CLK in a switched capacitor sample and hold
unit, the output of which feeds the ADC core, where analog-to-digital conversion is performed against the ADC
reference voltages REFT and REFB.
Internal or external ADC reference voltage configurations are selected by connecting the MODE pin
appropriately. When MODE = AGND, the user must provide external sources at pins REFB and REFT. When
MODE =AV
or MODE = AV /2, an internal ADC references generator(A2) is enabled which drives the REFT
DD
DD
and REFB pins using the voltage at pin VREF as its input. The user can choose to drive VREF from the internal
bandgap reference, or disable A1 and provide their own reference voltage at pin VREF.
On the fourth rising CLK edge following the edge that sampled AIN+ and AIN−, the conversion result is output
via data pins D0 to D9. The output buffers can be disabled by pulling pin OE high.
The following sections explain further:
D
D
D
How signals flow from AIN+ and AIN− to the ADC core, and how the reference voltages at REFT and REFB
set the ADC input range and hence the input range at AIN+ and AIN−.
How to set the ADC references REFT and REFB using external sources or the internal reference buffer (A2)
to match the device input range to the input signal.
How to set the output of the internal bandgap reference (A1) if required.
signal processing chain (sample and hold, ADC)
Figure 20 shows the signal flow through the sample and hold unit to the ADC core.
REFT
VQ+
Sample
and
Hold
ADC
Core
X1
AIN+
AIN−
X−1
VQ−
REFB
Figure 20. Analog Input Signal Flow
14
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
sample-and-hold
Differential input signal sources can be connected directly to the AIN+ and AIN− pins using either dc- or
ac-coupling.
For single-ended sources, the signal can be dc- or ac-coupled to one of AIN+ or AIN−, and a suitable reference
voltage (usually the midscale voltage, see operating configuration examples) must be applied to the other pin.
Note that connecting the signal to AIN− results in it being inverted during sampling.
The sample and hold differential output voltage VQ = (VQ+) − (VQ−) is given by:
VQ = (AIN+) − (AIN−)
(1)
analog-to-digital converter
VQ is digitized by the ADC, using the voltages at pins REFT and REFB to set the ADC zero-scale (code 0) and
full-scale (code 1023) input voltages.
(2)
(3)
VQ(ZS) + * (REFT * REFB)
VQ(FS) + (REFT * REFB)
Any inputs at AIN+ and AIN− that give VQ voltages less than VQ(ZS) or greater than VQ(FS) lie outside the
ADC’s conversion range and attempts to convert such voltages are signalled by driving pin OVR high when the
conversion result is output. VQ voltages less than VQ(ZS) digitize to give ADC output code 0 and VQ voltages
greater than VQ(FS) give ADC output code 1023.
complete system and system input range
Combining the above equations to find the input voltages [(AIN+) − (AIN−)] that correspond to the limits of the
ADC’s valid input range gives:
(4)
[(
)
(
)]
(REFB * REFT) v AIN) * AIN* v (REFT * REFB)
For both single-ended and differential inputs, the ADC can thus handle signals with a peak-to-peak input range
[(AIN+) − (AIN−)] of:
[(AIN+) − (AIN−)] pk-pk input range = 2 x (REFT − REFB)
(5)
The REFT and REFB voltage difference and the gain sets the device input range. The next sections describe
in detail the various methods available for setting voltages REFT and REFB to obtain the desired input span
and device performance.
15
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
ADC reference generation
The THS1040 ADC references REFT and REFB can be driven from external (off-chip) sources or from the
internal (on-chip) reference buffer A2. The voltage at the MODE pin determines the ADC references source.
Connecting MODE to AGND enables external ADC references mode. In this mode the internal buffer A2 is
powered down and the user must provide the REFT and REFB voltages by connecting external sources directly
to these pins. This mode is useful where several THS1040 devices must share common references for best
matching of their ADC input ranges, or when the application requires better accuracy and temperature stability
than the on-chip reference source can provide.
Connecting MODE to AV
or AV /2 enables internal ADC references mode. In this mode the buffer A2 is
DD
DD
powered up and drives the REFT and REFB pins. External reference sources should not be connected in this
mode. Using internal ADC references mode when possible helps to reduce the component count and hence
the system cost.
When MODE is connected to AV , a buffered AV /2 voltage is available at the BIASREF pin. This voltage
DD
DD
can be used as a dc bias level for any ac-coupling networks connecting the input signal sources to the AIN+
and AIN− pins.
MODE PIN
REFERENCE SELECTION
BIASREF PIN FUNCTION
High impedance
AGND
External
Internal
Internal
AV /2
DD
High impedance
AV
DD
AV /2 for AIN bias
DD
external reference mode (MODE = AGND)
Sample
and
Hold
ADC
Core
X1
AIN+
AIN−
X−1
Internal
Reference
Buffer
VREF
REFT
REFB
Figure 21. ADC Reference Generation, MODE = AGND
Connecting pin MODE to AGND powers down the internal references buffer A2 and disconnects its outputs from
the REFT and REFB pins. The user must connect REFT and REFB to external sources to provide the ADC
reference voltages required to match the THS1040 input range to their application requirements. The
common-mode reference voltage must be AV /2 for correct THS1040 operation:
DD
(6)
AV
(REFT ) REFB)
DD
+
2
2
16
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV or AV /2)
DD
DD
AV
DD
+ VREF
2
Sample
and
Hold
ADC
Core
X1
AIN+
AIN−
X−1
AV
DD
− VREF
2
Internal
Reference
Buffer
VREF
AGND
Figure 22. ADC Reference Generation, MODE = AV /2
DD
Connecting MODE to AV
or AV /2 enables the internal ADC references buffer A2. The outputs of A2 are
DD
DD
connected to the REFT and REFB pins and its inputs are connected to pins VREF and AGND. The resulting
voltages at REFT and REFB are:
(7)
ǒ
Ǔ
AV
) VREF
DD
DD
REFT +
2
(8)
ǒ
Ǔ
AV
* VREF
REFB +
2
Depending on the connection of the REFSENSE pin, the voltage on VREF may be driven by an off-chip source
or by the internal bandgap reference A1 (see onboard reference generator) to match the THS1040 input range
to their application requirements.
When MODE = AV
the BIASREF pin provides a buffered, stabilized AV /2 output voltage that can be used
DD
DD
as a bias reference for ac coupling networks connecting the signal sources to the AIN+ or AIN− inputs. This
removes the need for the user to provide a stabilized external bias reference.
17
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
internal reference mode (MODE = AV
or AV /2) (continued)
DD
DD
AV
DD
2
AV
DD
or
+FS
AIN+
AIN+
AIN−
MODE
−FS
+FS
AIN−
−FS
REFSENSE
0.1 µF
1 V (Output)
REFT
REFB
VREF
V
if MODE = AV
DD
MID
10 µF
0.1 µF
BIASREF
AV
DD
2
0.1 µF
High-Impedance if MODE =
Figure 23. Internal Reference Mode, 1-V Reference Span
AV
DD
2
or AV
DD
+FS
VM
−FS
AIN+
AIN−
MODE
DC SOURCE = VM
VM
+
_
0.1 µF
REFT
REFB
0.5 V (Output)
VREF
10 µF
0.1 µF
0.1 µF
REFSENSE
Figure 24. Internal Reference Mode, 0.5-V Reference Span, Single-Ended Input
18
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration
The internal bandgap reference A1 can provide a supply-voltage-independent and temperature-independent
voltage on pin VREF.
External connections to REFSENSE control A1’s output to the VREF pin as shown in Table 1.
Table 1. Effect of REFSENSE Connection on VREF Value
REFSENSE CONNECTION
VREF pin
A1 OUTPUT TO VREF
SEE:
0.5 V
1 V
Figure 25
Figure 26
Figure 27
Figure 28
AGND
External divider junction
(1 + R /R )/2 V
a b
AV
DD
Open circuit
REFSENSE = AV
If MODE is connected to AV
powers the internal bandgap reference A1 down, saving power when A1 is not required.
DD
or AV /2, then the voltage at VREF determines the ADC reference voltages:
DD
DD
AV
(9)
DD VREF
REFT +
REFB +
)
2
2
(10)
AV
DD VREF
*
2
2
(11)
REFT–REFB + VREF
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
2
+
_
VREF = 0.5 V
REFSENSE
+
VBG
_
0.1 µF 1 µF
AGND
Figure 25. 0.5-V VREF Using the Internal Bandgap Reference A1
19
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
DD
2
or AV
DD
+
_
VREF = 1 V
REFSENSE
+
VBG
_
0.1 µF 1 µF
10 kΩ
10 kΩ
AGND
Figure 26. 1-V VREF Using the Internal Bandgap Reference A1
ADC
References
Buffer A2
MODE =
AV
DD
or AV
DD
2
VREF = (1 + R /R )/2
+
_
a
b
+
VBG
_
0.1 µF 1 µF
Ra
REFSENSE
Rb
AGND
Figure 27. External Divider Mode
20
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
onboard reference generator configuration (continued)
ADC
References
Buffer A2
MODE =
AV
DD
2
or AV
DD
VREF = External
REFSENSE
+
_
+
VBG
_
AV
DD
AGND
Figure 28. Drive VREF Mode
operating configuration examples
Figure 29 shows a configuration using the internal ADC references for digitizing a single-ended signal with span
0 V to 2 V. Tying REFSENSE to ground gives 1 V at pin VREF. Tying MODE to AV /2 then sets the REFT and
DD
REFB voltages via the internal reference generator for a 2-V
ADC input range. The VREF pin provides the
p-p
1-V mid-scale bias voltage required at AIN−. VREF should be well decoupled to AGND to prevent
sample-and-hold switching at AIN− from corrupting the VREF voltage.
AV /2
DD
2 V
20 Ω
AIN+
AIN−
1 V
0 V
MODE
20 pF
20 Ω
20 pF
10 µF
VREF = 1 V
REFT
0.1 µF
10 µF
0.1 µF
REFSENSE
REFB
0.1 µF
Figure 29. Operating Configuration: 2-V Single-Ended Input, Internal ADC References
21
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
operating configuration examples (continued)
Figure 30 shows a configuration using the internal ADC references for digitizing a dc-coupled differential input
with 1.5-V
span and 1.5-V common-mode voltage. External resistors are used to set the internal bandgap
p-p
reference output at VREF to 0.75 V. Tying MODE to AV
reference generator for a 1.5-V
then sets the REFT and REFB voltages via the internal
DD
ADC input range.
p-p
If a transformer is used to generate the differential ADC input from a single-ended signal, then the BIASREF
pin provides a suitable bias voltage for the secondary windings center tap when MODE = AV
.
DD
AV
DD
1.875 V
20 Ω
20 Ω
AIN+
AIN−
MODE
1.5 V
1.125 V
20 pF
20 pF
1.875 V
1.5 V
1.125 V
VREF = 0.75 V
REFSENSE
5 kΩ
0.1 µF
10 µF
REFT
10 kΩ
10 µF
0.1 µF
REFB
0.1 µF
Figure 30. Operating Configuration: 1.5-V Differential Input, Internal ADC References
Figure 31 shows a configuration using the internal ADC references and an external VREF source for digitizing
a dc-coupled single-ended input with span 0.5 V to 2 V. A 1.25-V external source provides the bias voltage for
the AIN− pin and also, via a buffered potential divider, the 0.75 VREF voltage required to set the input range
to 1.5 V
MODE is tied to AV
to set internal ADC references configuration.
p-p
DD
AV
DD
2 V
20 Ω
AIN+
MODE
1.25 V
0.5 V
20 pF
20 pF
0.1 µF
20 Ω
1.25
Source
AIN−
REFT
REFB
10 µF
0.1 µF
10 kΩ
_
VREF
10 µF
+
(0.75 V)
0.1 µF
15 kΩ
AV
REFSENSE
DD
Figure 31. Operating Configuration: 1.5-V Single-Ended Input, External VREF Source
22
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
PRINCIPLES OF OPERATION
power management
In power-sensitive applications (such as battery-powered systems) where the THS1040 is not required to
convert continuously, power can be saved between conversion intervals by placing the THS1040 into
power-down mode. This is achieved by pulling the STBY pin high. In power-down mode, the device typically
consumes less than 0.1 mW of power.
If the internal VREF generator (A1) is not required, it can be powered down by tying pin REFSENSE to AV
saving approximately 1.2 mA of supply current.
,
DD
If the BIASREF function is not required when using internal references then tying MODE to AV /2 powers the
DD
BIASREF buffer down, saving approximately 1.2 mA.
digital I/O
While the OE pin is held low, ADC conversion results are output at pins D0 (LSB) to D9 (MSB). The ADC input
over-range indicator is output at pin OVR. OVR is also disabled when OE is held high.
The only ADC output data format supported is unsigned binary (output codes 0 to 1023). Twos complement
output (output codes −512 to 511) can be obtained by using an external inverter to invert the D9 output.
23
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the THS1040 analog inputs
driving the clock input
Obtaining good performance from the THS1040 requires care when driving the clock input.
Different sections of the sample-and-hold and ADC operate while the clock is low or high. The user should
ensure that the clock duty cycle remains near 50% to ensure that all internal circuits have as much time as
possible in which to operate.
The CLK pin should also be driven from a low jitter source for best dynamic performance. To maintain low jitter
at the CLK input, any clock buffers external to the THS1040 should have fast rising edges. Use a fast logic family
such as AC or ACT to drive the CLK pin, and consider powering any clock buffers separately from any other
logic on the PCB to prevent digital supply noise appearing on the buffered clock edges as jitter.
As the CLK input threshold is nominally around AV /2, any clock buffers need to have an appropriate supply
DD
voltage to drive above and below this level.
driving the sample and hold inputs
driving the AIN+ and AIN− pins
Figure 32 shows an equivalent circuit for the THS1040 AIN+ and AIN− pins. The load presented to the system
at the AIN pins comprises the switched input sampling capacitor, C
, and various stray capacitances, C
Sample
1
and C .
2
AV
DD
CLK
1.2 pF
C
AIN
C1
8 pF
C2
1.2 pF
Sample
AGND
CLK
+
_
VCM = AIN+/AIN− Common Mode Voltage
Figure 32. Equivalent Circuit for Analog Input Pins AIN+ and AIN−
The input current pulses required to charge C
circuit modelled as an equivalent resistor:
and C can be time averaged and the switched capacitor
2
Sample
(12)
1
f
R
+
IN2
C
S
CLK
where C is the sum of C
resistance for high impedance sources.
and C . This model can be used to approximate the input loading versus source
2
S
Sample
24
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
AV
DD
R2 = 1/C
f
S CLK
AIN
I
IN
C1
8 pF
+
_
VCM = AIN+/AIN− Common Mode Voltage
AGND
Figure 33. Equivalent Circuit for the AIN Switched Capacitor Input
AIN input damping
The charging current pulses into AIN+ and AIN− can make the signal sources jump or ring, especially if the
sources are slightly inductive at high frequencies. Inserting a small series resistor of 20 Ω or less and a small
capacitor to ground of 20 pF or less in the input path can damp source ringing (see Figure 34). The resistor and
capacitor values can be made larger than 20 Ω and 20 pF if reduced input bandwidth and a slight gain error (due
to potential division between the external resistors and the AIN equivalent resistors) are acceptable.
Note that the capacitors should be soldered to a clean analog ground with a common ground point to prevent
any voltage drops in the ground plane appearing as a differential voltage at the ADC inputs.
R < 20 Ω
AIN
V
S
C < 20 pF
Figure 34. Damping Source Ringing Using a Small Resistor and Capacitor
driving the VREF pin
Figure 35 shows the equivalent load on the VREF pin when driving the ADC internal references buffer via this
pin (MODE = AV /2 or AV
and REFSENSE = AV ).
DD
DD
DD
AV
DD
R
IN
VREF
10 kΩ
MODE = AV
REFSENSE = AV
MODE = AV /2 or AV
DD DD
,
DD
DD
AGND
+
(AV
DD
+ VREF) /4
_
Figure 35. Equivalent Circuit of VREF
The nominal input current I
3 V
is given by:
REF
(13)
* AV
REF
DD
I
+
REF
4 R
IN
25
www.ti.com
ꢀ ꢁꢂ ꢃ ꢄꢅ ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
driving the VREF pin (continued)
Note that the maximum current may be up to 30% higher. The user should ensure that VREF is driven from a
low noise, low drift source, well decoupled to analog ground and capable of driving the maximum I
.
REF
driving REFT and REFB (external ADC references, MODE = AGND)
AV
DD
To ADC Core
REFT
AGND
2 kΩ
AV
DD
REFB
To ADC Core
AGND
Figure 36. Equivalent Circuit of REFT and REFB Inputs
reference decoupling
VREF pin
When the on-chip reference generator is enabled, the VREF pin should be decoupled to the circuit board’s
analog ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
REFT and REFB pins
In any mode of operation, the REFT and REFB pins should be decoupled as shown in Figure 37. Use short
board traces between the THS1040 and the capacitors to minimize parasitic inductance.
0.1 µF
REFT
THS1040
0.1 µF
10 µF
REFB
0.1 µF
Figure 37. Recommended Decoupling for the ADC Reference Pins REFT and REFB
BIASREF pin
When using the on-chip BIASREF source, the BIASREF pin should be decoupled to the circuit board’s analog
ground plane close to the THS1040 AGND pin via a 1-µF capacitor and a 0.1-µF ceramic capacitor.
26
www.ti.com
ꢀꢁ ꢂ ꢃꢄ ꢅꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
supply decoupling
The analog (AV , AGND) and digital (DV , DGND) power supplies to the THS1040 must be separately
DD
DD
decoupled for best performance. Each supply needs at least a 10-µF electrolytic or tantalum capacitor (as a
charge reservoir) and a 100-nF ceramic type capacitor placed as close as possible to the respective pins (to
suppress spikes and supply noise).
digital output loading and circuit board layout
The THS1040 outputs are capable of driving rail-to-rail with up to 10 pF of load per pin at 40-MHz clock frequency
and 3-V digital supply. Minimizing the load on the outputs improves THS1040 signal-to-noise performance by
reducing the switching noise coupling from the THS1040 output buffers to the internal analog circuits. The
output load capacitance can be minimized by buffering the THS1040 digital outputs with a low input capacitance
buffer placed as close to the output pins as physically possible, and by using the shortest possible tracks
between the THS1040 and this buffer. Inserting small resistors in the range 100 Ω to 300 Ω between the
THS1040 I/O outputs and their loads can help minimize the output-related noise in noise-critical applications.
Noise levels at the output buffers, which may affect the analog circuits within THS1040, increase with the digital
supply voltage. Where possible, consider using the lowest DV
that the application can tolerate.
DD
Use good layout practices when designing the application PCB to ensure that any off-chip return currents from
the THS1040 digital outputs (and any other digital circuits on the PCB) do not return via the supplies to any
sensitive analog circuits. The THS1040 should be soldered directly to the PCB for best performance. Socketing
the device degrades performance by adding parasitic socket inductance and capacitance to all pins.
user tips for obtaining best performance from the THS1040
D
D
D
D
Choose differential input mode for best distortion performance.
Choose a 2-V ADC input span for best noise performance.
Choose a 1-V ADC input span for best distortion performance.
Drive the clock input CLK from a low-jitter, fast logic stage, with a well-decoupled power supply and short
PCB traces.
D
Use a small RC filter (typically 20 Ω and 20 pF) between the signal source(s) the AIN+ (and AIN−) input(s)
when the systems bandwidth requirements allow this.
27
www.ti.com
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢄ
SLAS290C − OCTOBER 2001 − REVISED OCTOBER 2004
APPLICATION INFORMATION
definitions
D
Integral nonlinearity (INL)—Integral nonlinearity refers to the deviation of each individual code from a line
drawn from zero to full scale. The point used as zero occurs 1/2 LSB before the first code transition. The
full-scale point is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from
the center of each particular code to the true straight line between these two endpoints.
D
Differential nonlinearity (DNL)—An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL
is the deviation from this ideal value. Therefore this measure indicates how uniform the transfer function
step sizes are. The ideal step size is defined here as the step size for the device under test (i.e., (last
transition level – first transition level) ÷ (2 – 2)). Using this definition for DNL separates the effects of gain
and offset error. A minimum DNL better than –1 LSB ensures no missing codes.
n
D
D
Zero-error—Zero-error is defined as the difference in analog input voltage—between the ideal voltage and
the actual voltage—that switches the ADC output from code 0 to code 1. The ideal voltage level is
determined by adding the voltage corresponding to 1/2 LSB to the bottom reference level. The voltage
corresponding to 1 LSB is found from the difference of top and bottom references divided by the number
of ADC output levels (1024).
Full-scale error—Full-scale error is defined as the difference in analog input voltage—between the ideal
voltage and the actual voltage—that switches the ADC output from code 1022 to code 1023. The ideal
voltage level is determined by subtracting the voltage corresponding to 1.5 LSB from the top reference level.
The voltage corresponding to 1 LSB is found from the difference of top and bottom references divided by
the number of ADC output levels (1024).
D
D
Wake-up time—Wake-up time is from the power-down state to accurate ADC samples being taken and is
specified for MODE = AGND with external reference sources applied to the device at the time of release
of power-down, and an applied 40-MHz clock. Circuits that need to power up are the bandgap, bias
generator, ADC, and SHA.
Power-up time—Power-up time is from the power-down state to accurate ADC samples being taken and
is specified for MODE = AV /2 or AV
and an applied 40-MHz clock. Circuits that need to power up
DD
DD
include VREF reference generation (A1), bias generator, ADC, the SHA, and the on-chip ADC reference
generator (A2).
D
D
Aperture delay—The delay between the 50% point of the rising edge of the clock and the instant at which
the analog input is sampled.
Aperture uncertainty (Jitter)—The sample-to-sample variation in aperture delay.
28
www.ti.com
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
THS1040CDW
Status (1)
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
28
20
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
THS1040CDWR
SOIC
DW
28
1000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
THS1040CPW
THS1040CPWR
THS1040IDW
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
SOIC
PW
PW
DW
28
28
28
50
2000
20
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
THS1040IDWR
ACTIVE
SOIC
DW
28
1000
Pb-Free
(RoHS)
CU NIPDAU Level-2-250C-1YEAR/
Level-1-220C-UNLIM
THS1040IPW
THS1040IPWR
THS1040IPWRG4
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
PW
PW
PW
28
28
28
50
None
None
CU NIPDAU Level-2-220C-1 YEAR
CU NIPDAU Level-2-220C-1 YEAR
2000
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
相关型号:
THS1040CDWRG4
IC 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28, Analog to Digital Converter
TI
THS1040CPWG4
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28
TI
THS1040CPWRG4
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28
TI
THS1040IDWG4
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28
TI
THS1040IDWRG4
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, SOIC-28
TI
THS1040IPWG4
1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28, GREEN, PLASTIC, TSSOP-28
TI
©2020 ICPDF网 联系我们和版权申明