THS3091IDGNR [TI]
单路、高电压、低失真电流反馈运算放大器 | DGN | 8 | -40 to 85;
| 型号： | THS3091IDGNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 单路、高电压、低失真电流反馈运算放大器 | DGN | 8 | -40 to 85 放大器 运算放大器 |
| 文件： | 总31页 (文件大小：1059K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
HIGH-VOLTAGE, LOW-DISTORTION, CURRENT-FEEDBACK
OPERATIONAL AMPLIFIERS
FEATURES
DESCRIPTION
•
Low Distortion
The THS3091 and THS3095 are high-voltage,
low-distortion, high-speed, current-feedback
amplifiers designed to operate over a wide supply
range of ±5 V to ±15 V for applications requiring
large, linear output signals such as Pin, Power FET,
and VDSL line drivers.
– 77 dBc HD2 at 10 MHz, RL = 1 kΩ
– 69 dBc HD3 at 10 MHz, RL = 1 kΩ
Low Noise
•
– 14 pA/√Hz Noninverting Current Noise
– 17 pA/√Hz Inverting Current Noise
– 2 nV/√Hz Voltage Noise
The THS3095 features a power-down pin (PD) that
puts the amplifier in low power standby mode, and
lowers the quiescent current from 9.5 mA to 500 µA.
•
•
•
•
•
High Slew Rate: 7300 V/µs (G = 5, VO = 20 VPP
Wide Bandwidth: 210 MHz (G = 2, RL = 100 Ω)
High Output Current Drive: ±250 mA
Wide Supply Range: ±5 V to ±15 V
Power-Down Feature: (THS3095 Only)
)
The wide supply range combined with total harmonic
distortion as low as -69 dBc at 10 MHz, in addition, to
the high slew rate of 7300 V/µs makes the
THS3091/5 ideally suited for high-voltage arbitrary
waveform driver applications. Moreover, having the
ability to handle large voltage swings driving into
high-resistance and high-capacitance loads while
maintaining good settling time performance makes
the devices ideal for Pin driver and PowerFET driver
applications.
APPLICATIONS
•
•
•
•
High-Voltage Arbitrary Waveform
Power FET Driver
Pin Driver
VDSL Line Driver
The THS3091 and THS3095 are offered in an 8-pin
SOIC (D), and the 8-pin SOIC (DDA) packages with
PowerPAD™.
TYPICAL ARBITARY WAVEFORM
GENERATOR OUTPUT DRIVE CIRCUIT
TOTAL HARMONIC DISTORTION
vs
FREQUENCY
−20
G = 5,
V
= 20 V
PP
O
R
R
= 1 kΩ,
= 100 Ω,
= ±15 V
F
L
−30
−40
−
+
THS3091
V
S
V
= 10 V
PP
O
−50
−60
−70
V
OUT
−
+
IOUT1
DAC5686
IOUT2
−
+
THS3091
V
= 5 V
PP
O
THS4271
−80
−90
V
= 2 V
PP
O
100 k
1 M
10 M
100 M
−
+
f − Frequency − Hz
THS3091
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
UNLESS OTHERWISE NOTED this document contains PRO-
DUCTION DATA information current as of publication date. Prod-
ucts conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
Copyright © 2003–2004, Texas Instruments Incorporated
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
TOP VIEW
D, DDA
TOP VIEW
D, DDA
THS3095
THS3091
NC
NC
REF
PD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
IN−
V
IN+
V
V
V
IN−
V
IN+
V
V
S+
S+
OUT
OUT
V
S−
NC
V
S−
NC
NC = No Internal Connection
NC = No Internal Connection
See Note A.
Note A: The devices with the power−down option defaults to the ON state if no signal is applied to the PD pin. Additionallly, the REF
pin functional range is from V to (V − 4 V).
S−
S+
ODERING INFORMATION
PART NUMBER
THS3091D
PACKAGE TYPE
TRANSPORT MEDIA, QUANTITY
Rails, 75
SOIC-8
THS3091DR
Tape and Reel, 2500
Rails, 75
THS3091DDA
THS3091DDAR
SOIC-8-PP(1)
Tape and Reel, 2500
Power-down
THS3095D
THS3095DR
Rails, 75
SOIC-8
Tape and Reel, 2500
Rails, 75
THS3095DDA
THS3095DDAR
SOIC-8-PP(1)
Tape and Reel, 2500
(1) The PowerPAD is electrically isolated from all other pins.
DISSIPATION RATING TABLE
(2)
POWER RATING
TJ = 125°C
PACKAGE
ΘJC (°C/W)
ΘJA (°C/W)(1)
TA = 25°C
1.02 W
TA = 85°C
410 mW
873 mW
D-8
DDA-8(3)
38.3
9.2
97.5
45.8
2.18 W
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and
long-term reliability.
(3) The THS3091 and THS3095 may incorporate a PowerPAD™ on the underside of the chip. This acts as a heatsink and must be
connected to a thermally dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI Technical Brief SLMA002 for more information about utilizing the
PowerPAD™ thermally enhanced package.
2
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
RECOMMENDED OPERATING CONDITIONS
MIN
±5
MAX UNIT
Dual supply
Supply voltage
±15
V
Single supply
10
30
TA Operating free-air temperature
-40
85
°C
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted)(1)
UNIT
33 V
VS- to VS+ Supply voltage
VI
Input voltage
± VS
VID
IO
Differential input voltage
± 4 V
350 mA
Output current
Continuous power dissipation
See Dissipation Ratings Table
TJ
Maximum junction temperature,
150°C
125°C
(2)
TJ
Maximum junction temperature, continuous operation, long-term reliability
Tstg
Storage temperature
-65°C to 150°C
300°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
ESD ratings CDM
MM
2000
1500
150
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
3
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
VS = ±15 V, RF = 1.21 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
AC PERFORMANCE
G = 1, RF = 1.78 kΩ, VO = 200 mVPP
G = 2, RF = 1.21 kΩ, VO = 200 mVPP
G = 5, RF = 1 kΩ, VO = 200 mVPP
G = 10, RF = 866 Ω, VO = 200 mVPP
G = 2, RF = 1.21 kΩ, VO = 200 mVPP
G = 5, RF = 1 kΩ , VO = 4 VPP
G = 2, VO = 10-V step, RF = 1.21 kΩ
G = 5, VO = 20-V step, RF = 1 kΩ
G = 2, VO = 5-VPP, RF = 1.21 kΩ
G = -2, VO = 2 VPP step
235
210
190
180
95
Small-signal bandwidth, -3 dB
MHz
TYP
0.1-dB bandwidth flatness
Large-signal bandwidth
135
5000
7300
5
Slew rate (25% to 75% level)
V/µs
ns
TYP
TYP
TYP
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
42
ns
G = -2, VO = 2 VPP step
72
RL = 100Ω
66
77
2nd Harmonic distortion
3rd Harmonic distortion
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
G = 2, RF = 1.21 kΩ,
VO = 2 VPP, f = 10 MHz
dBc
TYP
74
69
Input voltage noise
f > 10 kHz
f > 10 kHz
f > 10 kHz
2
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
14
17
NTSC
PAL
0.013%
0.011%
0.020°
0.026°
Differential gain
G = 2, RL = 150 Ω,
RF = 1.21 kΩ
TYP
NTSC
PAL
Differential phase
DC PERFORMANCE
Transimpedance
VO = ±7.5 V, Gain = 1
850
0.9
350
3
300
4
300
4
kΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
VCM = 0 V
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
20
±10
20
µV/°C
µA
4
15
15
10
VCM = 0 V
VCM = 0 V
VCM = 0 V
±20
20
±20
20
nA/°C
µA
3.5
1.7
±20
15
±20
15
nA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
Inverting input resistance
Inverting input capacitance
±20
±20
nA/°C
±13.6
78
±13.3
±13
±13
V
dB
MΩ
pF
Ω
MIN
MIN
TYP
TYP
TYP
TYP
VCM = ±10 V
68
65
65
1.3
0.1
30
1.4
pF
4
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to -40°C to
MIN/TYP/
MAX
25°C
25°C
UNIT
70°C
85°C
OUTPUT CHARACTERISTICS
RL = 1 kΩ
RL = 100 Ω
RL = 40 Ω
RL = 40 Ω
±13.2
±12.5
280
±12.8
±12.1
225
±12.5
±11.8
200
±12.5
±11.8
200
Output voltage swing
V
MIN
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
MIN
MIN
TYP
250
200
175
175
f = 1 MHz, Closed loop
0.06
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
±15
9.5
9.5
75
±16
10.5
8.5
70
±16
11
8
±16
11
8
V
MAX
MAX
MIN
MIN
MIN
mA
mA
dB
dB
VS+ = 15.5 V to 14.5 V, VS- = 15 V
VS+ = 15 V, VS- = -15.5 V to -14.5 V
65
65
65
65
73
68
POWER-DOWN CHARACTERISTICS (THS3095 ONLY)
Enable, REF = 0 V
Power-down voltage level
≤
V
MAX
MAX
MAX
Power-down , REF = 0 V
≥ 2
500
11
Power-down quiescent current
VPD quiescent current
PD = 0V
700
15
800
20
800
20
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
15
20
20
Turnon time delay
Turnoff time delay
60
µs
TYP
150
5
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
ELECTRICAL CHARACTERISTICS
VS = ±5 V, RF = 1.15 kΩ, RL = 100 Ω, and G = 2 (unless otherwise noted)
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
MIN/TYP/
MAX
25°C
25°C
UNIT
AC PERFORMANCE
G = 1, RF = 1.78 kΩ, VO = 200 mVPP
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
G = 5, RF = 1 kΩ, VO = 200 mVPP
G = 10, RF = 866 Ω, VO = 200 mVPP
G = 2, RF = 1.15 kΩ, VO = 200 mVPP
G = 2, RF = 1.15 kΩ , VO = 4 VPP
G = 2, VO= 5-V step, RF = 1.21 kΩ
G = 5, VO= 5-V step, RF = 1 kΩ
G = 2, VO = 5-V step, RF = 1.21 kΩ
G = -2, VO = 2 VPP step
190
180
160
150
65
Small-signal bandwidth, -3 dB
MHz
TYP
0.1-dB bandwidth flatness
Large-signal bandwidth
160
1400
1900
5
Slew rate (25% to 75% level)
V/µs
ns
TYP
TYP
TYP
Rise and fall time
Settling time to 0.1%
Settling time to 0.01%
Harmonic distortion
35
ns
G = -2, VO = 2 VPP step
73
RL = 100 Ω
77
73
2nd Harmonic distortion
3rd Harmonic distortion
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
G = 2, RF = 1.15 kΩ,
VO = 2 VPP, f = 10 MHz
dBc
TYP
70
68
Input voltage noise
f > 10 kHz
f > 10 kHz
f > 10 kHz
2
nV / √Hz
pA / √Hz
pA / √Hz
TYP
TYP
TYP
Noninverting input current noise
Inverting input current noise
14
17
NTSC
PAL
0.027%
0.025%
0.04°
0.05°
Differential gain
G = 2, RL = 150 Ω,
RF = 1.15 kΩ
TYP
NTSC
PAL
Differential phase
DC PERFORMANCE
Transimpedance
VO = ±2.5 V, Gain = 1
700
0.3
250
2
200
3
200
3
kΩ
mV
MIN
MAX
TYP
MAX
TYP
MAX
TYP
MAX
TYP
Input offset voltage
VCM = 0 V
Average offset voltage drift
Noninverting input bias current
Average bias current drift
Inverting input bias current
Average bias current drift
Input offset current
±10
20
±10
20
µV/°C
µA
2
5
1
15
15
10
VCM = 0 V
VCM = 0 V
VCM = 0 V
±20
20
±20
20
nA/°C
µA
±20
15
±20
15
nA/°C
µA
Average offset current drift
INPUT CHARACTERISTICS
Common-mode input range
Common-mode rejection ratio
Noninverting input resistance
Noninverting input capacitance
Inverting input resistance
Inverting input capacitance
±20
±20
nA/°C
±3.6
66
±3.3
±3
±3
V
dB
MΩ
pF
Ω
MIN
MIN
TYP
TYP
TYP
TYP
VCM = ±2.0 V, VO = 0 V
60
57
57
1.1
1.2
32
1.5
pF
6
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
TYP
OVER TEMPERATURE
PARAMETER
TEST CONDITIONS
0°C to
70°C
-40°C to
85°C
MIN/TYP/
MAX
25°C
25°C
UNIT
OUTPUT CHARACTERISTICS
RL = 1 kΩ
RL = 100 Ω
RL = 40 Ω
RL = 40 Ω
±3.4
±3.1
200
180
0.09
±3.1
±2.7
160
150
±2.8
±2.5
140
125
±2.8
±2.5
140
125
Output voltage swing
V
MIN
Output current (sourcing)
Output current (sinking)
Output impedance
mA
mA
Ω
MIN
MIN
TYP
f = 1 MHz, Closed loop
POWER SUPPLY
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
Power supply rejection (-PSRR)
±5
8.2
8.2
73
±4.5
9
±4.5
9.5
6.5
63
±4.5
9.5
6.5
63
V
MAX
MAX
MIN
MIN
MIN
mA
mA
dB
dB
7
VS+ = 5.5 V to 4.5 V, VS– = 5 V
VS+ = 5 V, VS– = –4.5 V to -5.5 V
68
65
71
60
60
POWER-DOWN CHARACTERISTICS (THS3095 ONLY)
Enable, REF = 0 V
≤0.8
≥ 2
300
11
Power-down voltage level
Power-down quiescent current
VPD quiescent current
V
MAX
MAX
MAX
Power-down , REF = 0 V
PD = 0V
500
15
600
20
600
20
µA
µA
VPD = 0 V, REF = 0 V,
VPD = 3.3 V, REF = 0 V
90% of final value
10% of final value
11
15
20
20
Turnon time delay
Turnoff time delay
60
µs
TYP
150
7
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
TYPICAL CHARACTERISTICS
TABLE OF GRAPHS
±15-V GRAPHS
FIGURE
Noninverting small-signal frequency response
Inverting small-signal frequency response
0.1-dB gain flatness frequency response
Noninverting large-signal frequency response
Inverting large-signal frequency response
Capacitive load frequency response
Recommended RISO
1, 2
3
4
5
6
7
vs Capacitive load
vs Frequency
8
2nd Harmonic distortion
3rd Harmonic distortion
2nd Harmonic distortion
3rd Harmonic distortion
Harmonic distortion
9, 11
10, 12
13
vs Frequency
vs Frequency
vs Frequency
14
vs Output voltage swing
vs Output voltage step
vs Frequency
15, 16
17, 18, 19
20
Slew rate
Noise
Settling time
21, 22
23
Quiescent current
vs Supply voltage
vs Frequency
Quiescent current
24
Output voltage
vs Load resistance
vs Case temperature
vs Case temperature
vs Frequency
25
Input bias and offset current
Input offset voltage
26
27
Transimpedance
28
Rejection ratio
vs Frequency
29
Noninverting small-signal transient response
Inverting large-signal transient response
Overdrive recovery time
Differential gain
30
31, 32
33
vs Number of loads
vs Number of loads
vs Frequency
34
Differential phase
35
Closed-loop output impedance
Power-down quiescent current
Turnon and turnoff time delay
36
vs Supply voltage
37
38
8
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
TABLE OF GRAPHS
±5-V GRAPHS
FIGURE
39
Noninverting small-signal frequency response
Inverting small-signal frequency response
0.1-dB gain flatness frequency response
Noninverting large-signal frequency response
Inverting large-signal frequency response
Settling time
40
41
42
43
44
2nd Harmonic distortion
3rd Harmonic distortion
vs Frequency
45, 47
46, 48
49, 50
51, 52, 53
54
vs Frequency
Harmonic distortion
vs Output voltage swing
vs Output voltage step
vs Frequency
Slew rate
Quiescent current
Output voltage
vs Load resistance
vs Case temperature
55
Input bias and offset current
Overdrive recovery time
Rejection ratio
56
57
vs Frequency
58
9
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
TYPICAL CHARACTERISTICS (±15 V)
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
24
22
20
18
16
14
12
9
8
7
6
5
4
3
2
24
22
20
18
16
14
R
= 750 Ω
F
G = −10, R = 866 Ω
F
G = 10, R = 866 Ω
F
G = −5, R = 909 Ω
G = 5, R = 1 kΩ
F
F
R =1.21kΩ
F
12
10
8
R
V
= 100 Ω,
= 200 mV
= ±15 V
L
O
S
R
O
S
= 100 Ω,
= 200 mV
= ±15 V
L
,
PP
10
8
V
V
,
PP
V
R
= 1.5 kΩ
F
6
6
4
G = 2, R = 1.21 kΩ
G = −2, R = 1 kΩ
F
F
4
Gain = 2,
2
2
R
L
=100 Ω,
0
−2
−4
0
V
V
= 200 mV ,
PP
= ±15 V
O
S
1
0
G = −1, R = 1.05 kΩ
G = 1, R = 1.78 kΩ
F
−2
−4
F
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
10 M
100 M
1 G
1 M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
Figure 3.
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
16
16
14
12
10
8
6.3
G = −5, R = 909 Ω
F
G = 5, R = 1 kΩ
Gain = 2,
F
14
12
R
F
R
L
= 1.21 kΩ,
= 100 Ω,
6.2
6.1
V
V
= 200 mV ,
PP
= ±15 V
O
S
10
8
G = −2, R = 1 kΩ
F
6
6
5.9
5.8
5.7
G = 2, R = 1.21 kΩ
F
4
6
2
4
V
= 4 V ,
PP
O
0
V
R
V
= 4 V ,
PP
O
R
= 100 Ω,
= ±15 V
L
= 100 Ω,
= ±15 V
2
0
L
−2
V
S
S
−4
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
f - Frequency - Hz
Figure 4.
Figure 5.
Figure 6.
RECOMMENDED RISO
vs
CAPTIVATE LOAD
2ND HARMONIC DISTORTION
CAPACITIVE LOAD
FREQUENCY RESPONSE
vs
FREQUENCY
16
14
45
−40
R
= 38.3 Ω
(ISO)
C
Gain = 5,
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±15 V
O
−45
−50
−55
−60
= 10 pF
L
40
35
30
R
V
= 100 Ω,
= ±15 V
L
L
S
S
12
10
8
R
R
= 30.9 Ω
(ISO)
C
= 22 pF
L
25
20
= 22.1 Ω
G = 1, R = 1.78 kΩ
(ISO)
C
F
−65
−70
= 47 pF
L
6
15
10
4
2
R
= 15.8 Ω
= 100 pF
(ISO)
C
L
−75
−80
−85
−90
G = 2, R = 1.21 kΩ
F
Gain = 5,
0
R
L
= 100 Ω,
=±15 V
5
0
V
S
−2
10 M
100 M
1 G
10
100
100 k
1 M
10 M
100 M
f − Frequency − Hz
C
L
− Capacitive Load − pF
f − Frequency − Hz
Figure 7.
Figure 8.
Figure 9.
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TYPICAL CHARACTERISTICS (±15 V) (continued)
3RD HARMONIC DISTORTION
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−40
−50
−40
-40
-50
V
R
V
= 2 V
= 1 kΩ,
= ±15 V
,
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±15 V
O
PP
V
R
V
= 2 V ,
PP
= 1 kΩ,
= ±15 V
O
O
−45
−50
−55
L
L
L
S
S
S
−60
−70
−80
-60
-70
-80
−60
−65
G = 1, R = 1.78 kΩ
F
G = 1, R = 1.78 kΩ
F
G = 1, R = 1.78 kΩ
F
−70
−75
G = 2, R = 1.21 kΩ
F
G = 2, R = 1.21 kΩ
G = 2, R = 1.21 kΩ
F
F
−80
−85
−90
−90
-90
−100
-100
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
f − Frequency − Hz
f − Frequency − Hz
f - Frequency - Hz
Figure 10.
Figure 11.
Figure 12.
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
FREQUENCY
-60
-65
-70
-75
−30
−40
−30
−40
G = 5,
G = 5,
V
= 20 V
PP
R
F
R
L
V
= 1 kΩ,
= 100 Ω,
= ±15 V
R
F
R
L
V
= 1 kΩ,
= 100 Ω,
= ±15 V
O
HD2
S
S
−50
−60
−50
−60
V
= 20 V
PP
O
-80
-85
-90
HD3
V
= 10 V
PP
−70
−80
−90
O
−70
−80
−90
Gain = 5,
V
= 10 V
PP
O
R
R
= 1 kΩ
= 100 Ω,
F
L
V
= 2 V
PP
O
f= 1 MHz
= ±15 V
-95
V
S
V
= 2 V
PP
O
-100
1 M
10 M
100 M
1 M
10 M
100 M
0
2
4
6
8
10 12 14 16 18 20
f − Frequency − Hz
f − Frequency − Hz
V
- Output Voltage Swing - V
O
PP
Figure 13.
Figure 14.
Figure 15.
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
2000
1800
1600
-40
-50
6000
5000
4000
3000
2000
1000
Gain = 5,
Gain = 1
Gain = 2
R
R
= 1 kΩ
= 100 Ω,
F
R
L
R
F
V
= 100 Ω
= 1.78 kΩ
= ±15 V
R
L
R
F
V
= 100 Ω
= 1.21 kΩ
= ±15 V
L
f= 8 MHz
= ±15 V
Rise
S
V
S
1400
1200
S
HD2
-60
-70
Fall
1000
800
600
400
-80
HD3
Rise
Fall
6
-90
200
0
-100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
2
4
6
8
10 12 14 16 18 20
0
1
2
3
4
5
7
8
9
10
V
− Output Voltage − V
O
PP
V
- Output Voltage Swing - V
V
- Output Voltage - V
PP
O
PP
O
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (±15 V) (continued)
SLEW RATE
vs
OUTPUT VOLTAGE STEP
NOISE
vs
FREQUENCY
SETTLING TIME
8000
7000
6000
5000
4000
3000
2000
1000
0
1000
100
1.25
1
Gain = 5
R
R
V
= 100 Ω
= 1 kΩ
= ±15 V
L
F
S
Rising Edge
0.75
0.5
0.25
0
Gain = -2
I
n−
Rise
R
R
V
= 100 Ω
=1 kΩ
= ±15 V
L
F
S
Fall
-0.25
-0.5
I
n+
10
1
V
-0.75
n
Falling Edge
-1
-1.25
10
100
1 k
10 k
100 k
0
1
2
3
4
5
6
7
8
9
10
0
2
4
6
8
10 12 14 16 18 20
f − Frequency − Hz
V
- Output Voltage - V
t - Time - ns
O
PP
Figure 19.
Figure 20.
Figure 21.
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
QUIESCENT CURRENT
vs
SETTLING TIME
FREQUENCY
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
10
9.5
9
22
20
T
= 85 °C
A
Rising Edge
T
= 25 °C
18
16
14
12
A
V
= 4V
PP
O
V
8.5
8
Gain = -2
T
= −40 °C
A
R
R
V
= 100 Ω
= 1 kΩ
= ±15 V
L
F
S
10
8
= 2V
PP
O
7.5
6
4
2
0
Gain = 5
7
6.5
6
R
R
= 1 kΩ,
= 100 Ω,
= ±15 V
F
L
Falling Edge
-3.5
-4
-4.5
V
S
3
4
5
6
7
8
9 10 11 12 13 14 15
0
2
4
6
8
10
12
100 M
1 G
100 k
10 M
1 M
t - Time - ns
V
− Supply Voltage − ±V
f − Frequency − Hz
S
Figure 22.
Figure 23.
Figure 24.
INPUT BIAS AND
OFFSET CURRENT
vs
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
CASE TEMPERATURE
7
3
16
12
8
V
= ±15 V
I
-
S
6.5
6
IB
2.5
5.5
5
2
4.5
4
4
I
+
V
= ±15 V
IB
S
V
T
A
= ±15 V
= -40 to 85°C
S
1.5
3.5
3
0
-4
2.5
2
1
-8
1.5
1
V = ±5 V
S
0.5
I
-12
-16
OS
0.5
0
0
10
100
1000
-40-30-20 -10
0 10 20 30 40 50 60 70 80 90
-40-30-20-10
0 10 20 30 40 50 60 70 80 90
R
L
- Load Resistance - Ω
T
C
- Case Temperature - °C
T
C
- Case Temperature - °C
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS (±15 V) (continued)
TRANSIMPEDANCE
vs
REJECTION RATIO
vs
NONINVERTING SMALL-SIGNAL
TRANSIENT RESPONSE
FREQUENCY
FREQUENCY
70
60
50
40
30
20
0.3
100
90
80
70
60
50
40
30
20
V
= ±15 V
S
0.25
V
= ±15 V and ±5 V
S
Output
0.2
PSRR−
0.15
Input
0.1
0.05
0
CMRR
-0.05
-0.1
-0.15
-0.2
-0.25
-0.3
Gain = 2
= 100 Ω
PSRR+
R
R
L
1 kΩ
F =
V
= ±15 V
S
10
0
10
0
100 k
1 M
10 M
100 M
1 G
0
10 20 30 40 50 60 70
100 k
1 M
10 M
100 M
1 G
t - Time - ns
f − Frequency − Hz
f − Frequency − Hz
Figure 28.
Figure 29.
Figure 30.
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
INVERTING LARGE-SIGNAL
TRANSIENT RESPONSE
OVERDRIVE RECOVERY TIME
20
15
10
12
6
5
4
Gain = 5,
10
8
Gain = -5
3
2
1
R
R
= 100 Ω,
= 1 kΩ,
= ±15 V
Output
L
F
S
4
R
R
= 100 Ω
=909 Ω
= ±15 V
L
F
S
6
4
2
3
V
V
2
5
1
Input
0
0
0
-2
-4
-6
-8
0
Input
−1
−2
−3
−4
−5
−6
−5
−1
−10
−2
−3
−4
Gain = −5
R
R
= 100 Ω
L
−15
−20
909 Ω
Output
F =
-10
V
= ±15 V
S
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
1
-12
0
10 20 30 40 50 60 70
0
5
10 15 20 25 30 35 40
t − Time − µs
t - Time - ns
t − Time − ns
Figure 31.
Figure 32.
Figure 33.
CLOSED-LOOP OUTPUT
IMPEDANCE
vs
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
FREQUENCY
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.05
0.04
0.03
0.02
0.01
0
100
10
1
Gain = 2
Gain = 2
Gain = 2,
R
V
= 1.21 kΩ
= ±15 V
F
S
R
V
= 1.21 kΩ
= ±15 V
F
S
R = 5.11 Ω,
ISO
R
V
= 1.21 KΩ,
= ±15 V
F
S
40 IRE - NTSC and Pal
Worst Case ±100 IRE Ramp
°
40 IRE − NTSC and Pal
Worst Case ±100 IRE Ramp
PAL
PAL
1.21 kΩ 1.21 kΩ
NTSC
0.1
V
O
5.11 Ω
−
+
NTSC
0.01
0
1
2
3
4
5
6
7
8
0
1
2
3
4
5
6
7
8
1 M
10 M
100 M
1 G
Number of Loads - 150 Ω
Number of Loads − 150 Ω
f − Frequency − Hz
Figure 34.
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS (±15 V) (continued)
POWER-DOWN QUIESCENT
CURRENT
vs
TURNON AND TURNOFF
TIME DELAY
SUPPLY VOLTAGE
600
500
6
5
Power-down Pulse
4
3
2
1
0
T
= 85°C
= 25°C
A
Gain = 2,
400
300
200
V
= 0.1 Vdc
I
R
L
= 100 Ω
V
= ±15 V and ±5 V
S
T
A
= -40°C
0.3
0.2
T
A
0.1
0
Output Voltage
100
0
−0.1
0
1
2
3
4
5
6
7
3
4
5
6
7
8
9
10 11 12 13 14 15
t − Time − ms
V
- Supply Voltage - ±V
S
Figure 37.
Figure 38.
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TYPICAL CHARACTERISTICS (±5 V)
NONINVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
INVERTING SMALL-SIGNAL
FREQUENCY RESPONSE
0.1-dB GAIN FLATNESS
FREQUENCY RESPONSE
24
22
20
18
16
14
12
10
8
24
22
20
18
16
14
12
6.3
6.2
6.1
Gain = 2,
G = 10, R = 909 Ω
G = −10, R = 866 Ω
F
F
R
R
V
= 1.21 kΩ,
= 100 Ω,
= 200 mV
F
L
,
O
S
PP
G = 5, R = 1 kΩ
G = −5, R = 909 Ω
F
F
V
= ±5 V
R
V
V
= 100 Ω,
= 200 mV
= ±5 V
R
V
V
= 100 Ω,
= 200 mV
= ±5 V
L
L
10
8
.
.
PP
6
O
S
PP
O
S
6
4
6
5.9
G = 2, R = 1.15 kΩ
F
G = −2, R = 1 kΩ
4
F
2
2
5.8
5.7
0
0
G =1, R = 1.5 kΩ
F
-2
-4
G = −1, R = 1.05 Ω
−2
−4
F
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
1 M
10 M
100 M
f − Frequency − Hz
f - Frequency - Hz
f - Frequency - Hz
Figure 39.
Figure 40.
Figure 41.
NONINVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
INVERTING LARGE-SIGNAL
FREQUENCY RESPONSE
SETTLING TIME
16
14
12
10
16
14
12
10
8
1.25
1
G = −5, R = 909 Ω
F
G = 5, R = 1 kΩ
F
Rising Edge
0.75
0.5
0.25
0
Gain = -2
R
R
V
= 100 Ω
= 1 kΩ
= ±5 V
L
F
6
8
6
4
G = −2, R = 1 kΩ
G = 2, R = 1.15 kΩ
F
F
4
-0.25
-0.5
-0.75
-1
S
2
0
R
L
= 100 Ω,
R
V
= 100 Ω,
L
Falling Edge
V
V
= 4 V
= ±5 V
,
= 4 V
,
2
0
O
S
PP
O
PP
−2
−4
V
= ±5 V
S
-1.25
1 M
10 M
100 M
1 G
0
1
2
3
4
5
6
7
8
9
10
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
t - Time - ns
Figure 42.
Figure 43.
Figure 44.
2ND HARMONIC DISTORTION
3RD HARMONIC DISTORTION
2ND HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
−40
−50
-40
−40
−50
V
R
V
= 2 V
= 100 Ω,
= ±5 V
,
V
R
V
= 2 V ,
PP
= 1 kΩ,
= ±5 V
O
PP
O
V
R
V
= 2 V ,
PP
= 100 Ω,
= ±5 V
O
L
L
L
-50
-60
-70
-80
S
S
S
−60
−70
−80
−60
−70
−80
G = 1, R = 1.78 kΩ
F
G = 1, R = 1.78 kΩ
F
G = 1, R = 1.78 kΩ
F
G = 2, R = 1.15 kΩ
F
G = 2, R = 1.15 kΩ
F
G = 2, R = 1.15 kΩ
−90
-90
−90
F
−100
-100
−100
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
100 k
1 M
10 M
100 M
f − Frequency − Hz
f - Frequency - Hz
f − Frequency − Hz
Figure 45.
Figure 46.
Figure 47.
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TYPICAL CHARACTERISTICS (±5 V) (continued)
3RD HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
OUTPUT VOLTAGE SWING
−40
−50
-20
-30
-40
-50
−20
−30
−40
−50
Gain = 5,
V
R
V
= 2 V ,
PP
= 1 kΩ,
= ±5 V
Gain = 5,
O
R
R
= 1 kΩ
= 100 Ω,
R
R
= 1 kΩ
= 100 Ω,
F
F
L
L
L
S
f= 8 MHz
= ±5 V
f= 1 MHz
= ±5 V
V
V
S
S
−60
−70
−80
HD3
G = 1, R = 1.78 kΩ
F
-60
-70
-80
−60
−70
−80
HD3
HD2
G = 2, R = 1.15 kΩ
F
−90
HD2
-90
−90
−100
-100
−100
100 k
1 M
10 M
100 M
0
1
2
3
4
5
6
0
1
2
3
4
5
6
f − Frequency − Hz
V
- Output Voltage Swing - V
V
− Output Voltage Swing − V
PP
O
PP
O
Figure 48.
Figure 49.
Figure 50.
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
SLEW RATE
vs
OUTPUT VOLTAGE STEP
1600
1400
1200
1000
800
1600
1400
1200
1000
800
2000
1800
1600
1400
1200
1000
800
Gain = 1
Gain = 1
Gain = 5
Fall
R
R
V
= 100 Ω
= 1.21 kΩ
= ±5 V
L
F
R
R
V
= 100 Ω
= 1.78 kΩ
= ±5 V
L
F
S
R
R
= 100 Ω
= 1 kΩ
= ±5 V
Fall
L
F
S
S
V
Rise
Rise
Fall
600
400
600
600
Rise
1.5
400
200
0
400
200
0
200
0
0
0.5
1
2
2.5
3
3.5
4
4.5
5
0
1
2
3
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
V
− Output Voltage −V
V
− Output Voltage −V
V
- Output Voltage -V
O
PP
O
PP
O
PP
Figure 51.
Figure 52.
Figure 53.
INPUT BIAS AND
QUIESCENT CURRENT
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
OFFSET CURRENT
vs
vs
FREQUENCY
CASE TEMPERATURE
22
20
18
16
14
12
10
8
8
3.5
V
= ±5 V
Gain = 5
S
3
2.5
7
6
5
4
3
2
R
R
= 1 kΩ,
= 100 Ω,
= ±5 V
F
L
2
1.5
1
I
IB-
V
S
V
= 4 V
I
O
PP
PP
OS
0.5
V
T
A
= ±5 V
= -40 to 85°C
S
0
-0.5
V
= 2 V
O
-1
-1.5
6
I
IB+
-2
4
-2.5
-3
1
0
2
0
-3.5
-40 -30 -20-10
0
10 20 30 40 50 60 70 80 90
100 k
1 M
10 M
100 M
1 G
10
100
1000
T - Case Temperature - °C
C
f − Frequency − Hz
R
L
- Load Resistance - Ω
Figure 54.
Figure 55.
Figure 56.
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TYPICAL CHARACTERISTICS (±5 V) (continued)
REJECTION RATIO
vs
OVERDRIVE RECOVERY
TIME
FREQUENCY
70
60
50
40
30
20
5
1
Gain = 5,
V
= ±5 V
S
4
3
2
1
0
0.8
0.6
0.4
0.2
R
R
V
= 100 Ω,
= 1 kΩ,
= ±5 V
L
F
S
PSRR-
0
CMRR
-0.2
-1
-0.4
-0.6
-2
-3
-4
-5
PSRR+
-0.8
-1
10
0
0
0.2
0.4
0.6
0.8
1
100 k
1 M
10 M
100 M
t - Time - µs
f - Frequency - Hz
Figure 57.
Figure 58.
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APPLICATION INFORMATION
WIDEBAND, NONINVERTING OPERATION
Current-feedback amplifiers are highly dependent on
the feedback resistor RF for maximum performance
and stability. Table 1 shows the optimal gain-setting
resistors RF and RG at different gains to give
maximum bandwidth with minimal peaking in the
frequency response. Higher bandwidths can be
achieved, at the expense of added peaking in the
frequency response, by using even lower values for
RF. Conversely, increasing RF decreases the
bandwidth, but stability is improved.
The THS3091/5 are unity gain stable 235-MHz
current-feedback operational amplifiers, designed to
operate from a ±5-V to ±15-V power supply.
Figure 59 shows the THS3091 in a noninverting gain
of 2-V/V configuration typically used to generate the
performance curves. Most of the curves were
characterized using signal sources with 50-Ω source
impedance, and with measurement equipment
presenting a 50-Ω load impedance.
Table 1. Recommended Resistor Values for
Optimum Frequency Response
15 V
+V
S
THS3091 and THS3095 RF and RG values for minimal peaking
+
with RL = 100 Ω
0.1 µF
49.9 Ω
6.8 µF
50-Ω Source
49.9 Ω
SUPPLY VOLTAGE
GAIN (V/V)
RG (Ω)
RF (Ω)
(V)
+
V
I
±15
–
1.78 k
1.78 k
1.21 k
1.15 k
1 k
THS3091
_
1
±5
–
50-Ω LOAD
R
F
±15
1.21 k
1.15 k
249
2
5
1.21 kΩ
±5
1.21 kΩ
R
G
0.1 µF
6.8 µF
±15
+
±5
249
1 k
±15
95.3
95.3
1.05 k
499
866
−V
S
10
±5
866
−15 V
–1
–2
±15 and ±5
±15 and ±5
±15 and ±5
±15 and ±5
1.05 k
1 k
Figure 59. Wideband, Noninverting Gain
Configuration
–5
182
909
–10
86.6
866
18
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
WIDEBAND, INVERTING OPERATION
+V
S
Figure 60 shows the THS3091 in a typical inverting
gain configuration where the input and output
impedances and signal gain from Figure 59 are
retained in an inverting circuit configuration.
50-Ω Source
+
49.9 Ω
50-Ω LOAD
V
I
THS3091
49.9 Ω
R
T
_
15 V
+V
S
+V
2
S
R
F
+
1.21 kΩ
R
G
0.1 µF
49.9 Ω
6.8 µF
1.21 kΩ
+
THS3091
+V
2
S
_
R
F
50-Ω LOAD
1 kΩ
50-Ω Source
R
G
V
S
R
F
50-Ω Source
R
G
_
V
I
499 Ω
1 kΩ
49.9 Ω
50-Ω LOAD
V
I
R
M
499 Ω
R
T
THS3091
0.1 µF
6.8 µF
56.2 Ω
56.2 Ω
+
+
+V
2
+V
2
S
S
−V
S
−15 V
Figure 61. DC-Coupled, Single-Supply Operation
Figure 60. Wideband, Inverting Gain
Configuration
Video Distribution
SINGLE-SUPPLY OPERATION
The wide bandwidth, high slew rate, and high output
drive current of the THS3091/5 matches the demands
for video distribution for delivering video signals down
multiple cables. To ensure high signal quality with
minimal degradation of performance, a 0.1-dB gain
flatness should be at least 7x the passband
frequency to minimize group delay variations from the
amplifier. A high slew rate minimizes distortion of the
video signal, and supports component video and
RGB video signals that require fast transition times
and fast settling times for high signal quality.
The THS3091/5 have the capability to operate from a
single-supply voltage ranging from 10 V to 30 V.
When operating from a single power supply, biasing
the input and output at mid-supply allows for the
maximum output voltage swing. The circuits shown in
Figure 61 show inverting and noninverting amplifiers
configured for single-supply operations.
1.21 kΩ
1.21 kΩ
15 V
75-Ω Transmission Line
V
O(1)
75 Ω
−
+
V
I
−15 V
75 Ω
n Lines
75 Ω
V
O(n)
75 Ω
75 Ω
Figure 62. Video Distribution Amplifier
Application
19
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
Driving Capacitive Loads
Placing a small series resistor, RISO, between the
amplifier’s output and the capacitive load, as shown
in Figure 64, is an easy way of isolating the load
capacitance.
Applications such as FET line drivers can be highly
capacitive and cause stability problems for
high-speed amplifiers.
Using a ferrite chip in place of RISO, as shown in
Figure 65, is another approach of isolating the output
of the amplifier. The ferrite's impedance characteristic
versus frequency is useful to maintain the
low-frequency load independence of the amplifier
while isolating the phase shift caused by the capaci-
tance at high frequency. Use a ferrite with similar
impedance to RISO, 20 Ω - 50 Ω, at 100 MHz and low
impedance at dc.
Figure 63 through Figure 68 show recommended
methods for driving capacitive loads. The basic idea
is to use a resistor or ferrite chip to isolate the phase
shift at high frequency caused by the capacitive load
from the amplifier’s feedback path. See Figure 63 for
recommended resistor values versus capacitive load.
45
Gain = 5,
40
R
L
= 100 Ω,
= ±15 V
V
S
35
30
Figure 66 shows another method used to maintain
the low-frequency load independence of the amplifier
while isolating the phase shift caused by the capaci-
tance at high frequency. At low frequency, feedback
is mainly from the load side of RISO. At high fre-
quency, the feedback is mainly via the 27-pF
capacitor. The resistor RIN in series with the negative
input is used to stabilize the amplifier and should be
equal to the recommended value of RF at unity gain.
Replacing RIN with a ferrite of similar impedance at
about 100 MHz as shown in Figure 67 gives similar
results with reduced dc offset and low-frequency
noise. (See the ADDITIONAL REFERENCE MA-
TERIAL section for expanding the usability of cur-
rent-feedback amplifiers.)
25
20
15
10
5
0
10
100
C
L
− Capacitive Load − pF
Figure 63. Recommended RISO vs Capacitive Load
1 kΩ
R
F
V
S
249 Ω
100-Ω LOAD
1 kΩ
_
+
5.11 Ω
27 pF
V
R
ISO
R
IN
1 µF
−V
S
S
R
1 kΩ
G
100-Ω LOAD
49.9 Ω
_
5.11 Ω
V
S
249 Ω
+
1 µF
−V
S
Figure 64.
49.9 Ω
V
S
1 kΩ
Figure 66.
V
S
249 Ω
Ferrite Bead
_
+
100-Ω LOAD
1 µF
−V
S
49.9 Ω
V
S
Figure 65.
20
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
R
F
V
S
V
S
1 kΩ
5.11 Ω
+
27 pF
V
_
F
IN
−V
S
S
R
FB
G
100-Ω LOAD
_
5.11 Ω
866 Ω
249 Ω
+
191 Ω
866 Ω
1 µF
−V
S
49.9 Ω
V
S
V
S
_
5.11 Ω
Figure 67.
+
−V
−V
S
S
Figure 68 is shown using two amplifiers in parallel to
double the output drive current to larger capacitive
loads. This technique is used when more output
current is needed to charge and discharge the load
faster like when driving large FET transistors.
Figure 69. PowerFET Drive Circuit
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY AND SETTING
THRESHOLD LEVELS WITH THE
REFERENCE PIN
1 kΩ
V
S
249 Ω
The THS3095 features a power-down pin (PD) which
lowers the quiescent current from 9.5 mA down to
500 µA, ideal for reducing system power.
_
+
5.11 Ω
24.9 Ω
−V
S
The power-down pin of the amplifier defaults to the
negative supply voltage in the absence of an applied
voltage, putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the positive rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and are given in the specification tables. Below
the Enable Threshold Voltage, the device is on.
Above the Disable Threshold Voltage, the device is
off. Behavior in between these threshold voltages is
not specified.
1 kΩ
V
S
V
S
1 nF
249 Ω
_
+
5.11 Ω
24.9 Ω
−V
S
Figure 68.
Figure 69 shows a push-pull FET driver circuit typical
of ultrasound applications with isolation resistors to
isolate the gate capacitance from the amplifier.
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and
gain-setting resistors, but the output impedance of the
device itself varies depending on the voltage applied
to the outputs.
Figure 70 shows the total system output impedance
which includes the amplifier output impedance in
parallel with the feedback plus gain resistors, which
cumulate to 2380 Ω. Figure 59 shows this circuit
configuration for reference.
21
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
PERFORMANCE
2500
V
= ±15 V and ±5 V
S
Achieving
optimum
performance
with
a
high-frequency amplifier, like the THS3091/5, re-
quires careful attention to board layout parasitic and
external component types.
2000
1500
1000
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance, a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
1.21 kΩ 1.21 kΩ
V
O
50 Ω
−
+
500
0
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
Figure 70. Power-down Output Impedance vs
Frequency
•
Minimize the distance (< 0.25 in.) from the power
supply pins to high-frequency 0.1-µF and 100-pF
decoupling capacitors. At the device pins, the
ground and power plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PC board.
As with most current feedback amplifiers, the internal
architecture places some limitations on the system
when in power-down mode. Most notably is the fact
that the amplifier actually turns ON if there is a ±0.7 V
or greater difference between the two input nodes
(V+ and V-) of the amplifier. If this difference exceeds
±0.7 V, the output of the amplifier creates an output
voltage
equal
to
approximately
[(V+ - V-) -0.7 V]×Gain. This also implies that if a
voltage is applied to the output while in power-down
mode, the V- node voltage is equal to
V
O(applied)× RG/(RF + RG). For low gain configurations
and a large applied voltage at the output, the
amplifier may actually turn ON due to the
aforementioned behavior.
•
Careful selection and placement of external
components
preserve
the
high-frequency
performance of the THS3091/5. Resistors should
be a low reactance type. Surface-mount resistors
work best and allow a tighter overall layout.
Again, keep their leads and PC board trace
length as short as possible. Never use wirebound
type resistors in a high-frequency application.
Because the output pin and inverting input pins
are the most sensitive to parasitic capacitance,
always position the feedback and series output
resistors, if any, as close as possible to the
inverting input pins and output pins. Other net-
work components, such as input termination re-
sistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach either 10% or 90% of the final
output voltage. The time delays are in the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
POWER-DOWN REFERENCE PIN
OPERATION
In addition to the power-down pin, the THS3095
features a reference pin (REF) which allows the user
to control the enable or disable power-down voltage
levels applied to the PD pin. In most split-supply
applications, the reference pin is connected to
ground. In either case, the user needs to be aware of
voltage-level thresholds that apply to the power-down
pin. The usable range at the REF pin is from VS- to
(VS+ - 4 V).
shunting
the
external
resistors,
excessively high resistor values can create sig-
nificant time constants that can degrade perform-
ance. Good axial metal-film or surface-mount
resistors have approximately 0.2 pF in shunt with
the resistor. For resistor values > 2 kΩ, this
parasitic capacitance can add a pole and/or a
zero that can effect circuit operation. Keep re-
sistor values as low as possible, consistent with
load-driving considerations.
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
•
Connections to other wideband devices on the
board may be made with short direct traces or
22
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils)
should be used, preferably with ground and
power planes opened up around them. Estimate
the total capacitive load and determine if isolation
resistors on the outputs are necessary. Low
parasitic capacitive loads (< 4 pF) may not need
an RS because the THS3091/5 are nominally
compensated to operate with a 2-pF parasitic
load. Higher parasitic capacitive loads without an
RS are allowed as the signal gain increases
(increasing the unloaded phase margin). If a long
trace is required, and the 6-dB signal loss intrin-
sic to a doubly terminated transmission line is
acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A
50-Ω environment is not necessary onboard, and
in the lead frame being exposed as a thermal pad on
the underside of the package [see Figure 71(c)].
Because this thermal pad has direct thermal contact
with the die, excellent thermal performance can be
achieved by providing a good thermal path away from
the thermal pad. Note that devices such as the
THS3091/5 have no electrical connection between
the PowerPAD and the die.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing oper-
ation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either
heat-dissipating device.
a ground plane or other
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
in fact,
a
higher impedance environment
improves distortion as shown in the distortion
versus load plots. With a characteristic board
trace impedance based on board material and
trace dimensions, a matching series resistor into
the trace from the output of the THS3091/5 is
used as well as a terminating shunt resistor at the
input of the destination device. Remember also
that the terminating impedance is the parallel
combination of the shunt resistor and the input
impedance of the destination device; this total
effective impedance should be set to match the
trace impedance. If the 6-dB attenuation of a
doubly terminated transmission line is unaccept-
able, a long trace can be series-terminated at the
source end only. Treat the trace as a capacitive
load in this case. This does not preserve signal
integrity as well as a doubly terminated line. If the
input impedance of the destination device is low,
there is some signal attenuation due to the
voltage divider formed by the series output into
the terminating impedance.
DIE
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Figure 71. Views of Thermal Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
0.300
0.100
0.035
0.026
0.010
Pin 1
0.030
•
Socketing a high-speed part like the THS3091/5
is not recommended. The additional lead length
and pin-to-pin capacitance introduced by the
socket can create an extremely troublesome
parasitic network which can make it almost im-
possible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
the THS3091/5 parts directly onto the board.
0.060
0.060
0.140
0.050
0.176
0.035
0.080
0.010
vias
All Units in Inches
PowerPAD™ DESIGN CONSIDERATIONS
Top View
The
THS3091/5
are
available
in
a
Figure 72. DDA PowerPAD PCB Etch and Via
Pattern
thermally-enhanced PowerPAD family of packages.
These packages are constructed using a downset
leadframe on which the die is mounted [see Fig-
ure 71(a) and Figure 71(b)]. This arrangement results
23
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
PowerPAD™ LAYOUT CONSIDERATIONS
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
1. PCB with a top-side etch pattern is shown in
Figure 72. There should be etch for the leads as
well as etch for the thermal pad.
The THS3091/5 incorporates automatic thermal
shutoff protection. This protection circuitry shuts down
the amplifier if the junction temperature exceeds
approximately 160°C. When the junction temperature
reduces to approximately 140°C, the amplifier turns
on again. But, for maximum performance and
reliability, the designer must ensure that the design
does not exeed a junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur,
but the performance of the amplifier begins to de-
grade and long-term reliability suffers. The thermal
characteristics of the device are dictated by the
package and the PC board. Maximum power dissi-
pation for a given package can be calculated using
the following formula.
2. Place 13 holes in the area of the thermal pad.
These holes should be 10 mils in diameter. Keep
them small so that solder wicking through the
holes is not a problem during reflow.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. This helps dissipate the heat generated by
the THS3091/5 IC. These additional vias may be
larger than the 10-mil diameter vias directly under
the thermal pad. They can be larger because
they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
Note that the PowerPAD is electrically isolated
from the silicon and all leads. Connecting the
PowerPAD to any potential voltage such as VS- is
acceptable as there is no electrical connection to
the silicon.
Tmax TA
qJA
PDmax
+
where:
P
Dmax
is the maximum power dissipation in the amplifier (W).
T
T
θ
is the absolute maximum junction temperature (°C).
max
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This makes the soldering of
vias that have plane connections easier. In this
application, however, low thermal resistance is
desired for the most efficient heat transfer. There-
fore, the holes under the THS3091/5 PowerPAD
package should make their connection to the
internal ground plane with a complete connection
around the entire circumference of the
plated-through hole.
is the ambient temperature (°C).
= θ + θ
A
JA
JC
CA
θ
is the thermal coefficient from the silicon junctions to the
JC
case (°C/W).
θ
is the thermal coefficient from the case to ambient air
CA
(°C/W).
For systems where heat dissipation is more critical,
the THS3091 and THS3095 are offered in an 8-pin
SOIC (DDA) with PowerPAD package. The thermal
coefficient for the PowerPAD packages are substan-
tially improved over the traditional SOIC. Maximum
power dissipation levels are depicted in the graph for
the available packages. The data for the PowerPAD
packages assume a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application note (literature
number SLMA002). The following graph also illus-
trates the effect of not soldering the PowerPAD to a
PCB. The thermal impedance increases substantially
which may cause serious heat and performance
issues. Be sure to always solder the PowerPAD to
the PCB for optimum performance.
6. The top-side solder mask should leave the ter-
minals of the package and the thermal pad area
with its 13 holes exposed. The bottom-side solder
mask should cover the 13 holes of the thermal
pad area. This prevents solder from being pulled
away from the thermal pad area during the reflow
process.
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This results in a part
that is properly installed.
24
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
DESIGN TOOLS
4
Τ
J
= 125°C
3.5
Evaluation
Fixtures,
Spice
Models,
and
θ
= 45.8°C/W
Application Support
JA
3
2.5
2
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS3091/5 operational
amplifier. The board is easy to use, allowing for
straightforward evaluation of the device. The evalu-
ation board can be ordered through the Texas
Instruments Web site, www.ti.com, or through your
local Texas Instruments sales representative.
θ
= 58.4°C/W
JA
θ
= 95°C/W
JA
1.5
1
0.5
θ
= 158°C/W
JA
0
−40
−20
0
20
40
60
80
100
T
− Free-Air Temperature − °C
A
Computer simulation of circuit performance using
SPICE is often useful when analyzing the perform-
ance of analog circuits and systems. This is particu-
larly true for video and RF-amplifier circuits where
parasitic capacitance and inductance can have a
major effect on circuit performance. A SPICE model
for the THS3091/5 is available through the Texas
Instruments Web site (www.ti.com). The Product
Information Center (PIC) is also available for design
assistance and detailed product information. These
models do a good job of predicting small-signal ac
and transient performance under a wide variety of
operating conditions. They are not intended to model
the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package
types in their small-signal ac performance. Detailed
information about what is and is not modeled is
contained in the model file itself.
Results are With No Air Flow and PCB Size = 3”x 3”
θJ = 45.8°C/W for 8-Pin SOIC w/PowerPAD (DDA)
θJ = 58.4°C/W for 8-Pin MSOP w/PowerPAD (DGN)
θJ = 95°C/W for 8-Pin SOIC High−K Test PCB (D)
θJ = 158°C/W for 8-Pin MSOP w/PowerPAD w/o Solder
A
A
A
A
Figure 73. Maximum Power Distribution vs
Ambient Temperature
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to consider not only quiescent power
dissipation, but also dynamic power dissipation. Often
times, this is difficult to quantify because the signal
pattern is inconsistent, but an estimate of the RMS
power dissipation can provide visibility into a possible
problem.
25
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
PIN8
(2)
REF
R9
(2)
C10
(2)
(2)
(2)
JP2
JP1
C9
J4
VS−
J5
GND
J6
VS+
TP1
TP2
(2) THS3095 EVM Only
FB2
FB1
VS−
VS+
+
C3
6.8 µF
C7
0.1 µF
C4
0.1 µF
C6
6.8 µF
+
J1
J2
R3
R4
1 kΩ
PIN8
249 Ω
R1
0 Ω
R5
VS+
REF
Open
R7
7
8
1
J3
2
3
6
49.9 Ω
4
R8
Open
R6
Open
5
R2
49.9 Ω
VS−
THS3091DDA or THS3095DDA
Figure 76. THS3091 EVM Board Layout
Figure 74. THS3091 EVM Circuit Configuration
(Second and Third Layers)
Figure 75. THS3091 EVM Board Layout
(Top Layer)
Figure 77. THS3091 EVM Board Layout
(Bottom Layer)
26
THS3091
THS3095
www.ti.com
SLOS423C–SEPTEMBER 2003–REVISED AUGUST 2004
Table 2. Bill of Materials
THS3091DDA and THS3095DDA EVM(1)
SMD
SIZE
REFERENCE
DESIGNATOR
PCB
QTY
MANUFACTURER'S
DISTRIBUTOR'S
PART NUMBER
ITEM
DESCRIPTION
PART NUMBER
(Steward) HI1206N800R-00
(AVX) TAJD685K050R
1
2
Bead, Ferrite, 3 A, 80 Ω
Cap, 6.8 µF, Tanatalum, 50 V, 10%
Cap, 0.1 µF, ceramic, X7R, 50 V
Cap, 0.1 µF, ceramic, X7R, 50 V
Resistor, 0 Ω, 1/8 W, 1%
Resistor, 249 Ω, 1/8 W, 1%
Resistor, 1 kΩ, 1/8 W, 1%
Open
1206
D
FB1, FB2
C3, C6
C9, C10
C4, C7
R9
2
2
(Digi-Key) 240-1010-1-ND
(Garrett) TAJD685K050R
(Garrett) 08055C104KAT2A
(Garrett) 08055C104KAT2A
(Garrett) RK73Z2ALTD
3
0805
0805
0805
0805
0805
1206
1206
1206
2512
2(2)
2
(AVX) 08055C104KAT2A
(AVX) 08055C104KAT2A
(KOA) RK73Z2ALTD
4
5
1(2)
1
6
R3
(KOA) RK73H2ALTD2490F
(KOA) RK73H2ALTD1001F
(Garrett) RK73H2ALTD2490F
(Garrett) RK73H2ALTD1001F
7
R4
1
8
R8
1
9
Resistor, 0 Ω, 1/4 W, 1%
Resistor, 49.9 Ω, 1/4 W, 1%
Open
R1
1
(KOA) RK73Z2BLTD
(Garrett) RK73Z2BLTD
10
11
R2, R7
R5, R6
2
(KOA) RK73Z2BLTD49R9F
(Garrett) RK73Z2BLTD49R9F
2
Header, 0.1-inch centers,
0.025-inch square pins
(2)
12
13
14
15
16
JP1, JP2
J1, J2, J3
J4, J5, J6
TP1, TP2
2
(Sullins) PZC36SAAN
(Amphenol) 901-144-8RFX
(SPC) 813
(Digi-Key) S1011-36-ND
(Newark) 01F2208
(Newark) 39N867
Connector, SMA PCB Jack
3
3
2
4
Jack, banana receptacle,
0.25-inch. dia. hole
Test point, black
(Keystone) 5001
(Digi-Key) 5001K-ND
(Newark) 89F1934
Standoff, 4-40 hex,
0.625-inch length
(Keystone) 1808
Screw, Phillips, 4-40,
0.25-inch
17
18
19
4
1
1
SHR-0440-016-SN
IC, THS3091(3)
IC, THS3095(2)
(TI) THS3091DDA(3)
(TI) THS3095DDA(2)
U1
(TI) EDGE # 6446289 Rev. A(3)
(TI) EDGE # 6446290 Rev. A(2)
Board, printed-circuit
(1) All items are designated for both the THS3091DDA and THS3095 EVMs unless otherwise noted.
(2) THS3095 EVM only.
(3) THS3091 EVM only.
ADDITIONAL REFERENCE MATERIAL
•
•
•
•
•
•
•
PowerPAD™ Made Easy, application brief (SLMA004)
PowerPAD™ Thermally Enhanced Package, technical brief (SLMA002)
Voltage Feedback vs Current Feedback Amplifiers, (SLVA051)
Current Feedback Analysis and Compensation (SLOA021)
Current Feedback Amplifiers: Review, Stability, and Application (SBOA081)
Effect of Parasitic Capacitance in Op Amp Circuits (SLOA013)
Expanding the Usability of Current-Feedback Amplifiers, 3Q 2003 Analog Applications Journal
(www.ti.com/sc/analogapps).
27
THERMAL PAD MECHANICAL DATA
www.ti.com
DDA (R-PDSO-G8)
THERMAL INFORMATION
This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an
external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be
used as a heatsink. In addition, through the use of thermal vias, the thermal pad can be attached directly to a
ground plane or special heatsink structure designed into the PCB. This design optimizes the heat transfer from
the integrated circuit (IC).
For additional information on the PowerPAD package and how to take advantage of its heat dissipating abilities,
refer to Technical Brief, PowerPAD Thermally Enhanced Package, Texas Instruments Literature No. SLMA002
and Application Brief, PowerPAD Made Easy, Texas Instruments Literature No. SLMA004. Both documents are
available at www.ti.com.
The exposed thermal pad dimensions for this package are shown in the following illustration.
8
5
Exposed Thermal Pad
2,85
1,27
1
4
2,85
1,27
Top View
NOTE: All linear dimensions are in millimeters
PPTD042
Exposed Thermal Pad Dimensions
PowerPAD is a trademark of Texas Instruments
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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Copyright 2004, Texas Instruments Incorporated
相关型号：
THS3092DG4
Dual- High-Voltage, Low Distortion, Current-Feedback Operational Amplifier 8-SOIC -40 to 85
TI
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