THS3215IRGVT_技术文档

THS3215

ZHCSEV9C –MARCH 2016 –REVISED JUNE 2021

THS3215 650MHz、差分转单端DAC 输出放大器

此双级放大器系统极具灵活性，可广泛应用于各类系统

中以提供低失真、直流耦合的差分转单端信号处理。输

入级会对 DAC 电阻端进行缓冲，并以 2V/V 的固定增

益对信号进行差分至单端转换。差分转单端输出可在外

部直接使用，也可经 RLC 滤波器或衰减器连接至内部

输出功率级 (OPS) 的输入端。宽带、电流反馈输出功

率级可在外部为全部引脚灵活设置增益。

1 特性

• 输入级：2V/V 的内部增益

– 经缓冲的差分输入

– 单端低阻抗输出

– 全功率带宽：350MHz (2V_PP

)

• 输出级：可从外部配置增益

– 全功率带宽：270MHz (5V_PP

– 压摆率：3000V/µs

– 单极双投(SPDT) 输入开关和多路复用器

输出功率级同相输入内部连接有一个 2×1 多路复用器

(mux)，方便选择内部差分转单端级 (D2S) 输出或外部

输入。

• 完整信号路径：输入级和输出级

可选片上中间电压缓冲器提供了宽带、低输出阻抗电

源，可在单电源运行期间通过信号路径级提供偏置。此

功能可为工作电源电压最高为 15.8V 的单电源、交流

耦合应用提供非常简单的偏置。此缓冲器接外部输入后

可实现直流纠错环路或简单的输出直流偏移功能。

– 三次谐波(HD2)（20MHz，5V_PP接至100Ω负

载）：-66dBc

– 三次谐波(HD3)（20MHz，5V_PP接至100Ω负

载）：-68dBc

– 10V_PP输出接至100Ω负载，使用

±6.5V 双电源

配套器件 THS3217 能够以更高的静态功率和带宽提供

相同的功能。THS3215 和 THS3217 支持面向 AWG

应用的德州仪器 (TI) 新上市的高速 DAC，例如

DAC38J82。

– 12V_PP输出接至高容性负载，使用15V 单电源

• 内部直流(DC) 基准缓冲器，具有低阻抗输出

• 电源电压范围：

器件信息⁽¹⁾

– 双电源：±4V 至±7.9V

– 单电源：8V 至15.8V

封装尺寸（标称值）

器件型号

THS3215

封装

VQFN (16)

4.00mm x 4.00mm

2 应用

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

• 数模转换器(DAC) 输出放大器

• 宽带任意波形发生器(AWG) 输出驱动器

• 前置驱动器接至> 20V_PP输出放大器(THS3091)

• 适用于压电式元件的单电源、高容性负载驱动器

3 描述

THS3215 整合了连接互补电流输出数模转换器 (DAC)

时所需的关键信号链组件。

VREF

162 ꢀ

THS3215

100 ꢀ

50 ꢀ

Output Power

Stage (OPS)

x1

D2S

Stage

249 ꢀ

25 ꢀ

SPDT

Switch

DAC

Complementary

Output Current

Input

Buffers

50 ꢀ

+

Vi

+

V_OUT= 5 Vi

50 ꢀ

Line

25 ꢀ

250 ꢀ

500 ꢀ

x1

RLC Filter

增益= 5V/V，带可选外部滤波器的差分转单端线路驱动器

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS780

THS3215

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ZHCSEV9C –MARCH 2016 –REVISED JUNE 2021

Table of Contents

7.5 Output Impedance Measurement............................. 26

7.6 Step-Response Measurement.................................. 26

7.7 Feedthrough Measurement.......................................26

7.8 Midscale Buffer R_OUTVersus C_LOADMeasurement..28

8 Detailed Description......................................................29

8.1 Overview...................................................................29

8.2 Functional Block Diagram.........................................30

8.3 Feature Description...................................................31

8.4 Device Functional Modes..........................................47

9 Application and Implementation..................................53

9.1 Application Information............................................. 53

10 Power Supply Recommendations..............................62

10.1 Thermal Considerations..........................................63

11 Layout...........................................................................64

11.1 Layout Guidelines................................................... 64

11.2 Layout Example...................................................... 65

12 Device and Documentation Support..........................66

12.1 Device Support....................................................... 66

12.2 Documentation Support.......................................... 66

12.3 接收文档更新通知................................................... 66

12.4 支持资源..................................................................66

12.5 Trademarks.............................................................66

12.6 Electrostatic Discharge Caution..............................67

12.7 Glossary..................................................................67

13 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 描述................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................4

6 Specifications.................................................................. 5

6.1 Absolute Maximum Ratings........................................ 5

6.2 ESD Ratings............................................................... 5

6.3 Recommended Operating Conditions.........................5

6.4 Thermal Information....................................................5

6.5 Electrical Characteristics: D2S....................................6

6.6 Electrical Characteristics: OPS...................................7

6.7 Electrical Characteristics: D2S + OPS......................10

6.8 Electrical Characteristics: Midscale (DC)

Reference Buffer..........................................................11

6.9 Typical Characteristics: D2S + OPS......................... 12

6.10 Typical Characteristics: D2S Only...........................14

6.11 Typical Characteristics: OPS Only.......................... 16

6.12 Typical Characteristics: Midscale (DC)

Reference Buffer......................................................... 20

6.13 Typical Characteristics: Switching Performance.....21

6.14 Typical Characteristics: Gain Drift...........................22

7 Parameter Measurement Information..........................23

7.1 Overview...................................................................23

7.2 Frequency Response Measurement.........................23

7.3 Harmonic Distortion Measurement........................... 25

7.4 Noise Measurement..................................................26

Information.................................................................... 67

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision B (December 2018) to Revision C (June 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• Changed the minimum Supply current parameter from: 23 mA to: 26 mA.........................................................6

• Changed the minimum VREF input pin gain parameter from: 0.985 V/V to: 0.975 V/V..................................... 6

• Changed the minimum Noninverting input resistance parameter from: 17.6 kΩ to: 16 kΩ................................ 7

• Changed the minimum Internal feedback resistor, R_Fparameter from: 17.6 kΩ to: 16 kΩ................................ 7

• Changed the Inverting input bias current –either input selected at T_J≈25°C from: -35 µA to: -75 µA (MIN)

and from: 35 µA to: 75 µA (MAX)........................................................................................................................7

• Changed the maximum Input pin bias current at 0-V input from: 4 µA to: 15µA................................................ 7

• Changed the maximum Supply current parameter from: 37.9 mA to: 39 mA...................................................10

• Changed the minimum VREF input pin gain parameter from: 0.985 V/V to: 0.975 V/V................................... 31

• Changed the I_biparameter from: -35 µA to: -75 µA (MIN) and -35 µA to: -75 µA (MAX)..................................42

• Changed the I_bi× R_Ferror term from: –7.095 µA to: -15.203 µA (MIN) and from: 7.095 µA to: 15.203 µA

(MAX)................................................................................................................................................................42

• Changed Total error from: –53.08 µA to: -61.19 µA (MIN) and from: 55.35 µA to: 63.46 µA (MAX)...............42

Changes from Revision A (April 2016) to Revision B (December 2018)

Page

• Changed DC output impedance parameter: deleted maximum specification, changed test level from A to C ....

6

• Changed DC output impedance parameter: deleted maximum specification, changed test level from A to C ....

7

2

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• Deleted minimum and maximum specifications from DC output impedance parameter.................................. 11

Changes from Revision * (March 2016) to Revision A (April 2016)

Page

• 将数据表状态从产品预发布更改为生产数据....................................................................................................... 1

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Device Comparison Table

TOTAL HARMONIC

DISTORTION

(5 V_PP, R_LOAD= 100 Ω,

20 MHz)

SMALL-SIGNAL

BANDWIDTH

0.1 V_PP

LARGE-SIGNAL

BANDWIDTH

5V_PP

QUIESCENT

CURRENT, Icc

(±6-V SUPPLIES)

CONTINUOUS

OUTPUT

CURRENT

PEAK

OUTPUT

CURRENT

DEVICE

(A_V= 5 V/V)⁽¹⁾

(A_V= 5 V/V)

140 mA

175 mA

THS3215

THS3217

650 MHz

800 MHz

270 MHz

500 MHz

35 mA

55 mA

95 mA

–64 dBc

–60 dBc

120 mA

(1) A_Vis the voltage gain.

5 Pin Configuration and Functions

1

2

3

4

12

VMID_IN

+IN

VINœ

VOUT

DISABLE

VIN+

11

10

9

œIN

(Thermal Pad)

PATHSEL

图5-1. RGV Package 16-Pin VQFN Top View

表5-1. Pin Functions

NAME

I/O

DESCRIPTION

NO.

1

VMID_IN

+IN

Input

DC reference buffer input

Positive signal input to D2S

Negative signal input to D2S

2

3

Input

–IN

4

PATHSEL

–VCC2⁽¹⁾

VO1

Input

Internal SPDT switch control: low selects the internal path, and high selects the external path

Negative supply for input stage

5

Power

Output

Power

Input

6

D2S external output

7

GND

Ground for control pins reference

–VCC1⁽¹⁾

VIN+

8

Negative supply for output stage

9

External OPS noninverting input

10

11

12

13

14

15

16

DISABLE

VOUT

Input

Output power stage shutdown control: low enables the OPS, and high disables the OPS

OPS output

Output

Input

OPS inverting input

VIN–

+VCC1⁽¹⁾

Power

Input

Positive supply for output stage

VREF

DC offsetting input to D2S

VMID_OUT

+VCC2⁽¹⁾

Output

Power

DC reference buffer output

Positive supply for input stage

Connect the thermal pad to GND for single-supply and split-supply operation. See 节10.1 section

for more information.

Thermal Pad

—

(1) Throughout this document +V_CCrefers to the voltage applied at the +VCC1 and +VCC2 pins, and –V_CCis the voltage applied at the

–VCC1 and –VCC2 pins.

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX

16.2

UNIT

Supply, +V_CC–(–V_CC

)

Voltage

Input/output

(+V_CC) + 0.5

±8

V

(–V_CC) –0.5

Differential input voltage (IN+ –IN–)

Continuous input current (IN+, IN–, VMID_IN, VIN+,

VIN–)⁽²⁾

±10

Current

mA

°C

Continuous output current⁽²⁾

±30

105

150

Operating, T_A

–55

–45

–65

Temperature

Junction, T_J

Storage, T_stg

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) Long-term continuous current for electromigration limits.

6.2 ESD Ratings

VALUE

±1000

UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾

V_(ESD)

Electrostatic discharge

V

Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

±4

NOM

±6

MAX

±7.9

15.8

85

UNIT

V

Bipolar supply

Single supply

V_CC

T_A

Supply voltage

8

12

Operating free-air temperature

25

°C

–40

6.4 Thermal Information

THS3215

THERMAL METRIC⁽¹⁾

RGV (VQFN)

UNIT

16 PINS

R_θJA

Junction-to-ambient thermal resistance

45

22

1

°C/W

R_θJC(top)

R_θJB

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

Junction-to-top characterization parameter

Junction-to-board characterization parameter

Junction-to-case (bottom) thermal resistance

ψ_JT

22

4

ψ_JB

R_θJC(bot)

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

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6.5 Electrical Characteristics: D2S

at +V_CC= 6.0 V, –V_CC= –6.0 V, A_V= 2 V/V, 25-Ωsource impedance, input common-mode voltage (V_IC) = 0.25 V, external

OPS input selected (PATHSEL ≥1.3 V), V_REF= GND, R_LOAD= 100 Ω, and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(1)

AC PERFORMANCE (Power Stage Disabled: DISABLE pin ≥1.3 V) ⁽⁵⁾

Small-signal bandwidth (SSBW)

Large-signal bandwidth (LSBW)

Bandwidth for 0.2-dB flatness

Slew rate⁽²⁾

V_OUT= 250 mV_PP, peaking < 1.0 dB

V_OUT= 2 V_PP

450

350

65

MHz

V/µs

C

V_OUT= 2 V_PP

V_OUT= 4-V step

1500

2%

1.2

Overshoot and undershoot

Rise and fall time

Input t_r= 1 ns, V_OUT= 2-V step

f = 20 MHz, V_OUT= 2 V_PP

f > 200 kHz

ns

Settling time to 0.1%

5

2nd-order harmonic distortion (HD2)

3rd-order harmonic distortion (HD3)

Output voltage noise

dBc

–72

–88

12

nV/√Hz

pA/√Hz

Ω

Input current noise (each input)

Output impedance

f > 200 kHz

2.0

f = 20 MHz

0.9

DC PERFORMANCE ⁽⁵⁾

Differential to single-ended gain

Differential to single-ended gain drift

±100-mV output

1.975

0.975

2.0

37

2.025

V/V

A

B

43 ppm/°C

T_J= –40°C to +125°C

Differential inputs = 0 V,

V_REF= ±100 mV

VREF input pin gain

1.0

1.015

V/V

A

VREF input pin gain drift

ppm/°C

mV

B

A

B

A

B

A

B

T_J= –40°C to +125°C

T_J≈25°C

–67

–74

35

±8

–35

–37

–39

–4

Output offset voltage

T_J= 0°C to 70°C

36

mV

38

mV

T_J= –40°C to +125°C

T_J≈25°C

Output offset voltage drift

Input bias current –each input⁽³⁾

Input bias current drift

Input offset current

µV/°C

µA

–25

–45

4

±2

–4

T_J= 0°C to 70°C

4.3

4.5

5

µA

–4.2

–4.3

3

µA

T_J= –40°C to +125°C

T_J≈25°C

4

nA/°C

nA

±50

400

535

700

3

–400

–475

–595

–3

T_J= 0°C to 70°C

nA

T_J= –40°C to +125°C

Input offset current drift

0.2

1.8

1.3

nA/°C

INPUTS⁽⁴⁾

1.9

2.0

1.4

1.5

V

A

B

A

B

A

C

T_J≈25°C

Common-mode input negative supply

headroom

V

T_J= –40°C to +85°C

T_J≈25°C

Common-mode input positive supply

headroom

V

T_J= –40°C to +125°C

–1 V ≤V_IC≤3 V

V_CM= 0 V

Common-mode rejection ratio (CMRR)

Input impedance differential mode

Input impedance common mode

OUTPUT⁽⁶⁾

42

48

20 || 2.3

dB

kΩ|| pF

V_CM= 0 V

6

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6.5 Electrical Characteristics: D2S (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, A_V= 2 V/V, 25-Ωsource impedance, input common-mode voltage (V_IC) = 0.25 V, external

OPS input selected (PATHSEL ≥1.3 V), V_REF= GND, R_LOAD= 100 Ω, and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(1)

1.4

1.5

1.75

1.95

V

A

B

A

C

T_J≈25°C

Output voltage headroom to either supply

T_J= –40°C to +85°C

±0.8 V_PP, R_LOAD= 20 Ω

Load current = ±20 mA

Output current drive

DC output impedance

±35

±45

0.3

mA

Ω

POWER SUPPLY (D2S + Midsupply Buffer Only; OPS Disabled: DISABLE pin ≥1.3 V)

Supply current

±6-V supplies

20.2

21.3

8

26

mA

A

C

Supply current temperature coefficient

µA/°C

Positive power-supply rejection ratio

(+PSRR)

Referred to input

62

61

71

dB

A

Negative power-supply rejection ratio (–

PSRR)

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈T_J≈25°C; over temperature limits by

characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for

information. DC limits tested with no self-heating. Add internal self heating to T_Afor T_J.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π× f_–3dB

(3) Currents out of pin treated as a positive polarity.

.

(4) Applies to input pins 2 (IN+) and 3 (IN–).

(5) Output measured at pin 6.

(6) Output measured at pin 6.

6.6 Electrical Characteristics: OPS

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF

=

GND, R_F= 249 Ω⁽¹⁾, R_G= 162 Ω, A_V= 2.5 V/V, OPS R_LOAD= 100 Ω, OPS enabled (DISABLE ≤0.7 V or floated), external

OPS input selected (PATHSEL ≥1.3 V), and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(2)

AC PERFORMANCE ⁽⁴⁾

Small-signal bandwidth (SSBW)

Large-signal bandwidth (LSBW)

Bandwidth for 0.2-dB flatness

Slew rate⁽³⁾

V_OUT= 100 mV_PP, peaking < 2.0 dB

V_OUT= 5 V_PP

700

270

110

3000

4%

MHz

V/µs

C

V_OUT= 5 V_PP

V_OUT= 5-V step

Overshoot and undershoot

Rise and fall time

Input t_r= 1 ns, V_OUT= 5-V step

f = 20 MHz, V_OUT= 5 V_PP

f > 200 kHz

1.7

ns

Settling time to 0.1%

25

2nd-order harmonic distortion (HD2)

3rd-order harmonic distortion (HD3)

Noninverting input voltage noise

Noninverting input current noise

Inverting input current noise

Closed-loop ac output impedance

dBc

–66

–68

2.7

nV/√Hz

pA/√Hz

Ω

f > 200 kHz

1.3

f > 200 kHz

18

f = 20 MHz

0.25

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6.6 Electrical Characteristics: OPS (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF

=

GND, R_F= 249 Ω⁽¹⁾, R_G= 162 Ω, A_V= 2.5 V/V, OPS R_LOAD= 100 Ω, OPS enabled (DISABLE ≤0.7 V or floated), external

OPS input selected (PATHSEL ≥1.3 V), and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(2)

DC PERFORMANCE ⁽⁴⁾

Open-loop transimpedance gain⁽¹⁾

Closed-loop gain

800

1700

A

V_OUT= ±1 V, R_LOAD= 500-Ω

kΩ

0.1% external R_Fand R_Gresistors

2.495

2.515

2.53

V/V

INPUT

±2.5

12

12.5

13.7

mV

A

B

T_J≈25°C

–12

–13

External input offset voltage

(pin 9 to pin 12)

T_J= 0°C to 70°C

T_J= –40°C to +125°C

–14.1

External input offset voltage drift

(pin 9 to pin 12)

µV/°C

B

T_J= –40°C to +125°C

–3

–12

–21

±2.5

15

15.4

16

mV

A

B

T_J≈25°C

–15

–15.7

–16.6

Internal input offset voltage

(pin 6 to pin 12)

T_J= 0°C to 70°C

T_J= –40°C to +125°C

Internal input offset voltage drift

(pin 6 to pin 12)

µV/°C

mV

B

C

T_J= –40°C to +125°C

–3

–7

–10

–16

External to internal input offset voltage

match

±1.2

±5

7

15

15.2

15.4

µA

A

B

T_J≈25°C

–5

External noninverting input bias current

(pin 9)⁽⁵⁾

T_J= 0°C to 70°C

T_J= –40°C to +125°C

–5.2

External noninverting input bias current

drift (pin 9)

0

2

3.3 nA/°C

B

T_J= –40°C to +125°C

±5

75

37

µA

A

B

A

C

T_J≈25°C

–75

–39

Inverting input bias current –either input

T_J= 0°C to 70°C

T_J= –40°C to +125°C

selected⁽⁵⁾

40.5

µA

–43.5

–15

Inverting input bias current drift

Input headroom to either supply

Common-mode rejection ratio (CMRR)

Noninverting input resistance

Noninverting input capacitance

Open-loop inverting input impedance

OUTPUT⁽⁶⁾

nA/°C

V

–50

2.6

53

–85

3.0

±3.4-V input range

45

16

dB

18.5

3.3

74

22.4

kΩ

pF

Ω

1.3

1.4

1.6

1.8

V

A

B

R_LOAD= 500 Ω, T_J≈25°C

Output voltage headroom to either supply

R_LOAD= 500 Ω, T_J= –40°C to

+125°C

Linear output current

Peak output current

75

90

140

mA

A

C

A

±1.7 V into 20-ΩR_LOAD

120

±2.6-V into 20-ΩR_LOAD

DC output impedance

Internal feedback resistor, R_F

0-V output, load current = ±40 mA

Between pins 11 and 12

0.05

18.5

Ω

16

22.4

kΩ

8

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ZHCSEV9C –MARCH 2016 –REVISED JUNE 2021

6.6 Electrical Characteristics: OPS (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, D2S input common-mode voltage (V_IC) = 0.25 V, V_REF

=

GND, R_F= 249 Ω⁽¹⁾, R_G= 162 Ω, A_V= 2.5 V/V, OPS R_LOAD= 100 Ω, OPS enabled (DISABLE ≤0.7 V or floated), external

OPS input selected (PATHSEL ≥1.3 V), and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(2)

PATHSEL (Pin 4; Logic Reference = Pin 7 = GND)

Input low logic level

Internal path selected

0.7

0.9

V

A

C

A

C

Input high logic level

External input selected at VIN pin

1.3

+V_CC

40

Input voltage range

V

–0.5

PATHSEL voltage when floated

Internal input from D2S selected

0-V input

0

20

mV

µA

15

Input pin bias current⁽⁷⁾

3.3-V input

–150

–250

Input pin impedance

18 || 1.5

80

kΩ|| pF

ns

Switching time

To 1% of final value

Both inputs at GND

± 2-V input

Input switching glitch

Deselected input dc isolation

Deselected input ac isolation

50

mV

70

55

80

dB

2 V_PP, at 20-MHz input

65

dB

DISABLE (Pin 10; Logic Reference = Pin 7 = GND)

Input low logic level

0.7

0.9

V

A

B

A

C

A

C

Input high logic level

1.3

+V_CC

40

Shutdown control voltage range

V

–0.5

Shutdown voltage when floated

Input pin bias current⁽⁷⁾

Output stage enabled

0

20

mV

µA

0-V input

4

3.3-V input

–150

–250

Input pin impedance

18 || 1.5

200

kΩ|| pF

ns

Switching time (turn on or off)

Shutdown dc isolation (either input)

Shutdown ac isolation (either input)

POWER SUPPLY

To 10% of final value

±2-V input

70

55

80

dB

2 V_PPat 20-MHz input

65

dB

Supply current (OPS only)

±6-V supplies

9.6

1.5

10.8

2

12

2.9

mA

µA

A

B

A

Disabled supply current in OPS

Logic reference current at pin 7⁽⁷⁾

±6-V supplies

Pins 4, 7, and 10 held at 0 V

200

280

380

Positive power-supply rejection ratio

(+PSRR)

Referred to input

55

53

60

56

dB

A

Negative power-supply rejection ratio (–

PSRR)

(1) Output power stage includes an internal 18.5-kΩfeedback resistor. This internal resistor, in parallel with an external 249-ΩR_Fand

162-ΩR_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈T_J≈25°C; over temperature limits by

characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for

information. DC limits tested with no self-heating. Add internal self heating to T_Afor T_J.

(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π× f_–3dB

(4) Output measured at pin 11.

.

(5) Currents out of pin treated as a positive polarity.

(6) Output measured at pin 11.

(7) Currents out of pin treated as a positive polarity.

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6.7 Electrical Characteristics: D2S + OPS

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, D2S input V_IC= 0.25 V, internal path selected to OPS

(PATHSEL ≤0.7 V or floated), V_REF= GND, combined A_V= 5 V/V, D2S R_LOAD= 200 Ω, R_F= 249 Ω⁽¹⁾, R_G= 162 Ω(OPS

A_V= 2.5 V/V), OPS enabled (DISABLE ≤0.7 V or floated), OPS R_LOAD= 100 Ω, and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(2)

AC PERFORMANCE⁽⁴⁾

Small-signal bandwidth (SSBW)

Large-signal bandwidth (LSBW)

Bandwidth for 0.2-dB flatness

Slew rate⁽³⁾

V_OUT= 100 mV_PP, peaking < 1.5 dB

V_OUT= 5 V_PP

650

270

110

3000

4%

MHz

V/µs

C

V_OUT= 2 V_PP

V_OUT= 8-V step

Overshoot and undershoot

Rise and fall time

Input t_r= 1 ns, V_OUT= 5-V step

1.7

ns

Settling time to 0.1%

25

2nd-order harmonic distortion (HD2) f = 20 MHz, V_OUT= 5 V_PP

3rd-order harmonic distortion (HD3) f = 20 MHz, V_OUT= 5 V_PP

dBc

–66

–68

33

Output voltage noise

f > 200 kHz, A_V= 5 V/V

nV/√Hz

DC PERFORMANCE⁽⁴⁾

0.1% tolerance external resistors, dc,

±100-mV output test

Total gain D2S to OPS output⁽¹⁾

4.92

32.7

5.02

5.12

39

V/V

A

POWER SUPPLY (Combined D2S, OPS, and Midscale Reference Buffer)

Supply current

±6-V supplies

34.5

±5

mA

A

C

Supply current temperature

coefficient

T_J= 0°C to 100°C

µA/°C

(1) Output power stage includes an internal 18.5-kΩfeedback resistor. This internal resistor, in parallel with an external 249-ΩR_Fand

162-ΩR_G, results in a gain of 2.5 V/V after including a nominal gain loss of 0.9935 V/V due to the input buffer and loop-gain effects.

(2) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈T_J≈25°C; over temperature limits by

characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for

information.

(3) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (Vpeak / √2) × 2π× f_–3dB

.

(4) Output measured at pin 11.

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6.8 Electrical Characteristics: Midscale (DC) Reference Buffer

at +V_CC= 6.0 V, –V_CC= –6.0 V, R_LOAD= 150 Ωat pin 15, and T_J≈25°C (unless otherwise noted)

TEST

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

LEVEL

(1)

AC PERFORMANCE (Output measured at pin 15)

Small-signal bandwidth (SSBW)

Large-signal bandwidth (LSBW)

Slew rate⁽²⁾

V_OUT= 100 mV_PP

200

50

MHz

C

V_OUT= 1 V_PP

V_OUT= 4-V step

f > 5 kHz

110

4.6

1.3

2.5

V/µs

Input voltage noise

nV/√Hz

pA/√Hz

Ω

Input current noise

f > 5 kHz

AC output impedance

f = 20 MHz, no load current

DC AND I/O PERFORMANCE (R_S= 25 Ω, and output measured at pin 15, unless otherwise noted)

Buffer gain

.9985

0.999

–1.2

30

1.001

–2.2

70

V/V

ppm/°C

mV

A

B

A

V_I= ±1 V, R_LOAD= 200 Ω

T_J= –40°C to +125°C

Buffer gain drift

Output offset from midsupply

Output offset voltage

Input floating, pin 1 open

–120

–1.0

4.0

15

mV

Input driven to 0 V from 0-Ωsource

T_J= –40°C to +125°C, input driven

to 0 V

Input offset voltage drift

4

9

15

µV/°C

B

Input bias current⁽³⁾

±1

10

5

µA

A

B

–10

–5

Input bias current drift

nA/°C

T_J= –40°C to +125°C

Input/output headroom to either

supply

gain change < 1%

1.1

1.4

V

A

C

Internal 50-kΩdivider resistors to

each supply

Input impedance

22 || 1.5

kΩ|| pF

mA

Linear output current into resistive

load

40

65

A

C

A

±1.62 V into 36 Ω

DC output impedance

Load current = ±30 mA

0.3

Ω

Positive power-supply rejection ratio Referred to input with VMID_IN (pin

(+PSRR)

60

69

dB

1) at GND

Negative power-supply rejection ratio

(—PSRR)

Referred to input with VMID_IN (pin

1) at GND

dB

A

(1) Test levels (all values set by characterization and simulation): (A) 100% tested at T_A≈T_J≈25°C; over temperature limits by

characterization and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for

information.

(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (V_PEAK/ √2) × 2π× f_–3dB

(3) Currents out of pin treated as a positive polarity.

.

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6.9 Typical Characteristics: D2S + OPS

at +V_CC= 6 V, –V_CC= –6 V, 25-ΩD2S source impedance , V_IC= 0.25 V, internal path selected (PATHSEL = GND), V_REF

GND, D2S R_LOAD= 200 Ωat pin 6, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5 V/V, OPS On (DISABLE = GND), OPS R_LOAD

100 Ωat pin 11, and T_J≈25°C (unless otherwise noted)

=

17

15

13

11

9

4

3

2

1

0

7

-1

-2

-3

-4

0.5 Vpp

1 Vpp

2 Vpp

5 Vpp

8 Vpp

5

500 mV_PP

5 V_PP

3

1

10M

100M

Frequency (Hz)

1G

Time (20ns/div.)

D001

D002

图6-1. Frequency Response vs Output Voltage

图6-2. Small- and Large-Signal Step Response

-20

-30

-40

-30

-40

-50

-60

-70

-80

-90

-100

-50

-60

-70

-80

-90

2 V_PP

5 V_PP

8 V_PP

2 V_PP

5 V_PP

8 V_PP

-100

-110

1M

10M

Test Frequency (Hz)

100M

1M

10M

Test Frequency (Hz)

100M

D003

D004

图6-3. HD2 vs Frequency

图6-4. HD3 vs Frequency

5.05

5.04

5.03

5.02

5.01

5

100

10

1

4.99

4.98

-55

-35

-15

5

25

45

65

85

105 125

100

1k

10k

100k

Frequency (Hz)

1M

10M

100M

Junction Temperature (èC)

D005

D006

30 units shown

25-Ωsource impedance on each D2S input

图6-6. Input-Referred Differential Noise

图6-5. Gain vs Temperature

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6.9 Typical Characteristics: D2S + OPS (continued)

at +V_CC= 6 V, –V_CC= –6 V, 25-ΩD2S source impedance , V_IC= 0.25 V, internal path selected (PATHSEL = GND), V_REF

=

GND, D2S R_LOAD= 200 Ωat pin 6, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5 V/V, OPS On (DISABLE = GND), OPS R_LOAD

100 Ωat pin 11, and T_J≈25°C (unless otherwise noted)

3

2

1

0

1

-1

-2

-3

-4

-5

-6

-7

0

-1

-2

-3

-4

-5

-6

-7

3 V/V

5 V/V

10 V/V

20 V/V

3 V/V

5 V/V

10 V/V

20 V/V

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D007

D008

V_OUT= 500 mV_PP, see 表8-1

V_OUT= 5 V_PP, see 表8-1

图6-7. Small-Signal Frequency Response vs Gain

图6-8. Large-Signal Frequency Response vs Gain

-20

-30

-40

-50

-60

-70

-30

-40

-50

-60

-70

-80

3 V/V

5 V/V

3 V/V

5 V/V

-90

10 V/V

20 V/V

10 V/V

20 V/V

-100

1M

10M

Frequency (Hz)

100M

1M

10M

Frequency (Hz)

100M

D009

D010

V_OUT= 5 V_PP, see 表8-1

图6-9. HD2 vs Gain

V_OUT= 5 V_PP, see 表8-1

图6-10. HD3 vs Gain

-40

-50

-20

-30

-40

-50

-60

-70

-80

-90

-100

1 V_PP

2 V_PP

5 V_PP

8 V_PP

-60

-70

-80

1 V_PP

2 V_PP

5 V_PP

8 V_PP

-90

-100

8

9

10

11

12

13

14

Total Balanced Supply Voltage (V)

15

16

8

9

10

11

12

13

14

Total Balanced Supply Voltage (V)

15

16

D012

D011

Test frequency = 20 MHz

图6-12. HD3 vs Supply Voltage

图6-11. HD2 vs Supply Voltage

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6.10 Typical Characteristics: D2S Only

at +V_CC= 6.0 V, –V_CC= –6.0 V, fixed gain of 2 V/V, 25-ΩD2S source impedance, V_IC= 0.25 V, external path selected

(PATHSEL = +V_CC), V_REF= GND, D2S R_LOAD= 100 Ωat pin 6, and T_J≈25°C (unless otherwise noted)

7

6

7

6

5

4

3

2

1

V_CM= -1 V

V_CM= 0 V

V_CM= 0.25 V

V_CM= 1 V

V_CM= 2 V

50 W

0

100 W

200 W

500 W

-1

-2

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D013

D014

V_OUT= 250 mV_PP

V_OUT= 2 V_PP

图6-13. Frequency Response vs Input Common-Mode Voltage

图6-14. Frequency Response vs Load Resistance

-20

-30

-40

-50

-60

-70

-30

-40

-50

-60

-70

-80

1 V_PP

2 V_PP

4 V_PP

1 V_PP

2 V_PP

4 V_PP

-90

-100

1M

10M

Frequency (Hz)

100M

1M

10M

Frequency (Hz)

100M

D015

D016

图6-15. HD2 vs Output Voltage

图6-16. HD3 vs Output Voltage

50

45

40

35

30

25

100

10

1

R_S= 0 W

R_S= 25 W

R_S= 100 W

R_S= 1 kW

V_CM= -1 V

V_CM= 0 V

V_CM= 0.25 V

V_CM= 1 V

V_CM= 2 V

V_CM= 3 V

100

1k

10k

100k

Frequency (Hz)

1M

10M

100M

1M

10M

Frequency (Hz)

100M

D018

D017

图6-18. Differential Input Noise vs Source Impedance

图6-17. Common-Mode Rejection Ratio vs Input Common-Mode

Voltage

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6.10 Typical Characteristics: D2S Only (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, fixed gain of 2 V/V, 25-ΩD2S source impedance, V_IC= 0.25 V, external path selected

(PATHSEL = +V_CC), V_REF= GND, D2S R_LOAD= 100 Ωat pin 6, and T_J≈25°C (unless otherwise noted)

14

12

10

8

10

1

6

4

ê4 V

ê5 V

2

ê6 V

ê7.5 V

0.1

0

100k

1M

10M

100M

-55

-35

-15

5

25

45

65

85

105 125

Frequency (Hz)

Junction Temperature (èC)

D020

D019

图6-20. Output Impedance vs Supply Voltage

30 units shown

图6-19. Output DC Offset Voltage vs Die Temperature

1.5

1.1

100 W

200 W

500 W

1.05

1

0.5

0

0.95

0.9

0.85

0.8

-0.5

-1

100 W

200 W

500 W

-1.5

Time (5 ns/div)

Time (20 ns/div)

D022

D021

±1-V output pulse

图6-22. Large-Signal Pulse Settling Response vs Load

图6-21. Large-Signal Step Response vs Load Resistance

Resistance

1

0

70

65

60

55

50

-1

-2

45

V_CM= -1 V, PSRR+

V_CM= -1 V, PSRR-

V_CM= 0 V, PSRR+

V_CM= 0 V, PSRR-

V_CM= 3 V, PSRR+

V_CM= 3 V, PSRR-

-3

0.1 Vpp

0.25 Vpp

0.5 Vpp

1 Vpp

2 Vpp

40

-4

35

30

-5

1M

10M

100M

Frequency (Hz)

1G

10k

100k

1M

10M

Frequency (Hz)

D023

D024

图6-24. Simulated Power-Supply Rejection Ratio vs Input

25-ΩD2S source impedance on each input

Common-Mode Voltage

图6-23. VREF Input Pin Frequency Response

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6.11 Typical Characteristics: OPS Only

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, V_REF= GND, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5V/V,

OPS R_LOAD= 100 Ωat pin 11, OPS enabled (DISABLE = GND), external input path selected (PATHSEL = +V_CC), and T_J≈

25°C (unless otherwise noted)

6

2

A_V= 1.5 V/V

A_V= 2.5 V/V

A_V= 5 V/V

4

A_V= 10 V/V

0

2

0

-2

-4

-6

-2

-4

-6

A_V= -1 V/V

A_V= -2.5 V/V

A_V= -5 V/V

A_V= -10 V/V

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D025

D026

V_OUT= 100 mV_PP, see 表8-1 for R_Fvalues vs gain

V_OUT= 100 mV_PP, see 表8-3 for R_Fvalues vs gain

图6-25. Frequency Response vs Noninverting Gain

图6-26. Frequency Response vs Inverting Gain

10

8

6

4

8

6

4

2

0.5 V_PP

2 V_PP

5 V_PP

6 V_PP

2 V_PP

5 V_PP

6 V_PP

0

-2

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D027

D028

图6-27. Noninverting Response vs Output Voltage

A_V= –2.5 V/V, see 表8-3 for R_Fvalue

图6-28. Inverting Response vs Output Voltage

3.5

3

2

500 mV_PP

5 V_PP

2.5

1.5

1

0.5

0

-0.5

-1.5

-2.5

-3.5

-1

-2

-3

500 mV_PP

5 V_PP

Time (10ns/div.)

D029

D030

图6-29. Noninverting Step Response

A_V= –2.5 V/V, see 表8-3 for R_Fvalue

图6-30. Inverting Step Response

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6.11 Typical Characteristics: OPS Only (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, V_REF= GND, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5V/V,

OPS R_LOAD= 100 Ωat pin 11, OPS enabled (DISABLE = GND), external input path selected (PATHSEL = +V_CC), and T_J≈

25°C (unless otherwise noted)

-25

-35

-45

-55

-65

-75

-85

-95

-105

-25

-35

-45

-55

-65

-75

-85

-95

-105

1 V_PP

2 V_PP

5 V_PP

8 V_PP

1 V_PP

2 V_PP

5 V_PP

8 V_PP

1M

10M

Frequency (Hz)

100M

1M

10M

Frequency (Hz)

100M

D032

D031

图6-32. HD3 vs Output Voltage

图6-31. HD2 vs Output Voltage

-35

-45

-55

-65

-75

-85

-95

-105

-35

-45

-55

-65

-75

-85

-95

-105

100 W

200 W

500 W

100 W

200 W

500 W

1M

10M

Frequency (Hz)

100M

1M

10M

Frequency (Hz)

100M

D033

D034

V_OUT= 5 V_PP

图6-33. HD2 vs Load Resistance

图6-34. HD3 vs Load Resistance

-25

-35

-45

-55

-65

-75

-85

-95

-105

-25

-35

-45

-55

-65

-75

-85

-95

-105

4 V

5 V

6 V

7.5 V

4 V

5 V

6 V

7.5 V

1M

10M

Frequency (Hz)

100M

1M

10M

Frequency (Hz)

100M

D035

D036

V_OUT= 5 V_PP

图6-35. HD2 vs Supply Voltage

图6-36. HD3 vs Supply Voltage

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6.11 Typical Characteristics: OPS Only (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, V_REF= GND, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5V/V,

OPS R_LOAD= 100 Ωat pin 11, OPS enabled (DISABLE = GND), external input path selected (PATHSEL = +V_CC), and T_J≈

25°C (unless otherwise noted)

-30

-40

-50

-60

-70

-80

-90

-30

-40

-50

-60

-70

-80

-90

0.25 V_PP

1 V_PP

2.5 V_PP

4 V_PP

0.25 V_PP

1 V_PP

2.5 V_PP

4 V_PP

1

10

Center Frequency (MHz)

100

1

10

Center Frequency (MHz)

100

D037

D038

±100-kHz tone separation, output voltage for each tone

图6-37. Second-Order Intermodulation Distortion vs Output

图6-38. Third-Order Intermodulation Distortion vs Output

Voltage

1000

5

4

Voltage Noise

Noninverting Current Noise

Inverting Current Noise

3

2

100

10

1

0

-1

-2

-3

-4

-5

100

1k

10k 100k

Frequency (Hz)

1M

10M

10

100

Load Resistance (W)

1k

D039

D040

图6-39. Input-Referred Spot Noise vs Frequency

Output swing with better than 0.1% linearity

图6-40. Linear Output Swing vs Load Resistance

11.8

12

Measured V_OUT

Ideal V_OUT

8

4

11.4

11

0

10.6

10.2

9.8

-4

-8

-12

-55

-35

-15

5

25

45

65

85

105 125

0

1

2

3

4

5

Junction Temperature (⁰C)

Time (ms)

D041

D042

30 units shown

±4.5-V input triangular wave, OPS A_V= –2.5 V/V

图6-42. Output Overdrive Response

图6-41. Quiescent Supply Current vs Temperature

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6.11 Typical Characteristics: OPS Only (continued)

at +V_CC= 6.0 V, –V_CC= –6.0 V, 25-ΩD2S source impedance, V_REF= GND, R_F= 249 Ω, R_G= 162 Ω, OPS A_V= 2.5V/V,

OPS R_LOAD= 100 Ωat pin 11, OPS enabled (DISABLE = GND), external input path selected (PATHSEL = +V_CC), and T_J≈

25°C (unless otherwise noted)

50

45

40

35

30

25

20

15

10

5

10

9

8

7

6

5

4

3

2

1

0

A_V= 2.5 V/V

A_V= 5 V/V

A_V= 10 V/V

0 pF

4.7 pF

10 pF

22 pF

47 pF

100 pF

220 pF

470 pF

1nF

0

1

10 100

Load Capacitance (pF)

1k

1M

10M

100M

Frequency (Hz)

1G

D043

D044

V_OUT= 500 mV_PP, see Series Output Resistance vs Load

Capacitance for R_Svalue

See 表8-6 for R_Fvalues vs OPS gain

图6-43. Series Output Resistance vs Load Capacitance

图6-44. Frequency Response vs Load Capacitance

-20

47 pF

100 pF

220 pF

330 pF

-40

47 pF

100 pF

220 pF

330 pF

-30

-40

-50

-60

-70

-80

-90

-100

-30

-50

-60

-70

-80

-90

1M

10M

20M

1M

10M

20M

Frequency (Hz)

D045

D046

±V_CC= ±7.5 V, R_F= 158 Ω, A_V= 5 V/V, V_OUT= 10 V_PP, see

Series Output Resistance vs Load Capacitance for R_Svalue

图6-45. HD2 vs Load Capacitance

图6-46. HD3 vs Load Capacitance

6

2 V_PP

10 V_PP

2 V_PP

10 V_PP

4

2

0

2

0

-2

-4

-2

-4

-6

Time (50 ns/div.)

Time (50 ns/div)

D047

D048

±V_CC= ±7.5 V, C_LOAD= 100 pF, R_F= 158 Ω, A_V= 5 V/V, see

±V_CC= ±7.5 V, C_LOAD= 150 pF, R_F= 158 Ω, A_V= 5 V/V, see

Series Output Resistance vs Load Capacitance for R_Svalue

Series Output Resistance vs Load Capacitance for R_Svalue.

图6-47. Pulse Response

图6-48. Pulse Response

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6.12 Typical Characteristics: Midscale (DC) Reference Buffer

at +V_CC= 6.0 V, –V_CC= –6.0 V, R_LOAD= 150 Ω, and T_J≈25°C (unless otherwise noted)

1

0

0.6

0.4

0.2

0

100 mV_PP

1 V_PP

-1

-2

-3

-4

-5

-6

-7

-8

-0.2

-0.4

-0.6

0.1V_PP

1.0V_PP

Time (20 ns/div)

1M

10M

Frequency (Hz)

100M

700M

D050

D049

图6-50. Step Response

图6-49. Frequency Response vs Output Voltage

100

60

50

40

30

20

10

0

I_O= 0 mA

I_O= -20 mA

I_O= 20 mA

GND I/P, I_LOAD= 0 mA

GND I/P, I_LOAD= -20 mA

GND I/P, I_LOAD= 20 mA

Float I/P, I_LOAD= 0 mA

Float I/P, I_LOAD= -20 mA

Float I/P, I_LOAD= 20 mA

10

1

0.1

0.01

100k

-10

-40

1M

10M

100M

-20

0

20

40

60

80

100

120

Frequency (Hz)

Junction Temperature (èC)

D051

D052

图6-51. Buffer Output Impedance vs Load Current

图6-52. Buffer Output Offset vs Load Current (I_LOAD

)

7

3

6

5

4

3

2

1

0

-3

-6

No Cap

1 nF

10 nF

100 nF

-9

-12

1M

10M

Frequency (Hz)

100M

500M

1

10

Load Capacitance (nF)

100

D054

D053

V_OUT= 100 mV_PP, R_LOAD= 150 Ωin parallel with C_LOAD, see

节7.8 for circuit setup

R_LOAD= 150 Ωin parallel with C_LOAD, see the 节7.8 section

for circuit setup

图6-53. Series Resistance vs Capacitive Load

图6-54. Frequency Response vs Capacitive Load

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6.13 Typical Characteristics: Switching Performance

at +V_CC= 6 V, –V_CC= –6 V, 25-ΩD2S source impedance , V_IC= 0.25 V, internal path selected (PATHSEL = GND), V_REF

=

GND, D2S R_LOAD= 200 Ωat pin 6, R_F= 249 Ω, R_G= 162 Ω, OPS On (DISABLE = GND), OPS R_LOAD= 100 Ωat pin 11,

and T_J≈25°C (unless otherwise noted)

3.5

3

3.5

3

2.5

2

2.5

2

1.5

1

1.5

1

0.5

0

0.5

0

-0.5

-1

PATHSEL In

OPS V_OUT

DISABLE In

OPS V_OUT

-0.5

-1.5

Time (100 ns/div.)

D055

D056

PATHSEL = high, OPS input: VIN+ = 1 V_PP, 10-MHz sine

wave

D2S Inputs: IN+ = IN–= GND, OPS input: VIN+ = 1 V

图6-55. PATHSEL Switching Time

图6-56. OPS Enable and Disable Time

-20

-10

Ext Path, OPS A_V= 2.5 V/V

Ext Path, OPS A_V= 10 V/V

-30

Int Path, OPS A_V= 2.5 V/V

Ext Path, OPS A_V= 2.5 V/V

-20

Int Path, OPS A_V= 10 V/V

-40

-50

-30

-40

-50

-60

-70

-80

-60

-70

-80

-90

-100

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D057

D058

图6-57. OPS Forward Feedthrough in Disable

图6-58. OPS Reverse Feedthrough in Disable

3

2.5

2

3.5

3

2.5

2

DISABLE In

ê5-V supply

ê6-V supply

ê7.5-V supply

1.5

1

1.5

1

0.5

0

0.5

0

PATHSEL In

ê5-V supply

ê6-V supply

ê7.5-V supply

-0.5

Time (1 ms/div.)

D059

D060

PATHSEL = high, OPS input: VIN+ = 1 V

D2S inputs: IN+ = IN–= GND, OPS input: VIN+ = 1 V

图6-60. OPS Shutdown Threshold vs Power Supply

图6-59. PATHSEL Switching Threshold vs Power Supply

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6.14 Typical Characteristics: Gain Drift

at +V_CC= 6 V, –V_CC= –6 V, 50-ΩD2S source impedance , V_IC= 0.25 V, internal path selected (PATHSEL = GND), V_REF

GND, D2S R_LOAD= 100 Ωat pin 6, R_F= 249 Ω, R_G= 162 Ω, OPS on (DISABLE = GND), OPS R_LOAD= 100 Ωat pin 11,

and T_J≈25°C (unless otherwise noted)

=

2

1.995

1.99

12

10

8

7

6

5

1.985

1.98

4

2

1

0

1.975

0

-55

-35

-15

5

25

45

65

85

105 125

Junction Temperature (⁰C)

Gain Drift (ppm/èC)

D061

D062

D064

D066

30 units shown

图6-61. D2S Gain Over Temperature

30 units from –40°C to +125°C

图6-62. D2S Gain Drift Histogram

2.524

2.522

2.52

10

9

8

7

6

5

4

3

2

1

0

9

8

6

2.518

2.516

2.514

2.512

2

1

0

-55

-35

-15

5

25

45

65

85

105 125

Junction Temperature (⁰C)

Gain Drift (ppm/èC)

D063

30 units shown

图6-63. OPS Gain Over Temperature

30 units from –40°C to +125°C

图6-64. OPS Gain Drift Histogram

0.9998

0.9997

0.9996

0.9995

0.9994

0.9993

0.9992

11

10

9

10

9

8

7

6

5

4

3

2

1

0

-55

-35

-15

5

25

45

65

85

105 125

Junction Temperature (⁰C)

D065

Gain Drift (ppm/èC)

30 units shown

30 units from –40°C to +125°C

图6-66. Midscale Buffer Gain Drift Histograms

图6-65. Midscale Buffer Gain Over Temperature

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7 Parameter Measurement Information

7.1 Overview

The THS3215 comprises three blocks of high-performance amplifiers. Each block requires both frequency-

response and step-response characterization. The midscale buffer and OPS use standard, single-ended I/O test

methods with network analyzers, pulse generators, and high-speed oscilloscopes. The differential to single-

ended input stage (D2S) requires a wideband differential source for test purposes. All ac characterization tests

were performed using the THS3215 evaluation module (EVM). The THS3215EVM offers many configuration

options. For most of the D2S-only tests, the OPS was disabled. 图 7-1 shows a typical configuration for an ac

frequency-response test of the D2S.

The THS3215EVM includes unpopulated, optional, passive elements at the D2S inputs to implement a

differential filter. These elements were not used in the D2S characterization, and the two input pins were

terminated to ground through 49.9 Ω resistors. DC test points are provided through 10 kΩ or 20 kΩ resistors on

all THS3215 nodes. 图 7-1 also shows the output network used to emulate a 200 Ω load resistance (R_LOAD

)

while presenting a 50 Ω source back to the D2S output pin. The R3 (= 169 Ω) and R4 (= 73.2 Ω) resistors

combine with the 50 Ω network analyzer input impedance to present a 200 Ω load at VO1 (pin 6), The

impedance presented from the input of the network analyzer back to the D2S output (VO1, pin 6) is 50 Ω. The

16.5 dB insertion loss intrinsic to this dc-coupled impedance network is removed from the characterization

curves. VREF (pin 14) was connected to GND for all the tests.

VREF

14

TP_IN+

R5

10 kꢀ

TP_VO1

R7

100 ꢀ

50 ꢀ

J1

Vin+

+IN

2

10 kꢀ

x1

R1

J3

D2S_OUT

50 ꢀ

R3

169 ꢀ

50-ꢀ

Measurement

System

From LMH3401

EVM

+

6

VO1

50 ꢀ

R2

73.2 ꢀ

R4

50 ꢀ

250 ꢀ

500 ꢀ

3

œIN

J2

Vin-

10 kꢀ

R6

TP_IN-

图7-1. D2S Input and Output Interface Showing 50 Ω Differential Input, and 200 Ω R_LOADat VO1

7.2 Frequency Response Measurement

For D2S and full-signal path (D2S + OPS) characterization, the LMH3401, a very wideband, dc-coupled, single-

ended to differential amplifier, was used. The LMH3401EVM was used as an interface between a single-ended

source and the differential input required by the D2S, shown in 图 7-2. The LMH3401 provides an input

impedance of 50 Ω, and converts a single-ended input to a differential output driving through 50 Ω outputs on

each side to what is a 50 Ω termination at each input of the THS3215 D2S.

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Network

Analyzer

GND

Port 1

50 ꢀ

Port 2

50 ꢀ

LMH3401EVM

THS3215EVM

IN+

+

_

+

œ

IN-

图7-2. Frequency-Response Measurement: D2S and Full-Path (D2S + OPS) Circuit Configurations

The LMH3401 provides 7 GHz bandwidth with 0.1-dB flatness through 700 MHz. From the single-ended

matched input (using active match through an internal 12.5 Ω resistor), the LMH3401 produces a differential

output with 16-dB gain to the internal output pins. Building out to a 50 Ω source by adding external 40.2 Ω

resistors on both differential outputs in series with the internal 10 Ω resistor, results in a net gain of 10 dB to the

matched 50 Ω load on the THS3215EVM.

The maximum output swing test for the D2S is 4 V_PP(see HD2 vs Output Voltage and HD3 vs Output Voltage).

With a fixed gain of 2 V/V, the tests in HD2 vs Output Voltage and HD3 vs Output Voltage require a 2 V_PP

differential input. In order to achieve the 2 V_PPdifferential swing at the D2S inputs, the LMH3401 internal outputs

must drive a 4 V_PPdifferential signal around the V_OCMof the LMH3401. This LMH3401 single-to-differential

preamplifier is normally operated with ±2.5 V supplies, and V_OCMset to ground. Under these conditions, the

LMH3401 supports ±1.4 V on each internal output pin; well beyond the maximum required for THS3215 D2S

characterization of ±1 V.

The output of the LMH3401EVM connects directly to the Vin+ (J1) and Vin– (J2) SMA connectors on the

THS3215EVM, as shown in 图7-1. The physical spacing of the SMA connectors lines up for a direct (no cabling)

connection between the two different EVMs using SMA barrels. For THS3215 designs that must be evaluated

before any DAC connection, consider using the LMH3401EVM as a gain of 10 dB, single-to-differential interface

to the inputs of the D2S. This setup allows single-ended sources to generate differential output signals through

the combined LMH3401EVM to THS3215EVM configuration. The D2S, small-signal, frequency-response curves

over input common-mode voltage (see Frequency Response vs Input Common-Mode Voltage) were generated

by adjusting the LMH3401 voltage supplies and maintaining V_OCMat midsupply to preserve input headroom on

the LMH3401. In order to make single-ended, frequency-response measurements, the configuration shown in 图

7-3 was used.

Network

Analyzer

GND

Port 1

50 ꢀ

Port 2

50 ꢀ

THS3215EVM

+

œ

图7-3. Frequency-Response Measurement: OPS Inverting and Noninverting, Midscale Buffer, and VREF-

Input Circuit Configurations

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7.3 Harmonic Distortion Measurement

The distortion plots for all stages used a filtered high-frequency function generator to generate a very low-

distortion input signal. The LMH3401 interface was used when testing the D2S and the full-signal path (D2S +

OPS) harmonic distortion performance. Running the filtered signal through the LMH3401, as shown in 图 7-4,

provided adequate input signal purity because of the approximately –100-dBc harmonic distortion performance

through 100 MHz provided by the LMH3401. In order to test the harmonic-distortion performance of the OPS and

midscale buffer, the configuration shown in 图7-5 was used.

Function

Generator

LMH3401EVM

THS3215EVM

<

>

-

Low-Pass Filter

IN+

+

Output

50 ꢀ

_

+

œ

IN-

I Input

Q Input

Spectrum

Analyzer

High-Pass Filter

RF

Input

Ext Trig

20-dB

Attenuator

50 ꢀ

图7-4. Harmonic-Distortion Measurement: D2S and Full-Path (D2S + OPS) Circuit Configurations

Function

Generator

THS3215EVM

<

>

-

Low-Pass Filter

Output

50 ꢀ

+

œ

I Input

Q Input

Spectrum

Analyzer

High-Pass Filter

RF

Input

Ext Trig

20-dB

Attenuator

50 ꢀ

图7-5. Harmonic-Distortion Measurement: OPS Inverting and Noninverting and Midscale Buffer Circuit

Configurations

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7.4 Noise Measurement

All the noise measurements were made using the very low-noise, high-gain bandwidth LMH6629 as a low-noise

preamplifier to boost the output noise from the THS3215 before measurement on a spectrum analyzer, as shown

in 图 7-6. The 0.69-nV/√ Hz input-voltage noise specification of the LMH6629 provides flat gain of 20 V/V

through 100 MHz with its ultrahigh, 6.3-GHz gain bandwidth product. The D2S and OPS noise was measured

with the common-mode voltage at GND.

I Input

Q Input

Ext Trig

Spectrum

Analyzer

RF

Input

50 ꢀ

LMH6629

Noise Preamp

THS3215EVM

+

œ

图7-6. Noise Measurement Using LMH6629 Preamplifier

7.5 Output Impedance Measurement

Output impedance measurement for the three stages under different conditions were performed as a small-

signal measurement calibrated to the device pins using an impedance analyzer. Calibrating the measurement to

the device pins removes the THS3215EVM parasitic resistance, inductance, and capacitance from the measured

data.

7.6 Step-Response Measurement

Generating a clean, fast, differential-input step for time-domain testing presents a considerable challenge. A

multichannel pulse generator with adjustable rise and fall times was used to generate the differential pulse to

drive D2S inputs in Large-Signal Step Response vs Load Resistance. A high-speed scope was used to digitize

the pulse response.

7.7 Feedthrough Measurement

In order to test the forward-feedthrough performance of the OPS in the disabled state, the circuit shown in 图7-7

was used. The PATHSEL pin was driven low to select the internal path between the D2S and OPS. A 100 mV_PP

,

swept-frequency, sinusoidal signal was applied at the VREF pin, and the output signal was measured at the OPS

output pin (VOUT, pin 11). The transfer function from VREF to the output of the D2S at VO1 has a gain of 0 dB,

as shown in VREF Input Pin Frequency Response. The results shown in OPS Forward Feedthrough in Disable

account for the 6 dB loss due to the doubly-terminated OPS output, and report the forward feedthrough between

VOUT and VO1 at different OPS gains. The D2S inputs were grounded through 50 Ωresistors for this test.

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Network

Analyzer

GND

Port 1

50 ꢀ

Port 2

50 ꢀ

75 ꢀ

V_REF

14

16

15

13

R_G

50 kꢀ

12

100 ꢀ

1

2

x1

18.5 kꢀ

R_F

50 kꢀ

50 ꢀ

49.9 ꢀ

x1

11

+

V_OUT

49.9 ꢀ

+

250 ꢀ

500 ꢀ

DISABLE = High

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

9

PATHSEL = Low

49.9 ꢀ

6

7

8

5

200 ꢀ

图7-7. Forward-Feedthrough Test Circuit

In order to test the reverse feedthrough performance of the OPS in its disabled state, the circuit shown in 图 7-8

was used. The PATHSEL pin was driven high to select the external path to the OPS noninverting pin, VIN+, pin

9. A 100 mV_PP, swept-frequency, sinusoidal signal was applied at the VIN+ pin and the output signal was

measured at the D2S output pin (VO1, pin 6). The results shown in OPS Reverse Feedthrough in Disable

account for the 16.5 dB loss due to the D2S termination, and the test reports the reverse feedthrough between

the VO1 and VIN+ pins. The D2S inputs were grounded through 50 Ωresistors for this test.

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16

15

14

13

162 Ω

50 kꢀ

12

100 ꢀ

1

2

x1

18.5 kꢀ

249 Ω

50 kꢀ

50 ꢀ

x1

11

+

49.9 ꢀ

100 ꢀ

+

250 ꢀ

500 ꢀ

DISABLE = High

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

V_IN+

Network

Analyzer

9

PATHSEL = High

49.9 ꢀ

GND

Port 1

50 ꢀ

Port 2

6

7

8

5

50 ꢀ

V_O1

169 ꢀ

73.2 ꢀ

图7-8. Reverse-Feedthrough Test Circuit

7.8 Midscale Buffer R_OUTVersus C_LOADMeasurement

For the tests in Series Resistance vs Capacitive Load and Frequency Response vs Capacitive Load, the circuit

shown in 图 7-9 was used. The 150 Ω load circuit configured as shown, provides a 50 Ω path from the network

analyzer back to the output of the buffer. As shown in 图7-9, place R_OUTbelow the load capacitor to improve the

phase margin of the closed-loop buffer output, while adding 0 Ω dc impedance into the line connecting

VMID_OUT (pin 15) to the VREF pin. When using the midscale buffer to drive the VREF input, use a decoupling

capacitor at VMID_OUT to reduce broadband noise and source impedance.

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Network

Analyzer

GND

Port 1

50 ꢀ

Port 2

50 ꢀ

+VCC2

16

150Ω

Load

50 kꢀ

VMID_OUT

15

VMID_IN

1

118 ꢀ

x1

C_LOAD

88.7 ꢀ

49.9 ꢀ

50 kꢀ

R_OUT

5

-VCC2

图7-9. R_OUTVersus C_LOADMeasurement Circuit

8 Detailed Description

8.1 Overview

The THS3215 is a differential-input to single-ended output amplifier system that provides the necessary

functional blocks to convert a differential output signal from a wideband DAC to a dc-coupled, single-ended,

high-power output signal. The THS3215 typically operates using balanced, split supplies. Signal swings through

the device can be adjusted around ground at several points within the device. Single-supply operation is also

supported for an ac-coupled signal path. The THS3215 supply voltage ranges from ±4.0 V to ±7.9 V. The two

internal logic gates rely on a logic reference voltage at pin 7 that is usually tied to ground for any combination of

power-supply voltages. The DISABLE control (pin 10) turns the output power stage (OPS) off to reduce power

consumption when not in use.

A differential-to-single-ended stage (D2S) provides a high input impedance for a high-speed DAC (plus any

reconstruction filter between the DAC and THS3215) operating over a common-mode input voltage range from

–1 V to +3.0 V. This range is intended to support either current sourcing or current sinking DACs. The D2S is

internally configured to reject the input common-mode voltage and convert the differential inputs to a single-

ended output at a fixed gain of 2 V/V (6 dB).

An uncommitted, on-chip, wideband, unity-gain buffer is provided (between pins 1 and 15) to drive the VREF pin.

The buffer offers extremely broad bandwidth to achieve very-low output impedance to high frequencies (Buffer

Output Impedance vs Load Current). The buffer does not provide a high full-power bandwidth because of a

relatively low slew rate. The buffer stage includes a default midsupply bias resistor string of 50 kΩ each to set

the default input to midsupply. This 25 kΩ Thevinin impedance is easily overridden with an external input

source, but is intended to provide a midsupply bias for single-supply operation. The buffer amplifier that drives

the VREF pin has two functions:

• Provides an easy-to-interface, dc-correction, servo-loop input

• Provides an optional offset injection point for the D2S output

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The final OPS provides a very high-performance, current-feedback amplifier for line-driving applications. The 700

MHz small-signal bandwidth (SSBW) stage provides 3000 V/μs of slew-rate, sufficient to drive a 5 V_PPoutput

with 270 MHz bandwidth. In addition, the OPS is able to drive a very-high continuous and peak output current

sufficient to drive the most demanding loads at very high speeds. A unique feature added to the OPS is a 2 × 1

input multiplexer at the noninverting input. The PATHSEL control (pin 4) is used to select the appropriate signal

path to the OPS noninverting input. One of the multiplexer select paths passes the internal D2S output directly to

the OPS. The other select path accepts an external input to the OPS at VIN+ (pin 9). This configuration allows

the D2S output, available at VO1 (pin 6), to pass through an external RLC filter and back into the OPS at VIN+

(pin 9).

If the OPS does not require power for certain application configurations, a shutdown feature has been included

to reduce power consumption. For designs that do not use the OPS at all, two internal fixed resistors are

included to define the operating points for the disabled OPS. An approximate 18.5 kΩ resistor to the logic

reference (GND, pin 7) from VIN+ (pin 9), and an approximate 18.5 kΩ, fixed, internal feedback resistor are

included to hold the OPS pin voltages in range if no external resistors are used around the OPS. These resistors

must be included in the design calculations for any external network.

Two sets of power supply-pins have been provided for both the positive and negative supplies. –VCC2 (pin 5)

and +VCC2 (pin 16) power the D2S and midscale buffer stages, while –VCC1 (pin 8) and +VCC1 (pin 13)

supply power to the OPS. The supply rails are connected internally by antiparallel diodes. Externally, connect

power first to the OPS, then connect back on each side with a π-filter (ferrite bead + capacitor) to the input-

stage supply pins (see 图 8-15). Do not use mismatched supply voltages on either the positive or negative sides

because the supplies are internally connected through the antiparallel diodes. Imbalanced positive and negative

supplies are acceptable, however.

When the OPS is disabled, the output pin goes to high impedance. Do not connect two OPS outputs from

different devices together and select them as a wired-or multiplexer. Although the high-impedance output is

disabled, the inverting node is still available through the feedback resistor, and can load the active signal. The

signal path through the inverting node typically degrades the distortion on the desired active signal in a wired-or

multiplexer configuration using current-feedback amplifiers (CFAs).

8.2 Functional Block Diagram

+VCC2

16

+VCC1

13

VREF

14

VMID_OUT

15

50 kꢀ

12 VINœ

100 ꢀ

VMID_IN

1

2

x1

18.5 kꢀ

50 kꢀ

50 ꢀ

+IN

x1

11 VOUT

+

250 ꢀ

500 ꢀ

3

4

x1

œIN

10

DISABLE

18.5 kꢀ

VIN+

9

PATHSEL

6

7

8

5

œVCC2

VO1

GND

œVCC1

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8.3 Feature Description

8.3.1 Differential to Single-Ended Stage (D2S) With Fixed Gain of 2 V/V (Pins 2, 3, 6, and 14)

This buffered-amplifier stage isolates the DAC output pins from the differential to single-ended conversion.

Present two high-impedance inputs to allow the DAC to operate in its best configuration independent of

subsequent operations. The two very wideband input buffers hold an approximately constant response shape

over a wide input common-mode operating voltage. Frequency Response vs Input Common-Mode Voltage

shows 6 dB of gain with 0.5 dB flatness through 100 MHz over the intended –1 V to +3 V input common-mode

range. In this case, the VREF pin is grounded, forcing the D2S output to be centered on ground for any input

common-mode voltage. For the D2S-only tests, a 100 Ωload is used to showcase the performance of this stage

directly driving a doubly-terminated cable. The wide, input common-mode range of the D2S satisfies the required

compliance voltage over a wide range of DAC types. Most current sourcing DACs require an average dc

compliance voltage on their outputs near ground. Current sinking DACs require an average dc compliance

voltage near their positive supply voltage for the analog section. The 3 V maximum common-mode range is

intended to support DAC supplies up to 3.3 V, where the average output operating current pulls down from 3.3 V

by the termination impedance from the supply. For instance, a 20 mA tail current DAC must level shift from a 3.3

V bias on the output resistors down to 3 V or lower. This DAC-to-THS3215 configuration requires at least a 300

mV dc level shift with half the tail current in each side, implying a 30 Ω load impedance to the supply on each

output side using a 20 mA reference current.

The overriding limits to the input common-mode operating range are due to the input buffer headroom. Over

temperature, the D2S input headroom specification is 2 V to the negative supply and 1.5 V to the positive supply.

Therefore, operation at a 3 V input common-mode voltage requires at least a 4.5 V positive supply, where 5 V is

a more conservative minimum.

While DAC outputs rarely have any common-mode signal present (unless the reference current is being

modulated), the D2S does a reasonable job of rejecting input common-mode signals over frequency. Common-

Mode Rejection Ratio vs Input Common-Mode Voltage shows the CMRR to decrease above 10 MHz. For

current-sinking DACs coming from a positive supply voltage, any noise on the positive supply looks like an input

common-mode signal. Keeping the noise low at higher frequencies reduces the possibility of feedthrough to the

D2S output due to the decreasing CMRR at higher frequencies. A current-sinking DAC uses pull-up resistors to

the voltage supply to convert the DAC output current to a voltage. Make sure that the DAC voltage supply is

properly decoupled through a ferrite-bead-and-capacitor, π-filter network, similar to the supply decoupling for

the THS3215 shown in 图8-15.

The D2S provides a differential gain of 6 dB. The gain is reasonably precise using internal resistor matching with

extremely low gain drift over temperature (see D2S Gain Over Temperature and D2S Gain Drift Histogram). The

single-ended D2S output signal can be placed over a wide range of dc offset levels using the VREF pin. The

VREF pin shows a precise gain of 1 V/V to the D2S output. Grounding VREF places the first stage output

centered on ground (with some offset voltage). For best ac performance through the D2S, anything driving the

VREF pin must have a very wide bandwidth with very low output impedance over frequency while driving a 150

Ω load. The on-chip midscale buffer provides these features (see Buffer Output Impedance vs Load Current).

When a dc offset (or other small-level ac signal) must be applied to the VREF pin, buffer the signal through the

midscale buffer stage. Maintain the total range of the dc offset plus signal swing within the available output swing

range of the D2S. The headroom to the supplies is a symmetric ±2.1 V (maximum) over temperature. Therefore,

on the minimum ±4 V supply, the D2S operates over a ±1.9 V output range. At the maximum ±7.9 V supply, a

±5.8 V output range is supported. At the higher swings, account for available linear output current, including the

current into the internal feedback resistor load of approximately 500-Ω.

图8-1 shows the internal structure of the D2S functional block. It consists of two internal stages:

1. The first stage consists of two wideband, closed-loop, fixed gain of 1 V/V buffers to isolate the requirements

of the complementary DAC output from the difference operation of the D2S.

2. The second stage is a wideband CFA configured as a difference amplifier, operating in a fixed gain of 2 V/V,

performing the differential to single-ended conversion.

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Complementary

Output DAC

10 mA

R_F

R_G

IN-

3

250 ꢀ

500 ꢀ

x1

V_O1= 2V_IN

25 ꢀ

V_IN

6

I_DIFF

+

R₁

VO1

50 ꢀ

2

R₂

IN+

100 ꢀ

25 ꢀ

10 mA

14 VREF

Optional DC

Source

图8-1. D2S Operating Example

The CFA design offers the best, full-power bandwidth versus supply current, with moderate noise and dc

precision. 图 8-1 shows a typical current-sourcing DAC with a 20 mA total tail current. The tail current is split

equally between the 25 Ω termination resistors to produce a dc common-mode voltage and a differential ac

current signal. This example sets the input common-mode voltage at 0.25 V, and is also the compliance voltage

of the DAC. The 25 Ω termination resistors shown here are typically realized as a 50 Ω matched reconstruction

(or Nyquist) filter between the DAC and the THS3215 buffer inputs for most AWG applications. The DAC signal

is further amplified by 6 dB in the second stage for a net transimpedance gain of 100 Ω to the D2S output at

VO1. This configuration produces a 2 V_PPoutput for the 20 mA reference current assumed in the example of 图

8-1. The input common-mode voltage is cancelled on the two sides of the op amp circuit to give a ground

referenced output. Any voltage applied to VREF (pin 14) has a gain transfer function of 1 V/V to VO1,

independent of the signal path, as long as the source impedance of VREF is very low at dc and over frequency.

The IN+ buffer output drives a 150 Ω load with VREF grounded. Any source driving VREF must have the ability

to drive a 150 Ω load with low output impedance across frequency. For differential input signals, the IN– buffer

drives a 150 Ω active load. The active load is realized by a combination of the 250 Ω R_Gresistor and the

inverted and attenuated signal present at the inverting terminal of the difference amplifier stage. If only IN– is

driven (with IN+ at a dc fixed level), the load is 250 Ω.

The resistor values around the D2S difference amplifier are derived in the following sequence, as shown in 图

8-2:

1. Select the feedback resistor value to set the response shape for the wideband CFA stage. The 500 Ω

design used here was chosen as a compromise between loading and noise.

2. Set the input resistor on the inverting input side to give the desired single-sided gain for that path. Setting

R_G= 250 Ωresults in a gain of –2 V/V from the buffered signal (–V) to the output of the difference

amplifier.

3. Solve the required attenuation to the noninverting input to get a matched gain magnitude for the signal

provided at the buffer output (+V) on the noninverting path. If α= R2 / (R1 + R2), as shown in 图8-2, then

the solution for αis shown in 方程式2:

≈

’

÷

◊

R_F

a 1+

= 2

∆

R_G

«

(1)

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2

R1

a =

=

3

R1+ R2

(

)

(2)

R_G

250 ꢀ

R_F

500 ꢀ

œV

.(+V)

V_O1

+

R1

+V

R2

图8-2. D2S Impedance Analysis

4. After solving the attenuation from the buffer output to the amplifier noninverting input, set the impedance

(R1 + R2). It is preferable to have the two first-stage buffer outputs drive the same load impedance to match

nonlinearity in their outputs in order to improve even-order harmonic distortion. The load impedance from –

V to R_Ghas an active impedance because of the inverted and attenuated version of the input signal

appearing at the inverting amplifier node from the +V input signal. Assuming a positive input signal into the

+V path, an attenuated version of the signal appears at the amplifier summing junction side of R_G, while the

inverted version of the signal appears on the input side of R_G.

The impedance seen at node –V in 图8-2 is derived in 方程式3 by solving for the V/I expression across R_G.

R_G

250 ꢀ

Z_i=

=

= 150 ꢀ

2

1+ a

(

)

1+

3

(3)

For load balancing, (R1 + R2) = 150 Ω while the attenuation is α. More generally, all the terms are now

available to solve for R2, as shown in 方程式4:

2

a

a +1

3

R2 = R_G

= 250 ꢀ

= 100 ꢀ

2

3

(

)

1+

(4)

R1 is then simply (Z_i–R2) = 50 Ω.

This analysis for matched gains and buffer loads can be applied to a more general, discrete design using

different target gains and starting R_Fvalues. It is clearly useful to have the attenuation and buffer loading

accurately controlled. Therefore, it is very important to control the impedance at VREF (pin 14) to be as low as

possible. For instance, using the midscale buffer to drive VREF only adds 0.21 Ω dc impedance in series with

R2. This low, dc output impedance can only be delivered with a closed-loop buffer design. For discrete

implementations of this D2S, consider the BUF602 buffer and LMH6702 wideband CFA. For even better dc and

ac output impedance in the buffers (and possibly better gain), use a closed-loop, dual, wideband op amp like the

OPA2889 for lower frequency applications, or the OPA2822 for higher frequency. These unity gain stable op

amps can be used as buffers, offering different performance options along with the LMH6702 wideband CFA

over the design point chosen for the THS3215.

After gain matching is achieved in the single op amp differential stage, the common-mode input voltage is

cancelled to the output, and the VREF input voltage is amplified by 1 V/V to the output. The analysis circuit is

shown in 图8-3, where VREF is shown grounded at the R2 element.

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R_G

R_F

250 ꢀ

500 ꢀ

V_CM

V_O1

+

R1

50 ꢀ

R2

100 ꢀ

图8-3. D2S Common-Mode Cancellation

The gain magnitudes are equal on each side of the differential inputs; therefore, the common-mode inputs

achieve the same gain magnitude, but opposite phase, resulting in common-mode signal cancellation. The

inverting path gain is V_CM× (R_F/ R_G). The noninverting path gain is V_CM× α× (1 + R_F/ R_G). Using 方程式5:

R_F

R_G

a =

≈

∆

«

’

÷

◊

R_F

1+

R_G

(5)

the noninverting path gain becomes +V_CM× R_F/ R_G, and adding that result to the inverting path signal cancels

the input common-mode voltage to zero. Slight gain mismatches reduce this rejection to the 48 dB typical

CMRR, with a 42 dB tested minimum. The 42 dB minimum over the 3 V maximum common-mode input range

adds another ±23.8 mV worst-case D2S output offset term to the specified maximum ±35 mV output offset with 0

V input common-mode voltage. The polarity of the gain mismatch is random.

The VREF pin input voltage (V_REF) generates a gain of 1 V/V using the analysis shown in 图8-4.

R_G

R_F

250 ꢀ

500 ꢀ

V_O1

+

R1

50 ꢀ

R2

100 ꢀ

V_REF

图8-4. Gain Transfer Function from VREF to VO1

The gain from VREF to VO1 is shown in 方程式6:

≈

∆

«

’

÷

◊

R_F

R1

V_REF

1+

= V

O1

R1+ R2

R_G

(

)

(6)

Getting both R1 and (R1 + R2) in terms of R_Gand the target attenuation, αsimplifies, as shown in 方程式7:

1- a

1+ a

1

R_G

R1

=

= 1- a

(

)

R1+ R2

(

)

R_G

1+ a

(7)

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Putting 方程式7 back into the gain expression (方程式6), and expanding out gives:

≈

’

÷

◊

R_F

V_REF1- a 1+

= V

(

)

∆

«

O1

R_G

(8)

Substituting the value of α from 方程式 5 into 方程式 8 reduces the expression to V_O1= V_REF, a gain of 1 V/V.

This gain is very precise, as shown in the D2S Electrical Characteristics table, where the tested dc limits are

0.975 V/V to 1.015 V/V.

The D2S output offset and drift are largely determined by the internal elements. The only external consideration

is the dc source impedance at the two buffer inputs. With low source impedance, the D2S output offset is tested

to be within ±35 mV, that becomes a maximum ±17 mV input differential offset specification. Assuming the dc

source impedances are closely matched, the mismatch in the two input bias currents adds another input offset

term for higher source impedances. The input bias offset current is limited in test to be < ±0.40 µA. This error

term does not rise to add more than ±1 mV input differential offset until the dc source impedance exceeds

2.5 kΩ. A high dc source impedance most commonly occurs in an input ac-coupled, single-supply application,

where dc offsets are less critical.

The absolute input bias currents modify the common-mode input voltage if the dc source resistance is too large.

The input bias current is tested to a limit of ±4 µA on each input. In order to move the input common-mode

voltage by ±100 mV, the dc source impedance must exceed 25 kΩ. This added input common-mode voltage is

cancelled by the D2S at the output (pin 6) and is set to the reference voltage applied at VREF (pin 14).

The D2S output noise is largely fixed by the internal elements. The D2S shows a differential input voltage noise

of 6 nV/√Hz, and a current noise of 2 pA/√ Hz on each input. Higher termination resistors increase this source

noise, as given by 方程式 9, where R_tis the dc termination impedance at each buffer input. The D2S has a 1/f

corner at approximately 10 kHz (see Differential Input Noise vs Source Impedance).

2

e_{i_ diff}

=

6 nV + 2 4kTR + 2 2 pA ìR

(

)

(

)

(

)

t

(9)

The total differential input noise is dominated by the differential voltage noise. For instance, evaluating this

expression for R_t= 200 Ω on each input, increases the total differential input noise to 6.5 nV/√ Hz, only slightly

greater than the 6 nV/√ Hz for the D2S with 0 Ω source R_ton each input. If higher final output SNR is desired,

consider generating as much input swing as the DAC can support by increasing the termination impedance. It is

possible that a lower tail current with higher R_tcan yield improved SNR at the D2S input. This differential input

noise appears at the D2S output times a gain of 2 V/V.

e_{out _ diff}= 2ì e_{i_ diff}

(10)

8.3.2 Midscale (DC) Reference Buffer (Pin 1 and Pin 15)

This optional block can be completely unconnected and not used if the design does not require this feature.

Internal 50 kΩ resistors to the power supplies bias the input of the buffer to the midpoint of the supplies used.

The internal resistors set a midsupply operating point when the buffer is not used, as well as a default midsupply

point at the buffer output to be used in other stages for single-supply, ac-coupled applications.

The buffer provides a very wideband, low output-impedance when used to drive VREF, pin 14 (see Buffer Output

Impedance vs Load Current). To provide this low broadband impedance, the closed-loop midscale (dc) reference

buffer offers a very broadband SSBW, but only a modest large-signal bandwidth (LSBW); see Frequency

Response vs Output Voltage. This path is not normally intended to inject a wideband signal, but can be used for

lower-amplitude signals. Driving the buffer output into the VREF pin allows a wideband small-signal term to be

added into the D2S along with the signal from the differential inputs.

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The midscale (or dc) reference buffer injects an offset voltage to the output offset of the D2S when it drives the

VREF pin. The offset has very low drift, but consider the effect of the input bias current times the dc source

impedance at VMID_IN (pin 1). When used as a default midsupply reference for single-supply operation, the

input to this buffer is just the average of the total power supplies though a 25 kΩ source impedance. Add an

external capacitor to filter the supply and the 50 kΩ internal resistors. A 1-µF capacitor on VMID_IN adds a 6-Hz

pole to the noise sources. If lower noise at lower frequencies is required, implement a midscale divider with

external, lower-valued resistors in parallel with the internal 50 kΩ values.

If the midscale buffer drives the VREF pin, the buffer noise is added to 方程式 9 and 方程式 10. The midscale

buffer 4.4 nV/√ Hz voltage noise is amplified by 0 dB, and adds (RMS) a negligible impact to the total D2S

output noise. The biggest impact comes when the internal default 50 kΩ dividers are used. Be sure to decouple

VMID_IN with at least a 1 µF capacitor in the application to reduce the noise contribution through this path. 图

8-5 shows the simulation circuit with the 1 µF capacitor installed. 图8-6 shows the simulated output noise for the

midscale buffer using the internal 50 kΩ divider with and without the 1 µF capacitor on VMID_IN.

+VCC2

16

50 kꢀ

VMID_IN

15 VMID_OUT

1

x1

1 …F

50 kꢀ

5

-VCC2

图8-5. Midscale Buffer Noise Model

1000

100

10

With 1mF capacitor

Without 1mF capacitor

1

10

100

1k 10k

Frequency (Hz)

100k

1M

D501

图8-6. Buffer-Output Noise Comparison With and Without the 1 µF Bypass Capacitor on VMID_IN

In the flat region, the 1 µF capacitor reduces the midscale buffer output spot noise from approximately 55 nV/√

Hz to 4.4 nV/√Hz. If the noise below 100 Hz is unacceptable, either add a low-noise buffer to drive this input, or

add lower-value resistors externally to set up the midsupply bias. Also, consider the noise impact of any

reference voltage source driving the midscale buffer path.

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8.3.3 Output Power Stage (OPS) (Pins 4, 7, 9, 10, 11, and 12)

A wideband CFA provides a flexible output driver with several unique features. The OPS can be left unused if

the specific application only uses the D2S alone, or a combination of the D2S with an off-chip power driver. If left

unused, simply tie DISABLE (pin 10) and PATHSEL (pin 4) to the positive supply. This logic configuration turns

the OPS off and opens up the external and internal OPS noninverting input paths. An internal fixed 18.5 kΩ

resistor holds the external input pin at the logic reference voltage on GND (pin 7). Additionally, the OPS output is

connected to the inverting input through another internal 18.5 kΩ resistor when no external resistors are installed

on VIN+, VOUT, or VIN– (pins 9, 11, or 12, repectively). Disabling the OPS saves approximately 11 mA of

supply current from the nominal total 35 mA, with all stages operating on ±6 V supplies.

The noninverting input to the OPS provides two possible paths controlled by the PATHSEL logic control. With the

logic reference (pin 7) at ground, floating PATHSEL or controlling it to a voltage < 0.7 V connects the input path

directly to the internal D2S output. Tying PATHSEL to the positive supply, or controlling it to a logic level > 1.3 V,

connects the input path to the external input at VIN+. The intent for this switched input is to allow an external

filter to be inserted between the D2S output and OPS inputs when needed, and bypass the filter when not.

Alternatively, this switched input also allows a completely different signal path to be inserted at the OPS input,

independent of that available at the internal D2S output.

In situations where the D2S output at VO1 (pin 6) is switched into another off-chip power driver, the OPS can be

disabled using DISABLE. With the logic reference (pin 7) at ground, floating DISABLE, or controlling it to a

voltage < 0.7 V, enables the OPS. Tying DISABLE to the positive supply, or controlling it to a logic level > 1.3 V,

disables the OPS.

Operation of the wideband, current-feedback OPS requires an external feedback resistor and a gain element.

After configuring, the OPS can amplify the D2S output through either the noninverting path, or be configured as

an inverting amplifier stage using the external OPS input at VIN+ as a dc reference.

One of the first considerations when designing with the OPS is determining the external resistor values as a

function of gain in order to hold the best ac performance. The loop gain (LG) of a CFA is set by the internal

open-loop transimpedance gain from the inverting error current to the output, and the effective feedback

impedance to the inverting input. The nominal internal open-loop transimpedance gain (Z_OL) magnitude and

phase are shown in 图8-7.

140

120

100

80

45

Phase

Magnitude

0

-45

-90

-135

-180

60

40

1k

10k

100k

1M 10M

Frequency (Hz)

100M

2G

D502

图8-7. Simulated OPS Z_OLGain Magnitude and Phase

The feedback transimpedance (Z_OPT) can be approximated as shown in 方程式 11, where R_iis the open-loop,

high-frequency impedance into the inverting node of the OPS. For a detailed derivation of 方程式 11, see the

Setting Resistor Values to Optimize Bandwidth section in the OPA695 datasheet (SBOS293).

≈

’

÷

◊

R_F

Z_OPTö R + 1+

R

i

∆

F

R_G

«

(11)

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As the signal gain is varied, hold Z_OPTapproximately constant to hold the ac response constant over gain.

Holding Z_OPTconstant is a requirement to solve for R_F. An example of the THS3215 OPS R_Fderivation is shown

in 方程式12:

≈

’

÷

◊

R_F

R = 430 ꢀ - 1+

ì 74 ꢀ

∆

F

R_G

«

(12)

The calculations are complicated by the internal feedback resistor value of approximately 18.5 kΩ. After the

external R_Fis approximately set by the constant bandwidth consideration, the R_Gmust be set considering the

other gain error terms. From the noninverting input of a CFA, the total gain to the output includes a loss through

the input buffer stage (described by the CMRR) and the loop gain (LG) loss set by the typical dc open-loop

transimpedance gain and the feedback transimpedance. Extract the buffer gain from the VIN+ input to the VIN–

input from the CMRR using 方程式 13. This gain loss only applies to the noninverting mode of operation and can

be ignored in inverting mode operation.

-CMRR

20

≈

’

÷

∆

b = 1-10

= Buffer Gain CFA

∆

«

÷

◊

(13)

The OPS has a typical CMRR of 53 dB (buffer gain, β = 0.9978) with a tested minimum of 47 dB (minimum

buffer gain of 0.9955). The dc LG adds to the gain error. The LG is given by 方程式 14, where the typical design

gain of 2.5 V/V value is also shown (the 245 Ω shown for R_Fis the external 249 Ω feedback resistor in parallel

with the internal 18.5 kΩ feedback resistor).

Z_OL

1.7 Mꢀ

LG =

=

= 3593

R + NGìR

245 ꢀ + 2.5ì74 ꢀ

(

)

(

)

F

i

(14)

The closed-loop output impedance with a heavy load also adds a minor gain loss that is neglected here. The

total noninverting gain is then set by 方程式 15 (remember to include the internal R_Fin this analysis). The R_F’

shown here is the parallel combination of the internal and external feedback resistors.

≈

’

÷

◊

R_F

LG

A⁺= bì 1+

ì

∆

v

R_G

1+ LG

(

)

«

(15)

Using nominal values for each term at the specified R_F= 249 Ω and R_G= 162 Ω gives the gain calculation in 方

程式16, yielding a nominal gain very close to 2.5 V/V.

245.7

162

3593

≈

’

A⁺_v= 0.9978ì 1+

ì

= 2.51

∆

÷

◊

1+ 3593

«

(16)

Testing the total gain spread with the internal variation in buffer gain, open-loop transimpedance gain, internal

feedback resistor, and ±1% external resistor variation gives a worst-case gain spread of 2.5 V/V to 2.52 V/V. The

gain error is primarily dominated by the external 1% resistors. For the tighter tolerance shown in 表 8-1, use

0.1% precision resistors.

At very low gains (< 1.5 V/V), parasitic effects at the inverting input due to stray inductance and capacitance

render a flat frequency response impossible. Looking then at gains from 1.5 V/V and up, a table of nominally

recommended R_Fand R_Gvalues is shown in 表 8-1. Do not operate the OPS in noninverting gains of less than

2.5 V/V for large output signals because the limited slew-rate of the CFA input buffer causes signal degradation.

表 8-1 accounts for the nominal gain losses described previously, and uses standardized resistor values to

minimize the nominal gain-error to target gain. The calculation also restricts the solution to a minimum R_G

=

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20 Ω. The gain calculations include the nominal buffer gain loss, the loop-gain effect, and the nominal internal

feedback resistor = 18.5 kΩ.

表8-1. Optimized R_FValues for Different OPS Noninverting Signal Gains

CALCULATED GAIN

BEST R_F

(Ω)

BEST R_G

TARGET GAIN

(V/V)

MEASURED SSBW

(MHz)

GAIN ERROR

(%)

(Ω)

(V/V)

1.498

2.004

2.510

2.980

3.510

3.972

4.533

4.984

5.467

6.029

6.547

6.989

7.437

8.060

8.578

8.955

9.558

10.006

(dB)

1.5

2

890

324

287

249

205

169

150

158

165

169

174

178

182

187

634

280

3.513

-0.1

0.22

0.41

-0.66

0.27

-0.7

6.039

—

2.5

3

700

162

7.995

102

9.485

—

3.5

4

66.5

49.9

44.2

39.2

36.5

33.2

30.1

28.7

26.7

24.9

23.2

22.1

21

10.905

11.980

13.128

13.952

14.755

15.605

16.321

16.888

17.429

18.127

18.668

19.041

19.608

20.005

—

4.5

5

0.73

-0.32

-0.6

—

390

5.5

6

—

93

0.49

0.73

-0.16

-0.83

0.75

0.92

-0.5

6.5

7

7.5

8

8.5

9

9.5

10

0.61

0.06

20.5

The measured bandwidths in 表 8-1 come from Frequency Response vs Noninverting Gain using the resistor

values in the table and a 100 Ω load. Plotting the R_Fvalue versus gain gives the curve of 图 8-8. The curve

shows some ripple due to the standard value resistors used to minimize the target dc gain error.

350

300

250

200

150

100

50

0

1

2

3

4

5

6

7

Target OPS Gain (V/V)

8

9

10

D503

图8-8. Suggested External R_FValue vs Noninverting Gain for the OPS

Using R_Fvalues greater than the recommended values in 表 8-1 band-limits the response, whereas using less

than the recommended R_Fvalues peaks the response. Using the values shown in 表 8-1 results in a more

constant SSBW (see Frequency Response vs Noninverting Gain. Holding a more constant loop-gain over the

external gain setting also acts to hold a more constant output impedance profile, as shown in 图 8-9. The swept-

frequency, closed-loop, output impedance is shown for gains of 2.5 V/V, 5 V/V, and 10 V/V using the R_Fand R_G

values of 表 8-1. The first two steps do a good job of delivering the same (and very low) output impedance over

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frequency, while the gain of 10 V/V shows the expected higher closed-loop output impedance due to the reduced

loop-gain and bandwidth.

10

1

0.1

A_V= 2.5 V/V

A_V= 5 V/V

A_V= 10 V/V

0.01

100k

1M

10M

100M

Frequency (Hz)

D504

图8-9. OPS Closed-Loop Output Impedance vs Gain Setting

Reducing the R_Fvalue with increasing gain also helps minimize output noise versus a fixed R_Fdesign. See

Input-Referred Spot Noise vs Frequency for the three noise terms for the OPS. The total output noise calculation

is shown in 方程式17:

2

NG²+ i R ²+ 4kTR NG

2

e_o= e_ni+ 4kTR + i R

(

)

(

)

(

)

S

bn

S

)

bi

F

(

(17)

where

• R_Sis the source impedance on the noninverting input. If the OPS is driven from the D2S directly using the

internal path, R_S≈0 Ω.

• NG = (1 + R_F/ R_G) for the design point.

• The flat-band noise numbers for the OPS are:

– E_ni= 2.7 nV/√Hz

– I_bn= 1.3 pA/√Hz

– I_bi= 18 pA/√Hz

Using the values of R_Fand R_Glisted in 表 8-1, a swept gain output- and input-referred noise estimate is

computed, as shown in 表 8-2. In this sweep, R_S= 0 Ω. The input-referred noise (E_ni) in 表 8-1 is at the

noninverting input of the OPS. To refer the noise to the D2S differential inputs, divide the output noise by two if

there is no interstage loss. Dividing the E_nicolumn by 2 V/V shows that the OPS noise contribution is negligible

when referred to the D2S inputs, where the 6 nV/√ Hz differential input noise dominates. Operating with higher

feedback resistors in the OPS quickly increases the output noise due to the inverting input current noise term.

Although increasing R_Fimproves phase margin (for example, when driving a capacitive load), be careful to

check the total output noise using 方程式17.

表8-2. Total Input- and Output-Referred Noise of the OPS Versus Gain

BEST R_F

(Ω)

BEST R_G

E_O

(nV/√Hz)

E_in

(nV/√Hz)

TARGET GAIN

(V/V)

(Ω)

1.5

2

324

287

249

205

169

150

158

634

280

162

102

66.5

49.9

44.2

7.63

8.07

5.09

4.03

3.47

3.15

2.97

2.89

2.87

2.5

3

8.72

9.39

3.5

4

10.42

11.48

13.01

4.5

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表8-2. Total Input- and Output-Referred Noise of the OPS Versus Gain (continued)

BEST R_F

BEST R_G

E_O

E_in

TARGET GAIN

(V/V)

(Ω)

(nV/√Hz)

5

158

165

169

174

178

182

187

39.2

36.5

33.2

30.1

28.7

26.7

24.9

23.2

22.1

21

14.21

15.53

17.04

18.42

19.63

20.83

22.51

23.89

29.41

26.54

27.77

2.85

2.84

2.83

2.81

2.8

5.5

6

6.5

7

7.5

8

2.79

2.78

8.5

9

9.5

10

20.5

Operating the OPS as an inverting amplifier is also possible. When driving the OPS directly from the D2S to the

R_Gresistor, use the values shown in 表 8-1 for the noninverting mode in order to achieve optimal results. Note

that the R_Gresistor is the load for the D2S. Operating with the D2S driving an R_G< 80 Ω increases the

harmonic distortion of the D2S. In that case, scaling up R_Fand R_Gin order to reduce the loading results in better

system performance at the cost of a lower OPS bandwidth. In order to reduce layout parasitics, consider splitting

the R_Gresistor in two, with the first half close to VO1 and the second half close to VIN– (pin 12). Splitting R_Gin

this manner places the trace capacitance inside the two resistors, thus keeping both active nodes more stable.

Using the OPS to receive and amplify a signal in the inverting mode with a matched terminating impedance

requires another resistor to ground (R_M) along with R_G. This R_Mresistor is shown in 图 8-10 for a 50 Ω matched

input impedance design.

VIN-

12

R_G

R_F

50-Ω

Source

R_M

OPS

Stage

6

11

VOUT

+

From D2S

VIN+

9

图8-10. Inverting OPS Operation With Matched Input Impedance

表 8-3 gives the recommended external resistor values versus gain for the inverting gain mode with input

matching configuration. 表 8-3 solves for the required R_Fto simultaneously allow the gain, input impedance

(50 Ω), and feedback transimpedance to be set to the optimal target values. The table includes the effect of the

internal 18.5 kΩ feedback resistor, and minimizes the RMS error to input impedance target (Z_I) and overall gain.

表8-3. Resistor Values Versus Gain for the Inverting OPS Configuration

TARGET

GAIN

—(V/V)

CALCULATED GAIN

MEASURED

SSBW

BEST

GAIN ERROR

(%)

Z_IERROR

(%)

(MHz)

R_F(Ω) R_G(Ω) R_M(Ω)

—(V/V)

1.008

1.533

2.009

2.543

(dB)

0.072

3.712

6.061

8.106

Z_I(Ω)

49.90

49.82

49.95

49.69

1

700

294

267

237

226

287

174

118

60.4

69.8

86.6

113

0.835

2.213

0.469

1.705

-0.003

-0.168

0.091

-0.415

1.5

2

—

2.5

700

88.7

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表8-3. Resistor Values Versus Gain for the Inverting OPS Configuration (continued)

TARGET

GAIN

—(V/V)

CALCULATED GAIN

MEASURED

SSBW

BEST

GAIN ERROR

(%)

Z_IERROR

(%)

(MHz)

R_F(Ω) R_G(Ω) R_M(Ω)

—(V/V)

3.017

3.553

4.006

4.529

4.990

5.491

6.032

6.493

6.974

7.495

8.056

8.457

8.998

9.519

10.000

(dB)

Z_I(Ω)

50.24

49.72

49.77

49.90

3

3.5

4

215

210

205

226

249

274

301

324

348

374

402

422

449

475

499

71.5

59

169

9.592

0.577

1.508

0.161

0.645

-0.201

-0.164

0424

0.688

—

316

11.011

12.055

13.120

13.962

14.793

15.609

16.249

16.870

17.495

18.122

18.544

19.083

19.572

20.000

-0.366

51.1

49.9

1910

Open

-0.264

—

4.5

5

–0.200

—

570

5.5

6

—

6.5

7

-0.108

-0.372

-0.067

0.701

-0.507

-0.023

0.200

0.000

—

7.5

8

—

8.5

9

—

9.5

10

—

175

At higher gains, R_Mincreases to larger values, and the resistor is excluded from the circuit. The resulting input

impedance of the network is resistor R_G. From that point, R_Fsimply increases to get higher gains, thereby

rapidly reducing the SSBW. However, below a gain of –5 V/V, the inverting design with the values shown in 表

8-3 holds a more constant SSBW versus the noninverting mode (see Frequency Response vs Inverting Gain).

8.3.3.1 Output DC Offset and Drift for the OPS

The OPS provides modest dc precision with typical, minimum, and maximum dc error terms in 表 8-4. The input

offset voltage applies to either input path with very little difference between the internal and external paths.

表8-4. Typical Offset and Bias Current Values for the OPS

PARAMETER

TYPICAL

MINIMUM

MAXIMUM

UNIT

mV

µA

V_IO

I_bn

I_bi

±1

5

15

75

–15

–5

±5

µA

–75

Selecting the internal path results in no source resistance for I_bn, so that term drops out. When the external path

is selected, a dc source impedance may be present, so the I_bnterm creates another error term, and adds to the

total output offset.

Stepping through an example design for the OPS output dc offset using the external path with a low insertion

loss filter shown in 图8-17, along with its R_Fand R_Gvalues, gives the following results:

• R_Sfor the I_bnterm = 90.9 Ω || 464 Ω = 76 Ω. (dc source impedance for the filter design)

• R_Fincluding the internal 18.5 kΩ resistor = 205 Ω || 18.5 kΩ = 202.7 Ω

• Resulting gain with the 102 Ω R_Gelement = 2.99 V/V

表 8-5 shows the typical and worst-case output error terms. Note that a positive current out of the noninverting

input gives a positive output offset term, whereas a positive current out of the inverting input gives a negative

output term.

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表8-5. Output Offset Voltage Contribution From Various Error Terms at 25°C

ERROR TERM

TYPICAL

MINIMUM

–1.136

–44.85

–15.203

–61.19

MAXIMUM

UNIT

mV

I_bn× R_S× A_V

V_IO× A_V

1.136

3.408

±2.99

44.85

mV

I_bi× R_F

±1.014

15.203

63.46

mV

Total error

mV

–2.87 to +5.14

The input offset voltage dominates the error terms. The worst-case numbers are calculated by adding the

individual errors algebraically, but is rarely seen in practice. None of the OPS input dc error terms are correlated.

To compute output drift numbers, use the same gains shown in 表8-5 with the specified drift numbers.

The OPS PATHSEL control responds extremely quickly with low-switching glitches, as shown in 图 8-11. For this

test, the D2S input is set to GND, and the output of the D2S is connected to the external OPS input. The

PATHSEL switch is then toggled at 10 MHz. The results show the offset between the internal and external paths

as well matched.

3

0.12

0.08

0.04

0

2

1

0

-1

-2

-3

-0.04

-0.08

-0.12

PATHSEL In

OPS V_OUT

Time (20 ns/div)

D505

图8-11. OPS Path-Select Switching Glitch

The OPS includes a disable feature that reduces power consumption from approximately 11 mA to 2 mA. The

logic controls are intended to be ground-referenced regardless of the power supplies used. The logic reference

(GND, pin 7) is normally grounded and also provides a connection to the internal 18.5 kΩ resistor on VIN+ (pin

9, default bias to pin 7). Operating in a single-supply configuration with –V_CCat GND and the external OPS

input (VIN+) floated, places VIN+ internally at –V_CC= GND. Driving the external OPS input (VIN+) from a

source within the operating range overrides the bias to –V_CC. However, if the application requires VIN+ to be

floated in a single-supply operation, consider centering the voltage on VIN+ with an added 18.5 kΩ external

resistor to the +V_CCsupply.

If the disable feature is not needed, simply float or ground DISABLE (pin 10) to hold the OPS in the enabled

state. Increasing the voltage on the DISABLE pin to greater than 1.3 V disables the OPS and reduces the

current to approximately 2 mA. In a single-supply design, the OPS can be disabled by setting DISABLE to +V_CC

even up to the maximum operating supply of 15.8 V.

,

Do not move the logic threshold away from those set by the logic ground at pin 7. If a different logic swing level

is required, and GND (pin 7) is biased to a different voltage, be sure the source can sink the typical 280 µA

coming out of GND. Also recognize that the 18.5 kΩ bias resistor on the external OPS input (VIN+) is connected

to GND voltage internally.

As shown in OPS Enable and Disable Time, the OPS enables in approximately 100 ns from the logic threshold

at 1.0 V, while disabling to a final value in approximately 500 ns.

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8.3.3.2 OPS Harmonic Distortion (HD) Performance

The OPS in the THS3215 provides one of the best HD solutions available through high power levels and

frequencies. HD2 vs Output Voltage and HD3 vs Output Voltage show the swept-frequency HD2 and HD3,

where the second harmonic is clearly the dominant term over the third harmonic. Typical wideband CFA

distortion is reported only through 2 V_PPoutput, while HD2 vs Output Voltage and HD3 vs Output Voltage

provide sweeps at 5 V_PPand 8 V_PPinto a 100 Ω load. These curves show an approximate 20 dB per decade rise

with frequency due to loop-gain roll-off.

The distortion performance is extremely robust as a function of load resistance (see HD2 vs Load Resistance

and HD3 vs Load Resistance). Normally, heavier loads degrade the distortion performance, as shown by the

HD2 in HD2 vs Load Resistance. However at frequencies greater than 30 MHz, the HD2 actually improves

slightly as the output load is increased from 500 Ω to 100 Ω.

One of the key advantages offered by the CFA design in the OPS is that the distortion performance holds

approximately constant over gain, as seen in the full-path distortion measurements of HD2 vs Gain and HD3 vs

Gain. Here, the D2S provides a fixed gain of 2 V/V driving a 200 Ω interstage load and using the internal path to

drive the OPS at gains from 1.5 V/V to 10 V/V. Hold the loop-gain approximately constant by adjusting the

feedback R_Fvalue with gain to achieve vastly improved performance versus a voltage-feedback-based design.

Testing a 5 V_PPoutput from the OPS with the supplies swept from the minimum ±4 V to ±7.5 V in HD2 vs Supply

Voltage and HD3 vs Supply Voltage show:

1. The 1.5 V headroom on ±4 V supplies and ±2.5 V output voltage results in degraded performance. At the

lower supplies, target lower output swings for improved linearity performance.

2. The HD2 does not change significantly with supply voltages above ±6 V. The HD3 does improve slightly at

higher supply-voltage settings.

From these plots at ±7.5 V supplies, a 5 V_PPoutput into 100 Ω load shows better than –60 dBc HD2 and HD3

performance through 30 MHz. This exceptional performance is available with the OPS configured as a

standalone amplifier. Combining the standalone OPS performance with the D2S (see HD2 vs Frequency and

HD3 vs Frequency) does not degrade the full, signal-path distortion levels. With the D2S and OPS running

together at a final 5 V_PPoutput and 30 MHz, the HD2 changes to –63 dBc and HD3 changes to –59 dBc on ±6

V supplies. Lower output swings for the combined stages provide much lower distortion. The 2 V_PPoutput curves

on HD2 vs Frequency and HD3 vs Frequency show –61 dBc for HD2 and HD3 at 50 MHz.

8.3.3.3 Switch Feedthrough to the OPS

The THS3215 uses two logic control pins that enable one of four combinations of states; therefore, various

feedthrough effects must be considered. OPS Forward Feedthrough in Disable and OPS Reverse Feedthrough

in Disable show the feedthrough of the switches with the OPS disabled. With the OPS enabled, the signal

feedthrough from the deselected input to the OPS output is shown in Forward Feedthrough With OPS Enabled,

Internal Path Selected and Forward Feedthrough With OPS Enabled, External Path Selected at different closed-

loop OPS gains. The results are shown for a 100 mV_PPsignal at the deselected input, and are not normalized to

the gain of the OPS. When the external input of the OPS is selected, add a low-pass filter between the DAC and

the D2S inputs to reduce the feedthrough of the DAC high-frequency content .

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-20

-30

-40

-50

-60

-70

-80

-90

-20

-30

-40

-50

-60

-70

-80

-90

-100

OPS Gain = 2.5 V/V

OPS Gain =10 V/V

OPS Gain = 2.5 V/V

OPS Gain =10 V/V

-100

1M

10M

100M

Frequency (Hz)

1G

1M

10M

100M

Frequency (Hz)

1G

D506

D507

PATHSEL < 0.7 V,

100 mV_PPsignal to VIN (pin 9)

PATHSEL > 1.3 V,

100 mV_PPsignal to VREF (pin 14) with D2S inputs grounded

图8-12. Forward Feedthrough With OPS Enabled, 图8-13. Forward Feedthrough With OPS Enabled,

Internal Path Selected

External Path Selected

8.3.3.4 Driving Capacitive Loads

The OPS can drive heavy capacitive loads very well, as shown in Series Output Resistance vs Load

Capacitance to Pulse Response. All high-speed amplifiers benefit from the addition of an external series resistor

to isolate the load capacitor from the feedback loop. Not using a series isolation resistor often leads to response

peaking and possibly oscillation. If frequency response flatness under capacitive load is the design goal, use

slightly higher R_Fvalues at the lower gains. Target a slightly-higher feedback transimpedance to increase the

nominal phase margin before the capacitive load acts to decrease it. Using a higher R_Fvalue increases the

frequency response flatness across a range of capacitive loads using lower external series resistor values.

Although the suggested R_Fand R_Gvalues of 表 8-1 apply when driving a 100 Ω load, if the intended load is

capacitive (for example, a passive filter with a shunt capacitor as the first element, another amplifier, or a Piezo

element), use the values reported in 表 8-6 as a starting point. The values in 表 8-6 were used to generate

Series Output Resistance vs Load Capacitance and Frequency Response vs Load Capacitance. The results

come from a nominal total feedback transimpedance target of 405 Ω (versus 351 Ω used for 表 8-3), and

includes the internal 18.5 kΩ resistor in the design. 表 8-6 finds the least error to target gain in the selection of

standard resistor values, and limits the minimum R_Gto 20 Ω. The gains calculated here put 18.5 kΩ in parallel

with the reported external standard value R_F.

表8-6. Suggested R_Fand R_GOver Gain When Driving a Capacitive Load

CALCULATED GAIN

BEST R_F

(Ω)

TARGET GAIN

(V/V)

GAIN ERROR

(%)

BEST R_G(Ω)

953

(V/V)

1.494

1.995

2.501

3.006

3.515

3.974

4.513

4.984

5.467

6.029

6.547

6.989

(dB)

3.488

6

1.5

2

487

432

402

332

274

221

165

158

165

169

174

–0..389

–0.233

0.048

422

2.5

3

261

7.963

9.559

10.917

11.984

13.090

13.952

14.755

15.605

16.321

16.888

162

0.191

3.5

4

107

0.416

73.2

–0.662

0.295

4.5

5

46.4

39.2

–0.320

–0.602

0.486

5.5

6

36.5

33.2

6.5

7

30.1

0.729

28.7

–0.161

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表8-6. Suggested R_Fand R_GOver Gain When Driving a Capacitive Load (continued)

CALCULATED GAIN

BEST R_F

(Ω)

TARGET GAIN

(V/V)

GAIN ERROR

BEST R_G(Ω)

26.7

(V/V)

(dB)

(%)

7.5

8

174

178

182

187

7.437

8.060

8.578

8.955

9.558

10.006

17.429

18.127

18.668

19.041

19.608

20.005

–0.833

0.753

24.9

8.5

9

23.2

0.915

22.1

–0.499

0.613

9.5

10

21

20.5

0.056

As the capacitive load or amplifier gain increases, the series resistor values can be reduced to hold a flat

response (see Series Output Resistance vs Load Capacitance). See Frequency Response vs Load Capacitance

for the measured SSBW shapes for various capacitive loads configured with the suggested series resistor from

the output of the OPS and the R_Fand R_Gvalues suggested in 表 8-6 for a gain of 2.5 V/V. This measurement

includes a 200 Ω shunt resistor in parallel with the capacitive load as a measurement path.

46

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HD2 vs Load Capacitance and HD3 vs Load Capacitance demonstrate the OPS harmonic distortion

performance when driving a range of capacitive loads. These figures show suitable performance for large-signal,

piezo-driver applications. If voltage swings higher than 12 V_PPare required, consider driving the OPS output into

a step-up transformer. The high peak-output current for the OPS supports very fast charging edge rates into

heavy capacitive loads, as shown in the step response plots (see Pulse Response and Pulse Response). This

peak current occurs near the center of the transition time driving a capacitive load. Therefore, the I × R drop to

the capacitive load through the series resistor is at a maximum at midtransition, and 0 V at the extremes (low

dV/dT points). For even better performance driving heavy capacitive loads, consider using the THS3217, a DAC

output amplifier with higher output current and slew rate.

8.3.4 Digital Control Lines

The THS3215 provides two logic input lines that control the input path to the OPS and the OPS power disable

feature; both are referenced to GND (pin 7). The control logic defaults to a logic-low state when the pins are

externally floated. The GND pin must have a dc path to some reference voltage for correct operation. Float the

two logic control lines to enable the OPS and select the internal path connecting the D2S internal output to the

OPS noninverting input. 图8-14 shows a simplified internal schematic for either logic control input pin.

+V_CC

50 mA

20 mA

1 kꢀ

Logic

Control

Input

Q1

Q2

17.5 kꢀ

Q3

V_CTRL

19 kꢀ

100 ꢀ

D3

D1

D2

PIN 7

图8-14. Logic Control Internal Schematic

The Q2 branch of the differential pair sets up a switch threshold approximately 1 V greater than the voltage

applied to the GND pin. If the control input is floating or < 0.7 V, the differential-pair tail current diverts to the

100-Ω detector load, and results in an output voltage (V_CTRL, shown in 图 8-14) that activates the desired mode.

The floated pin default voltage is the PNP base current into the 19 kΩ resistor. As the control pin voltage rises

above 1.3 V, the differential-pair current is completely diverted away from the 100 Ω side, thus switching states.

This unique design allows the logic control inputs to be connected to a single-supply as high as 15.9 V, in order

to hold the inputs permanently high, while still accepting a low ground-referenced logic swing for single-supply

operation. The NPN transistor (Q3) and two diodes (D1 and D2) act as a clamp to prevent large voltages from

appearing across the differential stage.

When the OPS is disabled, both input paths to the OPS are also opened up regardless of the state of PATHSEL

(pin 4).

8.4 Device Functional Modes

Any combination of the three internal blocks can be used separately, or in various combinations. The following

sections describe the various functional modes of the THS3215.

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8.4.1 Full-Signal Path Mode

The full-signal path from the D2S to the OPS is available in various options. Three options are described in the

following subsections.

8.4.1.1 Internal Connection With Fixed Common-Mode Output Voltage

The most basic operation is to ground VREF (pin 14), and use the internal connection from the D2S to the OPS

to provide a differential to single-ended, high-power driver. 图8-15 shows the characterization circuit used for the

combined performance specifications.

6 V

Ferrite

Bead

16

15

14

13

162 ꢀ

50 kꢀ

12

100 ꢀ

1

x1

18.5 kꢀ

249 ꢀ

50 kꢀ

50 ꢀ

49.9 ꢀ

2

x1

11

+

A_V= 5 V/V

To

50-Ω Load

49.9 ꢀ

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

x1

10

18.5 kꢀ

49.9 ꢀ

4

9

6

7

8

5

200 ꢀ

Ferrite

Bead

œ6 V

图8-15. Differential to Single-Ended, Gain of 5 V/V Configuration

This configuration shows the test circuit used to generate Frequency Response vs Output Voltage. Some of the

key features in this basic configuration include:

1. The power supplies are brought into the OPS first, then back to the input stage through a π-filter comprised

of a ferrite bead and local decoupling capacitors on –VCC2 and +VCC2 (pins 5 and 16, respectively). See

the 节10 section for more information.

2. The two logic lines are grounded. This logic configuration (with pin 7 grounded) selects the internal path from

the D2S to OPS, and enables the OPS.

3. The external I/O pins of the midscale buffer are left floating.

4. The VREF pin is grounded, thus setting the D2S output common-mode voltage at VO1 (pin 6) to ground.

5. The D2S external output is loaded with a 200 Ω resistor to ground. Lighter loading on the VO1 pin (versus

the 100 Ωused to characterize the D2S only) results in increased frequency response peaking. Heavier

loading degrades the D2S distortion performance.

48

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6. The external OPS input at VIN+ (pin 9) is left floating. However, VIN+ is internally tied to ground by the

internal 18.5 kΩresistor.

7. The feedback resistor in the OPS is set to the parallel combination of the external 249 Ω resistor and the

internal 18.5 kΩ resistor. This 245.7 Ω total R_Fwith the 162 Ω R_Gresistor results in a gain of approximately

2.5 V/V (7.98 dB) in the OPS.

8. The input D2S provides a gain of 2 V/V (6 dB), and along with the 2.5 V/V (7.98 dB) from the OPS, results in

an overall gain of 5 V/V (13.98 dB) with > 600 MHz of SSBW (see Frequency Response vs Output Voltage).

8.4.1.2 Internal Connection With Adjustable Common-Mode Output Voltage

The simplest modification to this starting configuration is using the midscale buffer to drive the VREF pin with

either a dc or ac source into VMID_IN (pin 1), shown in 图8-16.

Ferrite

Bead

6 V

V_{MID_OUT}

16

15

14

13

162 ꢀ

50 kꢀ

12

100 ꢀ

1

2

x1

+

18.5 kꢀ

V_{MID_IN}

249 ꢀ

œ

50 kꢀ

50 ꢀ

49.9 ꢀ

x1

11

+

A_V= 5 V/V

49.9 ꢀ

To

50-Ω Load

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

9

6

7

8

5

200 ꢀ

Ferrite

Bead

œ6 V

图8-16. Differential to Single-Ended, Gain of 5 V/V Configuration With VREF Driven by the Midscale

Buffer

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The VREF input is used to offset the output of the D2S that is then amplified by the OPS. Correct the total dc

offset at the output of the OPS by adjusting the voltage at VMID_IN (pin 1). Use the on-chip midscale buffer as a

low-impedance source to drive the correction voltage to the VREF pin. A wideband small-signal source can also

be summed into this path with a gain of 1 V/V to the D2S output pin. Frequency Response vs Output Voltage

shows the midscale buffer to have an extremely flat response through 100 MHz for < 100 mV_PPswings, while 1

V_PPis supported through 20 MHz with a flat response.

From this point on, the diagrams are simplified to not show the power-supply elements. However, the supplies

are required by any application, as described in the 节9 section.

8.4.1.3 External Connection

In the configuration shown in 图 8-17, the bias to PATHSEL (pin 4) is changed in order to select the external

input of the OPS. The external D2S output drives a low insertion loss, third-order Bessel filter. The filter in this

example is designed with a low frequency insertion loss of 1.55 dB and f_–3dB= 50 MHz, and results in an

additional insertion loss of 1 dB at 30 MHz. The OPS gain is slightly increased to recover the filter loss, in order

to give an input to output gain of 5 V/V. Using an interstage filter between the D2S and the OPS improves the

step response by reducing the overshoot. The filter in this example has a relatively low cutoff frequency but if the

application requires it, use a filter with a higher cutoff frequency.

16

15

14

13

102 ꢀ

50 kꢀ

12

100 ꢀ

1

2

x1

18.5 kꢀ

205 ꢀ

50 kꢀ

50 ꢀ

49.9 ꢀ

x1

11

+

A_V= 5 V/V

To

50-Ω Load

49.9 ꢀ

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

1-dB loss

at 30 MHz

V_PATHSEL> 1.3 V

9

464 ꢀ

6

7

8

5

50-MHz, Low Insertion Loss

3rd-Order Bessel Filter

90.9 ꢀ

250 nH

11 pF

56 pF

图8-17. External Path Configuration With Interstage Low-Pass Filter

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8.4.2 Dual-Output Mode

The D2S is also used to directly drive a doubly-terminated line, as shown in 图 8-18. In addition, the OPS

amplifies the internal D2S output by 5 V/V. The internal path to the OPS is selected with PATHSEL (pin 4) at

ground, and the OPS gain is increased to 5 V/V. A 2 V_PPoutput at VO1 produces a 10 V_PPoutput at VOUT (pin

11). This 10 V_PPswing requires higher supply operation to provide sufficient headroom in the OPS output stage

in order to preserve signal integrity. A power supply of ±7.5 V provides adequate headroom.

16

15

14

13

39.2 ꢀ

50 kꢀ

12

100 ꢀ

1

x1

18.5 kꢀ

158 ꢀ

50 kꢀ

50 ꢀ

49.9 ꢀ

A_V= 10 V/V

2

x1

11

+

To

49.9 ꢀ

+

Differential

V_IN

50-Ω Load

250 ꢀ

500 ꢀ

3

x1

10

18.5 kꢀ

49.9 ꢀ

4

9

6

7

8

5

To

50-Ω Load

A_V= 2 V/V

49.9 ꢀ

图8-18. Dual-Output Mode

A simple modification to the circuit in 图 8-18 is to disable the OPS. The D2S output at VO1 can then be used

either directly or through a filter to an even higher power driver, such as the ±15 V THS3091.

8.4.3 Differential I/O Voltage Mode

Having two amplifiers available also allows a simple differential I/O implementation with independent output

common-mode control, as shown in 图 8-19. In this configuration, the D2S provides one side of the differential

output, while simultaneously driving the OPS configured in an inverting gain of –1 V/V to provide the differential

output on the other side. The output at VMID_OUT (pin 15) biases the external noninverting input, VIN+ (pin 9).

This circuit configuration places the differential input to the output filter at a common-mode voltage, V_{MID_OUT}

.

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V_{MID_OUT}

V_O1

16

15

14

13

280 ꢀ

50 kꢀ

12

100 ꢀ

1

x1

+

18.5 kꢀ

V_{MID_IN}

287 ꢀ

œ

50 kꢀ

50 ꢀ

2

x1

11

+

V_OUT

Differential

Input Mixer

Differential

Filter

49.9 ꢀ

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

V_{MID_OUT}

9

V_PATHSEL> 1.3V

6

7

8

5

V_O1

图8-19. Differential I/O Configuration With Independent Output Common-Mode Voltage Control

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9 Application and Implementation

Note

Information in the following applications sections is not part of the TI component specification, and TI

does not warrant its accuracy or completeness. TI’s customers are responsible for determining

suitability of components for their purposes, as well as validating and testing their design

implementation to confirm system functionality.

9.1 Application Information

9.1.1 Typical Applications

The five example designs presented show a good, but not comprehensive, range of the possible solutions that

the THS3215 provides. Numerous more configurations are clearly possible to the creative designer.

9.1.1.1 High-Frequency, High-Voltage, Dual-Output Line Driver for AWGs

6 V

16

15

14

13

102 ꢀ

50 kꢀ

12

OPS A_V= 2.96 V/V

100 ꢀ

1

2

x1

18.5 kꢀ

Either 2.5 V_PP

or

10 V_PPat Load

203 ꢀ

50 kꢀ

50 ꢀ

49.9 ꢀ

V_O

x1

11

+

V_OUT= 5 V_PP

To

50-Ω Load

+

Differential

Filter

25-MHz, 3rd-order

Bessel filter

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

39 pF

49.9 Ω

270 nH

9

V_PATHSEL= 3.3 V

+15V

10 ꢀ

THS3095

A_V= 3.8 V/V

+

6

7

8

5

200 pF

402 ꢀ

œ

THS3095

10 ꢀ

-15V

1.2 kꢀ

œ6 V

50-MHz, 3rd-order Bessel filter

250 nH

432 ꢀ

90.9 ꢀ

11 pF

52 pF

464 ꢀ

图9-1. Dual-Channel Design: 5 V_PPat THS3215 Output and 20 V_PPat THS3095 Output

9.1.1.1.1 Design Requirements

For this design example, use the parameters listed in 表9-1 as the input parameters.

表9-1. Dual-Output Design Specifications

DESIGN PARAMETER

High-frequency, THS3215 channel

High-voltage, THS3095 channel

EXAMPLE VALUE

5 V_PP, 50 MHz bandwidth

20 V_PP, 25 MHz bandwidth

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9.1.1.1.2 Detailed Design Procedure

The THS3215 is well suited for high-speed, low-distortion arbitrary waveform generator (AWG) applications

commonly used in laboratory equipment. In this typical application, a high-speed, complementary-current-output

DAC is used to drive the D2S. The OPS of the THS3215 easily drives a 50 MHz, 2.5 V_PPsignal into a matched

50 Ωload. When a larger output signal is required, consider using the THS3095 as the final driver stage.

A passive RLC filter is commonly used on DAC outputs to reduce the high-frequency content in the DAC steps.

The filtering between the DAC output and the input to the D2S reduces higher-order DAC harmonics from

feeding into the internal OPS path when the external input path is selected. Feedthrough between the internal

and external OPS paths increases with increasing frequency; however, the input filter rolls off the DAC

harmonics before the harmonics couple to VOUT (pin 10) through the deselected OPS signal path. 图9-2 shows

an example of a doubly-terminated differential filter from the DAC to the THS3215 D2S inputs at +IN (pin 2) and

–IN (pin 3). The DAC is modeled as two, fixed, 10 mA currents and a differential, ac-current source. The 10 mA

dc midscale currents set up the average common-mode voltage at the DAC outputs and D2S inputs at 10 mA ×

25 Ω = 0.25 V_CM. The total voltage swing on each DAC output is 0 V to 0.5 V.

Complementary

Output DAC

D2S Stage with input

capacitance included

10 mA

IN+

2

150 nH

30 pF

27 pF

49.9 ꢀ

2.4 pF

49.9 ꢀ

I_DIFF

150 nH

3

IN-

30 pF

27 pF

49.9 ꢀ

2.4 pF

49.9 ꢀ

10 mA

图9-2. 105 MHz Butterworth Filter Between DAC and D2S Inputs

Some of the guidelines to consider in this filter design are:

1. The filter cutoff is adjusted to hit a standard value in the standard high-frequency, chip inductors kits.

2. The required filter output capacitance is reduced from the design value of 29.4 pF to 27 pF to account for the

D2S input capacitance of 2.4 pF, as reported in the D2S Electrical Characteristics table.

3. The capacitor at the DAC output pins must also be reduced by the expected DAC output pin capacitance.

The DAC output capacitance is often specified as 5 pF, but is usually much lower. Contact the DAC

manufacturer for an accurate value.

图 9-3 shows the TINA-simulated filter response for the input-stage filter. The low-frequency 34 dBΩ gain is due

to the 50 Ω differential resistance at the DAC output terminals. At 200 MHz, this filter is down 17 dB from the 50

Ω level; it is also very flat through 50 MHz.

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35

30

25

20

15

10

5

0

1M

10M

100M

Frequency (Hz)

1G

D508

图9-3. Simulated, Differential-Input Filter Response

In the example design of 图 9-1, a 50 MHz, third-order Bessel filter is placed between the D2S output and the

external OPS input. Another 25 MHz, third-order Bessel filter is placed at the input of a very-high output-swing

THS3095 stage. A double-pole, double-throw (DPDT) relay selects the THS3095 path when the internal OPS

path is selected in the THS3215. 图 9-1 shows this design. The key operational considerations in this design

include:

1. When the external input OPS path is selected, the 2 V_PPmaximum D2S output swing experiences a 1.55 dB

insertion loss from the interstage filter between VO1 (pin 6) and VIN+ (pin 9). A standard value inductor is

used and the 464 Ω termination accounts for the internal 18.5 kΩ element. The 10 Ω resistor at VIN+

isolates the OPS input from the 52 pF filter capacitor. To recover the insertion loss and produce a maximum

5 V_PPoutput, the OPS gain is set to 2.96 V/V. When the interstage filter path is selected, the two DPDT

relays pass the OPS output on directly from the 49.9 Ω output matching resistor to V_O. Disable the THS3095

to conserve power.

2. To deliver 20 V_PPat the V_Ooutput, select the THS3095 path. Select the internal OPS path to bypass the 50

MHz filter (1.55 dB insertion loss) in order to give a maximum 5.9 V_PPoutput at VOUT (pin 11). The two

DPDT relays switch position, and the 49.9 Ω at the OPS output becomes part of the 25 MHz, third-order

Bessel filter into the THS3095 stage. This filter has a 1 dB insertion loss requiring a gain of 3.8 V/V in the

THS3095 to deliver 20 V_PPfrom the OPS output.

3. Frequency Response of the 5 V_PPand 20 V_PPChannels and Harmonic Distortion Performance of the 5 V_PP

and 20 V_PPChannels show the frequency response and harmonic distortion performance of the dual output-

voltage system. The frequency response is normalized to 0 dB to make bandwidth comparisons easier.

9.1.1.1.3 Application Curves

3

0

-40

-50

5 V_PP

20 V_PP

-60

-3

-70

-6

-80

-9

HD2 -5 V_PP

HD3- 5 V_PP

HD2- 20 V_PP

HD3- 20 V_PP

-90

-12

-100

-15

1M

10M

Frequency (Hz)

1M

10M

Frequency (Hz)

100M 200M

D510

D509

图9-5. Harmonic Distortion Performance of the 5

图9-4. Frequency Response of the 5 V_PPand 20

V_PPand 20 V_PPChannels

V_PPChannels

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9.1.1.2 High-Voltage Pulse-Generator

7.5 V

13

16

15

14

102 ꢀ

50 kꢀ

OPS A_V= 3 V/V

12

100 ꢀ

1

2

x1

18.5 kꢀ

205 ꢀ

50 kꢀ

5 V_PPMax

at Load

50 ꢀ

49.9 ꢀ

0V

1V

0 to 10 mA

x1

11

+

V_OUT= 10 V_PP

To

50-Ω Load

100 ꢀ

+

250 ꢀ

500 ꢀ

0V

3

4

x1

0 to 10 mA

10

18.5 kꢀ

100 ꢀ

1.55-dB

insertion loss

9

V_PATHSEL= 3.3 V

6

7

8

5

10 ꢀ

œ7.5 V

35-MHz, 3rd-order Bessel filter

390 nH

100 ꢀ

13 pF

75 pF

511 ꢀ

图9-6. Driving a 10 V_PPPulse Output into a 100 Ω Load With a 35 MHz External Interstage Bessel Filter

9.1.1.2.1 Design Requirements

To design a high-voltage, high-speed pulse generator with minimum overshoot, use the parameters listed in 表

9-1 as the input parameters.

表9-2. Pulse-Generator Specifications

DESIGN PARAMETER

EXAMPLE VALUE

±7.5 V

Power supply

Pulse frequency

5 MHz

Pulse output voltage

10 V_PP

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9.1.1.2.2 Detailed Design Procedure

图 9-6 shows an example design using the THS3215 to deliver a 10 V_PPmaximum voltage from a DAC input,

and includes an example external, third-order, interstage Bessel filter. Some of the salient considerations for this

design include:

1. Termination resistance at the D2S inputs is increased to reduce DAC output current. This example is

intended to be used with a current-sourcing DAC with an output compliance voltage of at least 1 V on a

0.5 V common-mode voltage. The 10-mA, single-ended, DAC tail current produces a 0 V to 1 V swing on

each 100 Ω termination. The resulting 2 V_PPdifferential DAC signal produces a higher SNR signal at the

THS3215 inputs.

2. The midscale buffer is not used. VREF (pin 14) is grounded to set the inputs to a 4-V_PPground-centered

maximum output swing at VO1 (pin 6). The external input to the OPS is selected by setting PATHSEL (pin 4)

to 3.3 V (anything over 1.3 V is adequate, or tie this pin to +V_CCfor fixed, external-path operation).

3. The interstage Bessel filter is –0.3 dB flat through 12 MHz, with only 1.55 dB of insertion loss. The filter is

designed to be low insertion-loss with relatively high resistor values. The filter uses standard inductor values.

The capacitors are also standard-value, and slightly off from the exact filter solution. The final resistor to

ground is designed for 500 Ω, but increased here to a standard 511 Ω externally to account for the internal

18.5 kΩ resistor on the external OPS input pin to GND. To isolate the last 75 pF filter capacitor from the OPS

input stage, a 10 Ω series resistor is added close to the VIN+ (pin 9) input.

4. The filter adds 1.55 dB of insertion loss that is recovered, to achieve a 10 V_PPmaximum output by designing

the OPS for a gain of 3 V/V. Looking at 表8-6, this gain setting requires the 205 Ω external R_Fand 102 Ω R_G

to ground for best operation.

5. For 10 V_PPmaximum output, the ±7.5 V supplies shown in 图9-6 give adequate headroom in the OPS

output stage. The operating maximum supply of 15.8 V requires a 5% tolerance on these ±7.5 V supplies.

6. The Bessel filter gives a very low overshoot full-scale output step-response, as shown in the 5 MHz, ±5 V

square wave of Pulse Response of the System With the Interstage Bessel Filter. The frequency response of

the system is shown in Frequency Response of the System With the Interstage Bessel Filter.

9.1.1.2.3 Application Curves

16

14

12

10

8

6

4

10 V_PP

ê5 V

2

0

-2

-4

-6

6

4

1M

10M

Frequency (Hz)

100M

Time (20 ns/div)

D511

D512

图9-7. Frequency Response of the System With

图9-8. Pulse Response of the System With the

the Interstage Bessel Filter

Interstage Bessel Filter

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9.1.1.3 Single-Supply, AC-Coupled, Piezo Element Driver

V_{MID_OUT}

15 V

16

15 V

13

15

14

75 ꢀ

50 kꢀ

12

OPS A_V= 3.4 V/V

100 ꢀ

1

2

x1

1 …F

18.5 kꢀ

182 ꢀ

5.9 ꢀ

50 kꢀ

10 nF

50 ꢀ

x1

11

+

V_OUT= 12 V_PP

1.62 kꢀ

49.9 ꢀ

V_{MID_OUT}

49.9 ꢀ

220 pF

+

2 V_PP

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

10 nF

(V_{MID_OUT}+ 3.5 V_PP

)

V_PATHSEL=15 V

9

6

7

8

5

10 ꢀ

V_O1= V_{MID_OUT}+ 4 V_PP

390 nH

105 ꢀ

15-MHz, 2nd-order Chebyshev

filter (0.2 dB ripple)

68 pF

825 ꢀ

1 …F

图9-9. Single-Supply, Heavy Capacitive-Load Driving

9.1.1.3.1 Detailed Design Procedure

The very-high peak output current and slew rate of the THS3215 OPS make it particularly suitable for driving

heavy capacitive loads, such as the piezo elements used in continuous wave (CW) applications that require

high-amplitude, sinusoidal-type excitations. The driver is quickly disabled during the receive time when the

output transmit and receive switch is moved to receive mode. 图9-9 shows an example design using the internal

midscale buffer to bias all the stages to midsupply on a single 15 V design. There are many elements to this

example that also apply to any single-supply application. The key points here are:

1. The differential DAC input signal is ac-coupled to the D2S input, and the termination resistors are scaled up

and biased to midsupply using the output of the midscale buffer, VMID_OUT (pin 15). The 10-nF blocking

capacitors before the 1.62 kΩ termination resistors set the high-pass pole at 10 kHz.

2. The internal divider resistors of the midscale buffer are decoupled using a 1 µF capacitor on VMID_IN (pin

1). Use of the capacitor improves both noise and PSRR through the reference buffer stage. In turn, the noise

injected by the bias source is reduced at the various places the buffer output is used.

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3. V_{MID_OUT}is also applied to the VREF input (pin 14) to hold the D2S output centered on the single 15 V

supply. There is minimal dc current into VREF because the D2S input buffers operate at the same common-

mode voltage, V_{MID_OUT}

.

4. The D2S output is dc biased at midsupply and delivers two times the differential swing applied at its inputs.

Assuming 2 V_PPat the D2S inputs implies 4 V_PPat the D2S output pins. Lower input swings are supported

with the gain in the OPS adjusted to meet the desired output maximum.

5. The filter in 图9-9 is a 0.2 dB ripple, second-order Chebyshev filter at 15 MHz. For example, if the desired

maximum frequency is 12 MHz, this filter attenuates the HD2 and HD3 out of the D2S by approximately 3 dB

and 5 dB, respectively. Increased attenuation can be provided with higher-order filters, but this simple filter

does a good job of band-limiting the high-frequency noise from the D2S outputs before the noise gets into

the OPS.

6. The dc bias voltage at VO1 (pin 6) drives a small dc current into the 18.5 kΩ resistor to ground at the OPS

external input, VIN+ (pin 9). The error voltage due to the bias current level-shifts the dc voltage at the OPS

noninverting input through the 105 Ω filter resistor. This offset is amplified by the OPS gain because the R_G

element is referenced to the V_MIDoutput with a dc gain of 3.4 V/V.

7. The logic lines are still referenced to ground in this single-supply application. The external path to the OPS is

selected by connecting PATHSEL (pin 4) to +V_CC. DISABLE (pin 10) is grounded in this example in order to

hold the OPS on. If the disable feature is required by the application, drive DISABLE (pin 10) using a

standard logic control driver. Note that the midscale buffer output still drives R_Gand R_Fto midsupply in this

configuration with the OPS disabled.

8. To operate at midsupply, ac-couple the R_Gelement to ground through a capacitor. 图9-9 shows the

midscale buffer driving R_G, thus eliminating the need for an added capacitor. Use a blocking capacitor to

move the dc gain to 1 V/V. The voltage on the external, noninverting input of the OPS sets the dc operating

point. Use a blocking capacitor to lighten the load on the midscale buffer output and eliminate the bias on R_G

when the OPS is disabled.

9. Piezo element drivers operate in a relatively low-frequency range; therefore, the OPS R_Fis scaled up even

further than the values suggested in 表8-6. An increased R_Fallows R_Gto also be scaled up, thereby

reducing the load on the midscale buffer, and allow a lower series output resistor to be used into the 220 pF

capacitive load.

10. The peak charging current into the capacitive load occurs at the peak dV/dT point. Assuming a 12 MHz

sinusoid at 12 V_PPrequires a peak output current from the OPS of 6 V_PEAK× 2π× 12 MHz × 220 pF =

100 mA. This result is slightly lesser than the rated minimum peak output current of the OPS.

Using a very low series resistor limits the waveform distortion due to the I × R drop at the peak charging point

around the sinusoidal zero crossing. The 100 mA through 5.9 Ω causes a 0.59 V peak drop to the load

capacitance around zero crossing. The voltage drop across the series output resistor increases the apparent

third harmonic distortion at the capacitive load. HD2 vs Load Capacitance and HD3 vs Load Capacitance show

10 V_PPdistortion sweeps into various capacitor loads. The results shown in these figures are for the OPS only

because the results set the harmonic distortion performance in this example.

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9.1.1.4 Output Common-Mode Control Using the Midscale Buffer as a Level Shifter

V_{MID_OUT}

V_O1

7.5 V

16

7.5 V

13

15

14

51.1 ꢀ

50 kꢀ

12

100 ꢀ

1

2

x1

+

18.5 kꢀ

V_{MID_IN}

= 2 V

205 ꢀ

œ

50 kꢀ

50 ꢀ

x1

11

V_{MID_OUT}4 V

+

A_V= œ4 V/V

49.9 ꢀ

+

1 V_PP

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

V_{MID_OUT}

9

V_PATHSEL> 1.3V

6

7

8

5

V_O1= V_{MID_OU T}1 V

œ7.5 V

图9-10. Adding an Output DC Offset Using the Midscale Buffer

9.1.1.4.1 Detailed Design Procedure

An easy way to insert a dc offset into the signal channel (without sacrificing any of the DAC dynamic range) is to

apply the desired offset at VMID_IN (pin 1) and use it to bias VREF (pin 14) and VIN+ (pin 9). An example is

shown in 图 9-10. This example shows a relatively low maximum differential input of 1 V_PPon any compliance

voltage required by the DAC. Other configuration options include:

1. The D2S output is offset using a dc input at VMID_IN. Although shown here as ±2 V, the dc range expands

to ±3.5 V when using ±7.5 V supplies.

2. Connect VMID_OUT (pin 15) to the VREF input to place the D2S output at the dc offset voltage along with a

gain of 2 V/V version of the differential input voltage. The stated range of ±2 V, along with the ±0.5 V out of

the upper input buffer, requires a peak output current from VMID_OUT of 2.5 V / 150 Ω = 16.7 mA. This

value is well below the rated minimum linear output current of 40 mA for the midscale buffer.

3. The dc offset voltage is then applied to the external OPS non-inverting input, VIN+. Connecting the circuit in

this manner results in no additional dc gain for the dc offset between the D2S and OPS outputs, while

continuing to retain the signal gain of the OPS configured as an inverting amplifier. The values of R_Fand R_G

in this application example are derived from 表8-3. The OPS is setup for a gain of –4 V/V in this example.

Using the resistor values from 表8-3 results in the widest bandwidth for the OPS; however, the R_G= 51.1 Ω

resistor presents a heavy load to the D2S output. In such cases, the OPS external resistors can be scaled

up to reduce the D2S output load, but at the expense of reduced OPS bandwidth.

4. No filtering is shown in this example; however, introducing filtering in the OPS R_Gpath is certainly possible.

In such cases, the R_Gelement is also the filter termination resistor. Filtering adds insertion loss that can be

recovered by adjusting the OPS gain setting.

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9.1.1.5 Differential I/O Driver With independent Common-Mode Control

V_{MID_OUT}

V_O1

16

15

14

13

294 ꢀ

50 kꢀ

12

100 ꢀ

1

2

x1

+

18.5 kꢀ

V_{MID_IN}

294 ꢀ

œ

50 kꢀ

50 ꢀ

x1

11

+

Differential

Filter

V_OUT= V_{MID_OUT}œ 2V_IN

49.9 ꢀ

Input Mixer

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

4

x1

10

18.5 kꢀ

49.9 ꢀ

9

V_{MID_OUT}

V_PATHSEL> 1.3 V

6

7

8

5

V_O1= V_{MID_OUT}+ 2V_IN

图9-11. Differential I/O with Common-Mode Control

9.1.1.5.1 Detailed Design Procedure

Certain applications require the differential DAC output voltage to be translated from one common-mode

(compliance) level to a differential output at a different common-mode level. The THS3215 performs voltage-

level translation directly using the very flexible blocks provided internally. 图 9-11 shows an example of such an

application, where the differential gain is always 4 V/V. The differential gain is fine-tuned down by setting the

insertion loss in the differential post-filter. The considerations critical to this application include:

1. The input is dc-coupled with the appropriate termination impedance required by the DAC. Use a high-

frequency, antialiasing filter at the input to limit DAC feedthrough in the deselected OPS internal input.

2. The output common-mode control is set with the voltage applied to the VMID buffer input at VMID_IN (pin 1).

The circuit is configured so that the output at VMID_OUT (pin 15) drives both VREF (pin 14), in order to set

the D2S dc output voltage, and VIN+ (pin 9).

3. The D2S output available at VO1 (pin 6) provides one side of the differential-output, and is dc-biased at

V

_{MID_OUT}. VO1 also drives the R_Gresistor for the OPS in an inverting gain of –1 V/V. The dc bias level at

the R_Ginput and the VIN+ input of the OPS are the same voltage; therefore, no level shift through the OPS

occurs. The OPS outputs an inverted version of the D2S output signal at the same common-mode voltage

(V_{MID_OUT}). The wideband, differential signal with independent output common-mode voltage control can

now be applied to a differential filter and on to the next stage.

4. Make sure that the differential filter has only differential resistors and capacitors. Termination resistors to

ground level-shift the input common-mode voltage, while differential resistors transfer V_{MID_OUT}directly

through the filter as a common-mode input to the mixer.

5. If the desired V_{MID_OUT}+ differential signal combined clips in the OPS or D2S, offset the supplies to gain

headroom. For instance, if a 5 V output common-mode voltage is required with a 10 V_PPdifferential signal,

the OPS and D2S must deliver 2.5 V to 7.5 V output swings. The D2S has the higher headroom requirement

at 1.5 V (maximum). Operating the THS3215 with –5 V and 10 V supplies stays within the rated maximum

of

15.8 V total supply range, and provide adequate headroom for the positive offset swing requirement. Note

that the logic lines are still referenced to GND by pin 7. Tie PATHSEL (pin 4) to +V_CCto hold this design in

the external path mode required.

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10 Power Supply Recommendations

The THS3215 typically operates on balanced, split supplies. The specifications and characterization plots use

±6 V in most cases. The full operating range for the THS3215 spans ±4 V to ±7.9 V. The input and output stages

have separate supply pins that are isolated internally.

The recommended external supply configuration brings ±V_CCinto the output stage first, then back to the input

stage connections through a π-filter comprised of ferrite beads and added decoupling capacitors at +VCC2 (pin

16) and –VCC2 (pin 5). 图 10-1 shows an example decoupling configuration. This same circuit configuration

was used to characterize the D2S + OPS performance in Frequency Response vs Output Voltage to HD3 vs

Supply Voltage.

Ferrite Bead

4 ꢁH

6 V

2.2 …F

10 nF

220 nF

10 nF

220 nF

16

15

14

13

162 ꢀ

50 kꢀ

12

100 ꢀ

1

x1

18.5 kꢀ

249 ꢀ

50 kꢀ

50 ꢀ

49.9 ꢀ

2

x1

11

+

A_V= 5 V/V

To

50-Ω Load

49.9 ꢀ

+

Differential

V_IN

250 ꢀ

500 ꢀ

3

x1

10

18.5 kꢀ

49.9 ꢀ

4

9

6

7

8

5

200 ꢀ

Ferrite Bead

4 ꢁH

-6 V

2.2 …F

10 nF

220 nF

10 nF

220 nF

图10-1. Recommended Power-Supply Configuration

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The ferrite bead acts to break the feedback loop from the output stage load currents that re-enter the D2S and

midscale buffer stages. Operate the two positive supply pins and the two negative supply pins at the same

voltage. Using separate sources on the two pins risks forward-biasing the on-chip parallel diodes that connect

the two supply inputs together. +VCC1 (pin 13) and +VCC2 (pin 16) have two parallel diodes that are off if the

voltage at the two pins are equal. The same is true for –VCC1 (pin 8) and –VCC2 (pin 5).

The THS3215 provides considerable flexibility in the supply voltage settings. The overriding consideration is

always satisfying the required headroom to the supplies on all the I/O paths. The logic controls on PATHSEL (pin

4) and DISABLE (pin 10) are intended to operate ground referenced regardless of supplies used. The ground

connection on pin 7 is used to set the reference.

Power savings are certainly possible by operating with only the minimum required supplies for the intended

swings at each of the pins. For instance, consider an example design operating with a current-sinking DAC with

the input common-mode voltage at 3 V, with an output swing at the D2S output of ±1 V. Looking at just the D2S

under these conditions, the minimum positive supply is 3 V_CM+ the maximum input headroom of 1.5 V to the

positive supply + the input signal swing of 0.25 V, resulting in a minimum 4.75 V supply for this operation. The ±1

V output at VO1 (pin 6) along with the D2S output headroom sets the minimum negative supply voltage. The

maximum 1.5 V headroom gives a possible minimum negative supply of –2.75 V. However, the minimum

operating total of 8 V increases the negative supply to –3.5 V.

If the ±1 V swing is then amplified by the OPS, the output swing and headroom requirements set the minimum

operating supply. For instance, if the OPS is operating at a gain of 2.5 V/V, the ±2.5 V output requires a

maximum headroom of 1.6 V to either supply. Achieving a 1.6 V headroom requires a minimum balanced supply

of ±4.1 V. However, the input stage overrides the positive side because the required minimum is 4.75 V, while

the negative increases to –4.1 V. This example of absolute minimum supplies saves power. Using a typical 35-

mA quiescent current for all stages, going to the minimum 8.5 V total across the device, uses 310 mW of

quiescent power versus the 420 mW if a simple ±6 V supply is applied. However, ac performance degrades with

the lower headroom. For more power-sensitive applications, consider adjusting the supplies to the minimum

required on each side.

10.1 Thermal Considerations

The internal power for the THS3215 is a combination of its quiescent power and load power. The quiescent

power is simply the total supply voltage times the supply current. This current is trimmed to reduce power

dissipation variation and minimize variations in the ac performance. At a ±7.5 V supply, the maximum supply

current of 36.5 mA dissipates 548 mW of quiescent power. The worst-case load power occurs if the output is at

½ the single-sided supply voltage driving a dc load. Placing a ±3.75 V dc output into 100 Ω adds another

37.5 mA × 3.75 V = 140 mW of internal power. This total of approximately 688 mW of internal dissipation

requires the thermal pad be connected to a good heat-spreading ground plane to hold the internal junction

temperatures below the rated maximum of 150°C.

The thermal impedance is approximately 45 °C/W with the thermal pad connected. For 688 mW of internal

power dissipation there is a 31°C (approximate) rise in the junction temperature from ambient. Designing for the

intended 85°C maximum ambient temperature results in a maximum junction temperature of 116°C.

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11 Layout

11.1 Layout Guidelines

High-speed amplifier designs require careful attention to board layout in order to achieve the performance

specified in the data sheets. Poor layout techniques can lead to increased parasitics from the board and external

components resulting in suboptimal performance, and also instability in the form of oscillations. The THS3215

evaluation module (EVM) serves as a good reference for proper, high-speed layout methodology. The EVM

includes numerous extra elements needed for lab characterization, and also additional features that are useful in

certain applications. These additional components can be eliminated on the end system if not required by the

application. General suggestions for the design and layout of high-speed, signal-path solutions include:

1. Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the

output and input pins can cause instability. To reduce unwanted capacitance, open a window around the

signal I/O pins on all of the ground and power planes around those pins. On other areas of the board,

continuous ground and power planes are preferred for signal routing, with matched impedance traces for

longer runs.

2. Use high-quality, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power

pins. Higher value capacitors (2.2 µF) are required, but can be placed further from the device power pins

and shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors

that offer a much higher self-resonance frequency over standard capacitors. Avoid narrow power and ground

traces to minimize inductance between the pins and the decoupling capacitors. Follow the power-supply

guidelines recommended in the 节10 section.

3. Careful selection and placement of external components preserve the high-frequency performance of the

THS3215. Use low-reactance type resistors. Surface-mount resistors work best, and allow a tighter overall

layout. Keep the printed circuit board (PCB) trace length as short as possible. Never use wire-bound type

resistors in a high-frequency application. The output pin and inverting input pins are the most sensitive to

parasitic capacitance; therefore, always position the feedback and series output resistors, if any, as close as

possible to the inverting input pins and output pins. Place other network components, such as input

termination resistors, close to the gain-setting resistors.

4. When using differential signal routing over any appreciable distance, use microstrip layout techniques with

matched impedance traces. On differential lines, like those on the D2S inputs, match the routing in order to

minimize common-mode noise effects and improve HD2 performance.

5. The input summing junction of the OPS is very sensitive to parasitic capacitance. Connect the R_Gelement

into the summing junction with minimal trace length to the device-pin side of the resistor. The other side of

R_Gcan have more trace length to source or ground, if needed; however, a very-short, low-inductance

connection is preferred. For best results, do not socket a high-speed device such as the THS3215. The

additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely

troublesome parasitic network that makes it almost impossible to achieve a smooth, stable frequency

response. Best results are obtained by soldering the THS3215 directly onto the board.

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11.2 Layout Example

Remove ground and power planes

close to VOUT and VIN-

pins to minimize capacitance

Place bypass capacitors

close to power pins

Ground and power plane

on inner layers

Place R_Fand R_Gclose to device

pins to minimize stray capacitance

and feedback loop area

1

2

3

4

12

11

10

9

Place 50-Ω output resistor close

to VOUT pin to minimize

parasitic capacitance

Remove ground and power

planes close to D2S inputs

to minimize capacitance

Connect thermal pad to GND

图11-1. Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Development Support

12.1.1.1 TINA-TI^™(Free Software Download)

TINA^™is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a

free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range

of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain

analysis of SPICE, as well as additional design capabilities.

Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing

capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select

input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.

The THS3215 TINA model is available on the THS3215 product folder, under the Tools and software tab. After

downloading, open the model, right-click on a model symbol, and select Enter Macro to see the list of modeled

parameters.

Note

These files require that either the TINA software (from DesignSoft^™) or TINA-TI software be installed.

Download the free TINA-TI software from the TINA-TI folder.

12.2 Documentation Support

12.2.1 Related Documentation

For related documentation, see the following:

• Texas Instruments, OPA695 Ultra-Wideband, Current-Feedback Operational Amplifier With Disable data

sheet

• Texas Instruments, THS3215EVM and THS3217EVM user's guide

• Texas Instruments, Voltage Feedback Vs Current Feedback Op Amps application report

• Texas Instruments, Current Feedback Amplifier Analysis and Compensation application report

• Texas Instruments, Current Feedback Amplifiers: Review, Stability Analysis, and Applications application note

• Texas Instruments, Stabilizing Current-Feedback Op Amps While Optimizing Circuit Performance application

report

12.3 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

12.4 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

12.5 Trademarks

TINA-TI^™, TINA^™, and TI E2E^™are trademarks of Texas Instruments.

DesignSoft^™is a trademark of DesignSoft, Inc.

所有商标均为其各自所有者的财产。

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12.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

12.7 Glossary

TI Glossary

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

GENERIC PACKAGE VIEW

RGV 16

4 x 4, 0.65 mm pitch

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.

Refer to the product data sheet for package details.

4224748/A

www.ti.com

PACKAGE OUTLINE

RGV0016A

VQFN - 1 mm max height

S

C

A

L

E

3

.

0

PLASTIC QUAD FLATPACK - NO LEAD

4.15

3.85

A

B

PIN 1 INDEX AREA

4.15

3.85

C

1.0

0.8

SEATING PLANE

0.08 C

0.05

0.00

2.16 0.1

2X 1.95

SYMM

(0.2) TYP

5

8

(0.37) TYP

EXPOSED

THERMAL PAD

9

4

SYMM

2X 1.95

17

2.16 0.1

12X 0.65

1

12

PIN 1 ID

0.38

16X

0.23

13

16

0.1

C A B

0.65

0.45

16X

0.05

4219037/A 06/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com

EXAMPLE BOARD LAYOUT

RGV0016A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(

2.16)

SYMM

SEE SOLDER MASK

DETAIL

16

13

16X (0.75)

12

1

16X (0.305)

12X (0.65)

17

SYMM

(0.83)

(3.65)

4

9

(R0.05) TYP

(

0.2) TYP

VIA

5

8

(0.83)

(3.65)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 20X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

METAL UNDER

SOLDER MASK

METAL EDGE

EXPOSED METAL

SOLDER MASK

OPENING

EXPOSED

METAL

SOLDER MASK

OPENING

NON SOLDER MASK

SOLDER MASK DEFINED

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219037/A 06/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com

EXAMPLE STENCIL DESIGN

RGV0016A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(0.58) TYP

13

16

16X (0.75)

1

12

16X (0.305)

(0.58) TYP

(3.65)

17

SYMM

12X (0.65)

4X (0.96)

4

9

(R0.05) TYP

8

5

4X (0.96)

SYMM

(3.65)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 17

79% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

4219037/A 06/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

www.ti.com

重要声明和免责声明

TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，

不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担

保。

这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。

这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。

您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成

本、损失和债务，TI 对此概不负责。

TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改

TI 针对 TI 产品发布的适用的担保或担保免责声明。

TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	THS3215IRGVT
厂家：	TEXAS INSTRUMENTS
描述：	直流至 650MHz、差分转单端、DAC 输出放大器 \| RGV \| 16 \| -40 to 85 放大器
文件：	总77页 (文件大小：4080K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS3215IRGVT [TI]

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