THS4011IDGNRG4 [TI]
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS; 290 - MHz的低失真高速放大器型号: | THS4011IDGNRG4 |
厂家: | TEXAS INSTRUMENTS |
描述: | 290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS |
文件: | 总35页 (文件大小:1171K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS
Check for Samples: THS4011, THS4012
1
FEATURES
THS4011
D, DGN, OR JG PACKAGE
(TOP VIEW)
THS4012
†
2
D OR DGN PACKAGE
(TOP VIEW)
•
High Speed
–
–
–
290-MHz Bandwidth (G = 1, –3 dB)
310-V/ms Slew Rate
1OUT
1IN−
1IN+
−VCC
VCC+
2OUT
2IN−
2IN+
NULL
IN−
NULL
VCC+
OUT
NC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
37-ns Settling Time (0.1%)
IN+
•
Low Distortion
THD = –80 dBc (f = 1 MHz, RL = 150 Ω)
VCC−
–
•
•
•
110-mA Output Current Drive (Typical)
7.5-nV/√Hz Voltage Noise
NC − No internal connection
Excellent Video Performance
Cross-section view showing
PowerPAD option (DGN)
–
–
–
70-MHz Bandwidth (0.1 dB, G = 1)
0.006% Differential Gain Error
0.01° Differential Phase Error
†
This package is in the Product Preview stage of
development. Please contact your local TI sales of fice for
availability.
THS4011
•
•
±5-V to ±15-V Supply Voltage
Available in Standard SOIC, MSOP
PowerPAD™, JG, or FK Packages
FK PACKAGE
(TOP VIEW)
•
Evaluation Module Available
DESCRIPTION
3
2
1
20 19
The THS4011 and THS4012 are high-speed,
single/dual, voltage feedback amplifiers ideal for a
wide range of applications. The devices offer good ac
performance, with 290-MHz bandwidth, 310-V/ms
slew rate, and 37-ns settling time (0.1%). These
amplifiers have a high output drive capability of 110
mA and draw only 7.8-mA supply current per
channel. For applications requiring low distortion, the
NC
NC
IN−
NC
IN+
NC
4
5
6
7
8
18
17
16
15
14
VCC+
NC
OUT
NC
9
10 11 12 13
THS4011/4012 operate with
a
total harmonic
distortion (THD) of -80 dBc at f = 1 MHz. For video
applications, the THS4011/4012 offer 0.1-dB gain
flatness to 70 MHz, 0.006% differential gain error,
and 0.01° differential phase error.
RELATED DEVICES
DESCRIPTION
DEVICE
THS4011/4012
THS4031/4032
THS4061/4062
290-MHz low-distortion high-speed amplifiers
100-MHz low-noise high-speed-amplifiers
180-MHz high-speed amplifiers
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2010, Texas Instruments Incorporated
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DISTORTION
vs
FREQUENCY
−40
V
= ±15 V
CC
R
= 150 Ω
L
−50
G = 2
−60
−70
−80
2nd Harmonic
−90
−100
−110
3rd Harmonic
100k
1M
10M
f − Frequency − Hz
AVAILABLE OPTIONS
PACKAGED DEVICES(1)
PLASTIC SMALL PLASTIC MSOP(2)
PACKAGED DEVICES
NUMBER OF
CHANNELS
MSOP
SYMBOL
EVALUATION
MODULE
TA
CERAMIC DIP
(JG)
CHIP CARRIER
(FK)
OUTLINE(2) (D)
THS4011CD
THS4012CD
THS4011ID
(DGN)
1
2
1
2
THS4011CDGN
THS4012CDGN(3)
THS4011DGN
THS4012IDGN(3)
TIACI
TIABY
TIACJ
TIABZ
—
—
—
—
—
—
—
—
THS4011EVM
0°C to
70°C
THS4012EVM
—
—
–40°C to
85°C
THS4012ID
–55°C to
125°C
1
—
—
—
THS4011MJG
THS4011MFK
—
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).
(3) This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.
2
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
FUNCTIONAL BLOCK DIAGRAM
Null
1
2
8
IN−
−
6
OUT
3
IN+
+
Figure 1. THS4011 – Single Channel
V
CC
2
8
1IN−
1IN+
−
1
1OUT
3
+
6
5
2IN−
2IN+
−
7
2OUT
+
4
−V
CC
Figure 2. THS4012 – Dual Channel
Copyright © 1999–2010, Texas Instruments Incorporated
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3
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
VCC
VI
Supply voltage
±16.5
V
Input voltage
±VCC
IO
Output current
175
mA
V
VID
Differential input voltage
Continuous total power dissipation
Maximum junction temperature
±4
See Dissipation Rating Table
150
TJ
°C
°C
°C
°C
°C
THS401xC
0 to 70
TA
Operation free-air temperature range THS401xI
THS4011M
–40 to 85
–55 to 125
Tstg
Storage temperature range
–65 to 150
DISSIPATION RATINGS
qJA
(°C/W)
qJC
(°C/W)
TA = 25°C
POWER RATING
PACKAGE
D
DGN(2)
JG
167(1)
58.4
119
38.3
4.7
28
740 mW
2.14 W
1050 mW
1375 mW
FK
87.7
20
(1) This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC-proposed High-K test
PCB, the qJA is 95°C/W with a power rating at 1.32 W at TA = 25°C.
(2) This data was taken using 2-oz trace and copper pad that is soldered directly to a 3-in × 3-in PC. For
further information, refer to the Application Information section of this data sheet.
RECOMMENDED OPERATING CONDITIONS
MIN
±4.5
9
MAX UNIT
Split supply
±16
V
VCC
Supply voltage
Single supply
C suffix
32
0
70
TA
Operating free-air temperature
I suffix
–40
–55
85
°C
M suffix
125
4
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
THS4011C/I
THS4012C/I
PARAMETER
TEST CONDITIONS(1)
UNIT
TYP
DYNAMIC PERFORMANCE
VCC = ±15 V
290
270
70
Unity-gain bandwidth (–3 dB)
Gain = 1
Gain = 1
MHz
MHz
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VO(PP) = 20 V
VO(PP) = 5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
BW
Bandwidth for 0.1-dB flatness
Full-power bandwidth(2)
Slew rate
35
VCC = ±15 V, RL = 150 Ω
VCC = ±5 V, RL = 150 Ω
4.9
16
MHz
MHz
310
260
37
SR
ts
Gain = –1, RL = 150 Ω
V/ms
ns
Settling time to 0.1%
Settling time to 0.01%
VI = –2.5 V to 2.5 V, Gain = –12
VI = –2.5 V to 2.5 V, Gain = –12
35
90
ns
70
NOISE/DISTORTION PERFORMANCE
THD Total harmonic distortion
VCC = ±15 V, fc = 1 MHz,
VCC = ±5 V or ±15 V,
VCC = ±5 V or ±15 V,
VO(PP) = 2 V
f = 10 kHz
–80
7.5
dBc
Vn
In
Input voltage noise
Input current noise
nV/√Hz
pA/√Hz
f = 10 kHz
1
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
0.01%
0.01%
0.01°
0.001°
Differential gain error
Differential phase error
. Gain = 2, RL = 150 Ω, NTSC
. Gain = 2, RL = 150 Ω, NTSC
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
(2) Full-power bandwidth = Slew rate/2p VO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated
Submit Documentation Feedback
5
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THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
THS4011C/I
THS4012C/I
PARAMETER
DC PERFORMANCE
TEST CONDITIONS(1)
UNIT
MIN
TYP
25
12
1
MAX
TA = 25°C
10
8
VCC = ±15 V, VO = ±10 V, RL = 1 kΩ
VCC = ±5 V, VO = ±2.5 V, RL = 250 Ω
VCC = ±5 V or ±15 V
TA = Full range
TA = 25°C
Open loop gain
V/mV
7
TA = Full range
TA = 25°C
5
6
8
VIO
Input offset voltage
Input offset voltage drift
Input bias current
mV
mV/°C
mA
TA = Full range
15
6
TA = 25°C
2
25
IIB
VCC = ±5 V or ±15 V
TA = Full range
TA = 25°C
8
250
400
IIO
Input offset current
Offset current drift
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
nA
TA = Full range
0.3
nA/°C
INPUT CHARACTERISTICS
VCC = ±15 V
VCC = ±5 V
±13
±3.8
82
±14.1
±4.3
110
Common-mode input voltage
range
VICR
V
TA = 25°C
VCC = ±15 V, VIC = ±12 V
VCC = ±5 V, VIC = ±2.5 V
TA = Full range
TA = 25°C
77
dB
CMRR Common-mode rejection ratio
90
95
TA = Full range
83
RI
CI
Input resistance
2
MΩ
Input capacitance
1.2
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V,
VCC = ±5 V,
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
Open loop
±13
±3.4
±12
±3
±13.5
±3.7
±13
±3.4
110
75
RL = 1 kΩ
VO
Output voltage swing
V
RL = 250 Ω
RL = 150 Ω
70
IO
Output current
RL = 20 Ω
mA
50
IOS
RO
Short-circuit output current
Output resistance
150
12
mA
Ω
POWER SUPPLY
Dual supply
±4.5
9
±16.5
33
VCC
Supply voltage
V
Single supply
TA = 25°C
7.8
6.9
83
9.5
11
VCC = ±15 V
TA = Full range
TA = 25°C
ICC
Supply current (each amplifier)
Power-supply rejection ratio
mA
dB
8.5
10
VCC = ±5 V
TA = Full range
TA = 25°C
75
68
PSRR
VCC = ±5 V to ±15 V
TA = Full range
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
6
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 150 Ω, TA = 25°C (unless otherwise noted)
THS4011M
UNIT
PARAMETER
TEST CONDITIONS(1)
MIN
TYP
MAX
DYNAMIC PERFORMANCE
Unit-gain bandwidth
Closed loop, RL = 1 kΩ,
VCC = ±15 V
VCC = ±15 V
VCC = ±5 V
160(2)
200
70
35
30
2.5
8
Bandwidth for 0.1-dB flatness Gain = 1
MHz
BW
VCC = ±2.5 V
VO(PP) = 20 V
VO(PP) = 20 V
VCC = ±15 V, RL = 150 Ω,
VCC = ±5 V, RL = 150 Ω,
VCC = ±15 V, RL = 1 kΩ
Full-power bandwidth(3)
Slew rate
SR
ts
300(2)
400
37
35
90
70
V/ms
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
Settling time to 0.1%
VI = –2.5 to 2.5 V, Gain = –1
VI = –2.5 to 2.5 V, Gain = –1
ns
Settling time to 0.01%
NOISE/DISTORTION PERFORMANCE
THD
Vn
Total harmonic distortion
Input voltage noise
Input current noise
VCC = ±15 V, fc = 1 MHz, VO(PP) = 1 V
VCC = ±5 V or ±15 V,
–80
7.5
dBc
f = 10 kHz
f = 10 kHz
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V
VCC = ±5 V
nV/√Hz
pA/√Hz
In
VCC = ±5 V or ±15 V,
1
0.006%
0.001%
0.01°
0.002°
Differential gain error
Differential phase error
Gain = 2, RL = 150 Ω, NTSC
Gain = 2, RL = 150 Ω, NTSC
(1) Full range = –55°C to 125°C for the M suffix
(2) This parameter is not tested.
(3) Full-power bandwidth = Slew rate/2p VO(peak)
Copyright © 1999–2010, Texas Instruments Incorporated
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THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
ELECTRICAL CHARACTERISTICS (Continued)
VCC = ±15 V, RL = 1 kΩ, TA = full range (unless otherwise noted)
THS4011M
TYP
PARAMETER
DC PERFORMANCE
TEST CONDITIONS(1)
UNIT
MIN
MAX
VCC = ±15 V, VO = ±10 V, RL = 1 kΩ
VCC = ±5 V, VO = ±2.5 V, RL = 1 kΩ
6
5
14
10
2
V/mV
Open loop gain
TA = Full range
TA = 25°C
6
8
VIO
Input offset voltage
Input offset voltage drift
Input bias current
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
mV
mV/°C
mA
TA = Full range
2
15
2
TA = 25°C
6
8
IIB
IIO
TA = Full range
4
Input offset current
Offset current drift
VCC = ±5 V or ±15 V
VCC = ±5 V or ±15 V
25
0.3
250
nA
TA = 25°C
nA/°C
INPUT CHARACTERISTICS
VCC = ±15 V
±13
±3.8
75
±14.1
±4.3
90
Common-mode input voltage
range
VICR
V
VCC = ±5 V
VCC = ±15 V, VIC = ±12 V
VCC = ±5 V, VIC = ±2.5 V
CMRR Common-mode rejection ratio
dB
84
95
RI
CI
Input resistance
2
MΩ
Input capacitance
1.2
pF
OUTPUT CHARACTERISTICS
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V,
VCC = ±5 V,
VCC = ±15 V
VCC = ±5 V
VCC = ±15 V,
Open loop
±13
±3.4
±12
±3
±13.5
±3.7
±13
±3.4
115
75
RL = 1 kΩ
VO
Output voltage swing
V
RL = 250 Ω
RL = 150 Ω
65
IO
Output current
RL = 20 Ω
mA
40
IOS
RO
Short-circuit output current
Output resistance
TA = 25°C
150
12
mA
Ω
POWER SUPPLY
Dual supply
±4.5
9
±16.5
33
VCC
Supply voltage
V
Single supply
TA = 25°C
7.8
6.9
9.5
11
VCC = ±15 V
TA = Full range
TA = 25°C
ICC
Quiescent current
mA
dB
8.5
10
VCC = ±5 V
TA = Full range
TA = 25°C
80
78
86
83
PSRR
Power-supply rejection ratio
VCC = ±5 V to ±15 V
TA = Full range
(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.
8
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Copyright © 1999–2010, Texas Instruments Incorporated
Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
www.ti.com
SLOS216E –JUNE 1999–REVISED APRIL 2010
PARAMETER MEASUREMENT INFORMATION
1.5 kΩ
1.5 kΩ
1.5 kΩ
1.5 kΩ
_
_
+
V
O1
V
O2
V
I1
V
I2
+
CH1
CH2
150 Ω
150 Ω
50 Ω
50 Ω
Figure 3. THS4012 Crosstalk Test Circuit
TYPICAL CHARACTERISTICS
INPUT OFFSET VOLTAGE
vs
INPUT BIAS CURRENT
vs
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
14
1.4
3
T
= 25° C
A
V
= ±15 V
V
= ±15 V or±5 V
CC
CC
1.2
1
12
2.5
R
= 1 kΩ
L
10
8
2
R
= 150 Ω
L
0.8
0.6
1.5
6
1
0.4
0.2
0
4
2
0.5
0
5
7
9
11
13
15
−40 −20
0
20
40
60
80 100
−40 −20
0
20
40
60
80 100
− Free-Air Temperature − o
C
T
− Free-Air Temperature − o
C
±V − Supply Voltage − V
CC
T
A
A
Figure 4.
Figure 5.
Figure 6.
MAXIMUM OUTPUT VOLTAGE SWING
COMMON-MODE INPUT VOLTAGE
PSRR
vs
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
FREQUENCY
15
100
14
T
= 25° C
V
= ±15 V or ±5 V
A
CC
90
80
13.5
V
= ± 15 V
13
CC
RL = 1 kW
13
12.5
12
70
60
11
9
V
= ± 15 V
= 250 W
CC
R
L
50
40
4.5
4
V
= ± 5 V
= 1 kW
CC
R
7
L
30
20
3.5
5
3
V
= ± 5 V
CC
3
R
= 150 Ω
10
0
L
2.5
5
7
9
11
13
15
−40 −20
T
0
20
40
60
80 100
1k
10k
100k
1M
10M
100M
− Free-Air Temperature − o
C
f − Frequency − Hz
±V − Supply Voltage − V
CC
A
Figure 7.
Figure 8.
Figure 9.
Copyright © 1999–2010, Texas Instruments Incorporated
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Product Folder Link(s): THS4011 THS4012
THS4011
THS4012
SLOS216E –JUNE 1999–REVISED APRIL 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
CMRR
vs
CROSSTALK
vs
OPEN-LOOP GAIN RESPONSE
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
100
80
120
100
V
= ±15 V
V
= ±5 V
V
= ±15 V
CC
CC
CC
−10
−20
−30
60
40
20
0
80
60
40
V
= ±15 V
CC
V
= ±5 V
CC
−40
−50
V = CH2
I
V
= CH1
O
−60
−70
V = CH1
I
V
= CH2
O
20
0
−80
−90
−20
1k
1k
10k
100k
1M
10M
100M
100k
1M
10M
100M
1G
10K 100K 1M
10M 100M 1G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 10.
Figure 11.
Figure 12.
DISTORTION
vs
DISTORTION
vs
DISTORTION
vs
FREQUENCY
FREQUENCY
FREQUENCY
−40
−50
−40
−50
−40
−50
V
= ±15 V
V
= ±5 V
V
= ±15 V
CC
CC
CC
R
= 1 kΩ
R
= 1 kΩ
R = 150 Ω
L
L
L
G = 2
G = 2
G = 2
−60
−70
−80
−60
−70
−80
−60
−70
−80
2nd Harmonic
2nd Harmonic
2nd Harmonic
−90
−100
−110
−90
−100
−110
−90
−100
−110
3rd Harmonic
3rd Harmonic
3rd Harmonic
100k
1M
10M
100k
1M
10M
100k
1M
10M
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 13.
Figure 14.
Figure 15.
DISTORTION
vs
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
FREQUENCY
5
0
5
−40
−50
R
F
= 270 Ω
R = 270 Ω
F
V
= ±5 V
CC
R
= 150 Ω
L
G = 2
0
R
= 100 Ω
R
= 100 Ω
F
F
−60
−70
−80
−5
2nd Harmonic
−5
−10
−15
−10
−15
−90
−100
−110
3rd Harmonic
V
= ±15 V
V
= ±5 V
CC
CC
−20
−25
R
= 150 Ω
R = 150 Ω
L
L
G = 1
G = 1
−20
100k
1M
10M
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f − Frequency − Hz
f − Frequency − Hz
f − Frequency − Hz
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
NOISE SPECTRAL DENSITY
DIFFERENTIAL PHASE
vs
vs
FREQUENCY
NUMBER OF 150-Ω LOADS
0.35°
0.3°
100
Gain = 2
V
= ±15 V
CC
R
= 1 kΩ
F
40 IRE-NTSC Modulation
Worst-Case ±100 IRE Ramp
0.25°
0.2°
10
0.15°
0.1°
V
= ±5 V
CC
0.05°
V
= ±15 V or ±5 V
CC
1
0°
10
100
1k
10k
100k
1
2
3
4
f − Frequency − Hz
Number of 150-Ω Loads
Figure 20.
Figure 19.
DIFFERENTIAL PHASE
vs
DIFFERENTIAL GAIN
vs
DIFFERENTIAL GAIN
vs
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
NUMBER OF 150-Ω LOADS
0.05
0.4°
0.35°
0.3°
0.06
Gain = 2
= 1 kΩ
Gain = 2
= 1 kΩ
Gain = 2
R
R
F
F
R
F
= 1 kΩ
0.05
40 IRE-NTSC Modulation
40 IRE-PAL Modulation
40 IRE-PAL Modulation
0.04
0.03
Worst-Case ±100 IRE Ramp
Worst-Case ±100 IRE Ramp
Worst-Case ±100 IRE Ramp
0.04
0.03
0.25°
0.2°
V
= ±15 V
CC
0.02
0.01
V
= ±15 V
CC
0.15°
0.1°
V
= ±15 V
CC
0.02
0.01
V
= ±5 V
CC
V
= ±5 V
CC
0.05°
0°
V
2
= ±5 V
CC
0
0
1
3
4
1
2
3
4
1
2
3
4
Number of 150-Ω Loads
Number of 150-Ω Loads
Number of 150-Ω Loads
Figure 21.
Figure 22.
Figure 23.
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APPLICATION INFORMATION
THEORY OF OPERATION
The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using
a 30-V, dielectrically isolated, complementary bipolar process, with NPN and PNP transistors possessing fTs of
several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.
7
V
CC
+
6
OUT
2
IN−
3
IN+
4
V
CC
−
1
8
NULL
NULL
Pin numbers are for the D, DGN, and JG packages.
Figure 24. THS4011/4012 Simplified Schematic
Noise Calculations and Noise Figure (NF)
Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise
model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:
•
•
•
•
en = Amplifier internal voltage noise (nV/√Hz)
IN+ = Noninverting current noise (pA/√Hz)
IN– = Inverting current noise (pA/√Hz)
eRx = Thermal voltage noise associated with each resistor (eRx = 4 kTRx)
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e
Rs
e
n
R
S
Noiseless
+
_
e
ni
e
no
IN+
IN−
e
Rf
R
F
e
Rg
R
G
Figure 25. Noise Model
The total equivalent input noise density (eni) is calculated by using the following equation:
) ǒIN ) R Ǔ2 ) ǒIN– ǒR GǓǓ2 ) 4 kTR ) 4 kTǒR GǓ
2
Ǹ
ǒ Ǔ
e
+
e
ø R
ø R
n
s
ni
S
F
F
Where:
k = Boltzmann's constant = 1.380658 × 10-23
T = Temperature in degrees Kelvin (273 + °C)
RF || RG = Parallel resistance of RF and RG
To get the equivalent output noise density of the amplifier, multiply the equivalent input noise density (eni) by the
overall amplifier gain (AV):
R
F
+ e ǒ1 ) Ǔ(noninverting case)
e
+ e
A
no
ni
ni
V
R
G
As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the
closed-loop gain is increased (by reducing RG), the input noise is reduced considerably because of the parallel
resistance term. This leads to the general conclusion that the most dominant noise sources are the source
resistor (RS) and the internal amplifier noise voltage (en). Because noise is summed in a root-mean-squares
method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly
simplify the formula and make noise calculations much easier to calculate.
For more information on noise analysis, refer to the Noise Analysis section in the Operational Amplifier Circuits
Applications Report (SLVA043).
This brings up another noise measurement usually preferred in RF applications — the noise figure (NF). NF is a
measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is
typically 50 Ω in RF applications.
ȱ
ȳ
2
e
ni
NF + 10logȧ
ȧ
ȧ
ȧ
ǒe Ǔ2
Rs
Because the dominant noise components are generally the source resistance and the internal amplifier noise
voltage, approximate NF as:
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2
2
ȱ
ȳ
ȣ
ȡ
) ǒIN ) R
Ǔ
ǒe Ǔ
ȧ
ȧ
S
n
ȧ
ȧ
ȧ
Ȣ
Ȥ
ȧ
NF + 10log 1 )
ȧ
ȧ
ȧ
ȧ
4 kTR
S
ȧ
ȧ
Figure 26 shows the NF graph for the THS401x.
NOISE FIGURE
vs
SOURCE RESISTANCE
30
f = 10 kHz
= 25°C
T
A
25
20
15
10
5
0
10
100
1 k
10 k
100 k
Source Resistance − Ω
Figure 26. Noise Figure vs Source Resistance
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high performance amplifiers is not a problem, as long as certain precautions are
taken. The first precaution is to note that the THS401x has been internally compensated to maximize its
bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading
directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations.
Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with
the output of the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most
applications. For example, in 75-Ω transmission systems, setting the series-resistor value to 75 Ω both isolates
any capacitance loading and provides the proper line-impedance matching at the source end.
1.3 kΩ
1.3 kΩ
_
Input
20 Ω
Output
THS401x
+
C
LOAD
Figure 27. Driving a Capacitive Load
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OFFSET NULLING
The THS401x has low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided on the THS4011/4012. The input offset can be adjusted by
placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply (see
Figure 28).
V
CC
+
0.1 µF
+
THS4011/4012
_
10 kΩ
0.1 µF
V
CC
−
Figure 28. Offset Nulling Schematic
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OFFSET VOLTAGE
The output offset voltage (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 29. Output Offset Voltage Model
OPTIMIZING UNITY GAIN RESPONSE
Internal frequency compensation of the THS401x was selected to provide very wideband performance, yet
maintain stability when operating in a noninverting unity gain configuration. When amplifiers are compensated in
this manner, there is usually peaking in the closed-loop response and some ringing in the step response for fast
input edges, depending on the application. This is because a minimum phase margin is maintained for the
G = +1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should be
used (see Figure 30). Additional capacitance can also be used in parallel with the feedback resistance if even
finer optimization is required.
Input
+
Output
THS401x
_
100 Ω
Figure 30. Noninverting Unity Gain Schematic
GENERAL CONFIGURATIONS
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.
The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see
Figure 31).
Figure 31. Single-Pole Low-Pass Filter
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If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
2 RC
R1
R2
f
–3dB
C2
R
F
R
G
=
1
R
F
2 −
)
(
R
Q
G
Figure 32. 2-Pole Low-Pass Sallen-Key Filter
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the high-frequency performance levels of the THS401x, follow proper printed circuit board (PCB)
high-frequency design techniques. A general set of guidelines is given in the following paragraphs. In addition, a
THS401x evaluation board is available to use as a guide for layout or for evaluating the device performance.
•
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power-supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 in between the device power terminals and the ceramic capacitors.
•
•
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to
the PCB are the best implementation.
Short trace runs/compact part placements – Optimum high-frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the
input of the amplifier.
•
Surface-mount passive components – Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
GENERAL PowerPAD™ DESIGN CONSIDERATIONS
The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from
the thermal pad.
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The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat-dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
NOTE: The thermal pad is electrically isolated from all terminals in the package.
Figure 33. Thermally-Enhanced DGN Package Views
Although there are many ways to properly heatsink this device, the following steps show the recommended
approach:
1. Prepare the PCB with a top-side etch pattern as shown in Figure 34. There should be etch for the leads, as
well as etch for the thermal pad.
2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal-pad area. This helps
dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mils
diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad
area to be soldered so that wicking is not a problem.
4. Connect all holes to the internal ground plane.
5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the THS401xDGN package should make their connection to the internal ground plane with a
complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five
holes exposed. The bottom-side solder mask should cover the five holes of the thermal-pad area. This
prevents solder from pulling away from the thermal-pad area during the reflow process.
7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.
8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through the
solder reflow operation as any standard surface-mount component. This results in a part that is properly
installed.
Thermal-pad area (68 mils x 70 mils) with 5 vias
(via diameter = 13 mils)
Figure 34. PowerPAD™ PCB Etch and Via Pattern
The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the
application. In the previous example, if the size of the internal ground plane is approximately 3 in × 3 in, the
expected thermal coefficient, qJA, is approximately 58.4°C/W. For comparison, the non-PowerPAD version of the
THS401x IC (SOIC) is shown. For a given qJA, the maximum power dissipation is shown in Figure 35 and is
calculated by the following formula:
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T
* T
MAX
A
P
+
ǒ Ǔ
D
q
JA
Where:
PD = Maximum power dissipation of THS401x IC (watts)
TMAX = Absolute maximum junction temperature (150°C)
TA = Free-ambient air temperature (°C)
qJA = qJC + qCA
qJC = Thermal coefficient from junction to case
qCA = Thermal coefficient from case to ambient air (°C/W)
3.5
DGN Package
T
J
= 150°C
θ
JA
= 58.4°C/W
2-oz Trace and Copper Pad
With Solder
3
2.5
2
DGN Package
= 158°C/W
θ
JA
SOIC Package
2-oz Trace and
Copper Pad
High-K Test PCB
θ
JA
= 98°C/W
Without Solder
1.5
1
SOIC Package
0.5
0
Low-K Test PCB
θ
JA
= 167°C/W
−40
−20
0
20
40
60
80
100
T
A
− Free-Air Temperature − °C
A. Results are with no airflow and PCB size = 3 in × 3 in
Figure 35. Maximum Power Dissipation vs Free-Air Temperature
More complete details of the PowerPAD installation process and thermal-management techniques can be found
in the TI technical brief, PowerPAD™ Thermally-Enhanced Package. This document can be found at the TI web
site (www.ti.com) by searching on the keyword PowerPAD. The document can also be ordered through your
local TI sales office. Refer to literature number SLMA002 when ordering.
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multiple amplifier devices. Because these devices have linear output stages (Class A-B), most of the
heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect, along
with the quiescent heat, with an ambient air temperature of 50°C. When using VCC = ±5 V, there is generally not
a heat problem, even with SOIC packages. But, when using VCC = ±15 V, the SOIC package is severely limited
in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are
mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should
always be soldered to a copper plane to fully use the heat-dissipation properties of the PowerPAD package. The
SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and
copper area is placed around the device, qJA decreases and the heat dissipation capability increases. The
currents and voltages shown in these graphs are for the total package. For the dual amplifier package
(THS4012), the sum of the RMS output currents and voltages should be used to choose the proper package.
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THS4011
THS4011
MAXIMUM RMS OUTPUT CURRENT
MAXIMUM RMS OUTPUT CURRENT
vs
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
1000
Maximum Output
Current Limit Line
T
T
= 150°C
= 50°C
V
T
T
A
= ±5 V
= 150°C
= 50°C
V
CC
= ±15 V
J
CC
A
j
180
160
140
120
100
Maximum Output
Current Limit Line
DGN Package
θ
JA
= 58.4°C/W
Package With
θ
JA
< = 120°C/W
100
SO-8 Package
= 167°C/W
80
60
40
θ
JA
SO-8 Package
= 98°C/W
Low-K Test PCB
θ
JA
High-K Test PCB
SO-8 Package
= 167°C/W
Safe Operating
Area
θ
JA
Safe Operating
Area
20
0
Low-K Test PCB
10
0
1
2
3
4
5
0
3
6
9
12
15
|V | − RMS Output Voltage − V
O
|V | − RMS Output Voltage − V
O
Figure 36.
Figure 37.
THS4012
THS4012
MAXIMUM RMS OUTPUT CURRENT
vs
MAXIMUM RMS OUTPUT CURRENT
vs
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS
200
1000
Maximum Output
Current Limit Line
Package With
V
T
T
A
= ±15 V
= 150°C
= 50°C
Maximum Output
Current Limit Line
CC
θ
JA
≤ 60°C/W
180
160
140
120
100
J
Both Channels
100
SO-8 Package
= 167°C/W
SO-8 Package
= 98°C/W
θ
JA
80
60
40
10
θ
JA
Low-K Test PCB
Safe Operating Area
High-K Test PCB
DGN Package
= 58.4°C/W
V
CC
= ±5 V
SO-8 Package
SO-8 Package
θ
JA
T
= 150°C
J
θ
JA
= 98°C/W
θ
JA
= 167°C/W
20
0
T = 50°C
A
Both Channels
High-K Test PCB
Low-K Test PCB
Safe Operating Area
1
0
1
2
3
4
5
0
3
6
9
12
15
|V | − RMS Output Voltage − V
O
|V | − RMS Output Voltage − V
O
Figure 38.
Figure 39.
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EVALUATION BOARD
An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number
SLOP230). This board has been configured for low parasitic capacitance in order to realize the full performance
of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. For more
information, refer to the THS4011 EVM User's Guide (literature number SLOU028) or the THS4012 EVM User's
Guide (literature number SLOU041) To order the evaluation board, contact your local TI sales office or
distributor.
V +
CC
+
C1
6.8 mF
C2
0.1 mF
R1
1 kΩ
NULL
R2
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4011
NULL
R5
1 kΩ
C3
6.8 mF
+
C4
0.1 mF
IN−
V
CC
−
R4
49.9 Ω
Figure 40. THS4011 Evaluation Board
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REVISION HISTORY
Changes from Original (June 1999) to Revision A
Page
•
•
•
•
•
•
•
•
Changed Feature List item From: 0.006% Differential Gain Error To: 0.01% Differential Gain Error .................................. 1
Replaced the HIGH SPEED FAMILY of DEVICES table with the RELATED DEVICES table ............................................. 1
Changed the Available Options table, THS4012ID MSOP Symbol From: TAIBG To: TIABZ .............................................. 2
Changed the ELECTRICAL CHARACTERISTIC table ......................................................................................................... 5
Changed the TYPICAL CHARACTERISTICS section .......................................................................................................... 9
Changed Figure 26, Noise Figure vs Source Resistance ................................................................................................... 14
Changed Figure 36 through Figure 39 ............................................................................................................................... 20
Changed Figure 40, THS4011 Evaluation Board ............................................................................................................... 21
Changes from Revision A (February 2000) to Revision B
Page
•
•
•
Changed Feature List item From: 0.01% Differential Gain Error To: 0.006% Differential Gain Error .................................. 1
Added THS4011M to the Abs Max table .............................................................................................................................. 4
Added the ELECTRICAL CHARACTERISTICS for device number THS4011M .................................................................. 7
Changes from Revision B (February 2000) to Revision C
Page
•
Changed Figure 24, THS4011/4012 Simplified Schematic ................................................................................................ 12
Changes from Revision C (May 2006) to Revision D
Page
•
Changed Figure 29 - Output Offset Voltage Model docato-extra-info-title Output Offset Voltage Model ........................... 16
Changes from Revision D (June 2007) to Revision E
Page
•
•
Deleted Lead temperature and Case temperature from the Abs Max table ......................................................................... 4
Changed Figure 5 label - From: Input Bias Current - A To: Input Bias Current - µA ........................................................... 9
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PACKAGE OPTION ADDENDUM
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24-Jan-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
5962-9959301Q2A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
-55 to 125 5962-
9959301Q2A
THS4011MFKB
5962-9959301QPA
THS4011CD
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
SOIC
SOIC
JG
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
20
1
75
TBD
Call TI
Call TI
-55 to 125 9959301QPA
THS4011M
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
4011C
THS4011CDG4
THS4011CDGN
THS4011CDGNG4
THS4011CDGNR
THS4011CDGNRG4
THS4011CDR
D
75
Green (RoHS
& no Sb/Br)
4011C
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
ACI
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
ACI
MSOP-
PowerPAD
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
ACI
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ACI
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
4011C
THS4011CDRG4
THS4011ID
D
Green (RoHS
& no Sb/Br)
4011C
D
Green (RoHS
& no Sb/Br)
4011I
THS4011IDG4
D
75
Green (RoHS
& no Sb/Br)
4011I
THS4011IDGN
THS4011IDGNG4
THS4011IDGNR
THS4011IDGNRG4
THS4011MFKB
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
FK
80
Green (RoHS
& no Sb/Br)
ACJ
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
ACJ
ACJ
MSOP-
PowerPAD
2500
2500
1
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ACJ
LCCC
TBD
-55 to 125 5962-
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
Orderable Device
Status Package Type Package Pins Package Qty
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
(1)
(2)
(3)
(4)
9959301Q2A
THS4011MFKB
THS4011MJG
ACTIVE
ACTIVE
CDIP
CDIP
JG
JG
8
8
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125 THS4011MJG
THS4011MJGB
-55 to 125 9959301QPA
THS4011M
THS4012CD
THS4012CDG4
THS4012CDGN
THS4012CDGNG4
THS4012CDGNR
THS4012CDGNRG4
THS4012CDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
4012C
4012C
ABY
D
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
ABY
MSOP-
PowerPAD
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
ABY
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ABY
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
4012C
4012C
4012I
4012I
ABZ
THS4012CDRG4
THS4012ID
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
THS4012IDG4
D
75
Green (RoHS
& no Sb/Br)
THS4012IDGN
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
80
Green (RoHS
& no Sb/Br)
THS4012IDGNG4
THS4012IDGNR
THS4012IDGNRG4
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
ABZ
MSOP-
PowerPAD
2500
2500
Green (RoHS
& no Sb/Br)
ABZ
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ABZ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Jan-2013
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4011, THS4011M :
Catalog: THS4011
•
Military: THS4011M
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4011CDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4011CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
THS4011IDGNR
MSOP-
Power
PAD
DGN
THS4012CDGNR
MSOP-
Power
PAD
DGN
8
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
THS4012CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
THS4012IDGNR
MSOP-
Power
PAD
DGN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4011CDGNR
THS4011CDR
MSOP-PowerPAD
SOIC
DGN
D
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
358.0
367.0
358.0
358.0
367.0
358.0
335.0
367.0
335.0
335.0
367.0
335.0
35.0
35.0
35.0
35.0
35.0
35.0
THS4011IDGNR
THS4012CDGNR
THS4012CDR
MSOP-PowerPAD
MSOP-PowerPAD
SOIC
DGN
DGN
D
THS4012IDGNR
MSOP-PowerPAD
DGN
Pack Materials-Page 2
MECHANICAL DATA
MCER001A – JANUARY 1995 – REVISED JANUARY 1997
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE
0.400 (10,16)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.063 (1,60)
0.015 (0,38)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.023 (0,58)
0.015 (0,38)
0°–15°
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification.
E. Falls within MIL STD 1835 GDIP1-T8
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