THS4012CDGNG4 [TI]

290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS; 290 - MHz的低失真高速放大器


型号：	THS4012CDGNG4
厂家：	TEXAS INSTRUMENTS
描述：	290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS 290 - MHz的低失真高速放大器放大器
文件：	总35页 (文件大小：1171K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS4011

THS4012

www.ti.com

SLOS216E –JUNE 1999–REVISED APRIL 2010

290-MHz LOW-DISTORTION HIGH-SPEED AMPLIFIERS

Check for Samples: THS4011, THS4012

FEATURES

THS4011

D, DGN, OR JG PACKAGE

(TOP VIEW)

THS4012

†

D OR DGN PACKAGE

(TOP VIEW)

•

High Speed

–

290-MHz Bandwidth (G = 1, –3 dB)

310-V/ms Slew Rate

1OUT

1IN−

1IN+

−V_CC

V_CC+

2OUT

2IN−

2IN+

NULL

IN−

NULL

V_CC+

OUT

37-ns Settling Time (0.1%)

IN+

•

Low Distortion

THD = –80 dBc (f = 1 MHz, R_L= 150 Ω)

V_CC−

–

•

110-mA Output Current Drive (Typical)

7.5-nV/√Hz Voltage Noise

NC − No internal connection

Excellent Video Performance

Cross-section view showing

PowerPAD option (DGN)

–

70-MHz Bandwidth (0.1 dB, G = 1)

0.006% Differential Gain Error

0.01° Differential Phase Error

†

This package is in the Product Preview stage of

development. Please contact your local TI sales of fice for

availability.

THS4011

•

±5-V to ±15-V Supply Voltage

Available in Standard SOIC, MSOP

PowerPAD™, JG, or FK Packages

FK PACKAGE

(TOP VIEW)

•

Evaluation Module Available

DESCRIPTION

20 19

The THS4011 and THS4012 are high-speed,

single/dual, voltage feedback amplifiers ideal for a

wide range of applications. The devices offer good ac

performance, with 290-MHz bandwidth, 310-V/ms

slew rate, and 37-ns settling time (0.1%). These

amplifiers have a high output drive capability of 110

mA and draw only 7.8-mA supply current per

channel. For applications requiring low distortion, the

IN−

IN+

V_CC+

OUT

10 11 12 13

THS4011/4012 operate with

total harmonic

distortion (THD) of -80 dBc at f = 1 MHz. For video

applications, the THS4011/4012 offer 0.1-dB gain

flatness to 70 MHz, 0.006% differential gain error,

and 0.01° differential phase error.

RELATED DEVICES

DESCRIPTION

DEVICE

THS4011/4012

THS4031/4032

THS4061/4062

290-MHz low-distortion high-speed amplifiers

100-MHz low-noise high-speed-amplifiers

180-MHz high-speed amplifiers

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

THS4011

THS4012

SLOS216E –JUNE 1999–REVISED APRIL 2010

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

DISTORTION

FREQUENCY

−40

= ±15 V

= 150 Ω

−50

G = 2

−60

−70

−80

2nd Harmonic

−90

−100

−110

3rd Harmonic

100k

10M

f − Frequency − Hz

AVAILABLE OPTIONS

PACKAGED DEVICES⁽¹⁾

PLASTIC SMALL PLASTIC MSOP⁽²⁾

PACKAGED DEVICES

NUMBER OF

CHANNELS

MSOP

SYMBOL

EVALUATION

MODULE

T_A

CERAMIC DIP

(JG)

CHIP CARRIER

(FK)

OUTLINE⁽²⁾(D)

THS4011CD

THS4012CD

THS4011ID

(DGN)

THS4011CDGN

THS4012CDGN⁽³⁾

THS4011DGN

THS4012IDGN⁽³⁾

TIACI

TIABY

TIACJ

TIABZ

—

THS4011EVM

0°C to

70°C

THS4012EVM

—

–40°C to

85°C

THS4012ID

–55°C to

125°C

—

THS4011MJG

THS4011MFK

—

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2) The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4011CDGNR).

(3) This device is in the Product Preview stage of development. Please contact your local TI sales office for availability.

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SLOS216E –JUNE 1999–REVISED APRIL 2010

FUNCTIONAL BLOCK DIAGRAM

Null

IN−

−

OUT

IN+

Figure 1. THS4011 – Single Channel

1IN−

1IN+

−

1OUT

2IN−

2IN+

−

2OUT

−V

Figure 2. THS4012 – Dual Channel

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SLOS216E –JUNE 1999–REVISED APRIL 2010

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

V_CC

V_I

Supply voltage

±16.5

Input voltage

±V_CC

I_O

Output current

175

V_ID

Differential input voltage

Continuous total power dissipation

Maximum junction temperature

±4

See Dissipation Rating Table

150

T_J

°C

THS401xC

0 to 70

T_A

Operation free-air temperature range THS401xI

THS4011M

–40 to 85

–55 to 125

T_stg

Storage temperature range

–65 to 150

DISSIPATION RATINGS

q_JA

(°C/W)

q_JC

(°C/W)

T_A= 25°C

POWER RATING

PACKAGE

DGN⁽²⁾

167⁽¹⁾

58.4

119

38.3

4.7

740 mW

2.14 W

1050 mW

1375 mW

87.7

(1) This data was taken using the JEDEC standard Low-K test PCB. For the JEDEC-proposed High-K test

PCB, the q_JAis 95°C/W with a power rating at 1.32 W at T_A= 25°C.

(2) This data was taken using 2-oz trace and copper pad that is soldered directly to a 3-in × 3-in PC. For

further information, refer to the Application Information section of this data sheet.

RECOMMENDED OPERATING CONDITIONS

MIN

±4.5

MAX UNIT

Split supply

±16

V_CC

Supply voltage

Single supply

C suffix

T_A

Operating free-air temperature

I suffix

–40

–55

°C

M suffix

125

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SLOS216E –JUNE 1999–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS

V_CC= ±15 V, R_L= 150 Ω, T_A= 25°C (unless otherwise noted)

THS4011C/I

THS4012C/I

PARAMETER

TEST CONDITIONS⁽¹⁾

UNIT

TYP

DYNAMIC PERFORMANCE

V_CC= ±15 V

290

270

Unity-gain bandwidth (–3 dB)

Gain = 1

MHz

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

V_O(PP)= 20 V

V_O(PP)= 5 V

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

Bandwidth for 0.1-dB flatness

Full-power bandwidth⁽²⁾

Slew rate

V_CC= ±15 V, R_L= 150 Ω

V_CC= ±5 V, R_L= 150 Ω

4.9

MHz

310

260

t_s

Gain = –1, R_L= 150 Ω

V/ms

Settling time to 0.1%

Settling time to 0.01%

V_I= –2.5 V to 2.5 V, Gain = –12

NOISE/DISTORTION PERFORMANCE

THD Total harmonic distortion

V_CC= ±15 V, f_c= 1 MHz,

V_CC= ±5 V or ±15 V,

V_O(PP)= 2 V

f = 10 kHz

–80

7.5

dBc

V_n

I_n

Input voltage noise

Input current noise

nV/√Hz

pA/√Hz

f = 10 kHz

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

0.01%

0.01°

0.001°

Differential gain error

Differential phase error

. Gain = 2, R_L= 150 Ω, NTSC

(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.

(2) Full-power bandwidth = Slew rate/2p V_O(peak)

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ELECTRICAL CHARACTERISTICS (Continued)

V_CC= ±15 V, R_L= 150 Ω, T_A= 25°C (unless otherwise noted)

THS4011C/I

THS4012C/I

PARAMETER

DC PERFORMANCE

TEST CONDITIONS⁽¹⁾

UNIT

MIN

TYP

MAX

T_A= 25°C

V_CC= ±15 V, V_O= ±10 V, R_L= 1 kΩ

V_CC= ±5 V, V_O= ±2.5 V, R_L= 250 Ω

V_CC= ±5 V or ±15 V

T_A= Full range

T_A= 25°C

Open loop gain

V/mV

T_A= Full range

T_A= 25°C

V_IO

Input offset voltage

Input offset voltage drift

Input bias current

mV/°C

T_A= Full range

T_A= 25°C

I_IB

V_CC= ±5 V or ±15 V

T_A= Full range

T_A= 25°C

250

400

I_IO

Input offset current

Offset current drift

V_CC= ±5 V or ±15 V

T_A= Full range

0.3

nA/°C

INPUT CHARACTERISTICS

V_CC= ±15 V

V_CC= ±5 V

±13

±3.8

±14.1

±4.3

110

Common-mode input voltage

range

V_ICR

T_A= 25°C

V_CC= ±15 V, V_IC= ±12 V

V_CC= ±5 V, V_IC= ±2.5 V

T_A= Full range

T_A= 25°C

CMRR Common-mode rejection ratio

T_A= Full range

R_I

C_I

Input resistance

MΩ

Input capacitance

1.2

OUTPUT CHARACTERISTICS

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V,

V_CC= ±5 V,

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

Open loop

±13

±3.4

±12

±3

±13.5

±3.7

±13

±3.4

110

R_L= 1 kΩ

V_O

Output voltage swing

R_L= 250 Ω

R_L= 150 Ω

I_O

Output current

R_L= 20 Ω

I_OS

R_O

Short-circuit output current

Output resistance

150

Ω

POWER SUPPLY

Dual supply

±4.5

±16.5

V_CC

Supply voltage

Single supply

T_A= 25°C

7.8

6.9

9.5

V_CC= ±15 V

T_A= Full range

T_A= 25°C

I_CC

Supply current (each amplifier)

Power-supply rejection ratio

8.5

V_CC= ±5 V

T_A= Full range

T_A= 25°C

PSRR

V_CC= ±5 V to ±15 V

T_A= Full range

(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.

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SLOS216E –JUNE 1999–REVISED APRIL 2010

ELECTRICAL CHARACTERISTICS (Continued)

V_CC= ±15 V, R_L= 150 Ω, T_A= 25°C (unless otherwise noted)

THS4011M

UNIT

PARAMETER

TEST CONDITIONS⁽¹⁾

MIN

TYP

MAX

DYNAMIC PERFORMANCE

Unit-gain bandwidth

Closed loop, R_L= 1 kΩ,

V_CC= ±15 V

V_CC= ±5 V

160⁽²⁾

200

2.5

Bandwidth for 0.1-dB flatness Gain = 1

MHz

V_CC= ±2.5 V

V_O(PP)= 20 V

V_CC= ±15 V, R_L= 150 Ω,

V_CC= ±5 V, R_L= 150 Ω,

V_CC= ±15 V, R_L= 1 kΩ

Full-power bandwidth⁽³⁾

Slew rate

t_s

300⁽²⁾

400

V/ms

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

Settling time to 0.1%

V_I= –2.5 to 2.5 V, Gain = –1

Settling time to 0.01%

NOISE/DISTORTION PERFORMANCE

THD

V_n

Total harmonic distortion

Input voltage noise

Input current noise

V_CC= ±15 V, f_c= 1 MHz, V_O(PP)= 1 V

V_CC= ±5 V or ±15 V,

–80

7.5

dBc

f = 10 kHz

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V

V_CC= ±5 V

nV/√Hz

pA/√Hz

I_n

V_CC= ±5 V or ±15 V,

0.006%

0.001%

0.01°

0.002°

Differential gain error

Differential phase error

Gain = 2, R_L= 150 Ω, NTSC

(1) Full range = –55°C to 125°C for the M suffix

(2) This parameter is not tested.

(3) Full-power bandwidth = Slew rate/2p V_O(peak)

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ELECTRICAL CHARACTERISTICS (Continued)

V_CC= ±15 V, R_L= 1 kΩ, T_A= full range (unless otherwise noted)

THS4011M

TYP

PARAMETER

DC PERFORMANCE

TEST CONDITIONS⁽¹⁾

UNIT

MIN

MAX

V_CC= ±15 V, V_O= ±10 V, R_L= 1 kΩ

V_CC= ±5 V, V_O= ±2.5 V, R_L= 1 kΩ

V/mV

Open loop gain

T_A= Full range

T_A= 25°C

V_IO

Input offset voltage

Input offset voltage drift

Input bias current

V_CC= ±5 V or ±15 V

mV/°C

T_A= Full range

T_A= 25°C

I_IB

I_IO

T_A= Full range

Input offset current

Offset current drift

V_CC= ±5 V or ±15 V

0.3

250

T_A= 25°C

nA/°C

INPUT CHARACTERISTICS

V_CC= ±15 V

±13

±3.8

±14.1

±4.3

Common-mode input voltage

range

V_ICR

V_CC= ±5 V

V_CC= ±15 V, V_IC= ±12 V

V_CC= ±5 V, V_IC= ±2.5 V

CMRR Common-mode rejection ratio

R_I

C_I

Input resistance

MΩ

Input capacitance

1.2

OUTPUT CHARACTERISTICS

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V,

V_CC= ±5 V,

V_CC= ±15 V

V_CC= ±5 V

V_CC= ±15 V,

Open loop

±13

±3.4

±12

±3

±13.5

±3.7

±13

±3.4

115

R_L= 1 kΩ

V_O

Output voltage swing

R_L= 250 Ω

R_L= 150 Ω

I_O

Output current

R_L= 20 Ω

I_OS

R_O

Short-circuit output current

Output resistance

T_A= 25°C

150

Ω

POWER SUPPLY

Dual supply

±4.5

±16.5

V_CC

Supply voltage

Single supply

T_A= 25°C

7.8

6.9

9.5

V_CC= ±15 V

T_A= Full range

T_A= 25°C

I_CC

Quiescent current

8.5

V_CC= ±5 V

T_A= Full range

T_A= 25°C

PSRR

Power-supply rejection ratio

V_CC= ±5 V to ±15 V

T_A= Full range

(1) Full range = 0°C to 70°C for the C suffix and –40°C to 85°C for the I suffix.

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SLOS216E –JUNE 1999–REVISED APRIL 2010

PARAMETER MEASUREMENT INFORMATION

1.5 kΩ

CH1

CH2

150 Ω

50 Ω

Figure 3. THS4012 Crosstalk Test Circuit

TYPICAL CHARACTERISTICS

INPUT OFFSET VOLTAGE

INPUT BIAS CURRENT

OUTPUT VOLTAGE

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

1.4

= 25° C

= ±15 V

= ±15 V or±5 V

1.2

2.5

= 1 kΩ

= 150 Ω

0.8

0.6

1.5

0.4

0.2

0.5

−40 −20

80 100

−40 −20

80 100

− Free-Air Temperature − ^o

±V − Supply Voltage − V

Figure 4.

Figure 5.

Figure 6.

MAXIMUM OUTPUT VOLTAGE SWING

COMMON-MODE INPUT VOLTAGE

PSRR

FREE-AIR TEMPERATURE

SUPPLY VOLTAGE

FREQUENCY

100

= 25° C

= ±15 V or ±5 V

13.5

= ± 15 V

RL = 1 kW

12.5

= ± 15 V

= 250 W

4.5

= ± 5 V

= 1 kW

3.5

= ± 5 V

= 150 Ω

2.5

−40 −20

80 100

10k

100k

10M

100M

− Free-Air Temperature − ^o

f − Frequency − Hz

±V − Supply Voltage − V

Figure 7.

Figure 8.

Figure 9.

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TYPICAL CHARACTERISTICS (continued)

CMRR

CROSSTALK

OPEN-LOOP GAIN RESPONSE

FREQUENCY

100

120

100

= ±15 V

= ±5 V

= ±15 V

−10

−20

−30

= ±15 V

= ±5 V

−40

−50

V = CH2

= CH1

−60

−70

V = CH1

= CH2

−80

−90

−20

10k

100k

10M

100M

100k

10M

100M

10K 100K 1M

10M 100M 1G

f − Frequency − Hz

Figure 10.

Figure 11.

Figure 12.

DISTORTION

FREQUENCY

−40

−50

−40

−50

−40

−50

= ±15 V

= ±5 V

= ±15 V

= 1 kΩ

R = 150 Ω

G = 2

−60

−70

−80

−60

−70

−80

−60

−70

−80

2nd Harmonic

−90

−100

−110

−90

−100

−110

−90

−100

−110

3rd Harmonic

100k

10M

100k

10M

100k

10M

f − Frequency − Hz

Figure 13.

Figure 14.

Figure 15.

DISTORTION

OUTPUT AMPLITUDE

FREQUENCY

−40

−50

= 270 Ω

R = 270 Ω

= ±5 V

= 150 Ω

G = 2

= 100 Ω

−60

−70

−80

−5

2nd Harmonic

−5

−10

−15

−10

−15

−90

−100

−110

3rd Harmonic

= ±15 V

= ±5 V

−20

−25

= 150 Ω

R = 150 Ω

G = 1

−20

100k

10M

100k

10M

100M

100k

10M

100M

f − Frequency − Hz

Figure 16.

Figure 17.

Figure 18.

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TYPICAL CHARACTERISTICS (continued)

NOISE SPECTRAL DENSITY

DIFFERENTIAL PHASE

FREQUENCY

NUMBER OF 150-Ω LOADS

0.35°

0.3°

100

Gain = 2

= ±15 V

= 1 kΩ

40 IRE-NTSC Modulation

Worst-Case ±100 IRE Ramp

0.25°

0.2°

0.15°

0.1°

= ±5 V

0.05°

= ±15 V or ±5 V

0°

100

10k

100k

f − Frequency − Hz

Number of 150-Ω Loads

Figure 20.

Figure 19.

DIFFERENTIAL PHASE

DIFFERENTIAL GAIN

NUMBER OF 150-Ω LOADS

0.05

0.4°

0.35°

0.3°

0.06

Gain = 2

= 1 kΩ

Gain = 2

= 1 kΩ

Gain = 2

= 1 kΩ

0.05

40 IRE-NTSC Modulation

40 IRE-PAL Modulation

0.04

0.03

Worst-Case ±100 IRE Ramp

0.04

0.03

0.25°

0.2°

= ±15 V

0.02

0.01

= ±15 V

0.15°

0.1°

= ±15 V

0.02

0.01

= ±5 V

0.05°

0°

= ±5 V

Number of 150-Ω Loads

Figure 21.

Figure 22.

Figure 23.

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APPLICATION INFORMATION

THEORY OF OPERATION

The THS401x is a high-speed, operational amplifier configured in a voltage feedback architecture. It is built using

a 30-V, dielectrically isolated, complementary bipolar process, with NPN and PNP transistors possessing f_Ts of

several GHz. This results in an exceptionally high-performance amplifier that has a wide bandwidth, high slew

rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 24.

OUT

IN−

IN+

−

NULL

Pin numbers are for the D, DGN, and JG packages.

Figure 24. THS4011/4012 Simplified Schematic

Noise Calculations and Noise Figure (NF)

Noise can cause errors on very small signals. This is especially true when amplifying small signals. The noise

model for the THS401x is shown in Figure 25. This model includes all of the noise sources as follows:

•

e_n= Amplifier internal voltage noise (nV/√Hz)

IN+ = Noninverting current noise (pA/√Hz)

IN– = Inverting current noise (pA/√Hz)

e_Rx= Thermal voltage noise associated with each resistor (e_Rx= 4 kTR_x)

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Noiseless

IN+

IN−

Figure 25. Noise Model

The total equivalent input noise density (e_ni) is calculated by using the following equation:

₎ǒ_{IN ) R}Ǔ²₎ǒ_IN–ǒ_{R G}ǓǓ²_{) 4 kTR ) 4 kT}ǒ_{R G}Ǔ

ǒ Ǔ

ø R

Where:

k = Boltzmann's constant = 1.380658 × 10^-23

T = Temperature in degrees Kelvin (273 + °C)

R_F|| R_G= Parallel resistance of R_Fand R_G

To get the equivalent output noise density of the amplifier, multiply the equivalent input noise density (e_ni) by the

overall amplifier gain (A_V):

_{+ e}ǒ_{1 )}Ǔ_{(noninverting case)}

+ e

As the previous equations show, to keep noise at a minimum, small-value resistors should be used. As the

closed-loop gain is increased (by reducing R_G), the input noise is reduced considerably because of the parallel

resistance term. This leads to the general conclusion that the most dominant noise sources are the source

resistor (R_S) and the internal amplifier noise voltage (e_n). Because noise is summed in a root-mean-squares

method, noise sources smaller than 25% of the largest noise source can be effectively ignored. This can greatly

simplify the formula and make noise calculations much easier to calculate.

For more information on noise analysis, refer to the Noise Analysis section in the Operational Amplifier Circuits

Applications Report (SLVA043).

This brings up another noise measurement usually preferred in RF applications — the noise figure (NF). NF is a

measure of noise degradation caused by the amplifier. The value of the source resistance must be defined and is

typically 50 Ω in RF applications.

_{NF + 10log}ȧ

ǒ_eǓ²

Because the dominant noise components are generally the source resistance and the internal amplifier noise

voltage, approximate NF as:

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₎ǒ_{IN ) R}

ǒ_eǓ

NF + 10log 1 )

4 kTR

Figure 26 shows the NF graph for the THS401x.

NOISE FIGURE

SOURCE RESISTANCE

f = 10 kHz

= 25°C

100

1 k

10 k

100 k

Source Resistance − Ω

Figure 26. Noise Figure vs Source Resistance

DRIVING A CAPACITIVE LOAD

Driving capacitive loads with high performance amplifiers is not a problem, as long as certain precautions are

taken. The first precaution is to note that the THS401x has been internally compensated to maximize its

bandwidth and slew-rate performance. When the amplifier is compensated in this manner, capacitive loading

directly on the output decreases the device phase margin leading to high-frequency ringing or oscillations.

Therefore, for capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with

the output of the amplifier, as shown in Figure 27. A minimum value of 20 Ω should work well for most

applications. For example, in 75-Ω transmission systems, setting the series-resistor value to 75 Ω both isolates

any capacitance loading and provides the proper line-impedance matching at the source end.

1.3 kΩ

Input

20 Ω

Output

THS401x

LOAD

Figure 27. Driving a Capacitive Load

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OFFSET NULLING

The THS401x has low input offset voltage for a high-speed amplifier. However, if additional correction is

required, an offset nulling function has been provided on the THS4011/4012. The input offset can be adjusted by

placing a potentiometer between terminals 1 and 8 of the device and tying the wiper to the negative supply (see

Figure 28).

0.1 µF

THS4011/4012

10 kΩ

0.1 µF

−

Figure 28. Offset Nulling Schematic

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OFFSET VOLTAGE

The output offset voltage (V_OO) is the sum of the input offset voltage (V_IO) and both input bias currents (I_IB) times

the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:

Figure 29. Output Offset Voltage Model

OPTIMIZING UNITY GAIN RESPONSE

Internal frequency compensation of the THS401x was selected to provide very wideband performance, yet

maintain stability when operating in a noninverting unity gain configuration. When amplifiers are compensated in

this manner, there is usually peaking in the closed-loop response and some ringing in the step response for fast

input edges, depending on the application. This is because a minimum phase margin is maintained for the

G = +1 configuration. For optimum settling time and minimum ringing, a feedback resistor of 100 Ω should be

used (see Figure 30). Additional capacitance can also be used in parallel with the feedback resistance if even

finer optimization is required.

Input

Output

THS401x

100 Ω

Figure 30. Noninverting Unity Gain Schematic

GENERAL CONFIGURATIONS

When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often required.

The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier (see

Figure 31).

Figure 31. Single-Pole Low-Pass Filter

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If even more attenuation is needed, a multiple-pole filter is required. The Sallen-Key filter can be used for this

task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.

Failure to do this can result in phase shift of the amplifier.

R1 = R2 = R

C1 = C2 = C

Q = Peaking Factor

(Butterworth Q = 0.707)

2 RC

–3dB

2 −

)

(

Figure 32. 2-Pole Low-Pass Sallen-Key Filter

CIRCUIT LAYOUT CONSIDERATIONS

To achieve the high-frequency performance levels of the THS401x, follow proper printed circuit board (PCB)

high-frequency design techniques. A general set of guidelines is given in the following paragraphs. In addition, a

THS401x evaluation board is available to use as a guide for layout or for evaluating the device performance.

•

Ground planes – It is highly recommended that a ground plane be used on the board to provide all

components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,

the ground plane can be removed to minimize the stray capacitance.

•

Proper power-supply decoupling – Use a 6.8-mF tantalum capacitor in parallel with a 0.1-mF ceramic capacitor

on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the

application, but a 0.1-mF ceramic capacitor should always be used on the supply terminal of every amplifier.

In addition, the 0.1-mF capacitor should be placed as close as possible to the supply terminal. As this distance

increases, the inductance in the connecting trace makes the capacitor less effective. The designer should

strive for distances of less than 0.1 in between the device power terminals and the ceramic capacitors.

•

Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead

inductance in the socket pins often leads to stability problems. Surface-mount packages soldered directly to

the PCB are the best implementation.

Short trace runs/compact part placements – Optimum high-frequency performance is achieved when stray

series inductance has been minimized. To realize this, the circuit layout should be made as compact as

possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting

input of the amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the

input of the amplifier.

•

Surface-mount passive components – Using surface-mount passive components is recommended for

high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of

surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small

size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray

inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept

as short as possible.

GENERAL PowerPAD™ DESIGN CONSIDERATIONS

The THS401x is available packaged in a thermally-enhanced DGN package, which is a member of the

PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is

mounted [see Figure 33(a) and Figure 33(b)]. This arrangement results in the lead frame being exposed as a

thermal pad on the underside of the package [see Figure 33(c)]. Because this thermal pad has direct thermal

contact with the die, excellent thermal performance can be achieved by providing a good thermal path away from

the thermal pad.

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The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.

During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be

soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,

heat can be conducted away from the package into either a ground plane or other heat-dissipating device.

The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of

surface mount with the, heretofore, awkward mechanical methods of heatsinking.

DIE

Side View (a)

Thermal

Pad

DIE

End View (b)

Bottom View (c)

NOTE: The thermal pad is electrically isolated from all terminals in the package.

Figure 33. Thermally-Enhanced DGN Package Views

Although there are many ways to properly heatsink this device, the following steps show the recommended

approach:

1. Prepare the PCB with a top-side etch pattern as shown in Figure 34. There should be etch for the leads, as

well as etch for the thermal pad.

2. Place five holes in the area of the thermal pad. These holes should be 13 mils in diameter. Keep them small

so that solder wicking through the holes is not a problem during reflow.

3. Additional vias may be placed anywhere along the thermal plane outside of the thermal-pad area. This helps

dissipate the heat generated by the THS401xDGN IC. These additional vias may be larger than the 13-mils

diameter vias directly under the thermal pad. They can be larger because they are not in the thermal-pad

area to be soldered so that wicking is not a problem.

4. Connect all holes to the internal ground plane.

5. When connecting these holes to the ground plane, do not use the typical web or spoke via connection

methodology. Web connections have a high thermal-resistance connection that is useful for slowing the heat

transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In

this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the

holes under the THS401xDGN package should make their connection to the internal ground plane with a

complete connection around the entire circumference of the plated-through hole.

6. The top-side solder mask should leave the terminals of the package and the thermal-pad area with its five

holes exposed. The bottom-side solder mask should cover the five holes of the thermal-pad area. This

prevents solder from pulling away from the thermal-pad area during the reflow process.

7. Apply solder paste to the exposed thermal-pad area and all of the IC terminals.

8. With these preparatory steps in place, the THS401xDGN IC is simply placed in position and run through the

solder reflow operation as any standard surface-mount component. This results in a part that is properly

installed.

Thermal-pad area (68 mils x 70 mils) with 5 vias

(via diameter = 13 mils)

Figure 34. PowerPAD™ PCB Etch and Via Pattern

The actual thermal performance achieved with the THS401xDGN in its PowerPAD package depends on the

application. In the previous example, if the size of the internal ground plane is approximately 3 in × 3 in, the

expected thermal coefficient, q_JA, is approximately 58.4°C/W. For comparison, the non-PowerPAD version of the

THS401x IC (SOIC) is shown. For a given q_JA, the maximum power dissipation is shown in Figure 35 and is

calculated by the following formula:

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* T

MAX

ǒ Ǔ

Where:

P_D= Maximum power dissipation of THS401x IC (watts)

T_MAX= Absolute maximum junction temperature (150°C)

T_A= Free-ambient air temperature (°C)

q_JA= q_JC+ q_CA

q_JC= Thermal coefficient from junction to case

q_CA= Thermal coefficient from case to ambient air (°C/W)

3.5

DGN Package

= 150°C

= 58.4°C/W

2-oz Trace and Copper Pad

With Solder

2.5

DGN Package

= 158°C/W

SOIC Package

2-oz Trace and

Copper Pad

High-K Test PCB

= 98°C/W

Without Solder

1.5

SOIC Package

0.5

Low-K Test PCB

= 167°C/W

−40

−20

100

− Free-Air Temperature − °C

A. Results are with no airflow and PCB size = 3 in × 3 in

Figure 35. Maximum Power Dissipation vs Free-Air Temperature

More complete details of the PowerPAD installation process and thermal-management techniques can be found

in the TI technical brief, PowerPAD™ Thermally-Enhanced Package. This document can be found at the TI web

site (www.ti.com) by searching on the keyword PowerPAD. The document can also be ordered through your

local TI sales office. Refer to literature number SLMA002 when ordering.

The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent

power and output power. The designer should never forget about the quiescent heat generated within the device,

especially multiple amplifier devices. Because these devices have linear output stages (Class A-B), most of the

heat dissipation is at low output voltages with high output currents. Figure 36 to Figure 39 show this effect, along

with the quiescent heat, with an ambient air temperature of 50°C. When using V_CC= ±5 V, there is generally not

a heat problem, even with SOIC packages. But, when using V_CC= ±15 V, the SOIC package is severely limited

in the amount of heat it can dissipate. The other key factor when looking at these graphs is how the devices are

mounted on the PCB. The PowerPAD devices are extremely useful for heat dissipation. But, the device should

always be soldered to a copper plane to fully use the heat-dissipation properties of the PowerPAD package. The

SOIC package, on the other hand, is highly dependent on how it is mounted on the PCB. As more trace and

copper area is placed around the device, q_JAdecreases and the heat dissipation capability increases. The

currents and voltages shown in these graphs are for the total package. For the dual amplifier package

(THS4012), the sum of the RMS output currents and voltages should be used to choose the proper package.

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THS4011

MAXIMUM RMS OUTPUT CURRENT

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

200

1000

Maximum Output

Current Limit Line

= 150°C

= 50°C

= ±5 V

= 150°C

= 50°C

= ±15 V

180

160

140

120

100

Maximum Output

Current Limit Line

DGN Package

= 58.4°C/W

Package With

< = 120°C/W

100

SO-8 Package

= 167°C/W

SO-8 Package

= 98°C/W

Low-K Test PCB

High-K Test PCB

SO-8 Package

= 167°C/W

Safe Operating

Area

Safe Operating

Area

Low-K Test PCB

|V | − RMS Output Voltage − V

Figure 36.

Figure 37.

THS4012

MAXIMUM RMS OUTPUT CURRENT

RMS OUTPUT VOLTAGE DUE TO THERMAL LIMITS

200

1000

Maximum Output

Current Limit Line

Package With

= ±15 V

= 150°C

= 50°C

Maximum Output

Current Limit Line

≤ 60°C/W

180

160

140

120

100

Both Channels

100

SO-8 Package

= 167°C/W

SO-8 Package

= 98°C/W

Low-K Test PCB

Safe Operating Area

High-K Test PCB

DGN Package

= 58.4°C/W

= ±5 V

SO-8 Package

= 150°C

= 98°C/W

= 167°C/W

T = 50°C

Both Channels

High-K Test PCB

Low-K Test PCB

Safe Operating Area

|V | − RMS Output Voltage − V

Figure 38.

Figure 39.

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EVALUATION BOARD

An evaluation board is available for the THS4011 (literature number SLOP128) and THS4012 (literature number

SLOP230). This board has been configured for low parasitic capacitance in order to realize the full performance

of the amplifier. A schematic of the THS4011 evaluation board is shown in Figure 40. The circuitry has been

designed so that the amplifier may be used in either an inverting or noninverting configuration. For more

information, refer to the THS4011 EVM User's Guide (literature number SLOU028) or the THS4012 EVM User's

Guide (literature number SLOU041) To order the evaluation board, contact your local TI sales office or

distributor.

V +

6.8 mF

0.1 mF

1 kΩ

NULL

49.9 Ω

IN+

49.9 Ω

OUT

THS4011

NULL

1 kΩ

6.8 mF

0.1 mF

IN−

−

49.9 Ω

Figure 40. THS4011 Evaluation Board

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REVISION HISTORY

Changes from Original (June 1999) to Revision A

Page

•

Changed Feature List item From: 0.006% Differential Gain Error To: 0.01% Differential Gain Error .................................. 1

Replaced the HIGH SPEED FAMILY of DEVICES table with the RELATED DEVICES table ............................................. 1

Changed the Available Options table, THS4012ID MSOP Symbol From: TAIBG To: TIABZ .............................................. 2

Changed the ELECTRICAL CHARACTERISTIC table ......................................................................................................... 5

Changed the TYPICAL CHARACTERISTICS section .......................................................................................................... 9

Changed Figure 26, Noise Figure vs Source Resistance ................................................................................................... 14

Changed Figure 36 through Figure 39 ............................................................................................................................... 20

Changed Figure 40, THS4011 Evaluation Board ............................................................................................................... 21

Changes from Revision A (February 2000) to Revision B

Page

•

Changed Feature List item From: 0.01% Differential Gain Error To: 0.006% Differential Gain Error .................................. 1

Added THS4011M to the Abs Max table .............................................................................................................................. 4

Added the ELECTRICAL CHARACTERISTICS for device number THS4011M .................................................................. 7

Changes from Revision B (February 2000) to Revision C

Page

•

Changed Figure 24, THS4011/4012 Simplified Schematic ................................................................................................ 12

Changes from Revision C (May 2006) to Revision D

Page

•

Changed Figure 29 - Output Offset Voltage Model docato-extra-info-title Output Offset Voltage Model ........................... 16

Changes from Revision D (June 2007) to Revision E

Page

•

Deleted Lead temperature and Case temperature from the Abs Max table ......................................................................... 4

Changed Figure 5 label - From: Input Bias Current - A To: Input Bias Current - µA ........................................................... 9

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PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

5962-9959301Q2A

ACTIVE

LCCC

TBD

Call TI

-55 to 125 5962-

9959301Q2A

THS4011MFKB

5962-9959301QPA

THS4011CD

ACTIVE

CDIP

SOIC

TBD

Call TI

-55 to 125 9959301QPA

THS4011M

Green (RoHS

& no Sb/Br)

CU NIPDAU

POST-PLATE

Level-1-260C-UNLIM

N / A for Pkg Type

4011C

THS4011CDG4

THS4011CDGN

THS4011CDGNG4

THS4011CDGNR

THS4011CDGNRG4

THS4011CDR

Green (RoHS

& no Sb/Br)

4011C

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

ACI

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ACI

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

ACI

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ACI

SOIC

Green (RoHS

& no Sb/Br)

4011C

THS4011CDRG4

THS4011ID

Green (RoHS

& no Sb/Br)

4011C

Green (RoHS

& no Sb/Br)

4011I

THS4011IDG4

Green (RoHS

& no Sb/Br)

4011I

THS4011IDGN

THS4011IDGNG4

THS4011IDGNR

THS4011IDGNRG4

THS4011MFKB

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

ACJ

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ACJ

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ACJ

LCCC

TBD

-55 to 125 5962-

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

9959301Q2A

THS4011MFKB

THS4011MJG

ACTIVE

CDIP

TBD

A42

N / A for Pkg Type

-55 to 125 THS4011MJG

THS4011MJGB

-55 to 125 9959301QPA

THS4011M

THS4012CD

THS4012CDG4

THS4012CDGN

THS4012CDGNG4

THS4012CDGNR

THS4012CDGNRG4

THS4012CDR

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

4012C

ABY

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ABY

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

ABY

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ABY

SOIC

Green (RoHS

& no Sb/Br)

4012C

4012I

ABZ

THS4012CDRG4

THS4012ID

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

THS4012IDG4

Green (RoHS

& no Sb/Br)

THS4012IDGN

MSOP-

PowerPAD

DGN

Green (RoHS

& no Sb/Br)

THS4012IDGNG4

THS4012IDGNR

THS4012IDGNRG4

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ABZ

MSOP-

PowerPAD

2500

Green (RoHS

& no Sb/Br)

ABZ

MSOP-

PowerPAD

Green (RoHS

& no Sb/Br)

ABZ

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

24-Jan-2013

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF THS4011, THS4011M :

Catalog: THS4011

•

Military: THS4011M

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

THS4011CDGNR

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

THS4011CDR

SOIC

2500

330.0

12.4

6.4

5.3

5.2

3.4

2.1

1.4

8.0

12.0

THS4011IDGNR

MSOP-

Power

PAD

DGN

THS4012CDGNR

MSOP-

Power

PAD

DGN

2500

330.0

12.4

5.3

3.4

1.4

8.0

12.0

THS4012CDR

SOIC

2500

330.0

12.4

6.4

5.3

5.2

3.4

2.1

1.4

8.0

12.0

THS4012IDGNR

MSOP-

Power

PAD

DGN

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

THS4011CDGNR

THS4011CDR

MSOP-PowerPAD

SOIC

DGN

2500

358.0

367.0

358.0

367.0

358.0

335.0

367.0

335.0

367.0

335.0

35.0

THS4011IDGNR

THS4012CDGNR

THS4012CDR

MSOP-PowerPAD

SOIC

DGN

THS4012IDGNR

MSOP-PowerPAD

DGN

Pack Materials-Page 2

MECHANICAL DATA

MCER001A – JANUARY 1995 – REVISED JANUARY 1997

JG (R-GDIP-T8)

CERAMIC DUAL-IN-LINE

0.400 (10,16)

0.355 (9,00)

0.280 (7,11)

0.245 (6,22)

0.065 (1,65)

0.045 (1,14)

0.310 (7,87)

0.290 (7,37)

0.063 (1,60)

0.015 (0,38)

0.020 (0,51) MIN

0.200 (5,08) MAX

0.130 (3,30) MIN

Seating Plane

0.023 (0,58)

0.015 (0,38)

0°–15°

0.100 (2,54)

0.014 (0,36)

0.008 (0,20)

4040107/C 08/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a ceramic lid using glass frit.

D. Index point is provided on cap for terminal identification.

E. Falls within MIL STD 1835 GDIP1-T8

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THS4012CDGNG4 [TI]

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