THS4061CD [TI]
180-MHz HIGH-SPEED AMPLIFIERS; 180 MHz的高速放大器
| 型号： | THS4061CD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 180-MHz HIGH-SPEED AMPLIFIERS |
| 文件： | 总22页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
THS4061
JG, D AND DGN PACKAGE
(TOP VIEW)
THS4062
D AND DGN PACKAGE
(TOP VIEW)
High Speed
– 180 MHz Bandwidth (G = 1, –3 dB)
– 400 V/µs Slew Rate
– 40-ns Settling Time (0.1%)
NULL
IN–
NULL
1OUT
1IN–
1IN+
V
CC+
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
2OUT
2IN–
2IN+
High Output Drive, I = 115 mA (typ)
O
CC+
IN+
OUT
NC
Excellent Video Performance
– 75 MHz 0.1 dB Bandwidth (G = 1)
– 0.02% Differential Gain
V
–V
CC
CC–
NC – No internal connection
– 0.02° Differential Phase
Very Low Distortion
– THD = –72 dBc at f = 1 MHz
Cross-Section View Showing
PowerPAD Option (DGN)
Wide Range of Power Supplies
– V
= ±5 V to ±15 V
CC
THS4061
FK PACKAGE
(TOP VIEW)
Available in Standard SOIC, MSOP
PowerPAD , JG, or FK Package
Evaluation Module Available
description
3
2
1
20 19
The THS4061 and THS4062 are general-
purpose, single/dual, high-speed voltage feed-
back amplifiers ideal for a wide range of
applications including video, communication, and
imaging. The devices offer very good ac
performance with 180-MHz bandwidth, 400-V/µs
slew rate, and 40-ns settling time (0.1% ). The
THS4061/2 are stable at all gains for both
inverting and noninverting configurations. These
amplifiers have a high output drive capability of
115 mA and draw only 7.8 mA supply current per
channel. Excellent professional video results can
be obtained with the low differential gain/phase
errors of 0.02%/0.02° and wide 0.1 db flatness to
75 MHz. For applications requiring low distortion,
the THS4061/2 is ideally suited with total
harmonic distortion of –72 dBc at f = 1 MHz.
NC
IN–
NC
IN+
NC
NC
V
4
5
6
7
8
18
17
16
15
14
CC+
NC
OUT
NC
9
10 11 12 13
V
I
+
_
75 Ω
75 Ω
75 Ω
V
O
THS4061
2 kΩ
2 kΩ
LINE DRIVER (G = 2)
CAUTION: The THS4061 and THS4062 provide ESD protection circuitry. However, permanent damage can still occur if this
device is subjected to high-energy electrostatic discharges. Proper ESD precautions are recommended to avoid any
performance degradation or loss of functionality
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Insruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
RELATED DEVICES
DESCRIPTION
DEVICE
THS4011/2
THS4031/2
THS4061/2
290-MHz Low Distortion High-Speed Amplifiers
100-MHz Low Noise High Speed-Amplifiers
180-MHz High-Speed Amplifiers
AVAILABLE OPTIONS
PACKAGED DEVICES
PLASTIC
NUMBER OF
CHANNELS
MSOP
SYMBOL
EVALUATION
MODULES
PLASTIC
MSOP
(DGN)
CERAMIC
DIP
CHIP
CARRIER
(FK)
T
A
SMALL
OUTLINE
(D)
†
†
(JG)
1
2
1
2
THS4061CD
THS4062CD
THS4061ID
THS4062ID
THS4061CDGN
THS4062CDGN
THS4061IDGN
THS4062IDGN
—
—
—
—
—
—
—
—
TIABS
TIABM
TIABT
TIABN
THS4061EVM
0°C to
70°C
THS4062EVM
—
—
–40°C to
85°C
–55°C to
125°C
1
—
—
THS4061MJG
THS4061MFK
—
—
†
The D and DGN packages are available taped and reeled. Add an R suffix to the device type (i.e., THS4061CDGNR).
functional block diagram
Null
1
2
8
IN–
IN+
–
6
OUT
3
+
Figure 1. THS4061 – Single Channel
V
CC
8
2
3
1IN–
1IN+
–
1
7
1OUT
2OUT
+
6
5
2IN–
2IN+
–
+
4
–V
CC
Figure 2. THS4062 – Dual Channel
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, V + to V
–
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 V
CC
CC
Input voltage, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V
I
CC
Output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mA
O
Differential input voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±4 V
IO
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Maximum junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
J
Operating free-air temperature, T : C-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
I-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
M-suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds, D and DGN package . . . . . . . . . . . . 300°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds, JG package . . . . . . . . . . . . . . . . . . . . 300°C
Case temperature for 60 seconds, FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
T
≤ 25°C
DERATING FACTOR
T
= 70°C
T
= 85°C
T = 125°C
A
POWER RATING
A
A
A
PACKAGE
POWER RATING
ABOVE T = 25°C
POWER RATING
POWER RATING
A
D
740 mW
6 mW/°C
17.1 mW/°C
8.4 mW/°C
11 mW/°C
475 mW
385 mW
—
‡
DGN
JG
2.14 W
1.37 W
1.11 W
—
1057 mW
1375 mW
627 mW
546 mW
210 mW
275 mW
FK
880 mW
715 mW
‡
TheDGNpackageincorporatesaPowerPADontheundersideofthedevice. Thisactsasaheatsinkandmustbeconnectedtoathermaldissipation
plane for proper power dissipation. Failure to do so can result in exceeding the maximum specified junction temperature, which could permanently
damage the device.
recommended operating conditions
MIN NOM
MAX
±16
32
UNIT
Dual supply
Single supply
C-suffix
±4.5
9
Supply voltage, V + and V
CC CC
–
V
0
70
Operating free-air temperature, T
I-suffix
–40
–55
85
°C
A
M-suffix
125
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics at T = 25°C, V
= ±15 V, R = 150 Ω (unless otherwise noted)
A
CC
L
dynamic performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
180
50
MAX
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= ±5 V
Gain = 1
MHz
MHz
Dynamic performance small-signal
bandwidth (–3 dB)
= ±15 V
= ±5 V
= ±15 V
= ±5 V
= ±15 V
= ±5 V
Gain = –1
BW
SR
50
75
Bandwidth for 0.1 dB flatness
Slew rate
Gain = 1
MHz
V/µs
ns
20
400
350
40
Gain = –1
Gain = –1
Gain = –1
= ±15 V, 5-V step (0 V to 5 V)
= ±5 V, = –2.5 V to 2.5 V,
= ±15 V, 5-V step (0 V to 5 V)
Settling time to 0.1%
Settling time to 0.01%
V
40
O
t
s
140
150
ns
= ±5 V,
V
O
= –2.5 V to 2.5 V,
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
noise/distortion performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
–72
14.5
1.6
MAX
THD
Total harmonic distortion
Input voltage noise
Input current noise
f = 1 MHz
f = 10 kHz,
f = 10 kHz,
dBc
V
n
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
nV/√Hz
pA/√Hz
CC
I
n
CC
0.02
%
V
V
= ±15 V
= ±5 V
CC
Differential gain error
Gain = 2,
Gain = 2,
NTSC, 40 IRE modulation
NTSC, 40 IRE modulation
0.02
%
CC
V
V
= ±15 V
= ±5 V
0.02°
0.06°
CC
Differential phase error
CC
Channel-to-channel crosstalk
(THS4062 only)
V
CC
= ±5 V or ±15 V,
f = 1 MHz
65
dB
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
dc performance
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
T
= 25°C
5
4
15
A
V
V
= ±15 V,
= ±5 V,
V
V
= ±10 V,
= ±2.5 V,
R
R
= 1 kΩ
V/mV
V/mV
CC
O
L
T
A
= full range
= 25°C
Open loop gain
T
A
2.5
2
8
= 1 kΩ
CC
O
L
T
A
= full range
Input offset voltage
Offset drift
V
V
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
2.5
15
3
8
mV
µV/°C
µA
CC
CC
CC
CC
V
T
= full range
OS
A
I
I
Input bias current
Input offset current
Offset current drift
T
A
= full range
= full range
6
IB
T
A
75
0.3
250
nA
OS
T
A
= full range
nA/°C
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics at T = 25°C, V = ±15 V, R = 150 Ω (unless otherwise noted) (continued)
A
CC
L
input characteristics
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
±13.8 ±14.1
V
Common-mode input voltage range
V
ICR
±3.8
70
±4.3
110
95
1
= ±15 V,
= ±5 V,
V
V
= ±12 V
= ±2.5 V
ICR
CMRR Common mode rejection ratio
T
A
= full range
dB
70
ICR
R
C
Input resistance
MΩ
I
i
Input capacitance
2
pF
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
output characteristics
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
V
V
V
V
V
V
V
= ±15 V
= ±5 V
R
R
= 250 Ω
= 150 Ω
±11.5 ±12.5
CC
CC
CC
CC
CC
CC
CC
L
L
V
V
±3.2
±3.5
V
Output voltage swing
Output current
O
= ±15 V
= ±5 V
±13 ±13.5
R
R
= 1 kΩ
= 20 Ω
L
L
±3.5
80
±3.7
115
75
= ±15 V
= ±5 V
I
I
mA
O
50
Short-circuit current
Output resistance
= ±15 V
150
12
mA
SC
R
Open loop
Ω
O
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
power supply
THS4061C/I,
THS4062C/I
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
±16.5
33
Dual supply
±4.5
V
Supply voltage operating range
Quiescent current (per amplifier)
V
CC
Single supply
9
V
V
= ±15 V
= ±5 V
7.8
7.3
78
10.5
10
CC
I
T
= full range
mA
dB
CC
A
CC
T
A
= 25°C
70
68
PSRR Power supply rejection ratio
V
CC
= ±5 V or ±15 V
T
A
= full range
†
Full range = 0°C to 70°C for C suffix and –40°C to 85°C for I suffix
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics at T = 25°C, V
= ±15 V, R = 150 Ω (unless otherwise noted)
A
CC
L
dynamic performance
THS4061M
†
PARAMETER
UNIT
MHz
MHz
TEST CONDITIONS
MIN
TYP
180
180
180
50
MAX
Unity-gain bandwidth
Closed loop,
R
= 1 kΩ
V
= ±15 V
*140
L
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
Gain = 1
Gain = –1
Gain = 1
Dynamic performance small-signal
bandwidth (–3 dB)
BW
SR
= ±15 V
= ±5 V
MHz
50
= ±15 V
= ±5 V
75
Bandwidth for 0.1 dB flatness
Slew rate
MHz
V/µs
ns
20
= ±15 V
R
= 1 kΩ
*400
500
40
L
= ±15 V, 5-V step (0 V to 5 V)
= ±5 V, = –2.5 V to 2.5 V,
= ±15 V, 5-V step (0 V to 5 V)
Settling time to 0.1%
Gain = –1
Gain = –1
V
O
40
t
s
140
150
Settling time to 0.01%
ns
= ±5 V,
V
O
= –2.5 V to 2.5 V,
†
Full range = –55°C to 125°C for M suffix
*This parameter is not tested.
noise/distortion performance
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
–72
MAX
THD
Total harmonic distortion
Input voltage noise
Input current noise
f = 1 MHz
f = 10 kHz,
f = 10 kHz,
dBc
V
n
V
V
= ±5 V or ±15 V
= ±5 V or ±15 V
14.5
1.6
nV/√Hz
pA/√Hz
CC
I
n
CC
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
0.02
0.02
0.02°
0.06°
Differential gain error
Differential phase error
Gain = 2,
Gain = 2,
NTSC, 40 IRE Modulation
NTSC, 40 IRE Modulation
%
†
Full range = –55°C to 125°C for M suffix
dc performance
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
9
MAX
V
V
= ±15 V,
= ±5 V,
V
V
= ±10 V,
= ±2.5 V,
R
R
= 1 kΩ
= 1 kΩ
5
CC
O
L
L
Open loop gain
T
A
= full range
V/mV
2.5
6
CC
O
T
= 25°C
2.5
8
9
mV
mV
A
Input offset voltage
V
= ±5 V or ±15 V
R
= 1 kΩ
CC
L
V
IO
T
A
= full range
= full range
= full range
= full range
= full range
Offset drift
V
CC
V
CC
V
CC
V
CC
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
= ±5 V or ±15 V
R
R
R
R
= 1 kΩ
= 1 kΩ
= 1 kΩ
= 1 kΩ
T
A
15
3
µV/°C
µA
L
L
L
L
I
I
Input bias current
Input offset current
Offset current drift
T
A
6
IB
T
A
75
0.3
250
nA
IO
T
A
nA/°C
†
Full range = –55°C to 125°C for M suffix
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics at T = full range, V
A
= ±15 V, R = 1 kΩ (unless otherwise noted)
CC
L
(continued)
input characteristics
THS4061M
†
PARAMETER
UNIT
V
TEST CONDITIONS
MIN
TYP
MAX
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
±13.8 ±14.1
V
Common-mode input voltage range
ICR
±3.8
70
±4.3
86
90
1
= ±15 V,
= ±5 V,
V
V
= ±12 V
= ±2.5 V
ICR
CMRR Common mode rejection ratio
dB
80
ICR
R
C
Input resistance
MΩ
I
i
Input capacitance
2
pF
†
Full range = –55°C to 125°C for M suffix
output characteristics
THS4061M
†
TEST CONDITIONS
PARAMETER
UNIT
V
MIN
TYP
MAX
V
V
V
V
V
V
V
= ±15 V
= ±5 V
R
R
= 250 Ω
= 150 Ω
±12 ±13.1
CC
CC
CC
CC
CC
CC
CC
L
L
±3.2
±3.5
V
O
Output voltage swing
Output current
= ±15 V
= ±5 V
±13 ±13.5
R
R
= 1 kΩ
V
L
L
±3.5
70
±3.7
115
75
= ±15 V
= ±5 V
I
I
= 20 Ω
= 25°C
mA
O
50
Short-circuit current
Output resistance
= ±15 V
T
A
150
12
mA
SC
R
Open loop
Ω
O
†
Full range = –55°C to 125°C for M suffix
power supply
THS4061M
†
PARAMETER
UNIT
TEST CONDITIONS
MIN
TYP
MAX
±16.5
33
Dual supply
±4.5
V
Supply voltage operating range
Quiescent current
V
CC
Single supply
9
V
CC
V
CC
V
CC
V
CC
= ±15 V
= ±5 V
= ±15 V
= ±5 V
7.8
7.3
9
T
= 25°C
A
8.5
I
mA
dB
CC
11
T
A
= full range
10.5
T
A
= 25°C
76
74
80
78
PSRR Power supply rejection ratio
V
CC
= ±5 V or ±15 V
T
A
= full range
†
Full range = –55°C to 125°C for M suffix
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
FIGURE
3
I
Input bias current
Input offset voltage
Open-loop gain
Phase
vs Free-air temperature
vs Free-air temperature
vs Frequency
IB
V
4
IO
5
vs Frequency
5
Differential gain
Differential phase
Closed-loop gain
Output Amplitude
vs Number of loads
vs Number of loads
vs Frequency
6, 8
7, 9
10, 11
12, 13
14
vs Frequency
CMRR Common-mode rejection ratio
vs Frequency
vs Frequency
15
PSRR
Power-supply rejection ratio
vs Free-air temperature
vs Supply voltage
vs Free-air temperature
vs Frequency
16
V
Output voltage swing
Supply current
17
O(PP)
I
18
CC
E
nv
Noise spectral density
Total harmonic distortion
19
THD
vs Frequency
20, 21
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT
vs
INPUT OFFSET VOLTAGE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
4
3.5
3
0
–0.5
–1
VCC = ±15 V, ±5 V
VCC = ±5 V
–1.5
–2
VCC = ±15 V
–2.5
–3
2.5
2
–3.5
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
T
A
– Free-Air Temperature – °C
T
A
– Free-Air Temperature – °C
Figure 3
Figure 4
OPEN-LOOP GAIN AND PHASE
vs
FREQUENCY
90
80
70
60
50
40
30
VCC = ±15 V
VCC = ±5 V
0°
–45°
–90°
–135°
–180°
Phase
20
10
0
1k
10k
100k
1M
10M
100M
1G
f – Frequency – Hz
Figure 5
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.14%
0.7°
Gain = 2
Gain = 2
RF = 680 Ω
40 IRE – NTSC
Worst Case ±100 IRE Ramp
RF = 680 Ω
40 IRE – NTSC
Worst Case ±100 IRE Ramp
0.12%
0.1%
0.6
0.5°
0.4°
0.3°
0.2°
0.1°
0°
V
= ±5
CC
Phase
0.08%
0.06%
0.04%
0.02%
0%
V
= ±15
CC
Gain
V
= ±15
CC
Phase
V
CC
Gain
= ±5
1
2
3
4
1
2
3
4
Number of 150 Ω Loads
Number of 150 Ω Loads
Figure 6
Figure 7
DIFFERENTIAL GAIN
vs
NUMBER OF LOADS
DIFFERENTIAL PHASE
vs
NUMBER OF LOADS
0.2%
0.18%
0.16%
0.14%
0.12%
1°
Gain = 2
= 680 Ω
40 IRE – PAL
Worst Case ±100 IRE Ramp
Gain = 2
= 680 Ω
40 IRE – PAL
0.9°
0.8°
0.7°
0.6°
R
R
F
F
Worst Case ±100 IRE Ramp
V = ±15
CC
Gain
0.1%
0.08%
0.06%
0.04%
0.02%
0.5°
0.4°
0.3°
0.2°
0.1°
V
= ±5
Gain
CC
V
= ±5
CC
Phase
V
3
= ±15
CC
Phase
0%
0°
1
2
3
4
1
2
4
Number of 150 Ω Loads
Number of 150 Ω Loads
Figure 8
Figure 9
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
CLOSED-LOOP GAIN
vs
CLOSED-LOOP GAIN
vs
FREQUENCY
FREQUENCY
2
0
5
0
V
CC
= ±15 V
–2
–4
V
CC
= ±5 V
–5
–10
–6
–8
–10
V
= ±15 V, ±5 V
CC
Gain = –1
–15
–20
Gain = 1
–12
–14
R
R
= 510 Ω
= 150 Ω
R
R
= 270 Ω
= 150 Ω
F
L
F
L
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f – Frequency – Hz
f – Frequency – Hz
Figure 10
Figure 11
OUTPUT AMPLITUDE
vs
OUTPUT AMPLITUDE
vs
FREQUENCY
FREQUENCY
4
2
R
= 510 Ω
F
R
= 1 kΩ
F
2
0
0
R
= 3 kΩ
–2
F
R
= 270 Ω
F
–2
–4
R = 200 Ω
F
–4
–6
–6
–8
–8
Gain = 1
Gain = –1
R
= 150 Ω
L
R
= 150 Ω
L
–10
100k
1M
10M
100M
1G
100k
1M
10M
100M
1G
f – Frequency – Hz
f – Frequency – Hz
Figure 12
Figure 13
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
COMMON-MODE REJECTION RATIO
POWER SUPPLY REJECTION RATIO
vs
vs
FREQUENCY
FREQUENCY
120
100
80
–80
V
CC
= ±15 V, ±5 V
–70
–60
–50
–40
–30
–20
60
40
20
0
–10
0
V
CC
= ±15 V, ±5 V
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M
100M
f – Frequency – Hz
f – Frequency – Hz
Figure 14
Figure 15
POWER SUPPLY REJECTION RATIO
OUTPUT VOLTAGE SWING
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
90
30
25
20
15
88
86
84
82
80
78
76
R
= 1 kΩ
V
= –15 V
L
CC
R
= 150 Ω
L
V
CC
= 15 V
10
5
74
72
0
–40
–20
0
20
40
60
80
100
±4
±6
±8
±10
±12
±14
±16
T
A
– Free-Air Temperature – °C
V
CC
– Supply Voltage – V
Figure 16
Figure 17
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
NOISE SPECTRAL DENSITY
vs
FREQUENCY
10
9
180
160
140
120
100
80
T
A
= 25°C
V
CC
= ±15 V
8
V
CC
= ±5 V
7
6
5
4
60
40
20
0
–40
–20
0
20
40
60
80
100
10
100
1k
10k
100k
T
A
– Free-Air Temperature – °C
f – Frequency – Hz
Figure 18
Figure 19
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
–40
–50
–60
–70
–80
–90
–40
–50
–60
–70
–80
–90
Gain = 2
Gain = 2
= ±5 V
V = ±15 V
CC
= 150 Ω
V
CC
= 150 Ω
R
R
L
L
2nd Harmonic
2nd Harmonic
3rd Harmonic
3rd Harmonic
–100
–110
–100
–110
100k
1M
10M
100k
1M
10M
f – Frequency – MHz
f – Frequency – MHz
Figure 20
Figure 21
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
theory of operation
TheTHS406xisahighspeed, operationalamplifierconfiguredinavoltagefeedbackarchitecture. Itisbuiltusing
a 30-V, dielectrically isolated, complementary bipolar process with NPN and PNP transistors possessing f s of
T
several GHz. This results in an exceptionally high performance amplifier that has a wide bandwidth, high slew
rate, fast settling time, and low distortion. A simplified schematic is shown in Figure 22.
(7) V
+
CC
(6) OUT
IN– (2)
IN+ (3)
(4) V
–
CC
NULL (1)
NULL (8)
Figure 22. THS4061 Simplified Schematic
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
offset nulling
The THS4061 has very low input offset voltage for a high-speed amplifier. However, if additional correction is
required, an offset nulling function has been provided. By placing a potentiometer between terminals 1 and 8
and tying the wiper to the negative supply, the input offset can be adjusted. This is shown in
Figure 23.
V
CC
+
0.1 µF
+
_
THS4061
10 kΩ
0.1 µF
V
CC
–
Figure 23. Offset Nulling Schematic
optimizing unity gain response
Internal frequency compensation of the THS406x was selected to provide very wideband performance yet still
maintain stability when operated in a noninverting unity gain configuration. When amplifiers are compensated
in this manner there is usually peaking in the closed loop response and some ringing in the step response for
very fast input edges, depending upon the application. This is because a minimum phase margin is maintained
fortheG=+1configuration. Foroptimumsettlingtimeandminimumringing, afeedback resistorof 270Ω should
be used as shown in Figure 24. Additional capacitance can also be used in parallel with the feedback resistance
if even finer optimization is required.
Input
+
Output
THS406x
_
270 Ω
Figure 24. Noninverting, Unity Gain Schematic
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
driving a capacitive load
Driving capacitive loads with high performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS406x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device’s phase margin leading to high frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 25. A minimum value of 20 Ω should work well for most applications. For
example, in 75-Ω transmission systems, setting the series resistor value to 75 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
510 Ω
510 Ω
_
Input
20 Ω
Output
LOAD
THS406x
+
C
Figure 25. Driving a Capacitive Load
circuit layout considerations
In order to achieve the levels of high frequency performance of the THS406x, it is essential that proper
printed-circuit board high frequency design techniques be followed. A general set of guidelines is given below.
In addition, a THS406x evaluation board is available to use as a guide for layout or for evaluating the device
performance.
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distances increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
Sockets – Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductancein the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements – Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
APPLICATION INFORMATION
circuit layout considerations (continued)
Surface-mount passive components – Using surface-mount passive components is recommended for
high-frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance
of surface-mount components, the problem with stray series inductance is greatly reduced. Second, the
small size of surface-mount components naturally leads to a more compact layout, thereby minimizing both
stray inductance and capacitance. If leaded components are used, it is recommended that the lead lengths
be kept as short as possible.
evaluation board
An evaluation board is available for the THS4061 (literature number SLOP226) and THS4062 (literaure number
SLOP235). This board has been configured for very low parasitic capacitance in order to realize the full
performance of the amplifier. A schematic of the evaluation board is shown in Figure 26. The circuitry has been
designed so that the amplifier may be used in either an inverting or noninverting configuration. To order the
evaluation board contact your local TI sales office or distributor. For more detailed information, refer to the
THS4061 EVM User’s Manual (literature number SLOU038) or the THS4062 EVM User’s Manual (literature
number SLOU040)
V
CC
+
+
C2
C3
6.8 µF
0.1 µF
R4
1 kΩ
NULL
R5
49.9 Ω
IN+
+
_
R3
49.9 Ω
OUT
THS4061
NULL
R2
C1
1 kΩ
6.8 µF
+
C4
0.1 µF
IN–
V
CC
–
R1
49.9 Ω
Figure 26. THS4061 Evaluation Board Schematic
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
MECHANICAL INFORMATION
D (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
PINS **
0.050 (1,27)
8
14
16
DIM
0.020 (0,51)
0.014 (0,35)
0.010 (0,25)
0.197
(5,00)
0.344
(8,75)
0.394
(10,00)
M
A MAX
14
8
0.189
(4,80)
0.337
(8,55)
0.386
(9,80)
A MIN
0.244 (6,20)
0.228 (5,80)
0.008 (0,20) NOM
0.157 (4,00)
0.150 (3,81)
Gage Plane
1
7
A
0.010 (0,25)
0°–8°
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.004 (0,10)
0.010 (0,25)
0.004 (0,10)
0.069 (1,75) MAX
4040047/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
MECHANICAL INFORMATION
DGN (S-PDSO-G8)
PowerPAD PLASTIC SMALL-OUTLINE PACKAGE
0,38
0,25
0,65
M
0,25
8
5
Thermal Pad
(See Note D)
0,15 NOM
3,05
2,95
4,98
4,78
Gage Plane
0,25
0°–6°
1
4
0,69
0,41
3,05
2,95
Seating Plane
0,10
0,15
0,05
1,07 MAX
4073271/A 01/98
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions include mold flash or protrusions.
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad. This pad is electrically
and thermally connected to the backside of the die and possibly selected leads.
E. Falls within JEDEC MO-187
PowerPAD is a trademark of Texas Instruments Incorporated.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
MECHANICAL INFORMATION
FK (S-CQCC-N**)
LEADLESS CERAMIC CHIP CARRIER
28 TERMINAL SHOWN
A
B
NO. OF
TERMINALS
**
18 17 16 15 14 13 12
MIN
MAX
MIN
MAX
0.342
(8,69)
0.358
(9,09)
0.307
(7,80)
0.358
(9,09)
19
20
11
10
9
20
28
44
52
68
84
0.442
(11,23)
0.458
(11,63)
0.406
(10,31)
0.458
(11,63)
21
B SQ
22
0.640
(16,26)
0.660
(16,76)
0.495
(12,58)
0.560
(14,22)
8
A SQ
23
0.739
(18,78)
0.761
(19,32)
0.495
(12,58)
0.560
(14,22)
7
24
25
6
0.938
(23,83)
0.962
(24,43)
0.850
(21,6)
0.858
(21,8)
5
1.141
(28,99)
1.165
(29,59)
1.047
(26,6)
1.063
(27,0)
26 27 28
1
2
3
4
0.080 (2,03)
0.064 (1,63)
0.020 (0,51)
0.010 (0,25)
0.020 (0,51)
0.010 (0,25)
0.055 (1,40)
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.045 (1,14)
0.035 (0,89)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
4040140/D 10/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THS4061, THS4062
180-MHz HIGH-SPEED AMPLIFIERS
SLOS234D – DECEMBER 1998 – REVISED FEBRUARY 2000
MECHANICAL INFORMATION
JG (R-GDIP-T8)
CERAMIC DUAL-IN-LINE PACKAGE
0.400 (10,20)
0.355 (9,00)
8
5
0.280 (7,11)
0.245 (6,22)
1
4
0.065 (1,65)
0.045 (1,14)
0.310 (7,87)
0.290 (7,37)
0.020 (0,51) MIN
0.200 (5,08) MAX
0.130 (3,30) MIN
Seating Plane
0.063 (1,60)
0.015 (0,38)
0°–15°
0.023 (0,58)
0.015 (0,38)
0.100 (2,54)
0.014 (0,36)
0.008 (0,20)
4040107/C 08/96
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
E. Falls within MIL-STD-1835 GDIP1-T8
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明