THS4141CDGKG4 [TI]
Fully Differential Input/Output High Slew Rate Amplifier 8-VSSOP 0 to 70;
| 型号： | THS4141CDGKG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Fully Differential Input/Output High Slew Rate Amplifier 8-VSSOP 0 to 70 放大器 光电二极管 |
| 文件： | 总32页 (文件大小：1154K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4140
D−8
DGN−8 DGK−8
THS4141
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SLOS320F–MAY 2000–REVISED JANUARY 2006
HIGH-SPEED FULLY DIFFERENTIAL I/O AMPLIFIERS
FEATURES
KEY APPLICATIONS
•
•
•
•
•
Single-Ended to Differential Conversion
Differential ADC Driver
Differential Antialiasing
Differential Transmitter And Receiver
Output Level Shifter
•
High Performance
–
–
–
160 MHz –3 dB Bandwidth (VCC = ±15 V)
450 V/µs Slew Rate
–79 dB, Third Harmonic Distortion at
1 MHz
–
6.5 nV/√Hz Input-Referred Noise
THS4140
THS4141
D, DGN, OR DGK PACKAGE
(TOP VIEW)
D, DGN, OR DGK PACKAGE
•
Differential Input/Differential Output
(TOP VIEW)
–
Balanced Outputs Reject Common-Mode
Noise
V
V
V
V
IN+
IN−
IN+
IN−
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
OCM
PD
V
OCM
NC
–
Reduced Second Harmonic Distortion Due
to Differential Output
V
CC+
V
V
V
CC+
V
V
CC−
CC−
V
V
OUT+
OUT+
OUT−
OUT−
•
•
Wide Power-Supply Range
HIGH-SPEED DIFFERENTIAL I/O FAMILY
NUMBER OF
–
VCC = 5-V Single Supply to ±15-V Dual
Supply
DEVICE
SHUTDOWN
CHANNELS
THS4140
THS4141
1
1
X
−
ICC(SD) = 880 µA in Shutdown Mode (THS4140)
DESCRIPTION
The THS414x is one in a family of fully differential input/differential output devices fabricated using Texas
Instruments' state-of-the-art BiComI complementary bipolar process.
The THS414x is made of a true, fully differential signal path from input to output. This design leads to an
excellent common-mode noise rejection and improved total harmonic distortion.
RELATED DEVICES
DEVICE
THS412x
THS413x
THS415x
DESCRIPTION
100 MHz, 43 V/µs, 3.7 nV/√Hz
150 MHz, 51 V/µs, 1.3 nV/√Hz
150 MHz, 650 V/µs, 7.6 nV/√Hz
TOTAL HARMONIC DISTORTION vs FREQUENCY
−30
−40
−50
Typical A/D Application Circuit
5 V
VDD
AVDD DVDD
VIN
+
−
−60
−70
AIN
AIN
VOCM
DIGITAL
OUTPUT
+
AVSS
Vref
−
−80
−90
V
= 5 V to ± 15 V
CC
−5 V
−100
100 k
1 M
10 M
100 M
f
− Frequency − Hz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2000–2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
THS4140
THS4141
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SLOS320F–MAY 2000–REVISED JANUARY 2006
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. AVAILABLE OPTIONS
PACKAGED DEVICES(1)
EVALUATION
TA
MSOP PowerPAD™
MSOP
SMALL OUTLINE
(D)
MODULES
(DGN)
SYMBOL
(DGK)
SYMBOL
ATR
THS4140CD
THS4141CD
THS4140ID
THS4141ID
THS4140CDGN
THS4141CDGN
THS4140IDGN
THS4141IDGN
AOF
AOI
THS4140CDGK
THS4141CDGK
THS4140IDGK
THS4141IDGK
THS4140EVM
0°C to 70°C
ATS
THS4141EVM
AOG
AOK
ASQ
–
–
–40°C to 85°C
ASR
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
UNIT
VCC
VI
Supply voltage
VCC– to VCC+
±16.5 V
±VCC
Input voltage
IO
Output current(2)
150 mA
VID
Differential input voltage
Continuous total power dissipation
Maximum junction temperature(3)
±6 V
See Dissipation Rating Table
150°C
TJ
Maximum junction temperature, continuous operation, long term reliability(4)
125°C
C suffix
Operating free-air temperature
I suffix
0°C to 70°C
–40°C to 85°C
–65°C to 150°C
300°C
TA
Tstg
Storage temperature
Lead temperature 1,6 mm (1/16 Inch) from case for 10 seconds
HBM
2500 V
ESD ratings
CDM
MM
1500 V
200 V
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The THS414x may incorporate a PowerPad™ on the underside of the chip. This acts as a heatsink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical brief SLMA002 and SLMA004 for more information about utilizing the
PowerPad™ thermally enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATING TABLE
POWER RATING(2)
PACKAGE
θJA(1) (°C/W)
θJC (°C/W)
TA = 25°C
1.02 W
TA = 85°C
410 mW
685 mW
154 mW
D
97.5
58.4
260
38.3
4.7
DGN
DGK
1.71 W
54.2
385 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long
term reliability.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
RECOMMENDED OPERATING CONDITIONS
MIN
±2.5
TYP
MAX
±15
UNIT
Dual supply
Single supply
C suffix
VCC
Supply voltage, VCC– to VCC+
Operating free-air temperature
V
5
0
30
70
85
TA
°C
I suffix
–40
ELECTRICAL CHARACTERISTICS
VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted)(1)
PARAMETER
DYNAMIC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC = ±5,
VCC = ±15,
Gain = 1
Gain = 1, Rf = 390 Ω
Gain = 1, Rf = 390 Ω
150
MHz
MHz
V/µs
BW
SR
ts
Small signal bandwidth (–3 dB)
160
450
96
Slew rate(2)
Settling time to 0.1%
Settling time to 0.01%
Differential step voltage = 2 VPP
Gain = 1
,
ns
304
DISTORTION PERFORMANCE
1 MHz
VO = 2 VPP
VO = 2 VPP
VO = 2 VPP
VO = 2 VPP
f = 1 MHz
f = 1 MHz
f = 1 MHz
–85
–65
–79
–55.5
–78
–78
–79
–79
–103
37
Second harmonic distortion, differential
in/differential out
dB
dB
8 MHz
1 MHz
Third harmonic distortion, differential in/differential
out
8 MHz
Total harmonic distortion
VCC = 5
VCC = ±5
VCC = ±15
Differential input, differential output
Gain = 1, Rf = 390 Ω, RL = 800 Ω,
THD
dB
VO = 2 VPP
Spurious free dynamic range (SFDR)
Intermodulation distortion
Third-order intercept
dB
dBc
dB
5 MHz
20 MHz
NOISE PERFORMANCE
Vn
In
Input voltage noise
Input current noise
f = 10 kHz
f = 10 kHz
6.5
nV/√Hz
pA/√Hz
1.25
DC PERFORMANCE
TA = 25°C
63
60
67
1
Open loop gain
dB
TA = full range
TA = 25°C
Input offset voltage, differential
7
8.5
8
TA = full range
TA = 25°C
mV
VOS
Input offset voltage, referred to VOCM
0.5
7
Offset drift
TA = full range
µV/°C
µA
IIB
Input bias curent
Input offset current
Offset drift
5.1
0.1
0.3
15
1
IOS
TA = full range
µA
nA/°C
(1) The full range temperature is 0°C to 70°C for the C suffix, and –40°C to 85°C for the I suffix.
(2) Slew rate is measured from an output level range of 25% to 75%.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
ELECTRICAL CHARACTERISTICS (continued)
VCC = ±5 V, RL = 800 Ω, TA = 25°C (unless otherwise noted)
PARAMETER
INPUT CHARACTERISTICS
CMRR Common-mode rejection ratio
TEST CONDITIONS
MIN
TYP
MAX
UNIT
TA = full range
75
84
dB
V
–3.77 to
4.3
VICR
Common-mode input voltage range
–4 to 4.5
RI
CI
ro
Input resistance, closed loop
Input capacitance
Measured into each input terminal
Open loop
14.4
3.9
43
MΩ
pF
Ω
Output resistance
OUTPUT CHARACTERISTICS
TA = 25°C
VCC = 5 V
1.2 to 3.8 0.9 to 4.1
1.3 to 3.7
TA = full range
TA = 25°C
VCC = ±5 V
±3.7
±3.6
±12
±11
35
±3.9
±12.9
45
Output voltage swing
V
TA = full range
TA = 25°C
VCC = ±15 V
TA = full range
TA = 25°C
VCC = 5 V
TA = full range
25
TA = 25°C
VCC = ±5 V
45
60
IO
Output current, RL = 7Ω
mA
TA = full range
35
TA = 25°C
VCC = ±15 V
65
85
TA = full range
50
POWER SUPPLY
VCC Supply voltage range
Single supply
Split supply
4
33
V
±2
±16.5
16
TA = 25°C
VCC = ±5 V
13.2
ICC
Quiescent current
TA = full range
18
mA
VCC = ±15 V
TA = 25°C
TA = 25°C
15
0.88
1.2
1.4
Quiescent current (shutdown)
(THS4140)(3)
ICC(SD)
PSRR
mA
dB
TA = full range
TA = 25°C
70
65
90
Power supply rejection ratio (dc)
TA = full range
(3) For detailed information on the behavior of the power-down circuit, see the power-down mode description in the Principles of Operation
section of this data sheet.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
PSRR
Power supply rejection ratio
vs Frequency (differential out)
vs Frequency
1
2
Small signal frequency response
Large signal frequency response
3
CMMR Common-mode rejection ratio
Small signal frequency response
4
5
SR
Slew rate
6
vs Frequency
7
Second harmonic distortion
vs Output voltage
vs Frequency
8, 9
10, 11
12, 13
14
15
16
17
18
19
20
Third harmonic distortion
vs Output voltage
Settling time
Vn
Voltage noise
vs Frequency
Single-ended output voltage
Output voltage
vs Common-mode output voltage
vs Differential load resistance
vs Frequency
VO
zo
Output impedance
Input bias current
Output current range
vs Supply voltage
vs Supply voltage
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY (DIFFERENTIAL OUT)
SMALL SIGNAL FREQUENCY RESPONSE
45
40
35
−20
−30
V
CC
= 5 V to ±15 V
R
= 800 Ω,
=± 5 V,
L
V
CC
V = 45 mV
I
PP
R = 24 kΩ
f
30
25
20
15
10
5
−40
−50
V
CC−
R = 2.4 kΩ
f
R = 1.2 kΩ
f
R = 470 Ω
f
−60
−70
0
R = 240 Ω
f
V
CC
−5
−10
−15
−80
100 k
−20
100 k
1 M
10 M
100 M
1M
10 M
100 M
1 G
f − Frequency (Differential Out) − Hz
f − Frequency − Hz
Figure 1.
Figure 2.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
COMMON-MODE REJECTION RATIO
vs
LARGE SIGNAL FREQUENCY RESPONSE
FREQUENCY
−40
−50
−60
−70
−80
5
V = 0.8 mV
I
PP
V = 0.4 V
I
PP
0
−5
V
CC
= 5 V
V = 0.126 V
I
PP
−10
V
CC
= ±15 V
−15
−20
V = 40 m V
I
PP
V
CC
= ±5 V
−25
−30
R = 330 Ω,
f
R
L
= 800 Ω,
−90
V
CC
= ±5 V,
G = 1
−100
−35
100 k
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
f − Frequency − Hz
f − Frequency − Hz
Figure 3.
Figure 4.
SMALL SIGNAL FREQUENCY RESPONSE
SLEW RATE
1.25
1
1
V Peak = 1,
I
V
CC
= 5 V
T
= 25 °C
A
0.75
0.5
V
CC
= ±15 V
0
V
= ±5 V
0.25
0
CC
V
CC
= ±15 V
−1
V
= 5 V
CC
−0.25
−0.5
−0.75
−1
G = 1,
R = 330 Ω,
−2
R = 390 Ω,
f
f
R
L
= 800 Ω,
R
C
= 800 Ω,
= 1 pF,
L
V = 45 mV RMS
I
F
G = 1
C = 0
I
−3
100 k
−1.25
1 M
10 M
100 M
1 G
116
118
120
122
124
126
128
t − Time − ns
f − Frequency − Hz
Figure 5.
Figure 6.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
SECOND HARMONIC DISTORTION
SECOND HARMONIC DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
−80
−82
−84
−86
−88
−90
−92
−50
V
R
= 4 V
= 800 Ω,
f = 1 MHz
O
PP,
,
V
CC
= ±15 V
−55
−60
−65
−70
−75
−80
−85
−90
−95
−100
R
L
= 800 Ω,
L
V
CC
= ±5 V
R = 330 Ω,
G = 1
R = 330 Ω,
f
f
G = 1
V
CC
= ±5 V
V
CC
= ±15 V
V
CC
= 5 V
100 k
1M
10 M
100 M
1
2
3
4
5
6
V
O
− Output Voltage − V
f − Frequency − Hz
Figure 7.
Figure 8.
SECOND HARMONIC DISTORTION
THIRD HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE
FREQUENCY
−30
−57
−58
−59
−60
−61
−62
−63
−64
−65
−66
V
R
= 2 V
PP,
= 800 Ω,
O
L
−40
−50
V
CC
= 5 V
R = 330 Ω,
G = 1
f
V
= ±15 V
CC
−60
−70
V
= 5 V
CC
V
CC
= ±5 V
−80
V
CC
= ±15 V
−90
f = 16 MHz
R
R = 330 Ω,
G = 1
,
= 800 Ω,
L
−100
−110
f
V
CC
= ±5 V
100 k
1M
10 M
100 M
1
2
3
4
5
6
V
O
− Output Voltage − V
f − Frequency − Hz
Figure 9.
Figure 10.
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SLOS320F–MAY 2000–REVISED JANUARY 2006
TYPICAL CHARACTERISTICS (continued)
THIRD HARMONIC DISTORTION
THIRD HARMONIC DISTORTION
vs
vs
FREQUENCY
OUTPUT VOLTAGE
−30
−40
−71
−73
−75
−77
−79
−81
−83
−85
−87
−89
V
R
= 4 V
PP,
= 800 Ω,
O
f = 1 MHz
R = 800 Ω,
L
L
V
= ±5 V
CC
R = 330 Ω,
G = 1
f
R = 330 Ω,
f
G = 1
−50
−60
V
CC
= ±5 V
−70
V
CC
= 5 V
V
CC
= ±15 V
−80
−90
V
CC
= ±15 V
−100
−110
100 k
1M
10 M
100 M
1
1.5
2
2.5
3
3.5
4
4.5
5
f − Frequency − Hz
V
O
− Output Voltage − V
Figure 11.
Figure 12.
THIRD HARMONIC DISTORTION
vs
OUTPUT VOLTAGE
SETTLING TIME
−41
−43
−45
−47
−49
−51
−53
−55
−57
−59
−61
2.40
2.30
2.20
2.10
2
f = 16 MHz
= 800 Ω,
V
= ±5 V
R = 510 Ω,
CC
f
R
L
C = 1 pF,
F
R = 330 Ω,
f
V
O(PP)
= 4 V,
G = 1
V
CC
= 5 V,
Small Scale
19 ns to 1%
96 ns to 0.1%
304 ns to 0.01%
V
= ±15 V
1.90
1.80
1.70
CC
V
2
= 5 V
CC
1.60
1.50
0
50
100
150
200
250
300
1
3
4
5
6
V
O
− Output Voltage − V
t − Time − ns
Figure 13.
Figure 14.
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TYPICAL CHARACTERISTICS (continued)
VOLTAGE NOISE
vs
FREQUENCY
SINGLE-ENDED INPUT OFFSET VOLTAGE
vs
COMMON-MODE OUTPUT VOLTAGE
100
3
R = 1 kΩ,
f
R
L
= 800 Ω,
G = 1
2.5
V
CC
= ±5 V
V
CC
= ±2.5 V
2
10
1.5
1
V
CC
= ±15 V
0.5
0
1
10
100
1 K
10 K
100 K
−12 −9
−6
−3
0
3
6
9
12
f − Frequency − Hz
V
OCM
− Common-Mode Output Voltage − V
Figure 15.
Figure 16.
OUTPUT VOLTAGE
vs
DIFFERENTIAL LOAD RESISTANCE
OUTPUT IMPEDANCE
vs
FREQUENCY
15
100
10
1
R = 1 kΩ
G = 2
V
CC
= ±5 V
f
V
= ±15 V
= ±5 V
CC
CC
V
OUT+
10
5
V
V
OUT+
0
V
OUT−
−5
−10
−15
V
V
= − ±5 V
CC
0.1
V
OUT−
= − ±15 V
CC
0.01
100 k
1 M
10 M
100 M
1 G
100
1k
10 k
100 k
f − Frequency − Hz
R
L
− Differential Load Resistance − Ω
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS (continued)
INPUT BIAS CURRENT
vs
SUPPLY VOLTAGE
OUTPUT CURRENT RANGE
vs
SUPPLY VOLTAGE
90
80
70
60
50
40
30
20
10
6.50
6
T
A
= −40°C
T
A
= −40°C
T
A
= 25°C
5.50
5
T
A
= 85°C
T
A
= 85°C
T
A
= 25°C
4.50
4
3.50
3
0
11
13
15
1
3
5
7
9
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
V
CC
− Supply Voltage − ±V
V
CC
− Supply Voltage − ±V
Figure 19.
Figure 20.
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APPLICATION INFORMATION
RESISTOR MATCHING
Resistor matching is important in fully differential amplifiers. The balance of the output on the reference voltage
depends on matched ratios of the resistors. CMRR, PSRR, and cancellation of the second harmonic distortion
will diminish if resistor mismatch occurs. Therefore, it is recommended to use 1% tolerance resistors or better to
keep the performance optimized.
VOCM sets the dc level of the output signals. If no voltage is applied to the VOCM pin, it will be set to the midrail
voltage internally defined as:
ǒVCC)Ǔ ) ǒVCC–Ǔ
2
In the differential mode, the VOCM on the two outputs cancel each other. Therefore, the output in the differential
mode is the same as the input in the gain of 1. VOCM has a high bandwidth capability up to the typical operation
range of the amplifier. For the prevention of noise going through the device, use a 0.1 µF capacitor on the VOCM
pin as a bypass capacitor. Figure 21 shows the simplified diagram of the THS414x.
V
CC+
Output Buffer
V
IN-
x1
V
V
OUT+
C
R
R
V
IN+
Vcm Error
Amplifier
+
_
C
x1
OUT-
Output Buffer
V
CC+
30 kΩ
V
CC-
30 kΩ
V
CC-
V
OCM
Figure 21. THS414x Simplified Diagram
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APPLICATION INFORMATION (continued)
DATA CONVERTERS
Data converters are one of the most popular applications for the fully differential amplifiers. Figure 22 shows a
typical configuration of a fully differential amplifier attached to a differential ADC.
V
DD
V
CC
5 V
AV
DV
DD
DD
V
IN
+
-
-
A
A
IN1
V
OCM
IN2
+
0.1 µF
AV
V
ref
SS
-5 V
V -
CC
Figure 22. Fully Differential Amplifier Attached to a Differential ADC
Fully differential amplifiers can operate with a single supply. VOCM defaults to the midrail voltage, VCC/2. The
differential output may be fed into a data converter. This method eliminates the use of a transformer in the
circuit. If the ADC has a reference voltage output (Vref), then it is recommended to connect it directly to the VOCM
of the amplifier using a bypass capacitor for stability. For proper operation, the input common-mode voltage to
the input terminal of the amplifier should not exceed the common-mode input voltage range.
V
DD
V
CC
5 V
AV
DV
DD
DD
V
IN
+
-
-
A
A
IN1
V
OCM
IN2
+
0.1 µF
AV
V
ref
SS
Figure 23. Fully Differential Amplifier Using a Single Supply
Some single supply applications may require the input voltage to exceed the common-mode input voltage range.
In such cases, the following circuit configuration is suggested to bring the common-mode input voltage within the
specifications of the amplifier.
V
DD
V
CC
R
f
V
CC
R
PU
5 V
R
g
V
V
OUT
AV
DV
DD
DD
V
IN
+
-
-
V
P
A
A
IN
V
OCM
IN
+
0.1 µF
AV
V
ref
SS
R
g
OUT
R
PU
CC
V
R
f
Figure 24. Circuit With Improved Common-Mode Input Voltage
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APPLICATION INFORMATION (continued)
The following equation is used to calculate RPU
:
V
– V
P
ǒVIN PǓ ) ǒVCC
PǓ
R
+
PU
1
RG
1
RF
– V
– V
OUT
(1)
DRIVING A CAPACITIVE LOAD
Driving capacitive loads with high-performance amplifiers is not a problem as long as certain precautions are
taken. The first is to realize that the THS414x has been internally compensated to maximize its bandwidth and
slew rate performance. When the amplifier is compensated in this manner, capacitive loading directly on the
output will decrease the device's phase margin leading to high-frequency ringing or oscillations. Therefore, for
capacitive loads of greater than 10 pF, it is recommended that a resistor be placed in series with the output of
the amplifier, as shown in Figure 25. A minimum value of 20 Ω should work well for most applications. For
example, in 50-Ω transmission systems, setting the series resistor value to 50 Ω both isolates any capacitance
loading and provides the proper line impedance matching at the source end.
390 Ω
20 Ω
Output
390 Ω
THS414x
20 Ω
390 Ω
Output
390 Ω
Figure 25. Driving a Capacitive Load
ACTIVE ANTIALIAS FILTERING
For signal conditioning in ADC applications, it is important to limit the input frequency to the ADC. Low-pass
filters can prevent the aliasing of the high frequency noise with the frequency of operation. Figure 26 presents a
method by which the noise may be filtered in the THS414x.
C1
R2
V
CC
R4
+
C3
C3
R1
R1
R3
R3
-
+
V
-
V
V
+
IN
IN
R
(t)
THS414x
C2
THS1050
-
Vs
-
+
IN
V
+
IN
V
OCM
V
OCM
V
IC
R4
V -
CC
+
C1
R2
Figure 26. Antialias Filtering
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APPLICATION INFORMATION (continued)
The transfer function for this filter circuit is:
ȡ
ȣ
Rt
ȡ
ȧ
ȣ
2R4 ) Rt
K
R2
R1
ȧ
ȧx
ȧ
Where K +
H (f) + ȧ
j2πfR4RtC3ȧ
d
–ǒ
Ǔ2
jf
1 )
f
1
Ȣ
2R4 ) Rt Ȥ
)
) 1
FSF x fc
Q FSF x fc
(2)
(3)
Ǹ
2 x R2R3C1C2
R3C1 ) R2C1 ) KR3C1
1
FSF x fc +
and Q +
Ǹ
2π 2 x R2R3C1C2
K sets the pass band gain, fc is the cutoff frequency for the filter, FSF is a frequency-scaling factor, and Q is the
quality factor.
2
ǸRe2
|
|
) Im
2
2
ǸRe
|
|
FSF +
) Im
and Q +
2Re
(4)
Where Re is the real part, and Im is the imaginary part of the complex pole pair. Setting R2 = R, R3 = mR,
C1 = C, and C2 = nC results in:
Ǹ
2 x mn
1
FSF x fc +
and Q +
Ǹ
(
)
1 ) m 1 ) K
2πRC 2 x mn
(5)
Start by determining the ratios, m and n, required for the gain and Q of the filter type being designed, then select
C and calculate R for the desired fc.
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PRINCIPLES OF OPERATION
THEORY OF OPERATION
The THS414x is a fully differential amplifier. Differential amplifiers are typically differential in/single out, whereas
fully differential amplifiers are differential in/differential out.
Differential Amplifier
THS414x
Fully differential Amplifier
R
f
V
CC+
R
R
(g)
_
_
+
V
V
V
IN-
O+
+
_
V
IN+
O-
+
(g)
R
f
V
OCM
V
CC-
Figure 27. Differential Amplifier Versus a Fully Differential Amplifier
To understand the THS414x fully differential amplifiers, the definition for the pinouts of the amplifier are
provided.
ǒV Ǔ ǒV Ǔ
)
I)
I–
ǒVIǓ – ǒVI–Ǔ
Input voltage definition
V
+
V
+
ID
IC
2
(6)
ǒVO)Ǔ ) ǒVO–Ǔ
ǒVO)Ǔ – ǒVO–Ǔ
Output voltage definition
V
+
V
+
OD
OC
2
(7)
Transfer function
V
+
V
x A
ǒ Ǔ
OD
ID
f
(8)
(9)
Output common mode voltage V
+
V
OC
OCM
Differential Structure Rejects
Coupled Noise at the Input
Differential Structure Rejects
Coupled Noise at the Output
V
CC+
_
V
V
V
IN-
O+
+
_
V
IN+
O-
+
V
OCM
Differential Structure Rejects
Coupled Noise at the Power Supply
V
CC-
Figure 28. Definition of the Fully Differential Amplifier
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PRINCIPLES OF OPERATION (continued)
The following schematics depict the differences between the operation of the THS414x, fully differential
amplifier, in two different modes. Fully differential amplifiers can work with differential input or can be
implemented as single in/differential out.
R
f
V
CC+
R
(g)
(g)
V
IN-
-
V
V
O+
+
-
Vs
+
O-
V
IN+
V
OCM
R
Note: For proper operation, maintain
symmetry by setting
V
CC-
R 1 = R 2 = R and R 1 = R 2 = R
(g)
f
f
f
(g)
(g)
A = R /R
f
(g)
R
f
Figure 29. Amplifying Differential Signals
R
f
V
CC+
R
R
(g)
V
RECOMMENDED RESISTOR VALUES
IN-
GAIN
R
Ω
R Ω
-
V
V
(g)
f
O+
+
-
1
2
5
10
390
374
402
402
390
750
2010
4020
+
O-
V
IN+
V
OCM
(g)
Vs
V
CC-
R
f
Figure 30. Single In With Differential Out
If each output is measured independently, each output is one-half of the input signal when gain is 1. The
following equations express the transfer function for each output:
1
2
V
+
V
O
I
(10)
The second output is equal and opposite in sign:
1
2
V
+ –
V
O
I
(11)
Fully differential amplifiers may be viewed as two inverting amplifiers. In this case, the equation of an inverting
amplifier holds true for gain calculations. One advantage of fully differential amplifiers is that they offer twice as
much dynamic range compared to single-ended amplifiers. For example, a 1-VPP ADC can only support an input
signal of 1 VPP. If the output of the amplifier is 2 VPP, then it will not be practical to feed a 2-VPP signal into the
targeted ADC. Using a fully differential amplifier enables the user to break down the output into two 1-VPP
signals with opposite signs and feed them into the differential input nodes of the ADC. In practice, the designer
has been able to feed a 2-V peak-to-peak signal into a 1-V differential ADC with the help of a fully differential
amplifier. The final result indicates twice as much dynamic range. Figure 31 illustrates the increase in dynamic
range. The gain factor should be considered in this scenario. The THS414x fully differential amplifier offers an
improved CMRR and PSRR due to its symmetrical input and output. Furthermore, second harmonic distortion is
improved. Second harmonics tend to cancel because of the symmetrical output.
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PRINCIPLES OF OPERATION (continued)
a
V = 1-0 = 1
OD
V
CC+
+1
_
V
V
V
IN-
O+
+
_
0
V
+1
IN+
O-
+
0
V
OCM
V
OD
= 0-1 = -1
V
CC-
b
Figure 31. Fully Differential Amplifier With Two 1-VPP Signals
Similar to the standard inverting amplifier configuration, input impedance of a fully differential amplifier is
selected by the input resistor, R(g). If input impedance is a constraint in design, the designer may choose to
implement the differential amplifier as an instrumentation amplifier. This configuration improves the input
impedance of the fully differential amplifier. Figure 32 depicts the general format of instrumentation amplifiers.
The general transfer function for this circuit is:
V
R
OD
– V
f
2R2
R1
ǒ1 )
Ǔ
+
V
R
IN1
IN2
(g)
(12)
THS4012
R
(g)
R
f
+
_
V
IN1
R2
_
+
R1
R2
THS414x
_
+
V
IN2
R
(g)
R
f
THS4012
Figure 32. Instrumentation Amplifier
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PRINCIPLES OF OPERATION (continued)
CIRCUIT LAYOUT CONSIDERATIONS
To achieve the levels of high frequency performance of the THS414x, follow proper printed-circuit board high
frequency design techniques. A general set of guidelines is given below. In addition, a THS414x evaluation
board is available to use as a guide for layout or for evaluating the device performance.
•
Ground planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this
distance increases, the inductance in the connecting trace makes the capacitor less effective. The designer
should strive for distances of less than 0.1 inches (2,54 mm) between the device power terminals and the
ceramic capacitors.
•
•
Sockets—Sockets are not recommended for high-speed operational amplifiers. The additional lead
inductance in the socket pins will often lead to stability problems. Surface-mount packages soldered directly
to the printed-circuit board is the best implementation.
Short trace runs/compact part placements—Optimum high frequency performance is achieved when stray
series inductance has been minimized. To realize this, the circuit layout should be made as compact as
possible, thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting
input of the amplifier. Its length should be kept as short as possible. This will help to minimize stray
capacitance at the input of the amplifier.
•
Surface-mount passive components—Using surface-mount passive components is recommended for high
frequency amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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PRINCIPLES OF OPERATION (continued)
POWER-DOWN MODE
The power-down mode is used when power saving is required. The power-down terminal (PD) found on the
THS414x is an active low terminal. If it is left as a no-connect terminal, the device will always stay on due to an
internal 50 kΩ resistor to VCC. The threshold voltage for this terminal is approximately 1.4 V above VCC–. This
means that if the PD terminal is 1.4 V above VCC–, the device is active. If the PD terminal is less than 1.4 V
above VCC–, the device is off. For example, if VCC– = –5 V, then the device is on when PD reaches 3.6 V, (–5 V
+ 1.4 V = –3.6 V). By the same calculation, the device is off below –3.6 V. It is recommended to pull the terminal
to VCC– in order to turn the device off. Figure 33 shows the simplified version of the power-down circuit. While in
the power-down state, the amplifier goes into a high-impedance state. The amplifier output impedance is
typically greater than 1 MΩ in the power-down state.
V
CC
50 kΩ
To Internal Bias
Circuitry Control
PD
V
CC-
Figure 33. Simplified Power-Down Circuit
Due to the similarity of the standard inverting amplifier configuration, the output impedance appears to be very
low while in the power-down state. This is because the feedback resistor (Rf) and the gain resistor (R(g)) are still
connected to the circuit. Therefore, a current path is allowed between the input of the amplifier and the output of
the amplifier. An example of the closed-loop output impedance is shown in Figure 34.
OUTPUT IMPEDANCE (IN SHUTDOWN)
vs
FREQUENCY
2200
V
CC
= ±5 V,
V = 0.8 V RMS
I
PP
CC-
PD = V
1200
200
10 k
100 k
1 M
10 M
100 M
f - Frequency - Hz
Figure 34.
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PRINCIPLES OF OPERATION (continued)
GENERAL PowerPAD DESIGN CONSIDERATIONS
The THS414x is available packaged in a thermally-enhanced DGN package, which is a member of the
PowerPAD family of packages. This package is constructed using a downset leadframe upon which the die is
mounted [see Figure 35(a) and Figure 35(b)]. This arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see Figure 35(c)]. Because this thermal pad has direct thermal
contact with the die, excellent thermal performance can be achieved by providing a good thermal path away
from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of assembly of the
surface mount with the, heretofore, awkward mechanical methods of heatsinking.
More complete details of the PowerPAD installation process and thermal management techniques can be found
in the Texas Instruments Technical Brief, PowerPAD Thermally Enhanced Package (SLMA002). This document
can be found at the TI web site (www.ti.com) by searching on the key word PowerPAD. The document can also
be ordered through your local TI sales office. Refer to literature number SLMA002 when ordering.
DIE
Side View (a)
Thermal
Pad
DIE
End View (b)
Bottom View (c)
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 35. Views of Thermally Enhanced DGN Package
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PACKAGING INFORMATION
Orderable Device
THS4140CD
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
4140C
THS4140CDG4
THS4140CDGN
THS4140CDGNG4
THS4140ID
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
75
80
Green (RoHS
& no Sb/Br)
0 to 70
4140C
AOF
MSOP-
PowerPAD
DGN
DGN
D
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
0 to 70
AOF
SOIC
75
Green (RoHS
& no Sb/Br)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
0 to 70
4140I
4140I
ASQ
THS4140IDG4
THS4140IDGK
THS4140IDGKG4
THS4140IDGN
THS4140IDGNG4
THS4140IDGNR
THS4140IDGNRG4
THS4141CD
SOIC
D
75
Green (RoHS
& no Sb/Br)
VSSOP
VSSOP
DGK
DGK
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
80
Green (RoHS
& no Sb/Br)
ASQ
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AOG
AOG
AOG
AOG
4141C
4141C
ATS
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
2500
2500
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
THS4141CDG4
SOIC
D
75
Green (RoHS
& no Sb/Br)
0 to 70
THS4141CDGK
THS4141CDGKG4
THS4141CDGN
OBSOLETE
OBSOLETE
ACTIVE
VSSOP
VSSOP
DGK
DGK
DGN
8
8
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
MSOP-
PowerPAD
80
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AOI
AOI
THS4141CDGNG4
ACTIVE
MSOP-
DGN
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
PowerPAD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
THS4141CDGNR
ACTIVE
MSOP-
PowerPAD
DGN
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
AOI
AOI
THS4141CDGNRG4
ACTIVE
MSOP-
DGN
2500
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
0 to 70
PowerPAD
THS4141CDRG4
THS4141ID
OBSOLETE
ACTIVE
SOIC
SOIC
D
D
8
8
TBD
Call TI
Call TI
0 to 70
4141C
4141I
75
75
80
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
THS4141IDG4
THS4141IDGK
THS4141IDGKG4
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
4141I
ASR
ASR
ASR
VSSOP
VSSOP
DGK
DGK
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
THS4141IDGKR
THS4141IDGKRG4
THS4141IDGN
OBSOLETE
OBSOLETE
ACTIVE
VSSOP
VSSOP
DGK
DGK
DGN
8
8
8
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AOK
AOK
AOK
AOK
4141I
4141I
THS4141IDGNG4
THS4141IDGNR
THS4141IDGNRG4
THS4141IDR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
DGN
D
8
8
8
8
8
80
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
MSOP-
PowerPAD
2500
2500
2500
2500
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
SOIC
Green (RoHS
& no Sb/Br)
THS4141IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
2500
2500
2500
2500
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4140IDGNR
THS4141CDGNR
THS4141IDGNR
THS4141IDR
MSOP-
Power
PAD
DGN
DGN
DGN
D
8
8
8
8
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
5.3
5.3
5.3
6.4
3.4
3.4
3.4
5.2
1.4
1.4
1.4
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
MSOP-
Power
PAD
MSOP-
Power
PAD
SOIC
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4140IDGNR
THS4141CDGNR
THS4141IDGNR
THS4141IDR
MSOP-PowerPAD
MSOP-PowerPAD
MSOP-PowerPAD
SOIC
DGN
DGN
DGN
D
8
8
8
8
2500
2500
2500
2500
358.0
358.0
358.0
367.0
335.0
335.0
335.0
367.0
35.0
35.0
35.0
35.0
Pack Materials-Page 2
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