THS4304-SP [TI]
RAD-TOLERANT CLASS V, WIDEBAND OPERATIONAL AMPLIFIER; RAD容错V类，宽带运算放大器
| 型号： | THS4304-SP |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | RAD-TOLERANT CLASS V, WIDEBAND OPERATIONAL AMPLIFIER |
| 文件： | 总22页 (文件大小：836K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4304-SP
www.ti.com
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
RAD-TOLERANT CLASS V, WIDEBAND OPERATIONAL AMPLIFIER
1
FEATURES
DESCRIPTION/ORDERING INFORMATION
•
Wide Bandwidth: 1 GHz
The THS4304 is
a wideband, voltage-feedback
operational amplifier designed for use in high-speed
analog signal processing chains operating with a
single 5 V power supply. Developed in the BiCom3
silicon germanium process technology, the THS4304
offers best-in-class performance using a single 5 V
supply as opposed to previous generations of
operational amplifiers requiring ±5 V supplies.
•
•
•
•
•
•
•
Minimum Gain of 2 V/V (6 dB)
High Slew Rate: 800 V/μs
Low Voltage Noise: 2.4 nV/√Hz
Single Supply: 5 V, 3 V
Quiescent Current: 18 mA
Rad-Tolerant: 150 kRad (Si) TID
QML-V Qualified, SMD 5962-07219
The THS4304 is
a traditional voltage-feedback
topology that provides the following benefits:
balanced inputs, low offset voltage and offset current,
low offset drift, high common mode and power supply
rejection ratio.
APPLICATIONS
•
•
•
•
•
Active Filter
ADC Driver
Ultrasound
Gamma Camera
RF/Telecom
The THS4304 is offered in 10-pin ceramic flatpack
(U) and is specified over the full military temperature
range, –55°C to 125°C.
DIFFERENTIAL ADC DRIVE
From
50 W
Source
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
THS4304-SP
www.ti.com
SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
These devices have limited built in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
U PACKAGE
TOP VIEW
10
9
8
7
6
VS–
5
NC – No internal connection
ORDERING INFORMATION(1)
TRANSPORT MEDIA,
QUANTITY
PACKAGED DEVICES
PACKAGE TYPE(2)
PACKAGE MARKINGS
0721901VHA
5962-0721901VHA
Ceramic Flatpack
Tubes, 25
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DISSIPATION RATINGS
POWER RATING(1)
θJC
(°C/W)
θJA
(°C/W)
PACKAGE
TA ≤ 25°C
TA = 85°C
TA = 125°C
U (10)
14.7
189
661 mW
344 mW
132 mW
(1) Power rating determined for a maximum junction temperature of 150°C. However, distortion starts to substantially increase above
125°C. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance
and long-term reliability.
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
VS
VI
Supply voltage
+6.0 V
Input voltage
±VS
IO
Output current
150 mA
VID
Differential input voltage
Continuous power dissipation
Maximum junction temperature, any condition(2)
Storage temperature range
HBM
±2 V
See Dissipation Rating Table
150°C
TJ
Tstg
–65°C to 150°C
1600 V
ESD Ratings
CDM
MM
1000 V
100 V
(1) The absolute maximum ratings under any condition is limited by the constraints of the silicon process. Stresses above these ratings may
cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied.
(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
2
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN
±1.35
2.7
MAX UNIT
Dual supply
±2.5
V
Supply voltage, (VS+ and VS–
)
Single supply
5
Input common-mode voltage range
VS– – 0.2 VS+ + 0.2
V
ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
Specifications: VS = 5 V: RF = 249 Ω, RL = 100 Ω, and G = +3 unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
CONDITIONS
–55°C to
UNITS
125°C
MIN/
MAX
25°C
25°C
AC PERFORMANCE
G = +2, VO = 100 mVpp
1
GHz
MHz
MHz
GHz
Typ
Typ
Typ
Typ
Small-Signal Bandwidth
G = +3, VO = 100 mVpp
G = +5, VO = 100 mVpp
G > +5
800
220
1
Gain Bandwidth Product
0.1 dB Flat Bandwidth
G= +3, VO = 100 mVpp,
CF = 0 pF
100
MHz
Typ
Large-Signal Bandwidth
Slew Rate
G = +3, VO = 2 VPP
290
800
11
MHz
V/μs
ns
Typ
Typ
Typ
Typ
G = +3, VO = 2-V Step
G = +3, VO = 2-V Step
G = +3, VO = 2-V Step
Settling Time to 1%
Rise/Fall Times
2.5
ns
Harmonic Distortion
RL= 100 Ω
RL = 1 kΩ
RL = 100 Ω
RL = 1 kΩ
–67
–85
dBc
dBc
dBc
dBc
Typ
Typ
Typ
Typ
Second Harmonic
Distortion
G = +3,
VO = 2 VPP
f = 10 MHz
,
–100
–85
Third Harmonic Distortion
Third-Order Intermodulation
Distortion (IMD3)
–80
41
dBc
Typ
Typ
G = +3, VO= 2-VPP envelope,
200 kHz tone spacing,
f = 20 MHz
Third-Order Output Intercept
(OIP3)
dBm
Noise Figure
G = +2, f = 1 GHz
f = 1 MHz
15
2.4
2.1
dB
Typ
Typ
Typ
Input Voltage Noise
Input Current Noise
nV/√Hz
pA/√Hz
f = 1 MHz
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
Specifications: VS = ±2.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
CONDITIONS
–55°C to
125°C
MIN/
MAX
25°C
25°C
UNITS
DC PERFORMANCE
Open-Loop Voltage Gain
VO = ±0.8 V
58
54
4
49
dB
Min
(AOL
)
Input Offset Voltage
0.5
6
5
mV
μV/°C
μA
Max
Typ
Max
Typ
Max
Typ
Input Offset Voltage Drift
Input Bias Current
7
12
1
20
50
1.5
10
VO = 0 V
Input Bias Current Drift
Input Offset Current
nA/°C
μA
0.5
Input Offset Current Drift
INPUT CHARACTERISTICS
Common-Mode Input Range
nA/°C
±2.7
86
±2.3
78
±2
52
V
Min
Min
Common-Mode Rejection
Ratio
VO = 0 V, VCM = ±1 V
dB
Input Resistance
100
1.5
kΩ
Typ
Typ
Each input, referenced to GND
Input Capacitance
pF
OUTPUT CHARACTERISTICS
RL = 100 Ω
RL = 1 kΩ
RL = 10 Ω
RL = 10 Ω
f = 100 kHz
±1.4
±1.5
98
±1.3
±1.4
80
±1.15
±1.25
70
Output Voltage Swing
V
Min
Output Current (Sourcing)
Output Current (Sinking)
Output Impedance
mA
mA
Ω
Min
Min
Typ
95
70
55
0.016
POWER SUPPLY
Maximum Operating Voltage
Minimum Operating Voltage
±2.5
±2.5
18
±2.75
±1.35
18.9
±2.75
±1.35
19.7
Max
Min
Max
Min
V
Maximum Quiescent Current IO = 0 mA
Minimum Quiescent Current IO = 0 mA
Power Supply Rejection
mA
mA
18
17.5
16.0
VS+ = 3 V to 2 V, VS– = –2.5 V
78
60
72
57
64
53
dB
dB
Min
Min
(+PSRR)
Power Supply Rejection
(–PSRR)
VS+ = 2.5 V, VS– = –2 V to –3 V
4
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
Specifications: VS = 3 V: RF = 249 Ω, RL = 500 Ω, and G = +3 unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
CONDITIONS
MIN/
MAX
25°C
25°C
–55°C to 125°C
UNITS
AC PERFORMANCE
G = +2, VO = 100 mVpp
G = +5, VO = 100 mVpp
G > +5
1
GHz
MHz
GHz
V/μs
ns
Typ
Typ
Typ
Typ
Typ
Small-Signal Bandwidth
230
1
Gain Bandwidth Product
Slew Rate
G = +3, VO = 1-V Step
G = +3, VO = 0.5-V Step
675
1.5
Rise/Fall Times
HARMONIC DISTORTION
Second Harmonic Distortion G = +3,
–82
–82
dBc
dBc
Typ
Typ
VO = 0.5 VPP
f = 10 MHz
,
RL = 499 Ω
Third Harmonic Distortion
Noise Figure
G = +2, f = 1 GHz
f = 1 MHz
15
2.4
2.1
dB
Typ
Typ
Typ
Input Voltage Noise
Input Current Noise
nV/√Hz
pA/√Hz
f = 1 MHz
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
ELECTRICAL CHARACTERISTICS (Unchanged after 150 kRad)
Specifications: VS = ±1.5 V, VCM = 0 V, RL = 500 Ω unless otherwise noted
TYP
OVER TEMPERATURE
PARAMETER
CONDITIONS
MIN/
MAX
25°C
25°C
–55°C to 125°C
UNITS
DC PERFORMANCE
Open-Loop Voltage Gain (AOL
)
VO = ±0.3 V
57
1
52
4
50
6
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
5
μV/°C
μA
6
12
1
20
50
1.5
10
VO = 0 V
Input Bias Current Drift
Input Offset Current
nA/°C
μA
0.4
Input Offset Current Drift
INPUT CHARACTERISTICS
Common-Mode Input Range
nA/°C
±1.7
68
±1.3
62
±1
50
V
Min
Min
Common-Mode Rejection
Ratio
VO = 0 V, VCM = ±0.3 V
dB
Input Resistance
100
1.5
kΩ
Typ
Typ
Each input, referenced to GND
Input Capacitance
pF
OUTPUT CHARACTERISTIC
RL = 100 Ω
RL = 1 kΩ
RL = 10 Ω
RL = 10 Ω
f = 100 kHz
±0.4
±0.5
30
±0.3
±0.4
25
±0.2
±0.3
20
Output Voltage Swing
V
Min
Output Current (Sourcing)
Output Current (Sinking)
Output Impedance
mA
mA
Ω
Min
Min
Typ
32
27
21
0.016
POWER SUPPLY
Maximum Operating Voltage
Minimum Operating Voltage
Maximum Quiescent Current
Minimum Quiescent Current
±1.5
±1.5
17.2
17.2
±2.75
±1.35
17.9
±2.75
±1.35
18.6
Max
Min
Max
Min
V
IO = 0 mA
IO = 0 mA
mA
mA
16.5
15.0
Power Supply Rejection
(+PSRR)
VS+ = 1.8 V to 1.2 V, VS– = –1.5 V
VS+ = 1.5 V, VS– = –1.2 V to –1.8 V
80
60
60
55
53
52
dB
dB
Min
Min
Power Supply Rejection
(–PSRR)
6
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
5 V
Frequency Response
1 through 3, 5, 6
0.1 dB Flatness
4
7
S-Parameters
vs Frequency
2nd Harmonic Distortion
3rd Harmonic Distortion
Harmonic Distortion
3rd Order Intermodulation Distortion
3rd Order Output Intercept Point
Slew Rate
vs Frequency
8, 10
9, 11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
vs Frequency
vs Output voltage
vs Frequency
IMD3
OIP3
SR
vs Frequency
vs Output voltage
vs Frequency
Vn/In
Noise
Noise Figure
vs Frequency
Iq
Quiescent Current
vs Supply voltage
vs Frequency
Rejection Ratio
VO
Output Voltage
vs Load resistance
vs Input common-mode voltage
vs Case temperature
vs Case temperature
VOS
IIB/IIO
VOS
VO
Input Offset Voltage
Input Bias and Offset Current
Input Offset Voltage
Small-signal Transient Response
Large-signal Transient Response
Settling Time
VO
VO
VO
Overdrive Recovery Time
3 V
Frequency Response
Harmonic Distortion
Harmonic Distortion
Slew Rate
28 through 30
vs Frequency
31
32
33
34
35
36
vs Output voltage
vs Output voltage
vs Load resistance
vs Case temperature
vs Case temperature
SR
VO
Output Voltage
IIB/IIO
VOS
Input Bias and Offset Current
Input Offset Voltage
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (5 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
VO = 100 mVP-P
Gain = 2,
Gain = 2,
G = 2
CF = 0 pF
RF = 249 W,
RL = 100W,
VS = 5 V
VO = 100 mVpp
RF = 249 W,
RL = 100 W,
VS = 5 V
,
CF = 0.5 pF
G = 3
G = 5
VO = 1 VP-P
CF = 1 pF
VO = 2 VP-P
VO = 100 mVpp
,
RF = 249 W,
RL = 100 W,
VS = 5 V
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 1.
Figure 2.
Figure 3.
0.1 dB FLATNESS
FREQUENCY RESPONSE
FREQUENCY RESPONSE
Gain = 3,
VO = 100 mVpp
,
G = 5
G = 3
RF = 249 W,
RL = 100 W,
VS = 5 V
G = 5
G = 3
G = 2
VO = 1 Vpp
,
RF = 249 W,
RL = 100 W,
VS = 5 V
VO = 2 Vpp
,
RF = 249 W,
RL = 100 W,
VS = 5 V
G = 2
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
1 M
10 M
100 M
1 G
10 G
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 4.
Figure 5.
Figure 6.
S-PARAMETERS
vs
FREQUENCY
2nd-HARMONIC DISTORTION
3rd-HARMONIC DISTORTION
vs
vs
FREQUENCY
FREQUENCY
Gain = 3,
VO = 2 Vpp
Gain = 3,
VO = 2 Vpp
,
,
RF = 249 W,
S22
S21
RF = 249 W,
VS = 5 V
RL = 100
VS = 5 V
RL = 100
S12
S11
RL = 1 K
Gain = 3,
VO = 100 mVpp
RF = 249 W,
RL = 100 W,
VS = 5 V
,
RL = 1 K
1 M
10 M
100 M
1 G
10 G
f – Frequency – MHz
f – Frequency – MHz
f – Frequency – Hz
Figure 7.
Figure 8.
Figure 9.
8
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (5 V) (continued)
2nd-HARMONIC DISTORTION
3rd-HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
OUTPUT VOLTAGE
Gain = 3,
VO = 1 Vpp
Gain = 3,
VO = 1 Vpp
Gain = 3,
,
,
RF = 249 W,
RL = 100 W,
VS = 5 V
RF = 249 W,
RF = 249 W,
VS = 5 V
VS = 5 V
RL = 100
HD3
f = 10 MHz
HD2
RL = 1 K
RL = 1 K
RL = 100
f – Frequency – MHz
f – Frequency – MHz
Output Voltage – Vpp
Figure 10.
Figure 11.
Figure 12.
3rd-ORDER INTERMODULATION
3rd-ORDER OUTPUT INTERCEPT
DISTORTION
vs
POINT
vs
SLEW RATE
vs
OUTPUT VOLTAGE
FREQUENCY
FREQUENCY
900
850
800
750
700
650
600
550
500
450
400
Gain = 2,
Gain = 3,
RF = 249 Ω,
R
R
= 249 Ω,
= 100 Ω,
= 5 V
F
L
S
VO = 1 VPP
envelope
RL = 100 Ω,
V
200 kHz spacing,
VS = 5 V
VO = 1 VPP
envelope
Rise
VO = 2 VPP
envelope
Fall
VO = 2 VPP
envelope
VS = 5 V
Gain = 3,
RF = 249 W,
RL = 100 W,
200 kHz spacing
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage −V
O
PP
f – Frequency – MHz
f – Frequency – MHz
Figure 13.
Figure 14.
Figure 15.
NOISE
vs
FREQUENCY
NOISE FIGURE
vs
FREQUENCY
QUIESCENT CURRENT
vs
SUPPLY VOLTAGE
22
20
1000
T
= 85°C
A
T
A
= 125°C
20
18
16
14
12
10
8
18
16
14
12
10
8
T
= 25°C
100
A
T
A
= -40°C
T
= -55°C
A
I
n
10
1
6
Gain = 2,
6
R
F
R
G
R
L
= 249 Ω,
= 249 Ω,
= 100 Ω,
= 5 V
V
4
n
4
2
2
V
S
0
0
10
100
1 k
10 k 100 k 1 M 10 M
500 M
1 G
10 M
2.5
3.5
4.5
2
3
4
5
f − Frequency − Hz
V
− Supply Voltage − V
f − Frequency − Hz
S
Figure 16.
Figure 17.
Figure 18.
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (5 V) (continued)
REJECTION RATIO
vs
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT OFFSET VOLTAGE
vs
FREQUENCY
INPUT COMMON-MODE VOLTAGE
4
110
100
90
5
V
= 5 V
S
CMRR
4.5
V = 5 V
S
3.5
3
PSRR+
4
80
3.5
70
3
2.5
2
V
= 5 V
S
60
50
2.5
PSRR−
40
30
20
10
0
2
1.5
1
1.5
1
0.5
0
10
100
1000
−1
0
1
2
3
4
5
6
10 k
100 k
1 M
10 M
100 M
1 G
f − Frequency − Hz
R
L
− Load Resistance − Ω
V
− Input Common-Mode Range − V
ICR
Figure 19.
Figure 20.
Figure 21.
INPUT BIAS AND OFFSET
CURRENT
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
vs
SMALL-SIGNAL
TRANSIENT RESPONSE
CASE TEMPERATURE
VS = 5 V
VS = 5 V
Input
IIO
IIB–
Output
IIB
Gain = 3,
RF = 249 W,
RL = 100 W,
VS = 5 V
Case Temperature – °C
Time – ns
Case Temperature – °C
Figure 22.
Figure 23.
Figure 24.
LARGE-SIGNAL
TRANSIENT RESPONSE
OVERDRIVE
RECOVERY TIME
SETTLING TIME
Input
Input
Output
Output
Gain = 3,
RF = 249 W,
Gain = 3,
RF = 249 W,
Gain = 3,
RL = 100 W,
RF = 249 W,
RL = 100 W,
VS = 5 V
RL = 100 W,
VO = 2 VPP
VS = 5 V
VS = 5 V
Time – µs
Time – ns
Time – ns
Figure 25.
Figure 26.
Figure 27.
10
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
TYPICAL CHARACTERISTICS (3 V)
FREQUENCY RESPONSE
FREQUENCY RESPONSE
FREQUENCY RESPONSE
15
10
5
15
Gain = 2,
VO = 100 mV
Gain = 2,
RF = 249 W,
G = 5
VO = 100 mVpp
RF = 249 W,
RL = 499 W,
VS = 3 V
,
CF = 0 pF
RL = 499 W,
VO = 200 mV
VS = 3 V
10
VO = 500 mV
CF = 0.5 pF
G = 2
CF = 1 pF
5
VO = 100 mVpp
RF = 249 W,
RL = 499 W,
VS = 3 V
,
0
0
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
1 M
10 M
100 M
1 G
10 G
f – Frequency – Hz
f – Frequency – Hz
Figure 30.
f – Frequency – Hz
Figure 28.
Figure 29.
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
SLEW RATE
vs
OUTPUT VOLTAGE
vs
FREQUENCY
OUTPUT VOLTAGE
-40
900
850
800
750
700
650
600
550
500
450
400
Gain = 3,
Gain = 3,
RF = 249 W,
RL = 499 W,
Gain = 2,
Rise
RF = 249 W,
RL = 499 W,
VO = 500 mVpp
VS = 3 V
-50
R
R
= 249 Ω,
= 499 Ω,
= 3 V
F
L
S
,
f = 10 MHz,
VS = 3 V
V
-60
-70
HD2
Fall
HD3
-80
-90
HD2
HD3
-100
-110
1
10
100
0
0.1
0.2
0.3
0.4
0.5
0.6
f – Frequency – MHz
V
− Output Voltage − V
O
PP
Output Voltage – Vpp
Figure 31.
Figure 32.
Figure 33.
INPUT BIAS AND
OFFSET CURRENT
vs
OUTPUT VOLTAGE
vs
LOAD RESISTANCE
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
CASE TEMPERATURE
2.25
V
= 3 V
Vs = 3 V
S
IIB+
2
1.75
1.5
IIB-
IIO
1.25
1
0.75
0.5
Vs = 3 V
10
100
1000
TC – Case Temperature – °C
R
L
− Load Resistance − W
TC – Case Temperature – °C
Figure 34.
Figure 35.
Figure 36.
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
APPLICATION INFORMATION
For many years, high-performance analog design has required the generation of split power supply voltages, like
±15 V, ±8 V, and more recently ±5 V, to realize the full performance of the amplifiers available. Modern trends in
high-performance analog are moving toward single-supply operation at 5 V, 3 V, and lower. This reduces
power-supply cost due to less voltage being generated and conserves energy in low-power applications. It also
can take a toll on available dynamic range, a valuable commodity in analog design, if the available voltage swing
of the signal also must be reduced.
Two key figures of merit for dynamic range are signal-to-noise ratio (SNR) and spurious free dynamic range
(SFDR).
SNR is simply the signal level divided by the noise:
Signal
Noise
SNR +
and SFDR is the signal level divided by the highest spur:
Signal
SFDR +
Spur
In an operational amplifier, reduced supply voltage typically results in reduced signal levels due to lower voltage
available to operate the transistors within the amplifier. When noise and distortion remain constant, the result is a
commensurate reduction in SNR and SFDR. To regain dynamic range, the process and the architecture used to
make the operational amplifier must have superior noise and distortion performance with lower power supply
overhead required for proper transistor operation.
The THS4304 BiCom3 operational amplifier is just such a device. It is able to provide 2 Vpp signal swing at its
output on a single 5 V supply with noise and distortion performance similar to the best 10 V operational amplifiers
on the market today
GENERAL APPLICATION
The THS4304 is a traditional voltage-feedback topology with wideband performance up to 1 GHz at a gain of
2 V/V. Care must be taken to ensure that parasitic elements do not erode the phase margin.
Capacitance at the output and inverting input, and resistance and inductance in the feedback path, can cause
problems.
To reduce parasitic capacitance, the ground plane should be removed from under the part. To reduce inductance
in the feedback, the circuit traces should be kept as short and direct as possible.
For a gain of +2V/V, it is recommended to use a 249 Ω feedback resistor. With good layout, this should keep the
frequency response peaking to around 6 dB. This resistance is high enough to not load the output excessively,
and the part is capable of driving 100 Ω load with good performance. Higher-value resistors can be used, with
more peaking. Lower-value feedback resistors also can be used to reduce peaking, but degrade the distortion
performance with heavy loads.
Power supply bypass capacitors are required for proper operation. The most critical are 0.1 μF ceramic
capacitors; these should be placed as close to the part as possible. Larger bulk capacitors can be shared with
other components in the same area as the operational amplifier.
HARMONIC DISTORTION
For best second harmonic (HD2), it is important to use a single-point ground between the power supply bypass
capacitors when using a split supply. It also is recommended to use a single ground or reference point for input
termination and gain-setting resistors (R8 and R11 in the non-inverting circuit). It is recommended to follow the
EVM layout closely in your application.
12
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
EVALUATION MODULES
The THS4304 has two evaluation modules (EVMs) available. One is for the MSOP (DGK) package and the other
for the SOT-23 (DBV) package. These provide a convenient platform for evaluating the performance of the part
and building various different circuits. The full schematics, board layout, and bill of materials (as supplied) for the
boards are shown in the following illustrations.
−V
S
GND GND +V
S
J3
J4
J6
J5
−V
S
+V
S
FB1
FB2
V
REF
R3
R6
+V
S
C5
C1
C2
C4
GND
TP1
C3
R7
R8
R9
C8
−V
S
+V
S
*
C6
+V
S
U1
C9
J2
4
3
5
R2
THS4304
R1
C7
J1
1
R10
2
*
R12
R11
−V
S
V
REF
*C6 − DGK EVM Only
*R12 − DBV EVM Only
Figure 37. EVM Full Schematic
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
EVM BILL OF MATERIALS
THS4304 EVM(1)
SMD
Reference
Designator
PCB
Quantity
Manufacturer's
Part Number
Distributor's
Part Number
Item
Description
Size
1206
1206
1
FB1, FB2
2
2
2
(STEWARD)
HI1206N800R-00
(DIGI-KEY)
240-1010-1-ND
Bead, ferrite, 3 A, 80 Ω
2
3
Capacitor, 3.3 μF, Ceramic
C1, C2
C4, C5
(AVX) 1206YG335ZAT2A
(GARRETT)
1206YG335ZAT2A
Capacitor, 0.1 μF, Ceramic
0603
(AVX) 0603YC104KAT2A
(GARRETT)
0603YC104KAT2A
4
5
Open
Open
0603
0603
C3, C6(2)
2
5
R1, R3, R6,
R9, R12(3)
6
7
8
9
Resistor, 0 Ω, 1/10 W, 1%
Resistor, 49.9 Ω, 1/10 W, 1%
Resistor, 249 Ω, 1/10 W, 1%
0603
0603
0603
C7. C8, C9,
C10
4
2
2
4
(KOA) RK73Z1JTTD
(GARRETT)
RK73Z1JTTD
R2, R11
(KOA) RK73H1JLTD49R9F
(KOA) RK73H1JLTD2490F
(HH SMITH) 101
(GARRETT)
RK73H1JLTD49R9F
R7, R8
(GARRETT)
RK73H1JLTD2490F
Jack, banana recepticle, 0.25 in.
diameter hole
J3, J4, J5, J6
(NEWARK) 35F865
10 Test point, black
TP1
J1, J2
U1
1
2
1
(KEYSTONE) 5001
(DIGI-KEY) 5001K-ND
(NEWARK) 90F2624
11 Connector, edge, SMA PCB jack
12 Integrated Circuit, THS4304
(JOHNSON) 142-0701-801
(TI) THS4304DGK, or
(TI) THS4304DBV
13 Standoff, 4-40 HEX, 0.625 in.
Length
4
(KEYSTONE) 1808
NEWARK) 89F1934
14 Screw, Phillips, 4-40, 0.250 in.
15 Board, printed-circuit
4
1
SHR-0440-016-SN
(TI) THS4304DGK ENG A, or
(TI) THS4304DBV ENG A
(1) NOTE: All items are designated for both the DBV and DGK EVMs unless otherwise noted.
(2) C6 used on DGK EVM only.
(3) R12 used on DBV EVM only.
14
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
Figure 38. THS4304DGK EVM Layout Top and L2
Figure 39. THS4304DGK EVM Layout Bottom and L3
Figure 40. THS4304DBV EVM Layout Top and L2
Figure 41. THS4304DBV EVM Layout Bottom and L3
Copyright © 2007, Texas Instruments Incorporated
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
NON-INVERTING GAIN WITH SPLIT SUPPLY
The following schematic shows how to configure the operational amplifier for non-inverting gain with split power
supply (±2.5V). This is how the EVM is supplied from TI. This configuration is convenient for test purposes
because most signal generators and analyzer are designed to use ground-referenced signals by default. Note
the input and output provides 50 Ω termination.
−V
S
GND GND +V
S
J3
J4
J6
J5
+V
S
−V
S
FB1
FB2
C5
0.1 mF
C1
3.3 mF
C2
3.3 mF
C4
0.1 mF
GND
C8
0
R8
R7
TP1
249 W
249 W
+V
S
U1
4
3
J2
5
R2
49.9 W
C9
1
J1
R10
0
C7
0
0
2
THS4304DBV
R11
49.9 W
−V
S
Figure 42. Non-Inverting Gain With Split Power Supply
16
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
INVERTING GAIN WITH SPLIT POWER SUPPLY
The following schematic shows how to configure the operational amplifier for inverting gain of 1 (–1 V/V) with
split power supply (±2.5 V). Note the input and output provides 50 Ω termination for convenient interface to
common test equipment.
−V
S
GND GND +V
S
J3
J4
J6
J5
+V
S
−V
S
FB1
FB2
C4
0.1 mF
C5
0.1 mF
C1
3.3 mF
C2
3.3 mF
R7
GND
249 W
TP1
J1
C7
0
R9
+V
S
221 W
U1
R11
61.9 W
J2
4
4
3
3
5
5
R2
49.9 W
C9
−
+
1
1
THS4304DBV
0
2
2
R1
124 W
−V
S
C8
0
Figure 43. Inverting Gain With Split Power Supply
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
NON-INVERTING SINGLE-SUPPLY OPERATION
The THS4304 EVM can easily be configured for single 5 V supply operation, as shown in the following
schematic, with no change in performance. This circuit passes dc signals at the input, so care must be taken to
reference (or bias) the input signal to mid-supply.
If dc operation is not required, the amplifier can be ac coupled by inserting a capacitor in series with the input
(C7) and output (C9).
V
REF
−V
S
GND GND +V
S
R3
R6
J3
NC
J4
J6
J5
+V
S
+V
S
FB2
10 kW
10 kW
C8
R8
R7
C2
3.3 mF
C4
0.1 mF
249 W
249 W
GND
TP1
0.1 mF
+V
S
U1
5
5
4
3
3
4
J2
R2
49.9 W
C9
0
−
+
1
1
J1
C7
0
R10
0
THS4304DBV
2
2
R1
49.9 W
C5
0
V
REF
Figure 44. Non-Inverting 5-V Single-Supply Amplifier
DIFFERENTIAL ADC DRIVE AMPLIFIER
The circuit shown in Figure 44 is adapted as shown in Figure 45 to provide a high-performance differential
amplifier drive circuit for use with high-performance ADCs, like the ADS5500 (14 bit 125 MSP ADC). For testing
purposes, the circuit uses a transformer to convert the signal from a single-ended source to differential. If the
input signal source in your application is differential and biased to mid-rail, no transformer is required.
The circuit employs two amplifiers to provide a differential signal path to the ADS5500. A resistor divider (two
10 kΩ resistors) is used to obtain a mid-supply reference voltage of 2.5 V (VREF) (the same as shown in the
single-supply circuit of Figure 44). Applying this voltage to the one side of RG and to the positive input of the
operational amplifier (via the center-tap of the transformer) sets the input and output common-mode voltage of
the operational amplifiers to mid-rail to optimize their performance. The ADS5500 requires an input
common-mode voltage of 1.5 V. Due to the mismatch in required common-mode voltage, the signal is ac coupled
from the amplifier output, via the two 1 nF capacitors, to the input of the ADC. The CM voltage of the ADS5500 is
used to bias the ADC input to the required voltage, via the 1 kΩ resistors. Note: 100 μA common-mode current is
drawn by the ADS5500 input stage (at 125 MSPS). This causes a 100 mV shift in the input common-mode
voltage, which does not impact the performance when driving the input to –1 dB of full scale. To offset this effect,
a voltage divider from the power supply can be used to derive the input common-mode voltage reference.
Because the operational amplifiers are configured as non-inverting, the inputs are high impedance. This is
particularly useful when interfacing to a high-impedance source. In this situation, the amplifiers provide
impedance matching and amplification of the signal.
18
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SGDS038A–SEPTEMBER 2007–REVISED OCTOBER 2007
+5V
10 k W
10 k W
V
(= 2.5V)
REF
mF
0.1
R
R
F
G
V
REF
+5V
+3.3 VA +3.3 VD
THS4304
1:1
100 W
100 W
1nF
CM
V
IN
1kW
A
A
IN+
ADS 5500
D
A
49 .9 W
V
REF
+5V
From
1kW
IN−
CM
50 W
Source
THS4304
CM
1nF
0.1 mF
V
REF
R
R
F
G
Figure 45. Differential ADC Drive Amplifier Circuit
Copyright © 2007, Texas Instruments Incorporated
19
Product Folder Link(s): THS4304-SP
PACKAGE OPTION ADDENDUM
www.ti.com
15-Oct-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
5962-0721901VHA
ACTIVE
CFP
U
10
1
TBD
A42
N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4304-SP :
Catalog: THS4304
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 1
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相关型号：
THS4304DGKRG4
IC OP-AMP, 5000 uV OFFSET-MAX, 830 MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MSOP-8, Operational Amplifier
TI
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