THS4500CDRG4 [TI]
OP-AMP, 0uV OFFSET-MAX, 300MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | THS4500CDRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OP-AMP, 0uV OFFSET-MAX, 300MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8 放大器 光电二极管 |
| 文件： | 总46页 (文件大小：1258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4500
THS4501
DGN-8 DGK-8
D-8
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
WIDEBAND, LOW-DISTORTION, FULLY DIFFERENTIAL AMPLIFIERS
1
FEATURES
APPLICATIONS
•
High Linearity Analog-to-Digital Converter
Preamplifier
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
Differential Line Driver
23
•
Fully Differential Architecture
•
•
•
•
•
•
Bandwidth: 370 MHz
•
•
•
•
Slew Rate: 2800 V/µs
IMD3: –90 dBc at 30 MHz
OIP3: 49 dBm at 30 MHz
Output Common-Mode Control
Active Filtering of Differential Signals
Wide Power-Supply Voltage Range: 5 V, ±5 V,
12 V, 15 V
1
8
V
IN+
V
IN−
2
7
V
PD
V
OCM
•
Input Common-Mode Range Shifted to Include
Negative Power-Supply Rail
3
4
6
5
V
S+
S−
•
•
Power-Down Capability (THS4500)
Evaluation Module Available
V
OUT+
V
OUT−
RELATED DEVICES
DESCRIPTION
DEVICE(1)
THS4500/1
THS4502/3
THS4120/1
THS4130/1
THS4140/1
THS4150/1
DESCRIPTION
The THS4500 and THS4501 are high-performance
fully differential amplifiers from Texas Instruments.
The THS4500, featuring power-down capability, and
the THS4501, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 14-bit
operation through 40 MHz. Package options include
the SOIC-8 and the MSOP-8 with PowerPAD™ for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
370 MHz, 2800 V/µs, VICR Includes VS–
370 MHz, 2800 V/µs, Centered VICR
3.3 V, 100 MHz, 43 V/µs, 3.7 nV/√Hz
±15 V, 150 MHz, 51 V/µs, 1.3 nV/√Hz
±15 V, 160 MHz, 450 V/µs, 6.5 nV/√Hz
±15 V, 150 MHz, 650 V/µs, 7.6 nV/√Hz
(1) Even-numbered devices feature power-down capability.
10 pF
APPLICATION CIRCUIT DIAGRAM
THIRD-ORDER INTERMODULATION
DISTORTION
392 Ω
−62
10
12
5 V
V
= 5 V
S
−68
−74
−80
5 V
0.1 µF
10 µF
50 Ω
374 Ω
56.2 Ω
24.9 Ω
24.9 Ω
V
= ±5 V
+
S
−
ADC
12 Bit/80 MSps
IN
V
OCM
V
S
IN
+
−
V
ref
392 Ω
1 µF
V
+
S+
374 Ω
50 Ω
−86
−92
14
16
V
OUT
−
V
OCM
800 Ω
2.5 V
56.2 Ω
V
+
S
402 Ω
−
V
402 Ω
S−
392 Ω
392 Ω
−98
50
10
20
30
40
60
70
80
90
100
10 pF
f − Frequency − MHz
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments, Incorporated.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2008, Texas Instruments Incorporated
THS4500
THS4501
SLOS350E–APRIL 2002–REVISED MAY 2008.............................................................................................................................................................. www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ABSOLUTE MAXIMUM RATINGS(1)
Over operating free-air temperature range, unless otherwise noted.
UNIT
Supply voltage, VS
Input voltage, VI
16.5 V
±VS
(2)
Output current, IO
150 mA
Differential input voltage, VID
Continuous power dissipation
Maximum junction temperature, TJ
4 V
See Dissipation Rating Table
+150°C
(3)
Maximum junction temperature, continuous operation, long-term reliability, TJ
+125°C
C suffix
I suffix
0°C to +70°C
–40°C to +85°C
–65°C to +150°C
+300°C
(4)
Operating free-air temperature range, TA
Storage temperature range, Tstg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
HBM
CDM
MM
4000 V
ESD rating:
1000 V
100 V
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) The THS4500/1 may incorporate a PowerPAD on the underside of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature
which could permanently damage the device. See TI technical briefs SLMA002 and SLMA004 for more information about utilizing the
PowerPAD thermally-enhanced package.
(3) The absolute maximum temperature under any condition is limited by the constraints of the silicon process.
(4) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may
result in reduced reliability and/or lifetime of the device.
DISSIPATION RATINGS TABLE
POWER RATING(2)
(1)
θJC
θJA
PACKAGE
(°C/W)
(°C/W)
T
A ≤ +25°C
TA = +85°C
410 mW
685 mW
154 mW
D (8-pin)
38.3
4.7
97.5
58.4
260
1.02 W
DGN (8-pin)
DGK (8-pin)
1.71 W
54.2
385 mW
(1) This data was taken using the JEDEC standard High-K test PCB.
(2) Power rating is determined with a junction temperature of +125°C. This is the point where distortion starts to substantially increase.
Thermal management of the final PCB should strive to keep the junction temperature at or below +125°C for best performance and
long-term reliability.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
±5
MAX
±7.5
15
UNIT
Dual supply
Single supply
C suffix
Supply voltage
V
4.5
0
5
+70
+85
Operating free- air temperature, TA
°C
I suffix
–40
2
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Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
PACKAGE/ORDERING INFORMATION(1)
ORDERABLE PACKAGE AND NUMBER
PLASTIC MSOP(2)
TEMPERATURE
PLASTIC MSOP(2)
PLASTIC SMALL
OUTLINE (D)
PowerPAD
DGN
SYMBOL
BFB
DGK
SYMBOL
ATVB
ATW
THS4500CD
THS4501CD
THS4500ID
THS4501ID
THS4500CDGN
THS4501CDGN
THS4500IDGN
THS4501IDGN
THS4500CDGK
THS4501CDGK
THS4500IDGK
THS4501IDGK
0°C to +70°C
BFD
BFC
ASV
–40°C to +85°C
BFE
ASW
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) All packages are available taped and reeled. The R suffix standard quantity is 2500. The T suffix standard quantity is 250 (for example,
THS4501DT).
PIN ASSIGNMENTS
D, DGN, DGK
D, DGN, DGK
THS4500
(TOP VIEW)
THS4501
(TOP VIEW)
VIN-
VOCM
VS+
VIN+
PD
VIN-
VIN+
NC
1
8
1
8
VOCM
2
7
2
7
VS+
3
4
6
5
3
4
6
5
VS-
VS-
VOUT+
VOUT-
VOUT+
VOUT-
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350E–APRIL 2002–REVISED MAY 2008.............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = ±5 V
RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP
OVER TEMPERATURE
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
+70°C
–40°C to
+85°C
+25°C
+25°C
UNITS
AC PERFORMANCE
G = +1, PIN = –20 dBm, RF = 392 Ω
G = +2, PIN = –30 dBm, RF = 1 kΩ
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
G > +10
370
175
70
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Small-signal bandwidth
30
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate
300
150
220
2800
0.4
PIN = –20 dBm
VP = 2 V
4 VPP Step
Rise time
2 VPP Step
Fall time
2 VPP Step
0.5
ns
Settling time to 0.01%
0.1%
VO = 4 VPP
8.3
ns
VO = 4 VPP
6.3
ns
Harmonic distortion
G = +1, VO = 2 VPP
f = 8 MHz
–82
–71
–97
–74
dBc
dBc
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
f = 30 MHz
Third-order intermodulation
distortion
VO= 2 VPP, fC= 30 MHz, RF = 392 Ω,
–90
49
dBc
Typ
Typ
200 kHz tone spacing
fC = 30 MHz, RF = 392 Ω,
Referenced to 50 Ω
Third-order output intercept point
dBm
Input voltage noise
f > 1 MHz
f > 100 kHz
7
nV/√Hz Typ
pA/√Hz Typ
Input current noise
1.7
60
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
ns
Typ
55
–4
52
50
–8/0
±10
5
50
–9/+1
±10
5.2
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
–7/–1
Average offset voltage drift
Input bias current
µV/°C
µA
4
4.6
1
Average bias current drift
Input offset current
±10
2
±10
2
nA/°C
µA
0.5
Average offset current drift
INPUT
±40
±40
nA/°C
Common-mode input range
Common-mode rejection ratio
Input impedance
–5.7/2.6 –5.4/2.3
–5.1/2
70
–5.1/2
70
V
Min
Min
80
74
dB
107 || 1
Ω || pF Typ
OUTPUT
Differential output voltage swing
Differential output current drive
Output balance error
RL = 1 kΩ
RL = 20 Ω
±8
±7.6
110
±7.4
100
±7.4
100
V
Min
Min
Typ
120
–58
mA
dB
PIN = –20 dBm, f = 100 kHz
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
4
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Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = ±5 V (continued)
RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP
OVER TEMPERATURE
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
+70°C
–40°C to
+85°C
+25°C
+25°C
UNITS
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
RL = 400 Ω
180
92
MHz
V/µs
V/V
V/V
mV
µA
Typ
Typ
Min
Max
Max
Max
Min
2 VPP Step
Minimum gain
1
0.98
1.02
0.98
1.02
0.98
1.02
Maximum gain
1
Common-mode offset voltage
–0.4
100
±4
–4.6/+3.8 –6.6/+5.8 –7.6/+6.8
Input bias current
VOCM = 2.5 V
150
170
170
Input voltage range
±3.7
±3.4
±3.4
V
Input impedance
25 || 1
0
kΩ || pF Typ
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
0.05
0.10
0.10
V
V
Max
Min
0
–0.05
–0.10
–0.10
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power-supply rejection (±PSRR)
POWER-DOWN (THS4500 ONLY)
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
±5
23
23
80
7.5
28
18
76
7.5
32
14
73
7.5
34
12
70
V
Max
Max
Min
Min
mA
mA
dB
Device enabled ON above –2.9 V
Device disabled OFF below –4.3 V
–2.9
–4.3
1000
240
V
V
Min
Max
Max
Max
800
200
1200
260
1200
260
µA
µA
Input impedance
50 || 1
1000
800
kΩ || pF Typ
Turn-on time delay
ns
ns
Typ
Typ
Turn-off time delay
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350E–APRIL 2002–REVISED MAY 2008.............................................................................................................................................................. www.ti.com
ELECTRICAL CHARACTERISTICS: VS = 5 V
RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP
OVER TEMPERATURE
MIN/T
YP/M
AX
PARAMETER
TEST CONDITIONS
0°C to
+70°C
–40°C to
+85°C
+25°C
+25°C
UNITS
AC PERFORMANCE
G = +1, PIN = –20 dBm, RF = 392 Ω
G = +2, PIN = –30 dBm, RF = 1 kΩ
G = +5, PIN = –30 dBm, RF = 2.4 kΩ
G = +10, PIN = –30 dBm, RF = 5.1 kΩ
G > +10
320
160
60
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Small-signal bandwidth
30
Gain-bandwidth product
Bandwidth for 0.1-dB flatness
Large-signal bandwidth
Slew rate
300
180
200
1300
0.5
PIN = –20 dBm
VP = 1 V
2 VPP Step
Rise time
2 VPP Step
Fall time
2 VPP Step
0.6
ns
Settling time to 0.01%
0.1%
VO = 2 V Step
13.1
8.3
ns
VO = 2 V Step
ns
Harmonic distortion
G = +1, VO = 2 VPP
f = 8 MHz,
–80
–55
–76
–60
7
dBc
dBc
2nd harmonic
3rd harmonic
f = 30 MHz
f = 8 MHz
dBc
f = 30 MHz
dBc
Input voltage noise
f > 1 MHz
nV/√Hz
pA/√Hz
ns
Input current noise
f > 100 kHz
1.7
60
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Overdrive = 5.5 V
54
–4
51
49
–8/0
±10
5
49
–9/+1
±10
5.2
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
–7/–1
Average offset voltage drift
Input bias current
µV/°C
µA
4
4.6
0.7
Average bias current drift
Input offset current
±10
1.2
±20
±10
1.2
nA/°C
µA
0.5
Average offset current drift
INPUT
±20
nA/°C
Common-mode input range
Common-mode rejection ratio
Input Impedance
–0.7/2.6 –0.4/2.3
–0.1/2
70
–0.1/2
70
V
Min
Min
Typ
80
74
dB
107 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Output current drive
Output balance error
RL = 1 kΩ, Referenced to 2.5 V
RL = 20 Ω
±3.3
100
–58
±3
90
±2.8
80
±2.8
80
V
Min
Min
Typ
mA
dB
PIN = –20 dBm, f = 100 kHz
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
6
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Copyright © 2002–2008, Texas Instruments Incorporated
Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
ELECTRICAL CHARACTERISTICS: VS = 5 V (continued)
RF = RG = 392 Ω, RL = 800 Ω, G = +1, and single-ended input, unless otherwise noted.
THS4500 AND THS4501
TYP
OVER TEMPERATURE
MIN/T
YP/M
AX
PARAMETER
TEST CONDITIONS
0°C to
+70°C
–40°C to
+85°C
+25°C
+25°C
UNITS
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
RL = 400 Ω
180
80
MHz
V/µs
V/V
V/V
mV
µA
Typ
Typ
Min
Max
Max
Max
Min
Typ
Max
Min
2 VPP Step
Minimum gain
1
0.98
1.02
0.98
1.02
0.98
1.02
Maximum gain
1
Common-mode offset voltage
0.4
1
–2.6/3.4 –4.2/5.4 –5.6/6.4
Input bias current
VOCM = 2.5 V
2
3
3
Input voltage range
1/4
25 || 1
2.5
2.5
1.2/3.8
1.3/3.7
1.3/3.7
V
Input impedance
kΩ || pF
V
Maximum default voltage
Minimum default voltage
POWER SUPPLY
VOCM left floating
VOCM left floating
2.55
2.45
2.6
2.4
2.6
2.4
V
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power-supply rejection (+PSRR)
POWER -DOWN (THS4500 ONLY)
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
5
15
25
16
72
15
29
12
69
15
31
10
66
V
Max
Max
Min
Min
20
20
75
mA
mA
dB
Device enabled ON above 2.1 V
Device disabled OFF below 0.7 V
2.1
0.7
V
V
Min
Max
Max
Max
Typ
Typ
Typ
600
100
800
125
1200
140
1200
140
µA
µA
Input impedance
50 || 1
1000
800
kΩ || pF
ns
Turn-on time delay
Turn-off time delay
ns
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350E–APRIL 2002–REVISED MAY 2008.............................................................................................................................................................. www.ti.com
TYPICAL CHARACTERISTICS
Table of Graphs (±5 V)
FIGURE
Small-signal unity-gain frequency response
1
Small-signal frequency response
2
0.1-dB gain flatness frequency response
3
4
Large-signal frequency response
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
vs Frequency
5, 7, 13, 15
6, 8, 14, 16
9, 11, 17, 19
10, 12, 18, 20
21
vs Frequency
vs Output voltage swing
vs Output voltage swing
vs Load resistance
vs Load resistance
22
Third-order intermodulation distortion
(single-ended input to differential output)
vs Frequency
23
Third-order output intercept point
Slew rate
vs Frequency
24
25
vs Differential output voltage step
Settling time
26, 27
28
Large-signal transient response
Small-signal transient response
Overdrive recovery
29
30, 31
32
Voltage and current noise
Rejection ratios
vs Frequency
vs Frequency
33
Rejection ratios
vs Case temperature
vs Frequency
34
Output balance error
Open-loop gain and phase
Open-loop gain
35
vs Frequency
36
vs Case temperature
vs Case temperature
vs Supply voltage
vs Case temperature
vs Input common-mode range
vs Case temperature
37
Input bias offset current
Quiescent current
38
39
Input offset voltage
40
Common-mode rejection ratio
Output drive
41
42
Harmonic distortion
(single-ended and differential input to differential output)
vs Output common-mode voltage
43
Small-signal frequency response at VOCM
Output offset voltage at VOCM
44
45
46
47
48
49
50
vs Output common-mode voltage
vs Power-down voltage
Quiescent current
Turn-on and turn-off delay times
Single-ended output impedance in power-down
vs Frequency
vs Case temperature
vs Supply voltage
Power-down quiescent current
8
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
Table of Graphs (5 V)
FIGURE
Small-signal unity-gain frequency response
Small-signal frequency response
0.1-dB gain flatness frequency response
Large-signal frequency response
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
Harmonic distortion (single-ended input to differential output)
Harmonic distortion (differential input to differential output)
Third-order intermodulation distortion
Third-order intercept point
51
52
53
54
vs Frequency
55, 57, 63, 65
vs Frequency
56, 58, 64, 66
vs Output voltage swing
vs Output voltage swing
vs Load resistance
vs Load resistance
vs Frequency
59, 61, 67, 69
60, 62, 68, 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
vs Frequency
Slew rate
vs Differential output voltage step
Large-signal transient response
Small-signal transient response
Voltage and current noise
vs Frequency
Rejection ratios
vs Frequency
Rejection ratios
vs Case temperature
vs Frequency
Output balance error
Open-loop gain and phase
vs Frequency
Open-loop gain
vs Case temperature
vs Case temperature
vs Supply voltage
Input bias offset current
Quiescent current
Input offset voltage
vs Case temperature
vs Input common-mode range
vs Case temperature
vs Output common-mode voltage
Common-mode rejection ratio
Output drive
Harmonic distortion (single-ended and differential input)
Small-signal frequency response at VOCM
Output offset voltage
vs Output common-mode voltage
vs Power-down voltage
Quiescent current
Turn-on and turn-off delay times
Single-ended output impedance in power-down
vs Frequency
vs Case temperature
vs Supply voltage
Power-down quiescent current
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TYPICAL CHARACTERISTICS: ±5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
0.3
1
22
20
18
16
14
12
10
Gain = 1
Gain = 10, R = 5.1 kΩ
f
0.5
R
= 800 Ω
= −20 dBm
= ±5 V
L
0.2
0.1
0
P
V
IN
S
0
−0.5
−1
Gain = 5, R = 2.4 kΩ
f
R = 499 Ω
f
−1.5
−2
8
6
4
2
R = 392 Ω
f
Gain = 2, R = 1 kΩ
f
Gain = 1
−0.1
−2.5
−3
R
L
= 800 Ω
R = 392 Ω
f
R
P
V
= 800 Ω
= −30 dBm
= ±5 V
−0.2
−0.3
L
P
V
= −20 dBm
= ±5 V
IN
S
−3.5
−4
IN
S
0
−2
0.1
10
100
1000
0.1
1
10
100
1000
1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 1.
Figure 2.
Figure 3.
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
1
0
0
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−30
−40
−50
−60
−70
−80
−20
−30
−40
−50
−60
−70
−80
R
= 800 Ω
R = 800 Ω
L
R = 392 Ω
f
L
R = 392 Ω
f
V
V
= 1 V
= ±5 V
V
V
= 1 V
PP
= ±5 V
−1
−2
O
S
PP
O
S
Gain = 1
HD2
R
L
= 800 Ω
HD2
10
R = 392 Ω
−3
−4
f
P
V
= 10 dBm
= ±5 V
IN
S
−90
−90
HD3
HD3
−100
−100
0.1
1
100
0.1
1
10
100
0.1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 4.
Figure 5.
Figure 6.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
0
−10
−20
0
−10
−20
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
= 800 Ω
R = 392 Ω
Differential Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
= 800 Ω
R
R = 800 Ω
L
R = 392 Ω
f
L
L
−30
−40
−30
−40
R = 392 Ω
f
f
f= 8 MHz
V
V
= 2 V
= ±5 V
V
V
= 2 V
PP
= ±5 V
O
S
PP
O
S
V
= ±5 V
S
−50
−60
−70
−80
−50
−60
−70
−80
HD2
HD2
10
HD2
10
HD3
−90
−90
HD3
4
HD3
−100
−100
0
0.5
1
1.5
2
2.5
3
3.5
4.5
5
0.1
1
100
0.1
1
100
V
− Output Voltage Swing − V
f − Frequency − MHz
f − Frequency − MHz
O
Figure 7.
Figure 8.
Figure 9.
10
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
R = 499 Ω
R = 392 Ω
R = 392 Ω
f
f
f
f= 8 MHz
f= 30 MHz
f= 30 MHz
V = ±5 V
S
V
= ±5 V
V
= ±5 V
S
S
HD2
HD2
HD2
HD3
HD3
3
HD3
4.5
0
0.5
1
1.5
2
2.5
3
3.5
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3.5
4
4.5
5
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
V − Output Voltage Swing − V
O
O
O
Figure 10.
Figure 11.
Figure 12.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
0
0
−10
−20
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
= 800 Ω
R = 1 kΩ
Single-Ended Input to
Differential Output
Gain = 2
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
= 800 Ω
R
R = 800 Ω
L
R = 1 kΩ
f
L
L
−30
−40
−50
R = 1 kΩ
f
f
V
V
= 1 V
PP
= ±5 V
V
V
= 1 V
= ±5 V
V
V
= 2 V
PP
= ±5 V
O
S
O
S
PP
O
S
HD2
−60
−70
−80
HD2
HD2
HD3
HD3
−90
HD3
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 13.
Figure 14.
Figure 15.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−10
−20
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
−30
−40
−50
R = 1 kΩ
R = 1 kΩ
R = 1 kΩ
f
f
f
V
V
= 2 V
PP
= ±5 V
f= 8 MHz
f= 8 MHz
V = ±5 V
S
O
S
V
= ±5 V
S
HD2
−60
−70
−80
HD2
2.5
HD2
HD3
−90
HD3
3.5
HD3
3.5
−100
0
0.5
1
1.5
2
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0.1
1
10
100
f − Frequency − MHz
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
O
Figure 16.
Figure 17.
Figure 18.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs LOAD RESISTANCE
0
0
0
Single-Ended Input to
Differential Output
Gain = 2
Differentia Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 1
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
R
L
= 800 Ω
R = 800 Ω
L
V
= 2 V
PP
O
R = 1 kΩ
R = 1 kΩ
R = 392 Ω
f
f
f
f= 30 MHz
f= 8 MHz
V = ±5 V
S
f= 30 MHz
V
= ±5 V
V
= ±5 V
S
S
HD2
HD2
−60
−70
−80
HD2
HD3
HD3
3.5
HD3
3.5
−90
−100
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0
400
800
1200
1600
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
R
L
− Load Resistance − Ω
O
Figure 19.
Figure 20.
Figure 21.
HARMONIC DISTORTION
vs LOAD RESISTANCE
THIRD-ORDER INTERMODULATION
DISTORTION vs FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT vs FREQUENCY
55
−50
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
Gain = 1
−10
R
F
= 392 W
50
45
40
−60
−70
−80
−20
−30
−40
−50
V
= 2 V
O
S
PP
R
L
= 800 Ω
V
= 2 V
PP
O
V
= ± 5 V
R = 392 Ω
R = 392 Ω
f
f
V
V
= 2 V
PP
= ±5 V
f= 30 MHz
O
S
V
= ±5 V
S
−60
−70
−80
HD2
35
30
−90
HD3
−90
−100
−100
10
100
0
20
40
60
80
100
120
0
400
800
1200
1600
f − Frequency − MHz
f - Frequency - MHz
R
L
− Load Resistance − Ω
Figure 22.
Figure 23.
Figure 24.
SLEW RATE vs DIFFERENTIAL
OUTPUT VOLTAGE STEP
SETTLING TIME
SETTLING TIME
3000
2500
2000
1500
1.5
0.8
0.6
0.4
0.2
0
Gain = 1
Rising Edge
Rising Edge
R
L
= 800 Ω
1.0
0.5
R = 392 Ω
f
V
= ±5 V
S
Gain = 1
Gain = 1
= 800 Ω
R
R
= 800 W
= 499 W
R
L
L
R = 499 Ω
F
f
f = 1 MHz
= ±5 V
f= 1 MHz
0
-0.5
-1.0
V
V
= ±5 V
S
S
−0.2
−0.4
1000
500
0
Falling Edge
Falling Edge
−0.6
−0.8
-1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
5
10
15
20
0
2
4
6
8
10
12
14
t - Time - ns
t − Time − ns
V
− Differential Output Voltage Step − V
O
Figure 25.
Figure 26.
Figure 27.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
OVERDRIVE RECOVERY
0.4
0.3
0.2
0.1
2.5
2
5
4
3
2
Gain = 4
= 800 Ω
R = 499 Ω
Overdrive = 4.5 V
= ±5 V
S
R
1.5
L
1.5
f
1
1
2
1
V
Gain = 1
Gain = 1
0.5
R
L
= 800 Ω
R
L
= 800 Ω
0.5
0
R = 499 Ω
R = 499 Ω
f
f
0
0
0
−0.5
−1
t /t = 300 ps
t /t = 300 ps
r
f
r
f
V
= ±5 V
V
= ±5 V
−0.5
S
S
−1
−0.1
−1
−2
−3
−0.2
−0.3
−0.4
−1.5
−1.5
−2
−2
−4
−5
−2.5
−100
0
100
200
300
400
500
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−100
0
100
200
300
400
500
t − Time − ns
t − Time − ns
t − Time − µs
Figure 28.
Figure 29.
Figure 30.
VOLTAGE AND CURRENT NOISE
vs FREQUENCY
REJECTION RATIOS
vs FREQUENCY
OVERDRIVE RECOVERY
200
150
100
50
90
80
70
60
50
40
30
20
10
0
100
V
= ±5 V
S
PSRR+
Source
CMMR
V
n
PSRR−
10
0
−50
I
n
Sink
R
= 800 Ω
= ±5 V
L
−100
−150
V
S
1
0.01 0.1
−10
1
10
100 1000 10 k
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0.1
1
10
100
f − Frequency − MHz
f − Frequency − kHz
Case Temperature − °C
Figure 31.
Figure 32.
Figure 33.
REJECTION RATIOS
vs CASE TEMPERATURE
OUTPUT BALANCE ERROR
vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
0
120
100
60
30
P
R
= 10 dBm
= 800 Ω
Gain
P
R
V
= −30 dBm
= 800 Ω
= ±5 V
IN
IN
−10
−20
−30
−40
−50
−60
−70
−80
CMMR
L
L
50
40
30
20
0
R = 392 Ω
V
f
S
PSRR+
= ±5 V
S
80
60
40
20
0
−30
−60
−90
Phase
−120
−150
10
0
R
= 800 Ω
= ±5 V
L
V
S
0.1
1
10
100
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
0.01
0.1
1
10
100
1000
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 34.
Figure 35.
Figure 36.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
OPEN-LOOP GAIN
INPUT BIAS AND OFFSET CURRENT
QUIESCENT CURRENT
vs SUPPLY VOLTAGE
vs CASE TEMPERATURE
vs CASE TEMPERATURE
35
30
25
20
15
10
58
57
56
55
54
53
52
51
50
49
3.4
3.3
0
V
= ±5 V
S
T = 85°C
A
I
R
V
= 800 Ω
= ±5 V
−0.01
−0.02
−0.03
−0.04
−0.05
IB−
L
S
T
A
= 25°C
3.2
3.1
I
IB+
T
A
= −40°C
3
2.9
−0.06
−0.07
−0.08
−0.09
2.8
2.7
I
OS
2.6
2.5
5
0
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
V
− Supply Voltage − ±V
S
Figure 37.
Figure 38.
Figure 39.
INPUT OFFSET VOLTAGE
vs CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs INPUT COMMON-MODE RANGE
110
OUTPUT DRIVE
vs CASE TEMPERATURE
7
200
V
= ±5 V
S
V
= ±5 V
V = ±5 V
S
S
100
90
80
70
60
50
40
30
20
10
Source
150
100
50
6
5
4
3
2
0
−50
1
0
Sink
−100
−150
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
6
Case Temperature − °C
Case Temperature − °C
Input Common-Mode Voltage Range − V
Figure 40.
Figure 41.
Figure 42.
HARMONIC DISTORTION
vs OUTPUT COMMON-MODE
VOLTAGE
OUTPUT OFFSET VOLTAGE AT VOCM
vs OUTPUT COMMON-MODE
VOLTAGE
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
0
600
Single-Ended and Differential
Input to Differential Output
3
2
−10
Gain = 1
R = 800 Ω
L
400
200
Gain = 1, V = 2 V
O
PP
−20
R = 392 Ω
f= 8 MHz, R = 392 Ω
f
f
−30
−40
−50
−60
V
= ±5 V
P
V
= −20 dBm
= ±5 V
S
IN
1
S
HD2-SE
0
0
HD2
-Diff
HD3-SE
HD3-Diff
−200
−70
−80
−1
−400
−600
−2
−3
−90
−100
−3.5 −2.5 −1.5 −0.5 0.5
1.5
2.5 3.5
−5 −4 −3 −2 −1
0
1
2
3
4
5
1
10
100
1000
V
− Output Common-Mode Voltage − V
OC
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 43.
Figure 44.
Figure 45.
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TYPICAL CHARACTERISTICS: ±5 V (continued)
QUIESCENT CURRENT
vs POWER-DOWN VOLTAGE
TURN-ON AND TURN-OFF DELAY
TIME
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER-DOWN vs FREQUENCY
800
30
25
20
15
10
0.03
700
600
500
400
0.02
0.01
Current
0
0
−1
−2
−3
−4
300
Gain = 1
R
L
= 800 Ω
5
200
R = 392 Ω
f
P
V
= −1 dBm
= ±5 V
IN
S
0
100
0
−5
−6
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
0
0.1
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
Power-Down Voltage − V
t − Time − ms
Figure 46.
Figure 47.
Figure 48.
POWER-DOWN QUIESCENT
CURRENT vs CASE TEMPERATURE
POWER-DOWN QUIESCENT
CURRENT vs SUPPLY VOLTAGE
1000
900
800
700
1000
900
800
700
600
500
400
300
200
R
L
= 800 Ω
R
= 800 Ω
= ±5 V
L
V
S
600
500
400
300
200
100
0
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
V
− Supply Voltage − ±V
Case Temperature − °C
S
Figure 49.
Figure 50.
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TYPICAL CHARACTERISTICS: 5 V
SMALL-SIGNAL UNITY-GAIN
FREQUENCY RESPONSE
SMALL-SIGNAL FREQUENCY
RESPONSE
0.1-dB GAIN FLATNESS FREQUENCY
RESPONSE
0.2
1
0
22
20
18
16
14
12
10
Gain = 10, R = 5.1 kΩ
f
R = 499 Ω
f
0.1
0
Gain = 5, R = 2.4 kΩ
f
R = 392 Ω
f
−1
−2
−0.1
−0.2
8
6
4
2
Gain = 2, R = 1 kΩ
f
Gain = 1
−0.3
R
L
= 800 Ω
Gain = 1
R = 392 Ω
−3
−4
f
R
= 800 Ω
= −20 dBm
= 5 V
L
R
= 800 Ω
= −30 dBm
= 5 V
L
P
V
= −20 dBm
= 5 V
−0.4
−0.5
IN
S
P
V
IN
S
P
V
IN
S
0
−2
0.1
10
100
1000
0.1
1
10
100
1000
1
1
10
100
1000
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 51.
Figure 52.
Figure 53.
LARGE-SIGNAL FREQUENCY
RESPONSE
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
0
0
1
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
R
L
= 800 Ω
R
L
= 800 Ω
−30
−40
R = 392 Ω
R = 392 Ω
f
f
V
V
= 1 V
= 5 V
V
V
= 1 V
= 5 V
O
S
PP
−1
O
S
PP
−50
−60
−70
−80
−2
−3
−4
HD2
HD2
Gain = 1
R
L
= 800 Ω
R = 392 Ω
f
HD3
P
V
= 10 dBm
= 5 V
HD3
IN
S
−90
−100
0.1
1
10
100
1000
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 54.
Figure 55.
Figure 56.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−10
−20
−30
−40
−10
−20
−30
−40
−50
−60
R
= 800 Ω
R
= 800 Ω
L
L
R
= 800 Ω
L
R = 499 Ω
R = 392 Ω
f
f
R = 392 Ω
f
V
V
= 2 V
= 5 V
V
V
= 2 V
= 5 V
O
S
PP
O
S
PP
f= 8 MHz
V
= 5 V
S
−50
−60
−70
−80
HD3
HD3
HD3
−70
−80
HD2
HD2
HD2
2.5
−90
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0
0.5
1
1.5
2
3
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Swing − V
O
Figure 57.
Figure 58.
Figure 59.
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
−10
−20
0
−10
−20
0
−10
−20
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
R = 392 Ω
f = 30 MHz
−30
−40
−50
−60
−30
−40
−50
−60
−30
−40
−50
−60
R = 392 Ω
f= 8 MHz
R = 392 Ω
f= 30 MHz
V = 5 V
S
f
f
f
HD3
HD3
V
= 5 V
V
= 5 V
S
S
HD2
HD2
HD3
−70
−80
−70
−80
−70
−80
HD2
−90
−90
−90
−100
−100
−100
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
V − Output Voltage Swing − V
O
O
O
Figure 60.
Figure 61.
Figure 62.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs FREQUENCY
0
0
−10
−20
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−10
−20
−30
−20
−30
R
= 800 Ω
R
= 800 Ω
R = 800 Ω
L
R = 1 kΩ
f
L
L
−30
−40
−50
R = 1 kΩ
R = 1 kΩ
f
f
V
V
= 1 V
= 5 V
V
V
= 1 V
= 5 V
V
V
= 2 V
= 5 V
O
S
PP
O
S
PP
O
S
PP
−40
−40
−50
−60
−50
−60
HD2
HD3
−60
−70
−80
HD3
−70
−80
−70
HD2
−80
−90
HD2
HD3
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 63.
Figure 64.
Figure 65.
HARMONIC DISTORTION
vs FREQUENCY
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
0
0
0
Single-Ended Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
−10
−10
−20
10
20
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R
R
= 800 W
= 1 kW
L
R = 1 kΩ
R = 1 kΩ
−30
−40
−50
−60
30
40
50
60
f
f
F
f = 8 MHz
V
V
= 2 V
= 5 V
f = 8 MHz
= 5 V
O
S
PP
V
= 5 V
V
S
S
HD3
HD3
HD3
−70
−80
70
80
HD2
HD2
2.5
HD2
−90
90
−100
100
0
0.5
1
1.5
2
3
0.1
1
10
100
0
0.5
1
1.5
2
2.5
3
f − Frequency − MHz
V
− Output Voltage Swing − V
V
- Output Voltage Swing - V
O
O
Figure 66.
Figure 67.
Figure 68.
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs LOAD RESISTANCE
0
−10
−20
0
−10
−20
−30
−40
−50
−60
−70
−80
0
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 2
Differential Input to
Differential Output
Gain = 2
10
20
V
= 2 V
PP
R
L
= 800 Ω
O
R
R
= 800 W
= 1 kW
L
R = 392 Ω
R = 1 kΩ
−30
−40
−50
−60
30
40
50
60
f
f
F
f= 30 MHz
f = 30 MHz
f = 30 MHz
= 5 V
V
= 5 V
V
= 5 V
S
V
S
S
HD2
HD3
HD2
HD3
HD2
HD3
−70
−80
70
80
−90
90
−90
−100
100
−100
0
400
800
1200
1600
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
R
L
− Load Resistance − Ω
V
- Output Voltage Swing - V
O
O
Figure 69.
Figure 70.
Figure 71.
HARMONIC DISTORTION
vs LOAD RESISTANCE
THIRD-ORDER INTERMODULATION
DISTORTION vs FREQUENCY
THIRD-ORDER OUTPUT INTERCEPT
POINT vs FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
55
−50
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Gain = 1
= 2 V
V
O
PP
50
45
40
R
R
V
= 392 W
= 800 W
= 5 V
−60
−70
−80
F
L
V
= 2 V
PP
V
= 2 V
PP
O
O
R
F
= 392 W
R = 392 Ω
f
S
f = 30 MHz
= 5 V
R
V
= 800 Ω
= 5 V
L
V
S
S
HD2
HD3
35
30
−90
−100
-100
0
400
800
1200
1600
0
20
40
60
80
100
120
10
100
R
- Load Resistance - W
f − Frequency − MHz
f - Frequency - MHz
L
Figure 72.
Figure 73.
Figure 74.
SLEW RATE vs DIFFERENTIAL
OUTPUT VOLTAGE STEP
LARGE-SIGNAL TRANSIENT
RESPONSE
SMALL-SIGNAL TRANSIENT
RESPONSE
1400
1200
1000
800
600
400
200
0
2
0.4
0.3
0.2
Gain = 1
1.5
R
L
= 800 Ω
R = 392 Ω
f
1
V
= 5 V
S
Gain = 1
Gain = 1
R = 800 Ω
L
R = 392 Ω
f
0.5
0.1
0
R
L
= 800 Ω
R = 392 Ω
f
0
−0.5
−1
t /t = 300 ps
r
f
t /t = 300 ps
r
f
V
= 5 V
S
V
= 5 V
S
−0.1
−0.2
−0.3
−0.4
−1.5
−2
−100
0
100
200
300
400
500
0
0.5
1
1.5
2
2.5
3
−100
0
100
t − Time − ns
200
300
400
500
t − Time − ns
V
− Differential Output Voltage Step − V
O
Figure 75.
Figure 76.
Figure 77.
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TYPICAL CHARACTERISTICS: 5 V (continued)
VOLTAGE AND CURRENT NOISEvs
FREQUENCY
REJECTION RATIOS
vs FREQUENCY
REJECTION RATIOS
vs CASE TEMPERATURE
90
80
70
60
50
40
30
20
10
0
100
120
100
PSRR+
CMMR
PSRR−
80
60
40
CMMR
PSRR+
V
n
PSRR−
10
I
n
20
0
R
V
= 800 Ω
= 5 V
R
V
= 800 Ω
= 5 V
L
L
S
S
1
0.01 0.1
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
10
100 1000 10 k
0.1
1
10
100
Case Temperature − °C
f − Frequency − MHz
f − Frequency − kHz
Figure 78.
Figure 79.
Figure 80.
OUTPUT BALANCE ERROR
vs FREQUENCY
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
OPEN-LOOP GAIN
vs CASE TEMPERATURE
0
60
57
56
55
54
53
52
51
50
49
48
47
46
30
R = 800 Ω
L
Gain
P
R
V
= −30 dBm
= 800 Ω
= 5 V
P
= −20 dBm
IN
IN
−10
−20
−30
−40
−50
V
= 5 V
S
R
L
= 800 Ω
L
50
40
30
20
0
R = 499 Ω
S
f
V
= 5 V
S
−30
−60
−90
Phase
−120
−150
10
0
−60
−70
−40−30−20−100 10 20 30 40 50 60 70 80 90
0.1
1
10
100
0.01
0.1
1
10
100
1000
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 81.
Figure 82.
Figure 83.
INPUT BIAS AND OFFSET CURRENT
QUIESCENT CURRENT
vs SUPPLY VOLTAGE
INPUT OFFSET VOLTAGE
vs CASE TEMPERATURE
vs CASE TEMPERATURE
3.75
3.5
0
35
30
25
20
15
10
4
V
= 5 V
T
A
= 85°C
S
V
= 5 V
−0.01
−0.02
−0.03
−0.04
−0.05
−0.06
−0.07
−0.08
S
3.5
3
I
IB+
T
A
= 25°C
3.25
3
I
IB−
T
A
= −40°C
2.75
2.5
2.5
2
I
OS
2.25
1.5
2
1
0.5
0
1.75
5
0
−0.09
−0.1
1.5
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Case Temperature − °C
Case Temperature − °C
V
− Supply Voltage − ±V
S
Figure 84.
Figure 85.
Figure 86.
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TYPICAL CHARACTERISTICS: 5 V (continued)
HARMONIC DISTORTION
COMMON-MODE REJECTION RATIO
vs INPUT COMMON-MODE RANGE
OUTPUT DRIVE
vs OUTPUT COMMON-MODE
VOLTAGE
vs CASE TEMPERATURE
0
110
100
90
150
100
50
Single-Ended and
Differential Input
Gain = 1
V
= 5 V
S
Source
V
= 5 V
S
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
V
= 2 V
O PP
80
R = 392 Ω
f
70
f= 8 MHz, V = 5 V
S
60
50
0
HD3-SE
and Diff
40
30
−50
20
10
−100
−150
Sink
HD2-SE
HD2-Diff
0
−10
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
1
1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
−1
0
1
2
3
4
5
V
− Output Common-Mode Voltage − V
Input Common-Mode Range − V
Case Temperature − °C
OCM
Figure 87.
Figure 88.
Figure 89.
SMALL-SIGNAL FREQUENCY
RESPONSE AT VOCM
OUTPUT OFFSET VOLTAGE vs
QUIESCENT CURRENT
OUTPUT COMMON-MODE VOLTAGE
vs POWER-DOWN VOLTAGE
800
25
20
4
3
V
= 5 V
S
Gain = 1
600
400
200
R
L
= 800 Ω
R = 392 Ω
f
P
V
= −20 dBm
= 5 V
IN
2
S
15
10
5
1
0
0
−200
−400
−600
−800
−1
−2
−3
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
0.1
1
10
100
1000
Power-down Voltage − V
V
− Output Common-Mode Voltage − V
OC
f − Frequency − MHz
Figure 90.
Figure 91.
Figure 92.
TURN-ON AND TURN-OFF DELAY
TIME
SINGLE-ENDED OUTPUT IMPEDANCE
IN POWER-DOWN vs FREQUENCY
POWER-DOWN QUIESCENT
CURRENT vs CASE TEMPERATURE
1100
800
700
600
500
0.03
R
= 800 Ω
= 5 V
L
1000
900
800
700
0.02
V
S
0.01
Current
0
0
600
500
400
300
200
−1
400
300
−2
−3
−4
Gain = 1
= 400 Ω
R = 499 Ω
f
R
L
200
P
V
= −1 dBm
= 5 V
IN
S
100
0
100
0
0.1
−5
−6
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
f − Frequency − MHz
Case Temperature − °C
t − Time − ms
Figure 93.
Figure 94.
Figure 95.
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TYPICAL CHARACTERISTICS: 5 V (continued)
POWER-DOWN QUIESCENT
CURRENT vs SUPPLY VOLTAGE
1000
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
V
− Supply Voltage − V
S
Figure 96.
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APPLICATION INFORMATION
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
FULLY DIFFERENTIAL AMPLIFIERS
Fully differential amplifiers are typically packaged in
eight-pin packages, as shown in Figure 97. The
device pins include two inputs (VIN+, VIN–), two
outputs (VOUT–, VOUT+), two power supplies (VS+, VS–),
an output common-mode control pin (VOCM), and an
optional power-down pin (PD).
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems,
including
immunity
to
external
common-mode noise, suppression of even-order
nonlinearities, and increased dynamic range. Fully
differential amplifiers not only serve as the primary
means of providing gain to a differential signal chain,
but also provide a monolithic solution for converting
single-ended signals into differential signals for
easier, higher performance processing. The THS4500
family of amplifiers contains products in Texas
Instruments' expanding line of high-performance, fully
differential amplifiers. Information on fully differential
amplifier fundamentals, as well as implementation
specific information, is presented in the Applications
Section of this data sheet to provide a better
understanding of the operation of the THS4500 family
of devices, and to simplify the design process for
designs using these amplifiers.
VIN-
VOCM
VS+
VIN+
PD
1
8
2
7
3
4
6
5
VS-
VOUT+
VOUT-
Figure 97. Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in
Figure 97. The functionality of a fully differential
amplifier can be imagined as two inverting amplifiers
that share a common noninverting terminal (though
the voltage is not necessarily fixed). For more
information on the basic theory of operation for fully
differential amplifiers, refer to the Texas Instruments
application note Fully Differential Amplifiers, literature
number SLOA054, available for download at
www.ti.com.
APPLICATIONS SECTION
•
•
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
•
•
•
•
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
Setting the Output Common-Mode Voltage With
the VOCM Input
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the
four devices. The THS4502 and THS4503 have an
input common-mode range that is centered around
midrail, and the THS4500 and THS4501 have an
input common-mode range that is shifted to include
the negative power-supply rail. Selection of one or
the other amplifier is determined by the nature of the
application. Specifically, the THS4500 and THS4501
are designed for use in single-supply applications
where the input signal is ground-referenced, as
depicted in Figure 98. The THS4502 and THS4503
are designed for use in single-supply or split-supply
applications where the input signal is centered
between the power-supply voltages, as depicted in
Figure 99.
•
•
Saving Power with Power-Down Functionality
Linearity:
Definitions,
Terminology,
Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for
Optimal Performance
Power Dissipation and Thermal Considerations
•
•
•
•
Power Supply Decoupling Techniques and
Recommendations
•
•
Evaluation
Fixtures,
Spice
Models,
and
Applications Support
Additional Reference Material
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VIN)(1–β)–VIN–(1–β) ) 2VOCMβ
+
R
G1
R
F1
R
S
VOUT)
2β
(1)
+V
S
R
T
–VIN)(1–β) ) VIN–(1–β) ) 2VOCMβ
2β
V
S
VOUT–
+
(2)
(3)
+
-
V
OCM
VN + VIN–(1–β) ) VOUT)
β
+
-
Where:
RG
β +
R
R
F2
G2
RF ) RG
(4)
(5)
VP + VIN)(1–β) ) VOUT–β
Figure 98. Application Circuit for the THS4500 and
THS4501, Featuring Single-Supply Operation With
a Ground-Reference Input Signal
NOTE: The equations denote the device inputs as VN and VP, and
the circuit inputs as VIN+ and VIN–
.
R
G
R
F
R
G1
R
F1
R
S
V
IN+
+V
S
R
T
V
P
V
S
V
V
+
OUT-
-
+
-
V
OCM
+
V
OCM
-
+
OUT+
-
V
N
-V
S
V
IN-
R
G
R
F
R
G2
R
F2
Figure 100. Diagram For Input Common-Mode
Range Equations
Figure 99. Application Circuit for the THS4500 and
THS4501, Featuring Split-Supply Operation With
an Input Signal Referenced at the Midrail
Table 1 and Table 2 depict the input common-mode
range requirements for two different input scenarios,
an input referenced around the negative rail and an
input referenced around midrail. The tables highlight
the differing requirements on input common-mode
range, and illustrate the reasoning to choose either
the THS4500/1 or the THS4502/3. For signals
referenced around the negative power supply, the
THS4500/1 should be chosen because its input
common-mode range includes the negative supply
rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power-supply rails.
Equation 1 through Equation 5 are used to calculate
the required input common-mode range for a given
set of input conditions.
The equations allow calculation of the input
common-mode range requirements, given information
about the input signal, the output voltage swing, the
gain, and the output common-mode voltage.
Calculating the maximum and minimum voltage
required for VN and VP (the amplifier input nodes)
determines whether or not the input common-mode
range is violated or not. Four equations are required:
two calculate the output voltages and two calculate
the node voltages at VN and VP (note that only one of
these nodes needs calculation, because the amplifier
forces a virtual short between the two nodes).
Table 1. Negative-Rail Referenced
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
)
1
2
4
8
–2.0 to 2.0
–1.0 to 1.0
–0.5 to 0.5
–0.25 to 0.25
0
0
0
0
4
2
2.5
2.5
2.5
2.5
4
4
4
4
0.75
0.5
1.75
1.167
0.7
1
0.3
0.5
0.167
0.389
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Table 2. Midrail Referenced
Gain
(V/V)
VIN+
(V)
VIN–
(V)
VIN
(VPP
VOCM
(V)
VOD
(VPP)
VNMIN
(V)
VNMAX
(V)
)
1
2
4
8
0.5 to 4.5
1.5 to 3.5
2.0 to 3.0
2.25 to 2.75
2.5
2.5
2.5
2.5
4
2
2.5
2.5
2.5
2.5
4
4
4
4
2
3
2.16
2.3
2.83
2.7
1
0.5
2.389
2.61
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
BASIC DESIGN CONSIDERATIONS
The circuits in Figure 98 through Figure 100 are used
to highlight basic design considerations for fully
differential amplifier circuit designs.
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values
presented in this section provide the optimum
high-frequency performance (lowest distortion, flat
frequency response). Since the THS4500 family of
amplifiers is developed with a voltage feedback
architecture, the choice of resistor values does not
have a dominant effect on bandwidth, unlike a
current-feedback amplifier. However, resistor choices
do have second-order effects. For optimal
performance, the following feedback resistor values
are recommended. In higher gain configurations (gain
greater than two), the feedback resistor values have
much less effect on the high-frequency performance.
Example feedback and gain resistor values are given
in the section on basic design considerations
(Table 3).
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
R2 and R4
VOD
ǒ Ǔ
VIN
R1 (Ω)
R3 (Ω)
RT (Ω)
Gain
(Ω)
1
1
392
499
412
523
215
665
274
681
147
698
383
487
187
634
249
649
118
681
54.9
53.6
60.4
52.3
56.2
52.3
64.9
52.3
2
392
2
1.3 k
1.3 k
3.32 k
1.3 k
6.81 k
5
5
10
10
Amplifier loading, noise, and the flatness of the
frequency response are three design parameters that
should be considered when selecting feedback
resistors. Larger resistor values contribute more noise
and can induce peaking in the ac response in low
gain configurations; smaller resistor values can load
the amplifier more heavily, resulting in a reduction in
distortion performance. In addition, feedback resistor
values, coupled with gain requirements, determine
the value of the gain resistors and directly impact the
input impedance of the entire circuit. While there are
no strict rules about resistor selection, these trends
can provide qualitative design guidance.
Equations for calculating fully differential amplifier
resistor values in order to obtain balanced operation
in the presence of a 50-Ω source impedance are
given in Equation 6 through Equation 9.
R2
R1
1
K +
R2 + R4
RT +
K
1–
2(1)K)
1
RS
–
ǒ
TǓ
R3
R3 + R1 * Rs || R
(6)
(7)
R3 ) RT || RS
R3 ) RT || RS ) R4
R1
R1 ) R2
β1 +
β2 +
VOD
VS
1–β2
β1 ) β2
RT
RT ) RS
+ 2ǒ Ǔǒ Ǔ
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
(8)
(9)
VOD
VIN
1–β2
+ 2ǒ Ǔ
β1 ) β2
Fully differential amplifiers provide designers with a
great deal of flexibility in
a
wide variety of
applications. This section provides an overview of
some common circuit configurations and gives some
design guidelines. Designing the interface to an
analog-to-digital converter (ADC), driving lines
differentially, and filtering with fully differential
amplifiers are a few of the circuits that are covered.
For more detailed information about balance in fully
differential amplifiers, see the application report, Fully
Differential Amplifiers (SLOA054), referenced at the
end of this data sheet.
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INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
•
Decouple the VOCM pin to eliminate the antenna
effect. VOCM is a high-impedance node that can
act as an antenna. A large decoupling capacitor
on this node eliminates this problem.
Know the input common-mode range. If the input
signal is referenced around the negative
power-supply rail (for example, around ground on
The THS4500 family of amplifiers are designed
specifically
to
interface
to
today's
•
highest-performance ADCs. This section highlights
the key concerns when interfacing to an ADC and
provides example interface circuits.
a
single 5 V supply), then the THS4500/1
There are several key design concerns when
interfacing to an analog-to-digital converter:
accommodates the input signal. If the input signal
is referenced around midrail, choose the
THS4502/3 for the best operation.
•
Terminate the input source properly. In
high-frequency receiver chains, the source that
feeds the fully differential amplifier requires a
specific load impedance (that is, 50 Ω).
•
Packaging makes
a
difference at higher
frequencies. If possible, choose the smaller,
thermally-enhanced MSOP package for the best
performance. As
temperatures provide better performance. If
possible, use thermally-enhanced package,
even if the power dissipation is relatively small
compared to the maximum power dissipation
rating to achieve the best results.
Understand the effect of the load impedance seen
by the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level
of intermodulation distortion performance.
a
rule, lower junction
•
Design a symmetric printed circuit board (PCB)
layout. Even-order distortion products are heavily
influenced by layout, and careful attention to a
symmetric layout minimizes these distortion
products.
Minimize inductance in power-supply decoupling
traces and components. Poor power-supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power-supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the
current loop.
a
•
•
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
•
•
Use separate analog and digital power supplies
and grounds. Noise (bounce) in the power
supplies (created by digital switching currents) can
couple directly into the signal path, and
power-supply noise can create higher distortion
products as well.
Use care when filtering. While an RC low-pass
filter may be desirable on the output of the
amplifier to filter broadband noise, the excess
loading can negatively impact the amplifier
linearity. Filtering in the feedback path does not
have this effect.
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess
power dissipation that can occur due to
level-shifting the output through the output
common-mode voltage control.
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop
fully differential amplifiers drive a specific output
voltage regardless of the load impedance present.
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at
the output of the data converter. Two representative
circuits shown below highlight single-supply operation
and split supply operation, respectively. Specific
feedback resistor, gain resistor, and feedback
capacitor values are not shown, as these values
depend on the frequency of interest. Information on
calculating these values can be found in the
applications material above.
•
•
C
F
R
S
R
G
R
F
5 V
V
R
T
S
5 V
10 mF 0.1 mF
R
R
ISO
+
IN
-
ADS5410
V
OCM
+
12-Bit/80 MSPS
IN
-
CM
1 mF
THS4503
ISO
Terminating the output of
amplifier with a heavy load adversely affects the
amplifier linearity.
a fully differential
10 mF 0.1 mF
5
V
R
G
0.1 mF
R
F
•
Comprehend the VOCM input drive requirements.
Determine if the ADC voltage reference can
provide the required amount of current to move
VOCM to the desired value. A buffer may be
needed.
C
F
Figure 101. Using the THS4503 With the ADS5410
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FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
C
F
R
S
R
G
R
F
Similar to single-ended counterparts, fully differential
amplifiers have the ability to couple filtering
functionality with voltage gain. Numerous filter
topologies can be based on fully differential
amplifiers. Several of these are outlined in the
application report A Differential Circuit Collection
(literature number SLOA064), referenced at the end
of this data sheet. The circuit below depicts a simple,
two-pole, low-pass filter applicable to many different
types of systems. The first pole is set by the resistors
and capacitors in the feedback paths, and the second
pole is set by the isolation resistors and the capacitor
across the outputs of the isolation resistors.
5 V
V
R
S
T
5 V
10 mF 0.1 mF
R
ISO
+
ADS5421
-
IN
V
OCM
+
14-Bit/40 MSPS
IN
-
CM
1 mF
THS4501
R
ISO
R
G
R
F
C
F
0.1 mF
Figure 102. Using the THS4501 With the ADS5421
FULLY DIFFERENTIAL LINE DRIVERS
C
F1
R
G1
R
F1
R
S
R
R
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers.
ISO
R
T
V
S
+
-
V
C
O
The high power-supply voltage rating (16.5
V
+
-
absolute maximum) allows operation on a single 12-V
or a single 15-V supply. The high supply voltage,
coupled with the ability to provide differential outputs,
enables the ability to drive 26 VPP into reasonably
heavy loads (250 Ω or greater). The circuit in
Figure 103 illustrates the THS4500 family of devices
used as high-speed line drivers. For line driver
applications, close attention must be paid to thermal
design constraints because of the typically high level
of power dissipation.
R
G2
ISO
R
F2
C
F2
Figure 104. A Two-Pole, Low-Pass Filter Design
Using a Fully Differential Amplifier With Poles
Located at: P1 = (2πRFCF)–1 in Hz and
P2 = (4πRISOC)–1 in Hz
C
G
R
R
F
R
G
S
Often, filters like these are used to eliminate
broadband noise and out-of-band distortion products
in signal acquisition systems. It should be noted that
the increased load placed on the output of the
15 V
C
R
S
T
R
R
ISO
V
S
+
-
V
OCM
R
V
DD
L
THS4500/2
+
-
0.1 mF
amplifier by the second low-pass filter has
a
ISO
V
C
S
detrimental effect on the distortion performance. The
preferred method of filtering is to use the feedback
network, as the typically smaller capacitances
required at these points in the circuit do not load the
amplifier nearly as heavily in the passband.
R
F
= 26 V
PP
OD
R
G
C
G
Figure 103. Fully Differential Line Driver With High
Output Swing
26
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SETTING THE OUTPUT COMMON-MODE
VOLTAGE WITH THE VOCM INPUT
Since the VOCM pin provides the ability to set an
output common-mode voltage, the ability for
increased power dissipation exists. While this
possibility does not pose a performance problem for
the amplifier, it can cause additional power
dissipation of which the system designer should be
aware. The circuit shown in Figure 106 demonstrates
an example of this phenomenon. For a device
operating on a single 5-V supply with an input signal
referenced around ground and an output
common-mode voltage of 2.5 V, a dc potential exists
between the outputs and the inputs of the device. The
amplifier sources current into the feedback network in
order to provide the circuit with the proper operating
point. While there are no serious effects on the circuit
performance, the extra power dissipation may need to
be included in the system power budget.
The output common-mode voltage pin provides a
critical function to the fully differential amplifier; it
accepts an input voltage and reproduces that input
voltage as the output common-mode voltage. In other
words, the VOCM input provides the ability to level-shift
the outputs to any voltage inside the output voltage
swing of the amplifier.
A description of the input circuitry of the VOCM pin is
shown in Figure 105 to facilitate an easier
understanding of the VOCM interface requirements.
The VOCM pin has two 50-kΩ resistors between the
power supply rails to set the default output
common-mode voltage to midrail. A voltage applied to
the VOCM pin alters the output common-mode voltage
as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors.
This phenomenon is depicted in the VOCM equivalent
circuit diagram. Current drive is especially important
when using the reference voltage of an
analog-to-digital converter to drive VOCM. Output
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some
applications.
V
OCM
I
1
=
R
F1
+R + R || R
G1 S T
DC Current Path to Ground
R
G1
R
F1
R
S
2.5-V DC
5 V
R
T
V
S
+
-
R
L
V
OCM
= 2.5 V
+
-
V
S+
R = 50 kW
R = 50 kW
2.5-V DC
R
R
F2
G2
2 V
- V - V
S+ S-
OCM
I
IN
=
DC Current Path to Ground
V
OCM
R
V
OCM
I
IN
I
2
=
R
+ R
G2
F2
Figure 106. Depiction of DC Power Dissipation
Caused By Output Level-Shifting in a DC-Coupled
Circuit
V
S-
Figure 105. Equivalent Input Circuit for VOCM
By design, the input signal applied to the VOCM pin
propagates to the outputs as a common-mode signal.
As shown in Figure 105, the VOCM input has a high
impedance associated with it, dictated by the two
50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and
any associated PCB traces to act as an antenna. For
this reason, a decoupling capacitor is recommended
on this node for the sole purpose of filtering any
high-frequency noise that could couple into the signal
path through the VOCM circuitry. A 0.1-µF or 1-µF
capacitance is a reasonable value for eliminating a
great deal of broadband interference, but additional,
tuned decoupling capacitors should be considered if a
specific source of electromagnetic or radio frequency
interference is present elsewhere in the system.
Information on the ac performance (bandwidth, slew
rate) of the VOCM circuitry is included in the Electrical
Characteristics and Typical Characterisitcs sections.
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SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
Intercept points are specifications that have long
been used as key design criteria in the RF
communications world as
a
metric for the
The THS4500 family of fully differential amplifiers
contains devices that come with and without the
power-down option. Even-numbered devices have
power-down capability, which is described in detail
here.
intermodulation distortion performance of a device in
the signal chain (for example, amplifiers, mixers,
etc.). Use of the intercept point, rather than strictly the
intermodulation distortion, allows for simpler
system-level calculations. Intercept points, like noise
figures, can be easily cascaded back and forth
through a signal chain to determine the overall
receiver chain intermodulation distortion performance.
The relationship between intermodulation distortion
and intercept point is depicted in Figure 107 and
Figure 108.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (that is, an internal pull-up resistor is present),
putting the amplifier in the power-on mode of
operation. To turn off the amplifier in an effort to
conserve power, the power-down pin can be driven
towards the negative rail. The threshold voltages for
power-on and power-down are relative to the supply
rails and given in the specification tables. Above the
enable threshold voltage, the device is on. Below the
disable threshold voltage, the device is off. Behavior
between these threshold voltages is not specified.
P
O
P
O
∆f = f − f1
c
c
Note that this power-down functionality is just that;
the amplifier consumes less power in power-down
mode. The power-down mode is not intended to
provide a high-impedance output. In other words, the
power-down functionality is not intended to allow use
as a 3-state bus driver. When in power-down mode,
the impedance looking back into the output of the
amplifier is dominated by the feedback and gain
setting resistors.
∆f = f2 − f
c
c
IMD = P − P
O
3
S
P
S
P
S
f − 3∆f f1
f
f2
f + 3∆f
c
c
c
The time delays associated with turning the device on
and off are specified as the time it takes for the
amplifier to reach 50% of the nominal quiescent
current. The time delays are on the order of
microseconds because the amplifier moves in and out
of the linear mode of operation in these transitions.
f − Frequency − MHz
Figure 107. 2-Tone and 3rd-Order Intermodulation
Products
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
The
THS4500
family
of
devices
features
unprecedented distortion performance for monolithic
fully differential amplifiers. This section focuses on
the fundamentals of distortion, circuit techniques for
reducing nonlinearity, and methods for equating
distortion of fully differential amplifiers to desired
linearity specifications in RF receiver chains.
Amplifiers are generally thought of as linear devices.
In other words, the output of an amplifier is a linearly
scaled version of the input signal applied to it. In
reality, however, amplifier transfer functions are
nonlinear. Minimizing amplifier nonlinearity is
primary design goal in many applications.
a
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Ť
Ť
ǒ Ǔwhere
IMD3
2
OIP3 + PO )
P
OUT
(10)
(dBm)
V2Pdiff
P + 10 logǒ Ǔ
1X
O
2RL 0.001
OIP
3
NOTE: P is the output power of a single tone, R is the
o
L
differentialload resistance, and V
is the differential
P(diff)
peak voltage for a single tone.
(11)
P
O
As can be seen in the equations, when a higher
impedance is used, the same level of intermodulation
distortion performance results in a lower intercept
point. Therefore, it is important to understand the
impedance seen by the output of the fully differential
amplifier when selecting a minimum intercept point.
Figure 109 shows the relationship between the strict
definition of an intercept point with a normalized, or
equivalent, intercept point for the THS4500.
IMD
IIP
3
P
IN
3
(dBm)
3X
P
S
60
Normalized to 200 Ω
Figure 108. Graphical Representation of 2-Tone
and 3rd-Order Intercept Point
55
Normalized to 50 Ω
50
45
40
35
Due to the intercept point ease-of-use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related
design decisions. Traditionally, these systems use
primarily class-A, single-ended RF amplifiers as gain
blocks. These RF amplifiers are typically designed to
operate in a 50-Ω environment, just like the rest of
the receiver chain. Since intercept points are given in
dBm, this implies an associated impedance (50 Ω).
OIP R = 800 Ω
3
L
30
25
Gain = 1
R = 392 Ω
f
V
= ± 5 V
S
20
15
Tone Spacing = 200 kHz
0
10 20 30 40 50 60 70 80 90 100
f − Frequency − MHz
However, with a fully differential amplifier, the output
does not require termination as an RF amplifier
would. Because closed-loop amplifiers deliver signals
to the outputs regardless of the impedance present, it
is important to comprehend this feature when
evaluating the intercept point of a fully differential
amplifier. The THS4500 series of devices yields
optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of
an analog-to-digital converter over its input frequency
band. As a result, terminating the input of the ADC to
Figure 109. Equivalent 3rd-Order Intercept Point
for the THS4500
Comparing specifications between different device
types becomes easier when a common impedance
level is assumed. For this reason, the intercept points
on the THS4500 family of devices are reported
normalized to a 50-Ω load impedance.
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
50
Ω can actually be detrimental to system
performance.
Noise analysis in fully differential amplifiers is
analogous to noise analysis in single-ended
amplifiers; the same concepts apply. Figure 110
shows a generic circuit diagram consisting of a
voltage source, a termination resistor, two gain
setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the
relevant noise sources. From this circuit, the noise
factor (F) and noise figure (NF) are calculated. The
figures indicate the appropriate scaling factor for each
of the noise sources in two different cases. The first
case includes the termination resistor, and the
This discontinuity between open-loop, class-A
amplifiers and closed-loop, class-AB amplifiers
becomes apparent when comparing the intercept
points of the two types of devices. Equation 10 gives
the definition of an intercept point, relative to the
intermodulation distortion.
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second, simplified case assumes that the voltage
source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier
input noise power (NA) can be calculated by summing
each individual noise source with its scaling factor.
The noise delivered to the amplifier by the source (NI)
and input noise power are used to calculate the noise
factor and noise figure as shown in Equation 23
through Equation 27.
Scaling Factors for Individual Noise Sources
Asseming No Termination Resistance is Used
(that is, RT is Open)
N : Fully Differential Amplifier; termination = 2R
A
g
Noise
Source
Scale Factor
2
Rg
ȡRg
ȣ
Rs
Ȥ
)
2
(e )
ni
R
ȧ
f
ȧ
Rg )
Ȣ
2
(18)
(19)
(20)
e
g
e
f
2
(i )
ni
R
g
R
f
2
R
N
i
N
A
g
2
2
R
g
(i )
ii
2
S
e
i
n
ǒRgǓ
2
N
4kTR
N
S
i
f
Rf
o
(21)
(22)
2
ȣ
ȧ
R
+
s
Rg
ȧR )
o
ȡ
R
fully-diff
amp
−
t
i
ni
2
N
4kTR
o
R
g
s
2
g
e
s
Ȣ
Ȥ
e
t
Input Noise With a Termination Resistor
i
ii
2
e
g
e
f
ȡ
ȣ
R
g
R
f
2RtRg
N + 4kTR ȧ
ȧ
ȧ
Rt)2Rg
s
ȧ
i
2RtRg
R )
ȧ s R )2R ȧ
g
t
Figure 110. Noise Sources in a Fully Differential
Amplifier Circuit
Ȣ
Ȥ
(23)
Input Noise Assuming No Termination Resistor
Scaling Factors for Individual Noise Sources
Assuming a Finite Value Termination Resistor
N : Fully Differential Amplifier
A
2
2RG
Ni = 4kTRS
RS + 2RG
(24)
Noise
Source
Scale Factor
Noise Factor and Noise Figure Calculations
NA = S(Noise Source ´ Scale Factor)
2
(25)
ȡR
ȧR
ȣ
ȧ
Ȥ
Rg
RsRt
NA
F = 1 +
NI
g
)
2
(e )
ni
f
Rg )
(26)
(27)
ǒ
Ǔ
2 Rs)Rt
Ȣ
(12)
(13)
(14)
NF + 10 log (F)
2
R
2
(i )
ni
g
2
R
2
(i )
ii
g
2
2RsRG
ȡ
ȣ
Rs)2Rg
4kTR
t
ȧ
ȢRt )
ȧ
2RsRg
Ȥ
Rs)2Rg
(15)
(16)
2
ǒRgǓ
2
4kTR
f
Rf
2
ȡ
Rg
RsRt
ȣ
4kTR
2
g
ȧ
ȧ
Ǔ
t Ȥ
Rg )
ǒ
2 Rs)R
Ȣ
(17)
30
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THS4500
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PRINTED CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
values greater than 2.0 kΩ, this parasitic
capacitance can add a pole and/or a zero below
400 MHz that can affect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to PCB layout parasitic and external
component types.
•
Connections to other wideband devices on the
board may be made with short direct traces or
through onboard transmission lines. For short
connections, consider the trace and the input to
the next device as a lumped capacitive load.
Relatively wide traces (50 mils to 100 mils, or 1.27
mm to 2.54 mm) should be used, preferably with
ground and power planes opened up around
them. Estimate the total capacitive load and
determine if isolation resistors on the outputs are
necessary. Low parasitic capacitive loads (less
than 4 pF) may not need an RS since the
THS4500 family is nominally compensated to
operate with a 2-pF parasitic load. Higher parasitic
capacitive loads without an RS are allowed as the
signal gain increases (increasing the unloaded
phase margin). If a long trace is required, and the
6-dB signal loss intrinsic to a doubly-terminated
transmission line is acceptable, implement a
matched impedance transmission line using
microstrip or stripline techniques (consult an ECL
design handbook for microstrip and stripline layout
techniques).
Recommendations that optimize performance include:
•
Minimize parasitic capacitance to any ac ground
for all of the signal I/O pins. Parasitic capacitance
on the output and input pins can cause instability.
To reduce unwanted capacitance,
a window
around the signal I/O pins should be opened in all
of the ground and power planes around those
pins. Otherwise, ground and power planes should
be unbroken elsewhere on the board.
•
Minimize the distance (< 0.25”, 6.35 mm) from the
power-supply pins to high frequency 0.1-µF
decoupling capacitors. At the device pins, the
ground and power-plane layout should not be in
close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors.
Larger (6.8 µF or more) tantalum decoupling
capacitors, effective at lower frequency, should
also be used on the main supply pins. These may
be placed somewhat farther from the device and
may be shared among several devices in the
same area of the PCB. The primary goal is to
•
A 50-Ω environment is normally not necessary
onboard, and in fact,
a higher impedance
environment improves distortion as shown in the
distortion versus load plots. With a characteristic
board trace impedance defined based onboard
material and trace dimensions, a matching series
resistor into the trace from the output of the
THS4500 family is used as well as a terminating
shunt resistor at the input of the destination
device.
Remember also that the terminating impedance is
the parallel combination of the shunt resistor and
the input impedance of the destination device: this
total effective impedance should be set to match
the trace impedance. If the 6-dB attenuation of a
minimize
differential-current return paths.
Careful selection and placement of external
components preserve the high-frequency
performance of the THS4500 family. Resistors
should be very low reactance type.
the
impedance
seen
in
the
•
a
•
Surface-mount resistors work best and allow a
tighter overall layout. Metal-film and carbon
composition, axially-leaded resistors can also
provide good high frequency performance. Again,
keep the leads and PCB trace length as short as
possible. Never use wirewound type resistors in a
high-frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the
feedback and series output resistors, if any, as
close as possible to the inverting input pins and
output pins. Other network components, such as
input termination resistors, should be placed close
to the gain-setting resistors. Even with a low
parasitic capacitance shunting the external
resistors, excessively high resistor values can
create significant time constants that can degrade
doubly-terminated
unacceptable,
transmission
long trace
line
can
is
be
a
series-terminated at the source end only. Treat
the trace as a capacitive load in this case. This
configuration does not preserve signal integrity as
well as a doubly-terminated line. If the input
impedance of the destination device is low, there
is some signal attenuation due to the voltage
divider formed by the series output into the
terminating impedance.
Socketing a high-speed part such as the THS4500
family is not recommended. The additional lead
length and pin-to-pin capacitance introduced by
the socket can create an extremely troublesome
parasitic network that can make it almost
•
performance.
Good
axial
metal-film
or
surface-mount resistors have approximately
0.2 pF in shunt with the resistor. For resistor
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impossible to achieve a smooth, stable frequency
response. Best results are obtained by soldering
0.205
the THS4500 family parts directly onto the board.
0.060
0.017
PowerPAD DESIGN CONSIDERATIONS
Pin 1
0.013
The
THS4500
family
is
available
in
a
thermally-enhanced PowerPAD set of packages.
These packages are constructed using a downset
leadframe upon which the die is mounted [see
Figure 111(a) and Figure 111(b)]. This arrangement
results in the lead frame being exposed as a thermal
pad on the underside of the package [see
Figure 111(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good
thermal path away from the thermal pad.
0.030
0.075
0.025 0.094
0.035
0.040
0.010
vias
Top View
Figure 112. PowerPAD PCB Etch and Via Pattern
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as
shown in Figure 112. There should be etch for
the leads as well as etch for the thermal pad.
The PowerPAD package allows for both assembly
and thermal management in one manufacturing
operation. During the surface-mount solder operation
(when the leads are being soldered), the thermal pad
can also be soldered to a copper area underneath the
package. Through the use of thermal paths within this
copper area, heat can be conducted away from the
package into either a ground plane or other heat
dissipating device.
2. Place five holes in the area of the thermal pad.
These holes should be 13 mils (0.33 mm) in
diameter. Keep them small so that solder wicking
through the holes is not a problem during reflow.
The PowerPAD package represents a breakthrough
in combining the small area and ease of assembly of
surface mount with the, heretofore, awkward
mechanical methods of heatsinking.
3. Additional vias may be placed anywhere along
the thermal plane outside of the thermal pad
area. These holes help dissipate the heat
generated by the THS4500 family IC. These
additional vias may be larger than the 13-mil
diameter vias directly under the thermal pad.
They can be larger because they are not in the
thermal pad area to be soldered so that wicking
is not a problem.
DIE
Thermal
Pad
Side View (a)
DIE
4. Connect all holes to the internal ground plane.
End View (b)
Bottom View (c)
5. When connecting these holes to the ground
plane, do not use the typical web or spoke via
connection methodology. Web connections have
a high thermal resistance connection that is
useful for slowing the heat transfer during
soldering operations. This transfer slowing makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
Figure 111. Views of PowerPAD,
Thermally-Enhanced Package
Although there are many ways to properly heatsink
the PowerPAD package, the following steps illustrate
the recommended approach.
complete
connection
around
the
entire
circumference of the plated-through hole.
32
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6. The top-side solder mask should leave the
terminals of the package and the thermal pad
area with its five holes exposed. The bottom-side
solder mask should cover the five holes of the
thermal pad area. This configuration prevents
solder from being pulled away from the thermal
pad area during the reflow process.
Figure 113 for the two packages. The data for the
DGN package assumes a board layout that follows
the PowerPAD layout guidelines referenced above
and detailed in the PowerPAD application notes in
the Additional Reference Material section at the end
of the data sheet.
3.5
7. Apply solder paste to the exposed thermal pad
area and all of the IC terminals.
8-Pin DGN Package
3
8. With these preparatory steps in place, the IC is
simply placed in position and run through the
solder reflow operation as any standard
surface-mount component. This process results
in a part that is properly installed.
2.5
2
8-Pin D Package
1.5
1
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
0.5
0
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer
must take care to ensure that the design does not
violate the absolute maximum junction temperature of
the device. Failure may result if the absolute
maximum junction temperature of +150°C is
−40
−20
0
20
40
60
80
T
− Ambient Temperature − °C
A
θ
θ
Τ
= 170°C/W for 8-Pin SOIC (D)
= 58.4°C/W for 8-Pin MSOP (DGN)
= 150°C, No Airflow
JA
JA
J
exceeded. For best performance, design for
a
Figure 113. Maximum Power Dissipation vs
Ambient Temperature
maximum junction temperature of +125°C. Between
+125°C and +150°C, damage does not occur, but the
performance of the amplifier begins to degrade.
When determining whether or not the device satisfies
the maximum power dissipation requirement, it is
important to not only consider quiescent power
dissipation, but also dynamic power dissipation. Often
times, this consideration is difficult to quantify
because the signal pattern is inconsistent; an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
The thermal characteristics of the device are dictated
by the package and the PCB. Maximum power
dissipation for a given package can be calculated
using the following formula.
TMAX - TA
PDmax
=
qJA
(28)
Where:
DRIVING CAPACITIVE LOADS
PDmax is the maximum power dissipation in the
amplifier (W).
TMAX is the absolute maximum junction
temperature (°C).
TA is the ambient temperature (°C).
θJA = θJC + θCA
θJC is the thermal coefficient from the silicon
junctions to the case (°C/W).
θCA is the thermal coefficient from the case to
ambient air (°C/W).
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however,
the load capacitance should be isolated by two
isolation resistors in series with the output. The
requisite isolation resistor size depends on the value
of the capacitance, but 10 Ω to 25 Ω is a good place
to begin the optimization process. Larger isolation
resistors decrease the amount of peaking in the
frequency response induced by the capacitive load,
but this decreased peaking comes at the expense ofa
larger voltage drop across the resistors, increasing
the output swing requirements of the system.
For systems where heat dissipation is more critical,
the THS4500 family of devices is offered in an
MSOP-8 package with PowerPAD. The thermal
coefficient for the MSOP PowerPAD package is
substantially improved over the traditional SOIC.
Maximum power dissipation levels are depicted in
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
SLOS350E–APRIL 2002–REVISED MAY 2008.............................................................................................................................................................. www.ti.com
THS4501 product folder on the Texas Instruments
R
F
web site, www.ti.com, or through your local Texas
Instruments sales representative. A schematic for the
evaluation board is shown in Figure 115 with the
default component values. Unpopulated footprints are
shown to provide insight into design flexibility.
V
S
R
G
R
S
R
R
ISO
+
-
V
S
C
L
R
T
+
-
ISO
-V
S
C4
C0805
Riso = 10 - 25 W
R4
R
F
R0805
PD
R
G
V
S
U1
J2
J1
C5
C0805
THS450X
4
J2
J3
3
C1
R6
R2
7
1
8
_
R0805
C0805
C2
R1206
R0805
R0805
C7
C0805
R0805
R1
J3
Figure 114. Use of Isolation Resistors With a
Capacitive Load
+
5
C0805
R3
6
R7
2
PwrPad
C6
C0805
-V
S
V
OCM
R5 R0805
C3
POWER-SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
C0805
J2
J4
R8
Power-supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance
(most notably improved distortion performance). The
following guidelines ensure the highest level of
performance.
4
5
3
1
R0805
R9
R0805
R11
R1206
J3
R0805
6
R9
T1
Figure 115. Simplified Schematic of the
Evaluation Board
1. Place decoupling capacitors as close to the
power-supply inputs as possible, with the goal of
minimizing the inductance of the path from
ground to the power supply.
Computer simulation of circuit performance using
SPICE is often useful when analyzing the
performance of analog circuits and systems. This
practice is particularly true for video and RF amplifier
circuits where parasitic capacitance and inductance
can have a major effect on circuit performance. A
SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web
site (www.ti.com) or as one model on a disk from the
Texas Instruments Product Information Center
(1-800-548-6132). The PIC is also available for
design assistance and detailed product information at
this number. These models do a good job of
predicting small-signal ac and transient performance
under a wide variety of operating conditions. They are
not intended to model the distortion characteristics of
the amplifier, nor do they attempt to distinguish
between the package types in their small-signal ac
performance. Detailed information about what is and
is not modeled is contained in the model file itself.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
3. Use of solid power and ground planes is
recommended to reduce the inductance along
power-supply return current paths.
4. Recommended
values
for
power-supply
decoupling include 10-µF and 0.1-µF capacitors
for each supply. A 1000-pF capacitor can be
used across the supplies as well for extremely
high frequency return currents, but often is not
required.
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
Texas Instruments is committed to providing its
customers with the highest quality of applications
support. To support this goal, an evaluation board
has been developed for the THS4500 family of fully
differential amplifiers. The evaluation board can be
obtained by ordering through the THS4500 or
34
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Product Folder Link(s): THS4500 THS4501
THS4500
THS4501
www.ti.com .............................................................................................................................................................. SLOS350E–APRIL 2002–REVISED MAY 2008
ADDITIONAL REFERENCE MATERIAL
•
•
•
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
PowerPAD Thermally-Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number
SLOA054D.
•
•
•
•
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High-Speed ADCs, and
Differential Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature
Number SLOA064.
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments
Literature Number SLOA072.
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog
Applications Journal, July 2001.
Revision History
Changes from Revision D (January 2004) to Revision E ............................................................................................... Page
•
•
•
•
•
Updated document format ..................................................................................................................................................... 1
Clarified cross-references throughout the document............................................................................................................. 1
Added footnote 1 to Package/Ordering Information table ..................................................................................................... 3
Changed x-axis of Figure 27................................................................................................................................................ 12
Updated crossreferences for Figure 97 in first two paragraphs of the Fully Differential Amplifier Terminal Functions
section.................................................................................................................................................................................. 22
•
•
Added available for download at www.ti.com and end of second paragraph of the Fully Differential Amplifier
Terminal Functions section.................................................................................................................................................. 22
Changed allow for calculation of to are used to calculate in second paragraph of Input Common-Mode Voltage
Range and the THS4500 Family section............................................................................................................................. 22
•
•
•
•
•
•
•
•
Clarified last sentence of third paragraph of Input Common-Mode Voltage Range and the THS4500 Family section ...... 22
Changed two to four in first sentence of Input Common-Mode Voltage Range and the THS4500 Family section ............ 22
Corrected title of Basic Design Considerations section....................................................................................................... 24
Clarified cross-references of the circuits mentioned in the first sentence of the Basic Design Considerations section ..... 24
Deleted figure from Basic Design Considerations section................................................................................................... 24
Corrected cross-references in first sentence of Basic Design Considerations section ....................................................... 24
Clarified the Interfacing to an Analog-to-Digital Converter section...................................................................................... 25
Removed cross-reference to nonexistant tble in second paragraph of Setting the Output Common-Mode Voltage
with the VOCM Input section.................................................................................................................................................. 27
•
•
Added caption titles to figures in the Linearity: Definitions, Terminology, Circuit Techniques, and Design Treadeoffs
section.................................................................................................................................................................................. 28
Changed THS4502 to THS4500 in seventh paragraph of Linearity: Definitions, Terminology, Circuit Techniques, and
Design Treadeoffs section ................................................................................................................................................... 28
•
•
•
•
•
Corrected spelling in title of An Analysis of Noise in Fully Differential Amplifiers section................................................... 29
Added 6.35 mm to second bullet of Printed Circuit Board Layout Techniques for Optimal Performance list ..................... 31
Added 1.27 mm to 2.54 mm to fourth bullet of Printed Circuit Board Layout Techniques for Optimal Performance list .... 31
Added 0.33 mm to second list item in the PowerPAD PCB Layout Considerations section............................................... 32
Changed title of Figure 115 ................................................................................................................................................. 34
Copyright © 2002–2008, Texas Instruments Incorporated
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Product Folder Link(s): THS4500 THS4501
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2009
PACKAGING INFORMATION
Orderable Device
THS4500CD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500CDG4
THS4500CDGK
THS4500CDGKG4
THS4500CDGKR
THS4500CDGKRG4
THS4500CDGN
SOIC
MSOP
MSOP
MSOP
MSOP
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGK
DGK
DGK
DGK
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500CDGNG4
THS4500CDGNR
THS4500CDGNRG4
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500ID
THS4500IDG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500IDGK
THS4500IDGKG4
THS4500IDGKR
THS4500IDGKRG4
THS4500IDGN
MSOP
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGK
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500IDGNG4
THS4500IDGNR
ACTIVE
ACTIVE
ACTIVE
MSOP-
Power
PAD
DGN
DGN
DGN
8
8
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500IDGNRG4
MSOP-
Power
PAD
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500IDR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4500IDRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2009
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
no Sb/Br)
THS4501CD
THS4501CDG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501CDGK
THS4501CDGKG4
THS4501CDGKR
THS4501CDGKRG4
THS4501CDGN
MSOP
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGK
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501CDGNG4
ACTIVE
MSOP-
Power
PAD
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501ID
THS4501IDG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
D
8
8
8
8
8
8
8
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
75 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501IDGK
THS4501IDGKG4
THS4501IDGKR
THS4501IDGKRG4
THS4501IDGN
MSOP
MSOP
MSOP
MSOP
DGK
DGK
DGK
DGK
DGN
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
MSOP-
Power
PAD
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501IDGNG4
ACTIVE
MSOP-
Power
PAD
DGN
8
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501IDR
ACTIVE
ACTIVE
SOIC
D
D
8
8
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
THS4501IDRG4
SOIC
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
27-Aug-2009
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4500CDGKR
THS4500CDGNR
MSOP
DGK
DGN
8
8
2500
2500
330.0
330.0
12.4
12.4
5.2
5.2
3.3
3.3
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
THS4500IDGKR
THS4500IDGNR
MSOP
DGK
DGN
8
8
2500
2500
330.0
330.0
12.4
12.4
5.2
5.2
3.3
3.3
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
MSOP-
Power
PAD
THS4500IDR
THS4501CDGKR
THS4501IDGKR
THS4501IDR
SOIC
MSOP
MSOP
SOIC
D
8
8
8
8
2500
2500
2500
2500
330.0
330.0
330.0
330.0
12.4
12.4
12.4
12.4
6.4
5.2
5.2
6.4
5.2
3.3
3.3
5.2
2.1
1.6
1.6
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
DGK
DGK
D
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4500CDGKR
THS4500CDGNR
THS4500IDGKR
THS4500IDGNR
THS4500IDR
MSOP
MSOP-PowerPAD
MSOP
DGK
DGN
DGK
DGN
D
8
8
8
8
8
8
8
8
2500
2500
2500
2500
2500
2500
2500
2500
338.1
338.1
338.1
338.1
346.0
338.1
338.1
346.0
340.5
340.5
340.5
340.5
346.0
340.5
340.5
346.0
21.1
21.1
21.1
21.1
29.0
21.1
21.1
29.0
MSOP-PowerPAD
SOIC
THS4501CDGKR
THS4501IDGKR
THS4501IDR
MSOP
DGK
DGK
D
MSOP
SOIC
Pack Materials-Page 2
IMPORTANT NOTICE
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
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logic.ti.com
power.ti.com
microcontroller.ti.com
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Copyright © 2009, Texas Instruments Incorporated
相关型号：
THS4500CDT
IC OP-AMP, 0 uV OFFSET-MAX, 300 MHz BAND WIDTH, PDSO8, PLASTIC, MSOP-8, Operational Amplifier
TI
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