THS4500IDGNR [TI]
具有断电功能的 15V 高速全差分放大器 | DGN | 8 | -40 to 85;
| 型号： | THS4500IDGNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有断电功能的 15V 高速全差分放大器 | DGN | 8 | -40 to 85 放大器 光电二极管 运算放大器 放大器电路 |
| 文件： | 总37页 (文件大小：582K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢉ
ꢘ
ꢍ
ꢚ
ꢛ
ꢉ
ꢘ
ꢙ
ꢚ
ꢛ
ꢉ
ꢚ
ꢛ
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ꢇ
ꢈ
ꢉ
ꢊ
ꢋ
ꢌ
ꢍ
ꢉ
ꢎ
ꢏ
ꢐ
ꢇ
ꢑ
ꢉ
ꢈ
ꢂ
ꢀ
ꢐ
ꢒ
ꢀ
ꢈ
ꢐ
ꢍ
ꢓ
ꢔ
ꢏ
ꢏ
ꢕ
ꢉ
ꢈ
ꢓ
ꢓ
ꢊ
ꢒ
ꢊ
ꢍ
ꢀ
ꢈ
ꢌ
ꢏ
ꢌ
ꢖ
ꢗ
ꢏ
ꢈ
ꢓ
ꢈ
ꢊ
ꢒ
ꢂ
FEATURES
APPLICATIONS
D
High Linearity Analog-to-Digital Converter
Preamplifier
D
D
D
D
D
D
D
Fully Differential Architecture
Bandwidth: 370 MHz
D
D
D
D
Wireless Communication Receiver Chains
Single-Ended to Differential Conversion
Differential Line Driver
Slew Rate: 2800 V/µs
IMD : −90 dBc at 30 MHz
3
OIP : 49 dBm at 30 MHz
3
Active Filtering of Differential Signals
Output Common-Mode Control
Wide Power Supply Voltage Range: 5 V, 5 V,
12 V, 15 V
1
8
V
IN+
V
IN−
2
7
V
PD
V
OCM
D
Input Common-Mode Range Shifted to
Include the Negative Power Supply Rail
3
4
6
5
V
S+
S−
D
Power-Down Capability (THS4500)
Evaluation Module Available
V
V
OUT+
OUT−
D
RELATED DEVICES
DESCRIPTION
DEVICE(1)
DESCRIPTION
THS4500/1
THS4502/3
THS4120/1
THS4130/1
THS4140/1
THS4150/1
370 MHz, 2800 V/µs, V
Includes V
S−
The THS4500 and THS4501 are high-performance fully
differential amplifiers from Texas Instruments. The
THS4500, featuring power-down capability, and the
THS4501, without power-down capability, set new
performance standards for fully differential amplifiers
with unsurpassed linearity, supporting 14-bit operation
through 40 MHz. Package options include the 8-pin
SOIC and the 8-pin MSOP with PowerPAD for a
smaller footprint, enhanced ac performance, and
improved thermal dissipation capability.
ICR
370 MHz, 2800 V/µs, Centered V
ICR
3.3 V, 100 MHz, 43 V/µs, 3.7 nV√Hz
15 V, 150 MHz, 51 V/µs, 1.3 nV√Hz
15 V, 160 MHz, 450 V/µs, 6.5 nV√Hz
15 V, 150 MHz, 650 V/µs, 7.6 nV√Hz
(1)
Even numbered devices feature power-down capability
10 pF
APPLICATION CIRCUIT DIAGRAM
THIRD-ORDER INTERMODULATION
DISTORTION
392 Ω
−62
10
12
5 V
V
= 5 V
S
−68
−74
−80
5 V
0.1 µF
10 µF
50 Ω
374 Ω
56.2 Ω
24.9 Ω
24.9 Ω
V
= 5 V
+
S
−
ADC
12 Bit/80 MSps
IN
V
OCM
V
S
IN
+
−
V
ref
392 Ω
1 µF
V
+
S+
374 Ω
50 Ω
−86
−92
14
16
V
OUT
−
V
OCM
800 Ω
2.5 V
56.2 Ω
V
+
S
402 Ω
−
V
402 Ω
S−
392 Ω
392 Ω
−98
50
10
20
30
40
60
70
80
90
100
10 pF
f − Frequency − MHz
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
ꢔ ꢍꢏ ꢊꢂꢂ ꢐ ꢀꢁ ꢊꢒ ꢇ ꢈꢂ ꢊ ꢍ ꢐ ꢀꢊꢉ ꢜꢝꢞ ꢟ ꢠꢡꢢ ꢣꢤ ꢥꢦꢜ ꢢꢡ ꢦꢜꢧ ꢞꢦꢟ ꢗꢒ ꢐ ꢉ ꢔ ꢨꢀ ꢈꢐ ꢍ ꢉ ꢌꢀꢌ
ꢦ
Copyright 2002−2004, Texas Instruments Incorporated
ꢞ
ꢦ
ꢩ
ꢡ
ꢪ
ꢤ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢢ
ꢣ
ꢪ
ꢪ
ꢥ
ꢦ
ꢜ
ꢧ
ꢟ
ꢡ
ꢩ
ꢫ
ꢣ
ꢬ
ꢭ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢠ
ꢧ
ꢜ
ꢥ
ꢮ
ꢗ
ꢪ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢟ
ꢢ
ꢡ
ꢩ
ꢡ
ꢪ
ꢤ
ꢜ
ꢡ
ꢟ
ꢫ
ꢥ
ꢢ
ꢞ
ꢩ
ꢞ
ꢢ
ꢧ
ꢜ
ꢞ
ꢡ
ꢦ
ꢟ
ꢫ
ꢥ
ꢪ
ꢜ
ꢝ
ꢥ
ꢜ
ꢥ
ꢪ
ꢤ
ꢟ
ꢡ
ꢩ
ꢀ
ꢥ
ꢯ
ꢧ
ꢟ
ꢈ
ꢦ
ꢟ
ꢜ
ꢪ
ꢣ
ꢤ
ꢥ
ꢦ
ꢜ
ꢟ
ꢟ
ꢜ
ꢧ
ꢦ
ꢠ
ꢧ
ꢪ
ꢠ
ꢰ
ꢧ
ꢪ
ꢪ
ꢧ
ꢦ
ꢜ
ꢱ
ꢮ
ꢗ
ꢪ
ꢡ
ꢠ
ꢣ
ꢢ
ꢜ
ꢞ
ꢡ
ꢦ
ꢫ
ꢪ
ꢡ
ꢢ
ꢥ
ꢟ
ꢟ
ꢞ
ꢦ
ꢲ
ꢠ
ꢡ
ꢥ
ꢟ
ꢦ
ꢡ
ꢜ
ꢦ
ꢥ
ꢢ
ꢥ
ꢟ
ꢟ
ꢧ
ꢪ
ꢞ
ꢭ
ꢱ
ꢞ
ꢦ
ꢢ
ꢭ
ꢣ
ꢠ
ꢥ
ꢜ
ꢥ
ꢟ
ꢜ
ꢞ
ꢦ
ꢲ
ꢡ
ꢩ
ꢧ
ꢭ
ꢭ
ꢫ
ꢧ
ꢪ
ꢧ
ꢤ
ꢥ
ꢜ
ꢥ
ꢪ
ꢟ
ꢮ
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be
handledwith appropriate precautions. Failure to observe
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
(1)
proper handling and installation procedures can cause damage.
UNIT
Supply voltage, V
16.5 V
S
ESD damage can range from subtle performance degradation to
complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could
cause the device not to meet its published specifications.
Input voltage, V
I
V
S
(2)
Output current, I
150 mA
4 V
O
Differential input voltage, V
ID
PACKAGE DISSIPATION RATINGS
Continuous power dissipation
See Dissipation Rating Table
(2)
POWER RATING
(1)
θ
JA
(3)
θ
Maximum junction temperature, T
150°C
JC
(°C/W) (°C/W)
J
PACKAGE
T
A
≤ 25°C = 85°C
T
A
Maximum junction temperature, continuous
operation, long term reliability T
J
125°C
(4)
D (8 pin)
38.3
4.7
97.5
58.4
260
1.02 W
1.71 W
410 mW
685 mW
154 mW
C suffix
0°C to 70°C
−40°C to 85°C
−65°C to 150°C
DGN (8 pin)
DGK (8 pin)
Operating free-air temperature
range, T
I suffix
A
54.2
385 mW
(1)
(2)
Storage temperature range, T
stg
This data was taken using the JEDEC standard High-K test PCB.
Power rating is determined with a junction temperature of 125°C.
This is the point where distortion starts to substantially increase.
Thermalmanagement of the final PCB should strive to keep the
junctiontemperature at or below 125°C for best performance and
long term reliability.
Lead temperature
1,6 mm (1/16 inch) from case for 10 seconds
300°C
HBM
4000 V
2000 V
100 V
CDM
ESD ratings:
MM
(1)
Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods
may degrade device reliability. These are stress ratings only, and
functional operation of the device at these or any other conditions
beyond those specified is not implied.
The THS4500/1 may incorporate a PowerPAD on the underside
of the chip. This acts as a heat sink and must be connected to a
thermally dissipative plane for proper power dissipation. Failure
to do so may result in exceeding the maximum junction
temperature which could permanently damage the device. See TI
technical briefs SLMA002 and SLMA004 for more information
about utilizing the PowerPAD thermally enhanced package.
The absolute maximum temperature under any condition is
limited by the constraints of the silicon process.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM MAX UNIT
Dual supply
5
7.5
15
Supply voltage
V
Single supply
4.5
0
5
(2)
Operating free-
air temperature,
C suffix
I suffix
70
85
°C
−40
T
A
(3)
(4)
The maximum junction temperature for continuous operation is
limited by package constraints. Operation above this temperature
may result in reduced reliability and/or lifetime of the device.
PACKAGE/ORDERING INFORMATION
ORDERABLE PACKAGE AND NUMBER
(1)
PLASTIC MSOP
PowerPad
PLASTIC
SMALL OUTLINE
(D)
(1)
PLASTIC MSOP
TEMPERATURE
(DGN)
SYMBOL
BFB
(DGK)
SYMBOL
ATV
THS4500CD
THS4501CD
THS4500ID
THS4501ID
THS4500CDGN
THS4501CDGN
THS4500IDGN
THS4501IDGN
THS4500CDGK
THS4501CDGK
THS4500IDGK
THS4501IDGK
0°C to 70°C
BFD
ATW
BFC
ASV
−40°C to 85°C
BFE
ASW
(1)
All packages are available taped and reeled. The R suffix standard quantity is 2500. The T suffix standard quantity is 250 (e.g., THS4501DT).
2
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
PIN ASSIGNMENTS
D, DGN, DGK
D, DGN, DGK
THS4500
THS4501
(TOP VIEW)
(TOP VIEW)
VIN−
VOCM
VS+
VIN+
PD
VIN−
VOCM
VS+
VIN+
NC
1
8
1
8
2
7
2
7
3
4
6
5
3
4
6
5
VS−
VS−
VOUT+
VOUT−
VOUT+
VOUT−
ELECTRICAL CHARACTERISTICS V = 5 V
S
R = R = 392 Ω, R = 800 Ω, G = +1, Single-ended input unless otherwise noted.
f
g
L
THS4500 AND THS4501
OVER TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C to
85°C
25°C
25°C
UNITS
AC PERFORMANCE
G = +1, P = −20 dBm, R = 392 Ω
IN
370
175
70
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
f
G = +2, P = −30 dBm, R = 1 kΩ
IN
f
Small-signal bandwidth
G = +5, P = −30 dBm, R = 2.4 kΩ
IN
f
G = +10, P = −30 dBm, R = 5.1 kΩ
30
IN
f
Gain-bandwidth product
Bandwidth for 0.1dB flatness
Large-signal bandwidth
Slew rate
G > +10
= −20 dBm
300
150
220
2800
0.4
P
IN
V
P
= 2 V
4 V
2 V
2 V
Step
PP
PP
PP
Rise time
Step
Step
Fall time
0.5
ns
Settling time to 0.01%
0.1%
V
V
= 4 V
8.3
ns
O
PP
PP
= 4 V
6.3
ns
O
Harmonic distortion
G = +1, V = 2 V
O
PP
f = 8 MHz
f = 30 MHz
f = 8 MHz
f = 30 MHz
−82
−71
−97
−74
dBc
dBc
dBc
dBc
nd
2
3
harmonic
harmonic
rd
Third-order intermodulation
distortion
V
= 2 V , f = 30 MHz,
PP
O
c
−90
49
dBc
Typ
Typ
R = 392 Ω, 200 kHz tone spacing
f
f = 30 MHz, R = 392 Ω,
c
f
Third-order output intercept point
dBm
Referenced to 50 Ω
Input voltage noise
Input current noise
f > 1 MHz
f > 100 kHz
7
nV/√Hz
pA/√Hz
ns
Typ
Typ
Typ
1.7
60
Overdrive recovery time
Overdrive = 5.5 V
3
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS V = 5 V
S
R = R = 392 Ω, R = 800 Ω, G = +1, Single-ended input unless otherwise noted (continued).
f
g
L
THS4500 AND THS4501
OVER TEMPERATURE
TYP
MIN/
TYP/
MAX
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C to
85°C
25°C
25°C
UNITS
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Average offset voltage drift
Input bias current
55
−4
52
50
−8 / 0
10
50
−9 / +1
10
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
−7 / −1
µV/°C
µA
4
4.6
1
5
5.2
10
Average bias current drift
Input offset current
10
nA/°C
µA
0.5
2
2
Average offset current drift
INPUT
40
40
nA/°C
−5.7/2.
6
Common-mode input range
−5.4 / 2.3
74
−5.1 / 2
70
−5.1 / 2
70
V
Min
Common-mode rejection ratio
Input impedance
80
dB
Min
Typ
7
10 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Differential output current drive
Output balance error
R
R
= 1 kΩ
= 20 Ω
8
7.6
7.4
7.4
V
Min
Min
Typ
L
120
−58
110
100
100
mA
dB
L
P
IN
= −20 dBm, f = 100 kHz
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
R
= 400 Ω
180
92
MHz
V/µs
V/V
V/V
mV
µA
Typ
Typ
Min
Max
Max
Max
Min
L
2 V
step
PP
Minimum gain
1
0.98
1.02
0.98
1.02
0.98
1.02
Maximum gain
1
Common-mode offset voltage
−0.4
100
4
−4.6/+3.8 −6.6/+5.8 −7.6/+6.8
Input bias current
V
= 2.5 V
150
3.7
170
3.4
170
3.4
OCM
Input voltage range
V
Input impedance
25 || 1
0
kΩ || pF Typ
Maximum default voltage
Minimum default voltage
POWER SUPPLY
V
V
left floating
left floating
0.05
0.10
0.10
V
V
Max
Min
OCM
0
−0.05
−0.10
−0.10
OCM
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection ( PSRR)
POWER DOWN (THS4500 ONLY)
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
5
23
23
80
7.5
28
18
76
7.5
32
14
73
7.5
34
12
70
V
Max
Max
Min
Min
mA
mA
dB
Device enabled ON above –2.9 V
Device disabled OFF below –4.3 V
−2.9
−4.3
1000
240
V
V
Min
Max
Max
Max
800
200
1200
260
1200
260
µA
µA
Input impedance
50 || 1
1000
800
kΩ || pF Typ
Turnon time delay
ns
ns
Typ
Typ
Turnoff time delay
4
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS V = 5 V
S
R = R = 392 Ω, R = 800 Ω, G = +1, Single-ended input unless otherwise noted.
f
g
L
THS4500 AND THS4501
TYP
OVER TEMPERATURE
MIN/
PARAMETER
TEST CONDITIONS
TYP/
0°C to
70°C
−40°C to
85°C
25°C
25°C
UNITS
MAX
AC PERFORMANCE
G = +1, P = −20 dBm, R = 392 Ω
IN
320
160
60
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
ns
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
Typ
f
G = +2, P = −30 dBm, R = 1 kΩ
IN
f
Small-signal bandwidth
G = +5, P = −30 dBm, R = 2.4 kΩ
IN
f
G = +10, P = −30 dBm, R = 5.1 kΩ
30
IN
f
Gain-bandwidth product
Bandwidth for 0.1 dB flatness
Large-signal bandwidth
Slew rate
G > +10
= −20 dBm
300
180
200
1300
0.5
P
IN
V
P
= 1 V
2 V
2 V
2 V
Step
PP
PP
PP
Rise time
Step
Step
Fall time
0.6
ns
Settling time to 0.01%
0.1%
V
= 2 V Step
= 2 V Step
13.1
8.3
ns
O
V
O
ns
Harmonic distortion
G = +1, V = 2 V
O
PP
f = 8 MHz,
f = 30 MHz
f = 8 MHz
−80
−55
−76
−60
7
dBc
dBc
nd
2
3
harmonic
harmonic
dBc
rd
f = 30 MHz
f > 1 MHz
dBc
Input voltage noise
Input current noise
nV/√Hz
pA/√Hz
ns
f > 100 kHz
1.7
60
Overdrive recovery time
DC PERFORMANCE
Open-loop voltage gain
Input offset voltage
Average offset voltage drift
Input bias current
Overdrive = 5.5 V
54
−4
51
49
−8 / 0
10
49
−9 / +1
10
dB
mV
Min
Max
Typ
Max
Typ
Max
Typ
−7 / −1
µV/°C
µA
4
4.6
0.7
5
5.2
Average bias current drift
Input offset current
Average offset current drift
INPUT
10
10
nA/°C
µA
0.5
1.2
20
1.2
20
nA/°C
−0.7/2.
6
Common-mode input range
−0.4 / 2.3
74
−0.1 / 2
70
−0.1 / 2
70
V
Min
Common-mode rejection ratio
Input Impedance
80
dB
Min
Typ
7
10 || 1
Ω || pF
OUTPUT
Differential output voltage swing
Output current drive
Output balance error
R
= 1 kΩ, Referenced to 2.5 V
3.3
100
−58
3
2.8
80
2.8
80
V
Min
Min
Typ
L
R
L
= 20 Ω
90
mA
dB
P
= −20 dBm, f = 100 kHz
IN
Closed-loop output impedance
(single-ended)
f = 1 MHz
0.1
Ω
Typ
5
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ELECTRICAL CHARACTERISTICS V = 5 V
S
R = R = 392 Ω, R = 800 Ω, G = +1, Single-ended input unless otherwise noted (continued).
f
g
L
THS4500 AND THS4501
OVER TEMPERATURE
TYP
PARAMETER
TEST CONDITIONS
0°C to
70°C
−40°C
to 85°C
MIN/
MAX
25°C
25°C
UNITS
OUTPUT COMMON-MODE VOLTAGE CONTROL
Small-signal bandwidth
Slew rate
R
= 400 Ω
180
80
MHz
V/µs
V/V
V/V
mV
µA
Typ
Typ
Min
Max
Max
Max
Min
Typ
Max
Min
L
2 V
Step
PP
Minimum gain
1
0.98
1.02
0.98
1.02
0.98
1.02
Maximum gain
1
Common-mode offset voltage
Input bias current
0.4
1
−2.6/3.4
2
−4.2/5.4 −5.6/6.4
V
= 2.5 V
3
3
OCM
Input voltage range
1 / 4
25 || 1
2.5
2.5
1.2 / 3.8
1.3 / 3.7 1.3 / 3.7
V
Input impedance
kΩ || pF
V
Maximum default voltage
Minimum default voltage
POWER SUPPLY
V
V
left floating
left floating
2.55
2.45
2.6
2.4
2.6
2.4
OCM
OCM
V
Specified operating voltage
Maximum quiescent current
Minimum quiescent current
Power supply rejection (+PSRR)
POWER DOWN (THS4500 ONLY)
Enable voltage threshold
Disable voltage threshold
Power-down quiescent current
Input bias current
5
15
25
16
72
15
29
12
69
15
31
10
66
V
Max
Max
Min
Min
20
20
75
mA
mA
dB
Device enabled ON above 2.1 V
Device disabled OFF below 0.7 V
2.1
0.7
V
V
Min
Max
Max
Max
Typ
Typ
Typ
600
100
800
125
1200
140
1200
140
µA
µA
Input impedance
50 || 1
1000
800
kΩ || pF
ns
Turnon time delay
Turnoff time delay
ns
6
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs ( 5 V)
FIGURE
Small signal unity gain frequency response
Small signal frequency response
1
2
0.1 dB gain flatness frequency response
Large signal frequency response
3
4
Harmonic distortion (single-ended input to differential output) vs Frequency
Harmonic distortion (differential input to differential output) vs Frequency
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
Harmonic distortion (differential input to differential output) vs Output voltage swing
Harmonic distortion (single-ended input to differential output) vs Load resistance
Harmonic distortion (differential input to differential output) vs Load resistance
Third order intermodulation distortion (single-ended input to differential output) vs Frequency
Third order output intercept point vs Frequency
Slew rate vs Differential output voltage step
5, 7, 13, 15
6, 8, 14, 16
9, 11, 17, 19
10, 12, 18, 20
21
22
23
24
25
Settling time
26, 27
28
Large signal transient response
Small signal transient response
29
Overdrive recovery
30, 31
32
Voltage and current noise vs Frequency
Rejection ratios vs Frequency
33
Rejection ratios vs Case temperature
34
Output balance error vs Frequency
35
Open-loop gain and phase vs Frequency
36
Open-loop gain vs Case temperature
37
Input bias offset current vs Case temperature
Quiescent current vs Supply voltage
38
39
Input offset voltage vs Case temperature
40
Common-mode rejection ratio vs Input common-mode range
Output drive vs Case temperature
41
42
Harmonic distortion (single-ended and differential input to differential output) vs Output common-mode voltage
43
44
45
46
47
48
49
50
Small signal frequency response at V
OCM
vs Output common-mode voltage
Output offset voltage at V
OCM
Quiescent current vs Power-down voltage
Turnon and turnoff delay times
Single-ended output impedance in power down vs Frequency
Power-down quiescent current vs Case temperature
Power-down quiescent current vs Supply voltage
7
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS
Table of Graphs (5 V)
FIGURE
Small signal unity gain frequency response
Small signal frequency response
51
52
0.1 dB gain flatness frequency response
Large signal frequency response
53
54
Harmonic distortion (single-ended input to differential output) vs Frequency
Harmonic distortion (differential input to differential output) vs Frequency
Harmonic distortion (single-ended input to differential output) vs Output voltage swing
Harmonic distortion (differential input to differential output) vs Output voltage swing
Harmonic distortion (single-ended input to differential output) vs Load resistance
Harmonic distortion (differential input to differential output) vs Load resistance
Third-order intermodulation distortion vs Frequency
Third-order intercept point vs Frequency
55, 57, 63, 65
56, 58, 64, 66
59, 61, 67, 69
60, 62, 68, 70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
Slew rate vs Differential output voltage step
Large-signal transient response
Small-signal transient response
Voltage and current noise vs Frequency
Rejection ratios vs Frequency
Rejection ratios vs Case temperature
Output balance error vs Frequency
Open-loop gain and phase vs Frequency
Open-loop gain vs Case temperature
Input bias offset current vs Case temperature
Quiescent current vs Supply voltage
Input offset voltage vs Case temperature
Common-mode rejection ratio vs Input common-mode range
Output drive vs Case temperature
Harmonic distortion (single-ended and differential input) vs Output common-mode voltage
Small signal frequency response at V
OCM
Output offset voltage vs Output common-mode voltage
Quiescent current vs Power-down voltage
Turnon and turnoff delay times
Single-ended output impedance in power down vs Frequency
Power-down quiescent current vs Case temperature
Power-down quiescent current vs Supply voltage
8
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
22
1
0.3
Gain = 10, R = 5.1 kΩ
f
Gain = 1
20
18
16
14
12
10
0.5
R
L
= 800 Ω
0.2
0.1
0
P
V
= −20 dBm
IN
S
0
−0.5
−1
=
5 V
Gain = 5, R = 2.4 kΩ
f
R = 499 Ω
f
−1.5
−2
8
6
4
2
Gain = 2, R = 1 kΩ
R = 392 Ω
f
f
Gain = 1
−0.1
−2.5
−3
R
L
= 800 Ω
R = 392 Ω
f
R
L
= 800 Ω
−0.2
−0.3
P
V
= −20 dBm
IN
S
P
V
= −30 dBm
IN
S
−3.5
−4
=
5 V
0
−2
=
5 V
0.1
1
10
100
1000
0.1
1
10
100
1000
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 1
Figure 2
Figure 3
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
LARGE SIGNAL FREQUENCY RESPONSE
FREQUENCY
FREQUENCY
1
0
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−30
−40
−50
−60
−70
−80
−20
−30
−40
−50
−60
−70
−80
0
R
L
= 800 Ω
R
L
= 800 Ω
R = 392 Ω
R = 392 Ω
f
O
S
f
O
S
V
V
= 1 V
=
−1
V
V
= 1 V
=
PP
5 V
PP
5 V
−2
Gain = 1
HD2
R
L
= 800 Ω
HD2
10
R = 392 Ω
−3
−4
f
P
V
= 10 dBm
IN
S
−90
−90
=
5 V
HD3
HD3
−100
−100
0.1
1
100
0.1
1
10
100
1000
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 4
Figure 5
Figure 6
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
OUTPUT VOLTAGE SWING
0
0
−10
0
Single-Ended Input to
Differential Output
Gain = 1
= 800 Ω
R = 392 Ω
Differential Input to
Differential Output
Gain = 1
R = 800 Ω
L
R = 392 Ω
Single-Ended Input to
Differential Output
Gain = 1
−10
−10
−20
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
R
R
L
= 800 Ω
L
−30
−40
−30
−40
R = 392 Ω
f
O
S
f
O
S
f
V
= 2 V
=
V
V
= 2 V
f= 8 MHz
PP
5 V
PP
= 5 V
V
V
= 5 V
S
−50
−60
−70
−80
−50
−60
−70
−80
HD2
HD2
10
HD2
10
HD3
−90
−90
HD3
HD3
4
−100
−100
0
0.5
1
1.5
2
2.5
3
3.5
4.5
5
0.1
1
100
0.1
1
100
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Swing − V
O
Figure 7
Figure 8
Figure 9
9
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R = 800 Ω
L
R
L
= 800 Ω
R = 499 Ω
R = 392 Ω
R = 392 Ω
f
f
f
f= 8 MHz
f= 30 MHz
V = 5 V
S
f= 30 MHz
V
=
5 V
V
= 5 V
S
S
HD2
HD2
HD2
HD3
HD3
3
HD3
4.5
0
0.5
1
1.5
2
2.5
3
3.5
4
5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
0.5
1
1.5
2
2.5
3.5
4
4.5
5
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
V
− Output Voltage Swing − V
O
O
Figure 10
Figure 11
Figure 12
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−10
−20
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
= 800 Ω
L
R
= 800 Ω
R
= 800 Ω
L
L
−30
−40
−50
R = 1 kΩ
f
O
S
R = 1 kΩ
R = 1 kΩ
f
O
S
f
O
S
V
V
= 1 V
=
PP
5 V
V
V
= 1 V
=
V
V
= 2 V
=
PP
5 V
PP
5 V
−60
−70
−80
HD2
HD2
HD2
HD3
HD3
−90
HD3
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 13
Figure 14
Figure 15
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
0
−10
−20
0
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
−30
−40
−50
R = 1 kΩ
f
O
S
R = 1 kΩ
R = 1 kΩ
f
f
V
V
= 2 V
=
PP
5 V
f= 8 MHz
f= 8 MHz
V = 5 V
S
V
=
5 V
S
HD2
−60
−70
−80
HD2
2.5
HD2
HD3
−90
HD3
3.5
HD3
3.5
−100
0.1
1
10
100
0
0.5
1
1.5
2
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
f − Frequency − MHz
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
O
Figure 16
Figure 17
Figure 18
10
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
LOAD RESISTANCE
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
0
0
0
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 2
Differentia Input to
Differential Output
Gain = 2
−10
−10
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
−60
−70
−80
−90
−100
−20
−30
−40
−50
V
= 2 V
PP
O
R
L
= 800 Ω
R = 800 Ω
L
R = 392 Ω
f
R = 1 kΩ
R = 1 kΩ
f
f
f= 30 MHz
f= 30 MHz
f= 8 MHz
V = 5 V
S
V
= 5 V
S
V
=
5 V
S
HD2
HD2
−60
−70
−80
HD2
HD3
HD3
3.5
HD3
3.5
−90
−100
0
400
800
1200
1600
0
0.5
1
1.5
2
2.5
3
4
4.5
5
0
0.5
1
1.5
2
2.5
3
4
4.5
5
R
L
− Load Resistance − Ω
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
O
Figure 19
Figure 20
Figure 21
THIRD-ORDER INTERMODULATION
THIRD-ORDER OUTPUT INTERCEPT
DISTORTION
vs
POINT
vs
HARMONIC DISTORTION
vs
FREQUENCY
FREQUENCY
LOAD RESISTANCE
0
55
−50
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Gain = 1
−10
R = 392 Ω
f
O
S
50
45
40
−60
−70
−80
−20
−30
−40
−50
V
V
= 2 V
PP
V
= 2 V
PP
R
L
= 800 Ω
O
=
5 V
R = 392 Ω
R = 392 Ω
f
f
O
S
f= 30 MHz
V
V
= 2 V
PP
V
= 5 V
=
5 V
S
−60
−70
−80
HD2
35
30
−90
HD3
−90
−100
−100
0
400
800
1200
1600
10
100
0
20
40
60
80
100
120
f − Frequency − MHz
R
L
− Load Resistance − Ω
f − Frequency − MHz
Figure 22
Figure 23
Figure 24
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
SETTLING TIME
SETTLING TIME
3000
0.8
0.6
0.4
0.2
0
1.5
Gain = 1
Rising Edge
Rising Edge
R
= 800 Ω
L
2500
2000
1500
1
R = 392 Ω
f
V
= 5 V
S
Gain = 1
= 800 Ω
Gain = 1
0.5
R
L
R
L
= 800 Ω
R = 499 Ω
R = 499 Ω
f
f
f= 1 MHz
f= 1 MHz
0
−0.5
−1
V
= 5 V
V
= 5 V
S
S
−0.2
−0.4
1000
500
0
Falling Edge
Falling Edge
−0.6
−0.8
−1.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0
5
10
t − Time − ns
15
20
0
20
40
60
80
100 120 140
V
− Differential Output Voltage Step − V
O
t − Time − ns
Figure 25
Figure 26
Figure 27
11
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
LARGE-SIGNAL TRANSIENT RESPONSE
SMALL-SIGNAL TRANSIENT RESPONSE
OVERDRIVE RECOVERY
0.4
2.5
2
2
5
4
3
Gain = 4
= 800 Ω
0.3
0.2
1.5
1
R
L
R = 499 Ω
1.5
f
Overdrive = 4.5 V
1
2
1
Gain = 1
= 800 Ω
Gain = 1
0.1
V = 5 V
S
0.5
R
R = 800 Ω
L
L
0.5
0
R = 499 Ω
R = 499 Ω
f
f
0
0
0
−0.5
−1
t /t = 300 ps
r f
t /t = 300 ps
r f
V
=
5 V
V = 5 V
S
S
−0.5
−0.1
−1
−1
−2
−3
−0.2
−0.3
−0.4
−1.5
−1.5
−2
−2
−4
−5
−2.5
−100
0
100
200
300
400
500
−100
0
100
200
300
400
500
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t − Time − ns
t − Time − ns
t − Time − µs
Figure 28
Figure 29
Figure 30
VOLTAGE AND CURRENT NOISE
REJECTION RATIOS
vs
vs
FREQUENCY
FREQUENCY
OVERDRIVE RECOVERY
90
100
3
6
5
4
3
2
1
Gain = 4
PSRR+
80
70
60
50
40
30
20
10
0
R
L
= 800 Ω
2
1
R = 499 Ω
f
Overdrive = 5.5 V
V
= 5 V
S
CMMR
V
n
PSRR−
10
0
0
−1
−1
−2
−3
−4
I
n
−2
−3
R
V
= 800 Ω
L
= 5 V
S
−5
−6
1
0.01 0.1
−10
1
10
100 1000 10 k
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0.1
1
10
100
f − Frequency − MHz
t − Time − µs
f − Frequency − kHz
Figure 31
Figure 32
Figure 33
REJECTION RATIOS
vs
CASE TEMPERATURE
OPEN-LOOP GAIN AND FHASE
OUTPUT BALANCE ERROR
vs
vs
FREQUENCY
FREQUENCY
120
100
60
30
0
Gain
P
= −30 dBm
IN
P
= 10 dBm
IN
CMMR
R
L
= 800 Ω
−10
−20
−30
−40
−50
−60
−70
−80
R
L
= 800 Ω
50
40
30
20
0
V
= 5 V
S
R = 392 Ω
f
PSRR+
V
= 5 V
S
80
60
40
20
0
−30
−60
−90
Phase
−120
−150
10
0
R
L
= 800 Ω
V
= 5 V
S
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
0.1
1
10
100
0.01
0.1
1
10
100
1000
Case Temperature − °C
f − Frequency − MHz
f − Frequency − MHz
Figure 34
Figure 35
Figure 36
12
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
OPEN-LOOP GAIN
QUIESCENT CURRENT
vs
INPUT BIAS AND OFFSET CURRENT
vs
vs
CASE TEMPERATURE
SUPPLY VOLTAGE
CASE TEMPERATURE
35
30
25
20
15
10
58
57
56
55
54
53
52
51
50
49
3.4
3.3
0
T
A
= 85°C
V
= 5 V
R
V
= 800 Ω
S
L
S
I
−0.01
IB−
=
5 V
T
A
= 25°C
−0.02
−0.03
−0.04
−0.05
3.2
3.1
I
IB+
T
A
= −40°C
3
2.9
−0.06
−0.07
−0.08
−0.09
2.8
2.7
I
OS
5
0
2.6
2.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−100 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Case Temperature − °C
V
− Supply Voltage − V
S
Figure 37
Figure 38
Figure 39
INPUT OFFSET VOLTAGE
vs
CASE TEMPERATURE
COMMON-MODE REJECTION RATIO
vs
OUTPUT DRIVE
vs
CASE TEMPERATURE
INPUT COMMON-MODE RANGE
7
110
200
150
100
50
V
= 5 V
V
= 5 V
S
V
= 5 V
S
100
90
80
70
60
50
40
30
20
10
S
Source
6
5
4
3
2
0
−50
1
0
Sink
−100
−150
0
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−6 −5 −4 −3 −2 −1
0
1
2
3
4
5
6
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
Case Temperature − °C
Input Common-Mode Voltage Range − V
Case Temperature − °C
Figure 40
Figure 41
Figure 42
OUTPUT OFFSET VOLTAGE at V
vs
HARMONIC DISTORTION
vs
OCM
SMALL SIGNAL FREQUENCY RESPONSE
OUTPUT COMMON-MODE VOLTAGE
at V
OUTPUT COMMON-MODE VOLTAGE
OCM
600
3
0
Single-Ended and Differential
Gain = 1
−10
Input to Differential Output
Gain = 1, V = 2 V
R
L
= 800 Ω
2
1
400
200
R = 392 Ω
O
PP
−20
f
f= 8 MHz, R = 392 Ω
P
= −20 dBm
f
IN
−30
−40
−50
−60
V
=
5 V
V
=
5 V
S
S
HD2-SE
0
0
HD2
-Diff
HD3-SE
HD3-Diff
−1
−200
−70
−80
−2
−3
−400
−600
−90
−100
1
10
100
1000
−5 −4 −3 −2 −1
0
1
2
3
4
5
−3.5 −2.5 −1.5 −0.5 0.5
1.5
2.5 3.5
f − Frequency − MHz
V
− Output Common-Mode Voltage − V
V
− Output Common-Mode Voltage − V
OC
OC
Figure 43
Figure 44
Figure 45
13
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS ( 5 V Graphs)
SINGLE-ENDED OUTPUT IMPEDANCE
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
IN POWER DOWN
vs
FREQUENCY
TURNON AND TURNOFF DELAY TIME
0.03
30
800
0.02
0.01
0
700
600
500
400
25
20
15
10
Current
0
−1
−2
−3
−4
300
Gain = 1
R
L
= 800 Ω
5
200
R = 392 Ω
f
P
V
= −1 dBm
IN
S
0
100
0
−5
−6
=
5 V
−5
−5 −4.5 −4 −3.5 −3 −2.5 −2 −1.5 −1 −0.5
Power-Down Voltage − V
Figure 46
0
0.1
1
10
100
1000
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
t − Time − ms
f − Frequency − MHz
Figure 47
Figure 48
POWER-DOWN QUIESCENT CURRENT
vs
POWER-DOWN QUIESCENT CURRENT
vs
CASE TEMPERATURE
SUPPLY VOLTAGE
1000
1000
R
= 800 Ω
= 5 V
R = 800 Ω
L
L
900
800
700
900
800
700
600
500
400
300
200
V
S
600
500
400
300
200
100
0
100
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
Case Temperature − °C
V
− Supply Voltage − V
S
Figure 49
Figure 50
14
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
0.1 dB GAIN FLATNESS
FREQUENCY RESPONSE
SMALL SIGNAL UNITY GAIN
FREQUENCY RESPONSE
SMALL SIGNAL FREQUENCY RESPONSE
22
1
0
0.2
0.1
0
Gain = 10, R = 5.1 kΩ
f
20
18
16
14
12
10
R = 499 Ω
f
Gain = 5, R = 2.4 kΩ
f
R = 392 Ω
f
−1
−2
−0.1
−0.2
8
6
4
2
Gain = 2, R = 1 kΩ
f
Gain = 1
R
L
= 800 Ω
−0.3
Gain = 1
R = 392 Ω
−3
−4
f
R
P
= 800 Ω
L
R
P
V
= 800 Ω
L
P
V
= −20 dBm
= 5 V
IN
S
= −30 dBm
−0.4
−0.5
IN
S
= −20 dBm
= 5 V
IN
S
0
−2
V
= 5 V
0.1
1
10
100
1000
0.1
1
10
100
1000
10
100
1000
1
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 51
Figure 52
Figure 53
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
LARGE SIGNAL FREQUENCY RESPONSE
FREQUENCY
FREQUENCY
0
1
0
Single-Ended Input to
Differential Output
Gain = 1
Differential Input to
Differential Output
Gain = 1
−10
−10
−20
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
R
L
= 800 Ω
R
L
= 800 Ω
R = 392 Ω
−30
−40
f
O
S
R = 392 Ω
f
O
S
V
V
= 1 V
= 5 V
−1
PP
V
V
= 1 V
= 5 V
PP
−50
−60
−70
−80
−2
HD2
HD2
Gain = 1
R
L
= 800 Ω
R = 392 Ω
−3
−4
f
P
V
= 10 dBm
HD3
IN
S
HD3
= 5 V
1
−90
−100
0.1
10
100
1000
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 54
Figure 55
Figure 56
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
vs
FREQUENCY
FREQUENCY
0
0
0
Differential Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
−10
−20
−30
−40
−50
−60
−70
−80
−10
−20
−30
−40
−10
−20
R
L
= 800 Ω
R
L
= 800 Ω
R
L
= 800 Ω
R = 499 Ω
−30
−40
−50
−60
R = 392 Ω
f
O
S
f
O
S
R = 392 Ω
f
V
V
= 2 V
= 5 V
V
V
= 2 V
= 5 V
PP
PP
f= 8 MHz
V
= 5 V
S
−50
−60
−70
−80
HD3
HD3
HD3
−70
−80
HD2
HD2
HD2
2.5
−90
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0
0.5
1
1.5
2
3
f − Frequency − MHz
f − Frequency − MHz
V
− Output Voltage Swing − V
O
Figure 57
Figure 58
Figure 59
15
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
0
−10
−20
0
−10
−20
0
−10
−20
Single-Ended Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
Differentia Input to
Differential Output
Gain = 1
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
R = 392 Ω
f = 30 MHz
−30
−40
−50
−60
−30
−40
−50
−60
−30
−40
−50
−60
R = 392 Ω
R = 392 Ω
f
f
f
HD3
f= 8 MHz
f= 30 MHz
HD3
V
= 5 V
V
= 5 V
V = 5 V
S
S
S
HD2
HD2
HD3
−70
−80
−70
−80
−70
−80
HD2
−90
−90
−90
−100
−100
−100
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
V − Output Voltage Swing − V
O
O
O
Figure 60
Figure 61
Figure 62
HARMONIC DISTORTION
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0
0
0
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
−10
−20
−30
−10
−20
−30
−10
−20
R
L
= 800 Ω
R
L
= 800 Ω
R = 800 Ω
L
−30
−40
−50
R = 1 kΩ
R = 1 kΩ
R = 1 kΩ
f
O
S
f
O
S
f
O
S
V
V
= 1 V
= 5 V
V
V
= 1 V
= 5 V
V
V
= 2 V
= 5 V
PP
PP
PP
−40
−40
−50
−60
−50
−60
HD2
HD3
−60
−70
−80
HD3
−70
−80
−70
HD2
−80
−90
HD2
HD3
−90
−90
−100
−100
−100
0.1
1
10
100
0.1
1
10
100
0.1
1
10
100
f − Frequency − MHz
f − Frequency − MHz
f − Frequency − MHz
Figure 63
Figure 64
Figure 65
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
HARMONIC DISTORTION
vs
OUTPUT VOLTAGE SWING
vs
FREQUENCY
0
0
−10
−20
0
−10
−20
Differential Input to
Differential Output
Gain = 2
Single-Ended Input to
Differential Output
Gain = 2
Differentia Input to
Differential Output
Gain = 2
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
R
L
= 800 Ω
R
= 800 Ω
L
R
L
= 800 Ω
R = 1 kΩ
R = 1 kΩ
−30
−40
−50
−60
f
O
S
−30
−40
−50
−60
f
R = 1 kΩ
f
V
V
= 2 V
= 5 V
f = 8 MHz
PP
f= 8 MHz
V
= 5 V
S
V
= 5 V
S
HD3
HD3
HD3
−70
−80
−70
−80
HD2
HD2
2.5
HD2
−90
−90
−100
0
−100
0.1
1
10
100
0.5
1
1.5
2
3
0
0.5
1
1.5
2
2.5
3
f − Frequency − MHz
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
O
O
Figure 66
Figure 67
Figure 68
16
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
HARMONIC DISTORTION
HARMONIC DISTORTION
vs
HARMONIC DISTORTION
vs
vs
OUTPUT VOLTAGE SWING
OUTPUT VOLTAGE SWING
LOAD RESISTANCE
0
−10
−20
0
−10
−20
0
−10
−20
−30
−40
−50
−60
−70
−80
Single-Ended Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 2
Differentia Input to
Differential Output
Gain = 2
V
= 2 V
PP
R
L
= 800 Ω
R
L
= 800 Ω
O
R = 392 Ω
R = 1 kΩ
−30
−40
−50
−60
−30
−40
−50
−60
R = 1 kΩ
f
f
f
f= 30 MHz
f = 30 MHz
f= 30 MHz
V
= 5 V
V
= 5 V
V
= 5 V
S
S
S
HD2
HD3
HD2
HD3
HD2
HD3
−70
−80
−70
−80
−90
−90
−90
−100
−100
−100
0
400
800
1200
1600
0
0.5
1
1.5
2
2.5
3
0
0.5
1
1.5
2
2.5
3
V
− Output Voltage Swing − V
V
− Output Voltage Swing − V
R − Load Resistance − Ω
L
O
O
Figure 69
Figure 70
Figure 71
THIRD-ORDER INTERMODULATION
THIRD-ORDER OUTPUT INTERCEPT
HARMONIC DISTORTION
vs
DISTORTION
vs
POINT
vs
LOAD RESISTANCE
FREQUENCY
FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
55
−50
Differentia Input to
Differential Output
Gain = 1
Single-Ended Input to
Differential Output
Gain = 1
Gain = 1
V
R = 392 Ω
R
= 2 V
O
f
L
S
PP
50
45
40
−60
−70
−80
V
= 2 V
PP
V
= 2 V
O
O
f
L
S
PP
R = 392 Ω
= 800 Ω
= 800 Ω
= 5 V
R = 392 Ω
f
V
f= 30 MHz
R
V
V
= 5 V
= 5 V
S
HD2
HD3
35
30
−90
−90
−100
−100
0
400
800
1200
1600
0
20
40
60
80
100
120
10
100
R
L
− Load Resistance − Ω
f − Frequency − MHz
f − Frequency − MHz
Figure 72
Figure 73
Figure 74
SLEW RATE
vs
DIFFERENTIAL OUTPUT VOLTAGE STEP
LARGE-SIGNAL TRANSIENT RESPONSE
SMALL-SIGNAL TRANSIENT RESPONSE
0.4
1400
2
Gain = 1
1.5
R
= 800 Ω
0.3
0.2
L
1200
1000
800
600
400
200
0
R = 392 Ω
f
1
V
= 5 V
S
Gain = 1
Gain = 1
= 800 Ω
0.5
R
L
= 800 Ω
0.1
R
L
R = 392 Ω
f
R = 392 Ω
f
0
−0.1
−0.2
0
−0.5
−1
t /t = 300 ps
r f
t /t = 300 ps
r f
V
= 5 V
S
V
= 5 V
S
−0.3
−0.4
−1.5
−2
−100
0
100
200
300
400
500
0
0.5
1
1.5
2
2.5
3
−100
0
100
200
300
400
500
t − Time − ns
V
− Differential Output Voltage Step − V
t − Time − ns
O
Figure 75
Figure 76
Figure 77
17
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
REJECTION RATIOS
VOLTAGE AND CURRENT NOISE
REJECTION RATIOS
vs
vs
vs
CASE TEMPERATURE
FREQUENCY
FREQUENCY
120
100
90
80
70
60
50
40
30
20
10
0
100
PSRR+
CMMR
PSRR−
80
60
40
PSRR+
CMMR
V
n
PSRR−
10
I
n
20
0
R = 800 Ω
L
R
= 800 Ω
= 5 V
L
V
= 5 V
V
S
S
1
0.01 0.1
−10
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
1
10
100 1000 10 k
0.1
1
10
100
Case Temperature − °C
f − Frequency − MHz
f − Frequency − kHz
Figure 78
Figure 79
Figure 80
OUTPUT BALANCE ERROR
OPEN-LOOP GAIN
vs
CASE TEMPERATURE
OPEN-LOOP GAIN AND PHASE
vs
vs
FREQUENCY
FREQUENCY
60
50
40
30
20
0
30
0
57
56
55
54
53
52
51
50
49
48
47
46
Gain
P
R
V
= −30 dBm
= 800 Ω
= 5 V
R
V
= 800 Ω
= 5 V
P
R
= −20 dBm
= 800 Ω
IN
L
S
L
S
IN
L
f
S
−10
−20
−30
−40
−50
R = 499 Ω
V
= 5 V
−30
−60
Phase
−90
−120
−150
10
0
−60
−70
0.1
1
10
100
−40−30−20−100 10 20 30 40 50 60 70 80 90
0.01
0.1
1
10
100
1000
f − Frequency − MHz
Case Temperature − °C
f − Frequency − MHz
Figure 81
Figure 82
Figure 83
INPUT BIAS AND OFFSET CURRENT
INPUT OFFSET VOLTAGE
vs
QUIESCENT CURRENT
vs
vs
CASE TEMPERATURE
CASE TEMPERATURE
SUPPLY VOLTAGE
35
30
25
20
15
10
3.75
0
4
T
A
= 85°C
V
= 5 V
S
V
= 5 V
S
−0.01
3.5
3.5
I
IB+
I
T
A
= 25°C
−0.02
−0.03
−0.04
−0.05
−0.06
−0.07
−0.08
3.25
3
3
IB−
T
A
= −40°C
2.5
2.75
2.5
2
I
OS
2.25
1.5
2
1
0.5
0
1.75
5
0
−0.09
−0.1
1.5
1.25
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
Case Temperature − °C
Case Temperature − °C
V
− Supply Voltage −
V
S
Figure 84
Figure 85
Figure 86
18
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
COMMON-MODE REJECTION RATIO
vs
OUTPUT DRIVE
vs
HARMONIC DISTORTION
vs
INPUT COMMON-MODE RANGE
CASE TEMPERATURE
OUTPUT COMMON-MODE VOLTAGE
110
100
90
0
150
100
50
Single-Ended and
Differential Input
V
= 5 V
S
V
= 5 V
Source
S
−10
Gain = 1
−20
V
= 2 V
80
O
f
PP
−30
−40
−50
−60
−70
−80
−90
−100
R = 392 Ω
f= 8 MHz, V = 5 V
70
S
60
50
0
HD3-SE
and Diff
40
30
−50
20
10
−100
−150
Sink
HD2-SE
0
HD2-Diff
−10
−40−30−20−10
0 10 20 30 40 50 60 70 80 90
1
1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5
−1
0
1
2
3
4
5
Input Common-Mode Range − V
V
− Output Common-Mode Voltage − V
Case Temperature − °C
OCM
Figure 87
Figure 88
Figure 89
QUIESCENT CURRENT
vs
POWER-DOWN VOLTAGE
OUTPUT OFFSET VOLTAGE
vs
OUTPUT COMMON-MODE VOLTAGE
SMALL SIGNAL FREQUENCY RESPONSE
at V
OCM
800
25
4
3
Gain = 1
= 800 Ω
V
= 5 V
S
600
400
200
R
L
R = 392 Ω
20
f
P
V
= −20 dBm
= 5 V
IN
S
2
15
10
5
1
0
0
−200
−1
−400
−600
−800
−2
−3
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
0.1
1
10
100
1000
Power-down Voltage − V
V
− Output Common-Mode Voltage − V
f − Frequency − MHz
OC
Figure 90
Figure 91
Figure 92
TURNON AND TURNOFF DELAY TIME
0.03
0.02
0.01
0
Current
0
−1
−2
−3
−4
−5
−6
0 0.5 1 1.5 2 2.5
3
100.5101 102
103
t − Time − ms
Figure 93
19
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
TYPICAL CHARACTERISTICS (5 V Graphs)
SINGLE-ENDED OUTPUT IMPEDANCE
POWER-DOWN QUIESCENT CURRENT POWER-DOWN QUIESCENT CURRENT
IN POWER DOWN
vs
vs
vs
CASE TEMPERATURE
SUPPLY VOLTAGE
FREQUENCY
800
700
600
500
1000
900
800
700
600
500
400
300
200
1100
R
V
= 800 Ω
L
1000
900
800
700
= 5 V
S
600
500
400
300
400
Gain = 1
R
= 400 Ω
200
L
300
200
R = 499 Ω
f
100
0
P
V
= −1 dBm
= 5 V
IN
S
100
0
100
0
−40−30−20−10 0 10 20 30 40 50 60 70 80 90
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5 5
0.1
1
10
100
1000
Case Temperature − °C
V
− Supply Voltage − V
S
f − Frequency − MHz
Figure 94
Figure 95
Figure 96
20
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
APPLICATION INFORMATION
V
), two power supplies (V , V ), an output
S+ S−
FULLY DIFFERENTIAL AMPLIFIERS
OUT+
common-mode control pin (V
power-down pin (PD).
), and an optional
OCM
Differential signaling offers a number of performance
advantages in high-speed analog signal processing
systems, including immunity to external common-mode
noise, suppression of even-order nonlinearities, and
increased dynamic range. Fully differential amplifiers not
only serve as the primary means of providing gain to a
differential signal chain, but also provide a monolithic
solution for converting single-ended signals into
differential signals for easier, higher performance
processing. The THS4500 family of amplifiers contains
products in Texas Instruments’ expanding line of
high-performance fully differential amplifiers. Information
on fully differential amplifier fundamentals, as well as
implementation specific information, is presented in the
applications section of this data sheet to provide a better
understanding of the operation of the THS4500 family of
devices, and to simplify the design process for designs
using these amplifiers.
VIN−
VOCM
VS+
VIN+
PD
1
8
2
7
3
4
6
5
VS−
VOUT+
VOUT−
Fully Differential Amplifier Pin Diagram
A standard configuration for the device is shown in the
figure. The functionality of a fully differential amplifier can
be imagined as two inverting amplifiers that share a
common noninverting terminal (though the voltage is not
necessarily fixed). For more information on the basic
theory of operation for fully differential amplifiers, refer to
the Texas Instruments application note titled Fully
Differential Amplifiers, literature number SLOA054.
Applications Section
D
D
Fully Differential Amplifier Terminal Functions
Input Common-Mode Voltage Range and the
THS4500 Family
Choosing the Proper Value for the Feedback and
Gain Resistors
Application Circuits Using Fully Differential
Amplifiers
Key Design Considerations for Interfacing to an
Analog-to-Digital Converter
INPUT COMMON-MODE VOLTAGE RANGE
AND THE THS4500 FAMILY
D
D
D
D
The key difference between the THS4500/1 and the
THS4502/3 is the input common-mode range for the two
devices. The THS4502 and THS4503 have an input
common-mode range that is centered around midrail, and
the THS4500 and THS4501 have an input common-mode
range that is shifted to include the negative power supply
rail. Selection of one or the other is determined by the
nature of the application. Specifically, the THS4500 and
THS4501 are designed for use in single-supply
applications where the input signal is ground-referenced,
as depicted in Figure 97. The THS4502 and THS4503 are
designed for use in single-supply or split-supply
applications where the input signal is centered between
the power supply voltages, as depicted in Figure 98.
Setting the Output Common-Mode Voltage With the
V
OCM Input
D
Saving Power with Power-Down Functionality
Linearity: Definitions, Terminology, Circuit
Techniques, and Design Tradeoffs
An Abbreviated Analysis of Noise in Fully
Differential Amplifiers
Printed-Circuit Board Layout Techniques for Optimal
Performance
Power Dissipation and Thermal Considerations
Power Supply Decoupling Techniques and
Recommendations
D
D
D
R
g1
R
f1
D
R
S
D
+V
S
R
T
V
S
D
D
Evaluation Fixtures, Spice Models, and Applications
Support
Additional Reference Material
+
−
−
+
V
OCM
FULLY DIFFERENTIAL AMPLIFIER
TERMINAL FUNCTIONS
R
g2
R
f2
Application Circuit for the THS4500 and THS4501,
Featuring Single-Supply Operation With a
Ground-Referenced Input Signal
Fully differential amplifiers are typically packaged in
eight-pin packages as shown in the diagram. The device
Figure 97
pins include two inputs (V , V ), two outputs (V ,
IN+
IN−
OUT−
21
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
R
R
f
R
R
f1
R
S
g
g1
V
IN+
+V
S
R
T
V
S
V
p
V
+
−
OUT−
+
−
−
+
−
+
V
V
OCM
OCM
V
OUT+
V
n
−V
S
V
IN−
R
g
R
g2
R
f
R
f2
Diagram For Input Common-Mode Range Equations
Application Circuit for the THS4500 and THS4501,
Featuring Split-Supply Operation With an Input
Signal Referenced at the Midrail
Figure 99
The two tables below depict the input common-mode
range requirements for two different input scenarios, an
input referenced around the negative rail and an input
referenced around midrail. The tables highlight the
differing requirements on input common-mode range, and
illustrate reasoning for choosing either the THS4500/1 or
the THS4502/3. For signals referenced around the
negative power supply, the THS4500/1 should be chosen
since its input common-mode range includes the negative
supply rail. For all other situations, the THS4502/3 offers
slightly improved distortion and noise performance for
applications with input signals centered between the
power supply rails.
Figure 98
Equations 1−5 allow for calculation of the required input
common-mode range for a given set of input conditions.
The equations allow calculation of the input common-
mode range requirements given information about the
input signal, the output voltage swing, the gain, and the
output common-mode voltage. Calculating the maximum
and minimum voltage required for V and V (the
N
P
amplifier’s input nodes) determines whether or not the
input common-mode range is violated or not. Four
equations are required. Two calculate the output voltages
and two calculate the node voltages at V and V (note
that only one of these needs calculation, as the amplifier
forces a virtual short between the two nodes).
N
P
Table 1. Negative-Rail Referenced
Gain
(V/V)
V
V
V
V
V
V
IN−
IN
OCM
(V)
OD
NMIN
(V)
NMAX
(V)
V
(V)
IN+
(V)
(V
)
(V
)
PP
PP
VIN)(1–β)–VIN–(1–β) ) 2VOCMβ
−2.0 to
2.0
(1)
VOUT)
+
1
2
4
8
0
4
2
1
2.5
2.5
2.5
2.5
4
0.75
0.5
1.75
2β
−1.0 to
1.0
0
0
0
4
4
4
1.167
0.7
–VIN)(1–β) ) VIN–(1–β) ) 2VOCMβ
2β
(2)
VOUT–
+
−0.5 to
0.5
0.3
VN + VIN–(1–β) ) VOUT)
β
(3)
(4)
(5)
−0.25 to
0.25
0.5
0.167
0.389
RG
RF ) RG
Where: β +
NOTE: This table assumes a negative-rail referenced, single-ended
input signal on a single 5-V supply as shown in Figure 97.
V
NMIN
= V
and V
= V .
PMIN
NMAX
PMAX
VP + VIN)(1–β) ) VOUT–β
Table 2. Midrail Referenced
NOTE:
Gain
(V/V)
V
(V)
V
V
V
(V
V
V
IN−
IN
OCM
(V)
OD
PP
NMIN
(V)
NMAX
(V)
The equations denote the device inputs as VN and
VP, and the circuit inputs as VIN+ and VIN−
V
(V)
IN+
(V
)
)
PP
.
0.5 to
4.5
1
2
4
8
2.5
4
2
1
2.5
2.5
2.5
2.5
4
2
3
1.5 to
3.5
2.5
2.5
2.5
4
4
4
2.16
2.3
2.83
2.7
2.0 to
3.0
2.25 to
2.75
0.5
2.389
2.61
NOTE: This table assumes a midrail referenced, single-ended input
signal on a single 5-V supply.
V
NMIN
= V
PMIN
and V
NMAX
= V .
PMAX
22
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
Table 3. Resistor Values for Balanced Operation
in Various Gain Configurations
CHOOSING THE PROPER VALUE FOR THE
FEEDBACK AND GAIN RESISTORS
VOD
VIN
R2 & R4 (Ω)
R1 (Ω)
R3 (Ω)
R (Ω)
T
ǒ Ǔ
Gain
The selection of feedback and gain resistors impacts
circuit performance in a number of ways. The values in this
section provide the optimum high frequency performance
(lowest distortion, flat frequency response). Since the
THS4500 family of amplifiers is developed with a voltage
feedback architecture, the choice of resistor values does
not have a dominant effect on bandwidth, unlike a current
feedback amplifier. However, resistor choices do have
second-order effects. For optimal performance, the
following feedback resistor values are recommended. In
higher gain configurations (gain greater than two), the
feedback resistor values have much less effect on the high
frequency performance. Example feedback and gain
resistor values are given in the section on basic design
considerations (Table 3).
1
1
392
499
412
523
215
665
274
681
147
698
383
487
187
634
249
649
118
681
54.9
53.6
60.4
52.3
56.2
52.3
64.9
52.3
2
392
2
1.3k
1.3k
3.32k
1.3k
6.81k
5
5
10
10
NOTE: Values in the table above assume a 50 Ω source impedance.
R1
R2
V
n
V
−
+
out+
Amplifier loading, noise, and the flatness of the frequency
response are three design parameters that should be
considered when selecting feedback resistors. Larger
resistor values contribute more noise and can induce
peaking in the ac response in low gain configurations, and
smaller resistor values can load the amplifier more heavily,
resulting in a reduction in distortion performance. In
addition, feedback resistor values, coupled with gain
requirements, determine the value of the gain resistors,
directly impacting the input impedance of the entire circuit.
While there are no strict rules about resistor selection,
these trends can provide qualitative design guidance.
+
R3
R
S
−
V
out−
V
P
V
OCM
R
V
S
T
R4
Figure 100
Equations for calculating fully differential amplifier resistor
values in order to obtain balanced operation in the
presence of a 50-Ω source impedance are given in
equations 6 through 9.
1
R2
R1
APPLICATION CIRCUITS USING FULLY
DIFFERENTIAL AMPLIFIERS
RT +
K +
R2 + R4
K
1–
(6)
2(1)K)
1
RS
–
R3
ǒ
TǓ
R3 + R1 * Rs || R
Fully differential amplifiers provide designers with a great
deal of flexibility in a wide variety of applications. This
section provides an overview of some common circuit
configurations and gives some design guidelines.
Designing the interface to an ADC, driving lines
differentially, and filtering with fully differential amplifiers
are a few of the circuits that are covered.
R3 ) RT || RS
R3 ) RT || RS ) R4
R1
R1 ) R2
β1 +
β2 +
(7)
VOD
VS
1–β2
RT
+ 2ǒ Ǔǒ Ǔ
(8)
(9)
β1 ) β2
RT ) RS
VOD
VIN
1–β2
+ 2ǒ Ǔ
β1 ) β2
BASIC DESIGN CONSIDERATIONS
The circuits in Figures 100 through 104 are used to
highlight basic design considerations for fully differential
amplifier circuit designs.
For more detailed information about balance in fully
differential amplifiers, see Fully Differential Amplifiers,
referenced at the end of this data sheet.
23
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
the required amount of current to move V
desired value. A buffer may be needed.
to the
INTERFACING TO AN ANALOG-TO-DIGITAL
CONVERTER
OCM
D
D
Decouple the V pin to eliminate the antenna
OCM
The THS4500 family of amplifiers are designed
specifically to interface to today’s highest-performance
analog-to-digital converters. This section highlights the
key concerns when interfacing to an ADC and provides
example ADC/fully differential amplifier interface circuits.
effect. V
is a high-impedance node that can act as
OCM
an antenna. A large decoupling capacitor on this node
eliminates this problem.
Be cognizant of the input common-mode range. If the
input signal is referenced around the negative power
supply rail (e.g., around ground on a single 5 V
supply), then the THS4500/1 accommodates the
input signal. If the input signal is referenced around
midrail, choose the THS4502/3 for the best operation.
Key design concerns when interfacing to an
analog-to-digital converter:
D
D
D
Terminate the input source properly. In high-frequency
receiver chains, the source feeding the fully
D
D
Packaging makes a difference at higher frequencies.
If possible, choose the smaller, thermally enhanced
MSOP package for the best performance. As a rule,
lower junction temperatures provide better
performance. If possible, use a thermally enhanced
package, even if the power dissipation is relatively
small compared to the maximum power dissipation
rating to achieve the best results.
differential amplifier requires
a
specific load
impedance (e.g., 50 Ω).
Design a symmetric printed-circuit board layout.
Even-order distortion products are heavily influenced
by layout, and careful attention to a symmetric layout
will minimize these distortion products.
Comprehend the effect of the load impedance seen by
the fully differential amplifier when performing
system-level intercept point calculations. Lighter
loads (such as those presented by an ADC) allow
smaller intercept points to support the same level of
intermodulation distortion performance.
Minimize inductance in power supply decoupling
traces and components. Poor power supply
decoupling can have a dramatic effect on circuit
performance. Since the outputs are differential,
differential currents exist in the power supply pins.
Thus, decoupling capacitors should be placed in a
manner that minimizes the impedance of the current
loop.
EXAMPLE ANALOG-TO-DIGITAL
CONVERTER DRIVER CIRCUITS
D
D
D
D
Use separate analog and digital power supplies and
grounds. Noise (bounce) in the power supplies
(created by digital switching currents) can couple
directly into the signal path, and power supply noise
can create higher distortion products as well.
The THS4500 family of devices is designed to drive
high-performance ADCs with extremely high linearity,
allowing for the maximum effective number of bits at the
output of the data converter. Two representative circuits
shown below highlight single-supply operation and split
supply operation. Specific feedback resistor, gain resistor,
and feedback capacitor values are not specified, as their
values depend on the frequency of interest. Information on
calculating these values can be found in the applications
material above.
Use care when filtering. While an RC low-pass filter
may be desirable on the output of the amplifier to filter
broadband noise, the excess loading can negatively
impact the amplifier linearity. Filtering in the feedback
path does not have this effect.
C
F
AC-coupling allows easier circuit design. If
dc-coupling is required, be aware of the excess power
dissipation that can occur due to level-shifting the
output through the output common-mode voltage
control.
R
S
R
g
R
f
5 V
V
R
T
S
5 V
10 µF 0.1 µF
R
R
iso
+
V
IN
IN
−
OCM
ADS5410
12 Bit/80 MSps
Do not terminate the output unless required. Many
open-loop, class-A amplifiers require 50-Ω
termination for proper operation, but closed-loop fully
differential amplifiers drive a specific output voltage
regardless of the load impedance present.
Terminating the output of a fully differential amplifier
with a heavy load adversely effects the amplifier’s
linearity.
+
−
CM
1 µF
THS4503
iso
10 µF 0.1 µF
−5 V
R
g
0.1 µF
R
f
C
F
Using the THS4503 With the ADS5410
D
Comprehend the V
Determine if the ADC’s voltage reference can provide
input drive requirements.
OCM
Figure 101
24
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
C
F
applicable to many different types of systems. The first
pole is set by the resistors and capacitors in the feedback
paths, and the second pole is set by the isolation resistors
and the capacitor across the outputs of the isolation
resistors.
R
S
R
g
R
f
5 V
V
R
T
S
5 V
10 µF 0.1 µF
R
iso
+
V
ADS5421
−
OCM
+
IN
C
F1
14 Bit/40 MSps
IN
−
CM
1 µF
THS4501
R
iso
R
R
R
S
g1
g2
f1
R
g
R
f
R
R
iso
R
T
V
S
+
−
C
F
−
+
V
C
O
0.1 µF
R
iso
Using the THS4501 With the ADS5421
R
f2
Figure 102
C
F2
A Two-Pole, Low-Pass Filter Design Using a Fully
Differential Amplifier With Poles Located at:
FULLY DIFFERENTIAL LINE DRIVERS
−1
−1
P1 = (2πR C ) in Hz and P2 = (4πR C) in Hz
f F iso
The THS4500 family of amplifiers can be used as
high-frequency, high-swing differential line drivers. Their
high power supply voltage rating (16.5 V absolute
maximum) allows operation on a single 12-V or a single
15-V supply. The high supply voltage, coupled with the
ability to provide differential outputs enables the ability to
Figure 104
Often times, filters like these are used to eliminate
broadband noise and out-of-band distortion products in
signal acquisition systems. It should be noted that the
increased load placed on the output of the amplifier by the
second low-pass filter has a detrimental effect on the
distortion performance. The preferred method of filtering
is using the feedback network, as the typically smaller
capacitances required at these points in the circuit do not
load the amplifier nearly as heavily in the pass-band.
drive 26 V
into reasonably heavy loads (250 Ω or
PP
greater). The circuit in Figure 103 illustrates the THS4500
family of devices used as high speed line drivers. For line
driver applications, close attention must be paid to thermal
design constraints due to the typically high level of power
dissipation.
C
G
R
R
f
R
g
S
SETTING THE OUTPUT COMMON-MODE
15 V
C
R
S
T
R
R
iso
V
S
VOLTAGE WITH THE V
INPUT
OCM
+
V
−
OCM
R
L
THS4500/2
V
DD
+
−
The output common-mode voltage pin provides a critical
function to the fully differential amplifier; it accepts an input
voltage and reproduces that input voltage as the output
0.1 µF
iso
C
S
R
f
V
= 26 V
PP
OD
R
g
common-mode voltage. In other words, the V
input
OCM
C
G
provides the ability to level-shift the outputs to any voltage
inside the output voltage swing of the amplifier.
Fully Differential Line Driver With High Output Swing
Figure 103
A description of the input circuitry of the V
pin is shown
OCM
below to facilitate an easier understanding of the V
OCM
interface requirements. The V
pin has two 50-kΩ
OCM
resistors between the power supply rails to set the default
output common-mode voltage to midrail. A voltage
FILTERING WITH FULLY DIFFERENTIAL
AMPLIFIERS
applied to the V
pin alters the output common-mode
OCM
Similar to their single-ended counterparts, fully differential
amplifiers have the ability to couple filtering functionality
with voltage gain. Numerous filter topologies can be based
on fully differential amplifiers. Several of these are outlined
in A Differential Circuit Collection, (literature number
SLOA064) referenced at the end of this data sheet. The
circuit below depicts a simple two-pole low-pass filter
voltage as long as the source has the ability to provide
enough current to overdrive the two 50-kΩ resistors. This
phenomenon is depicted in the V
equivalent circuit
OCM
diagram. The table contains some representative
examples to aid in determining the current drive
requirement for the V
voltage source. This parameter
OCM
is especially important when using the reference voltage
25
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
V
OCM
of an analog-to-digital converter to drive V
current drive capabilities differ from part to part, so a
voltage buffer may be necessary in some applications.
. Output
OCM
I
=
1
R
+ R + R || R
S T
f1 g1
DC Current Path to Ground
R
R
R
g1
f1
S
2.5-V DC
5 V
R
V
S+
T
V
S
+
−
+
R = 50 kΩ
R
V
= 2.5 V
L
OCM
−
2 V
OCM
− V − V
S+
S−
I
IN
=
V
OCM
R
I
IN
2.5-V DC
R = 50 kΩ
R
R
g2
f2
DC Current Path to Ground
V
S−
V
OCM
+ R
I
=
2
Equivalent Input Circuit for V
R
OCM
f2
g2
Figure 105
Depiction of DC Power Dissipation Caused By
Output Level-Shifting in a DC-Coupled Circuit
Figure 106
By design, the input signal applied to the V
pin
OCM
propagates to the outputs as a common-mode signal. As
shown in the equivalent circuit diagram, the V input
SAVING POWER WITH POWER-DOWN
FUNCTIONALITY
OCM
has a high impedance associated with it, dictated by the
two 50-kΩ resistors. While the high impedance allows for
relaxed drive requirements, it also allows the pin and any
associated printed-circuit board traces to act as an
antenna. For this reason, a decoupling capacitor is
recommended on this node for the sole purpose of filtering
any high frequency noise that could couple into the signal
The THS4500 family of fully differential amplifiers contains
devices that come with and without the power-down
option. Even-numbered devices have power-down
capability, which is described in detail here.
The power-down pin of the amplifiers defaults to the
positive supply voltage in the absence of an applied
voltage (i.e. an internal pullup resistor is present), putting
the amplifier in the power-on mode of operation. To turn off
the amplifier in an effort to conserve power, the
power-down pin can be driven towards the negative rail.
The threshold voltages for power-on and power-down are
relative to the supply rails and given in the specification
tables. Above the enable threshold voltage, the device is
on. Below the disable threshold voltage, the device is off.
Behavior in between these threshold voltages is not
specified.
path through the V
circuitry. A 0.1-µF or 1-µF
OCM
capacitance is a reasonable value for eliminating a great
deal of broadband interference, but additional, tuned
decoupling capacitors should be considered if a specific
source of electromagnetic or radio frequency interference
is present elsewhere in the system. Information on the ac
performance (bandwidth, slew rate) of the V
circuitry
OCM
is included in the specification table and graph section.
Since the V pin provides the ability to set an output
OCM
Note that this power-down functionality is just that; the
amplifier consumes less power in power-down mode. The
common-mode voltage, the ability for increased power
dissipation exists. While this does not pose a performance
problem for the amplifier, it can cause additional power
dissipation of which the system designer should be aware.
The circuit shown in Figure 106 demonstrates an
example of this phenomenon. For a device operating on
a single 5-V supply with an input signal referenced around
ground and an output common-mode voltage of 2.5 V, a
dc potential exists between the outputs and the inputs of
the device. The amplifier sources current into the
feedback network in order to provide the circuit with the
proper operating point. While there are no serious effects
on the circuit performance, the extra power dissipation
may need to be included in the system’s power budget.
power-down mode is not intended to provide
a
high-impedance output. In other words, the power-down
functionality is not intended to allow use as a 3-state bus
driver. When in power-down mode, the impedance looking
back into the output of the amplifier is dominated by the
feedback and gain setting resistors.
The time delays associated with turning the device on and
off are specified as the time it takes for the amplifier to
reach 50% of the nominal quiescent current. The time
delays are on the order of microseconds because the
amplifier moves in and out of the linear mode of operation
in these transitions.
26
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
LINEARITY: DEFINITIONS, TERMINOLOGY,
CIRCUIT TECHNIQUES, AND DESIGN
TRADEOFFS
P
OUT
(dBm)
1X
OIP
3
The THS4500 family of devices features unprecedented
distortion performance for monolithic fully differential
amplifiers. This section focuses on the fundamentals of
distortion, circuit techniques for reducing nonlinearity,
and methods for equating distortion of fully differential
amplifiers to desired linearity specifications in RF receiver
chains.
P
O
IMD
IIP
3
P
3
IN
(dBm)
Amplifiers are generally thought of as linear devices. In
other words, the output of an amplifier is a linearly scaled
version of the input signal applied to it. In reality, however,
amplifier transfer functions are nonlinear. Minimizing
amplifier nonlinearity is a primary design goal in many
applications.
3X
P
S
Figure 108
Due to the intercept point’s ease of use in system level
calculations for receiver chains, it has become the
specification of choice for guiding distortion-related design
decisions. Traditionally, these systems use primarily
class-A, single-ended RF amplifiers as gain blocks. These
RF amplifiers are typically designed to operate in a 50-Ω
environment, just like the rest of the receiver chain. Since
intercept points are given in dBm, this implies an
associated impedance (50 Ω).
Intercept points are specifications that have long been
used as key design criteria in the RF communications
world as a metric for the intermodulation distortion
performance of a device in the signal chain (e.g.,
amplifiers, mixers, etc.). Use of the intercept point, rather
than strictly the intermodulation distortion, allows for
simpler system-level calculations. Intercept points, like
noise figures, can be easily cascaded back and forth
through a signal chain to determine the overall receiver
chain’s intermodulation distortion performance. The
relationship between intermodulation distortion and
intercept point is depicted in Figure 107 and Figure 108.
However, with a fully differential amplifier, the output does
not require termination as an RF amplifier would. Because
closed-loop amplifiers deliver signals to their outputs
regardless of the impedance present, it is important to
comprehend this when evaluating the intercept point of a
fully differential amplifier. The THS4500 series of devices
yields optimum distortion performance when loaded with
200 Ω to 1 kΩ, very similar to the input impedance of an
analog-to-digital converter over its input frequency band.
As a result, terminating the input of the ADC to 50 Ω can
actually be detrimental to system performance.
P
O
P
O
∆f = f − f1
c
c
∆f = f2 − f
c
c
This discontinuity between open-loop, class-A amplifiers
and closed-loop, class-AB amplifiers becomes apparent
when comparing the intercept points of the two types of
devices. Equation 10 gives the definition of an intercept
point, relative to the intermodulation distortion.
IMD = P − P
O
3
S
P
S
P
S
Ť
Ť
ǒ Ǔwhere
IMD3
2
(10)
(11)
OIP3 + PO )
f
c
− 3∆f f1
f
f2
f + 3∆f
c
c
V2Pdiff
P + 10 logǒ Ǔ
f − Frequency − MHz
O
2RL 0.001
Figure 107
NOTE: P is the output power of a single tone, R is the differential load
o
L
resistance, and V
is the differential peak voltage for a
P(diff)
single tone.
27
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
As can be seen in the equation, when a higher impedance
is used, the same level of intermodulation distortion
performance results in a lower intercept point. Therefore,
it is important to comprehend the impedance seen by the
output of the fully differential amplifier when selecting a
minimum intercept point. The graphic below shows the
relationship between the strict definition of an intercept
point with a normalized, or equivalent, intercept point for
the THS4502.
delivered to the amplifier by the source (N ) and input noise
power are used to calculate the noise factor and noise
figure as shown in equations 23 through 27.
I
e
g
e
f
R
g
R
f
N
i
N
A
S
i
e
n
N
i
N
o
R
+
s
THIRD-ORDER OUTPUT INTERCEPT POINT
S
o
vs
R
t
fully-diff
amp
−
i
ni
N
FREQUENCY
o
e
s
60
Normalized to 200 Ω
e
t
55
Normalized to 50 Ω
50
i
ii
45
40
35
e
g
e
f
R
g
R
f
OIP R = 800 Ω
3
L
30
25
Gain = 1
R = 392 Ω
Figure 110. Noise Sources in a Fully
Differential Amplifier Circuit
f
S
V
=
5 V
20
15
Tone Spacing = 200 kHz
N : Fully Differential Amplifier
A
Noise
Source
0
10 20 30 40 50 60 70 80 90 100
Scale Factor
f − Frequency − MHz
2
Figure 109
ȡR
ȧR
Ȣ
ȣ
ȧ
Ȥ
Rg
RsRt
g
)
2
(12)
(e )
ni
f
Rg )
Comparing specifications between different device types
becomes easier when a common impedance level is
assumed. For this reason, the intercept points on the
THS4500 family of devices are reported normalized to a
50-Ω load impedance.
ǒ
Ǔ
2 Rs)Rt
2
2
2
R
g
(i )
ni
(13)
(14)
2
R
g
(i )
ii
AN ANALYSIS OF NOISE IN FULLY
DIFFERENTIAL AMPLIFIERS
2
2RsRG
Rs)2Rg
2RsRg
ȡ
ȧ
ȢRt )
ȣ
ȧ
Ȥ
4kTR
t
(15)
Noise analysis in fully differential amplifiers is analogous
to noise analysis in single-ended amplifiers. The same
concepts apply. Below, a generic circuit diagram
consisting of a voltage source, a termination resistor, two
gain setting resistors, two feedback resistors, and a fully
differential amplifier is shown, including all the relevant
noise sources. From this circuit, the noise factor (F) and
noise figure (NF) are calculated. The figures indicate the
appropriate scaling factor for each of the noise sources in
two different cases. The first case includes the termination
resistor, and the second, simplified case assumes that the
voltage source is properly terminated by the gain-setting
resistors. With these scaling factors, the amplifier’s input
Rs)2Rg
2
ǒRgǓ
2
4kTR
(16)
(17)
f
Rf
2
ȡ
Rg
RsRt
2 Rs)R
ȣ
4kTR
2
g
ȧ
Rg )
ȧ
Ǔ
t Ȥ
ǒ
Ȣ
Figure 111. Scaling Factors for Individual Noise
Sources Assuming a Finite Value Termination
Resistor
noise power (N ) can be calculated by summing each
A
individual noise source with its scaling factor. The noise
28
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
N : Fully Differential Amplifier; termination = 2R
A
D
D
Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the
output and input pins can cause instability. To reduce
unwanted capacitance, a window around the signal
I/O pins should be opened in all of the ground and
power planes around those pins. Otherwise, ground
and power planes should be unbroken elsewhere on
the board.
g
Noise
Source
Scale Factor
2
ȡRg
ȣ
Rs
Ȥ
Rg
(18)
)
2
(e )
ni
R
ȧ
f
ȧ
Rg )
Ȣ
2
2
(i )
ni
2
R
R
(19)
(20)
g
Minimize the distance (< 0.25”) from the power supply
pins to high frequency 0.1-µF decoupling capacitors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize
inductance between the pins and the decoupling
capacitors. The power supply connections should
always be decoupled with these capacitors. Larger
(6.8 µF or more) tantalum decoupling capacitors,
effective at lower frequency, should also be used on
the main supply pins. These may be placed somewhat
farther from the device and may be shared among
several devices in the same area of the PC board. The
primary goal is to minimize the impedance seen in the
differential-current return paths.
2
2
(i )
ii
g
2
ǒRgǓ
2
(21)
4kTR
f
Rf
2
Rg
ȧR )
ȡ
ȣ
(22)
2
4kTR
R
2
ȧ
g
s
g
Ȣ
Ȥ
Figure 112. Scaling Factors for Individual Noise
Sources Asseming No Termination Resistance is
Used (e.g., R is open)
T
2
ȡ
ȣ
2RtRg
D
Careful selection and placement of external
N + 4kTR ȧ
ȧ
ȧ
Rt)2Rg
(23)
components preserve
the
high
frequency
s
ȧ
i
2RtRg
performance of the THS4500 family. Resistors should
be a very low reactance type. Surface-mount resistors
work best and allow a tighter overall layout. Metal-film
and carbon composition, axially-leaded resistors can
also provide good high frequency performance.
Again, keep their leads and PC board trace length as
short as possible. Never use wirewound type resistors
in a high frequency application. Since the output pin
and inverting input pins are the most sensitive to
parasitic capacitance, always position the feedback
and series output resistors, if any, as close as possible
to the inverting input pins and output pins. Other
network components, such as input termination
resistors, should be placed close to the gain-setting
resistors. Even with a low parasitic capacitance
shunting the external resistors, excessively high
resistor values can create significant time constants
that can degrade performance. Good axial metal-film
or surface-mount resistors have approximately 0.2 pF
in shunt with the resistor. For resistor values > 2.0 kΩ,
this parasitic capacitance can add a pole and/or a zero
below 400 MHz that can effect circuit operation. Keep
resistor values as low as possible, consistent with
load driving considerations.
R )
ȧ s R )2R ȧ
g
t
Ȣ
Ȥ
Figure 113. Input Noise With a Termination
Resistor
2
2Rg
ǒ Ǔ
(24)
Ni + 4kTRs
Rs ) 2Rg
Figure 114. Input Noise Assuming No
Termination Resistor
Noise Factor and Noise Figure Calculations
ǒ
Ǔ
NA + S Noise Source Scale Factor
(25)
(26)
(27)
NA
F + 1 )
NI
NF + 10 log (F)
PRINTED-CIRCUIT BOARD LAYOUT
TECHNIQUES FOR OPTIMAL
PERFORMANCE
D
Connections to other wideband devices on the board
may be made with short direct traces or through
onboard transmission lines. For short connections,
consider the trace and the input to the next device as
a lumped capacitive load. Relatively wide traces
(50 mils to 100 mils) should be used, preferably with
Achieving optimum performance with high frequency
amplifier-like devices in the THS4500 family requires
careful attention to board layout parasitic and external
component types.
Recommendations that optimize performance include:
29
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ground and power planes opened up around them.
Estimate the total capacitive load and determine if
isolation resistors on the outputs are necessary. Low
Figure 115(c)]. Because this thermal pad has direct
thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal
path away from the thermal pad.
parasitic capacitive loads (< 4 pF) may not need an R
S
since the THS4500 family is nominally compensated
to operate with a 2-pF parasitic load. Higher parasitic
The PowerPAD package allows for both assembly and
thermal management in one manufacturing operation.
During the surface-mount solder operation (when the
leads are being soldered), the thermal pad can also be
soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either
a ground plane or other heat dissipating device.
capacitive loads without an R are allowed as the
S
signal gain increases (increasing the unloaded phase
margin). If a long trace is required, and the 6-dB signal
loss intrinsic to a doubly-terminated transmission line
is acceptable, implement a matched impedance
transmission line using microstrip or stripline
techniques (consult an ECL design handbook for
microstrip and stripline layout techniques).
The PowerPAD package represents a breakthrough in
combining the small area and ease of assembly of surface
mount with the, heretofore, awkward mechanical methods
of heatsinking.
A 50-Ω environment is normally not necessary
onboard, and in fact, a higher impedance environment
improves distortion as shown in the distortion versus
load plots. With
a characteristic board trace
DIE
impedance defined based on board material and trace
dimensions, a matching series resistor into the trace
from the output of the THS4500 family is used as well
as a terminating shunt resistor at the input of the
destination device.
Thermal
Pad
Side View (a)
DIE
End View (b)
Bottom View (c)
Remember also that the terminating impedance is the
parallel combination of the shunt resistor and the input
impedance of the destination device: this total
effective impedance should be set to match the trace
impedance. If the 6-dB attenuation of a doubly
terminated transmission line is unacceptable, a long
trace can be series-terminated at the source end only.
Treat the trace as a capacitive load in this case. This
does not preserve signal integrity as well as a
doubly-terminated line. If the input impedance of the
destination device is low, there is some signal
attenuation due to the voltage divider formed by the
series output into the terminating impedance.
Figure 115. Views of Thermally Enhanced
Package
Although there are many ways to properly heatsink the
PowerPAD package, the following steps illustrate the
recommended approach.
0.205
0.060
0.017
Pin 1
0.013
0.030
D
Socketing a high speed part like the THS4500 family
is not recommended. The additional lead length and
pin-to-pin capacitance introduced by the socket can
create an extremely troublesome parasitic network
which can make it almost impossible to achieve a
smooth, stable frequency response. Best results are
obtained by soldering the THS4500 family parts
directly onto the board.
0.075
0.025 0.094
0.035
0.040
0.010
vias
Top View
Figure 116. PowerPAD PCB Etch and Via Pattern
PowerPAD DESIGN CONSIDERATIONS
The THS4500 family is available in a thermally-enhanced
PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die
is mounted [see Figure 115(a) and Figure 115(b)]. This
arrangement results in the lead frame being exposed as a
thermal pad on the underside of the package [see
PowerPAD PCB LAYOUT CONSIDERATIONS
1. Prepare the PCB with a top side etch pattern as shown
in Figure 116. There should be etch for the leads as
well as etch for the thermal pad.
30
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
2. Place five holes in the area of the thermal pad. These
holes should be 13 mils in diameter. Keep them small
so that solder wicking through the holes is not a
problem during reflow.
The thermal characteristics of the device are dictated by
the package and the PC board. Maximum power
dissipation for a given package can be calculated using the
following formula.
3. Additional vias may be placed anywhere along the
thermal plane outside of the thermal pad area. This
helps dissipate the heat generated by the THS4500
family IC. These additional vias may be larger than the
13-mil diameter vias directly under the thermal pad.
They can be larger because they are not in the thermal
pad area to be soldered so that wicking is not a
problem.
Tmax–TA
+
qJA
(28)
PDmax
Where:
P
T
is the maximum power dissipation in the amplifier (W).
Dmax
is the absolute maximum junction temperature (°C).
max
T is the ambient temperature (°C).
A
θ
θ
= θ + θ
JC CA
JA
is the thermal coefficient from the silicon junctions to the
JC
case (°C/W).
4. Connect all holes to the internal ground plane.
θ
is the thermal coefficient from the case to ambient air
CA
(°C/W).
5. When connecting these holes to the ground plane, do
not use the typical web or spoke via connection
methodology. Web connections have a high thermal
resistance connection that is useful for slowing the
heat transfer during soldering operations. This makes
the soldering of vias that have plane connections
easier. In this application, however, low thermal
resistance is desired for the most efficient heat
transfer. Therefore, the holes under the THS4500
family PowerPAD package should make their
connection to the internal ground plane with a
complete connection around the entire circumference
of the plated-through hole.
For systems where heat dissipation is more critical, the
THS4500 family of devices is offered in an 8-pin MSOP
with PowerPAD. The thermal coefficient for the MSOP
PowerPAD package is substantially improved over the
traditional SOIC. Maximum power dissipation levels are
depicted in the graph for the two packages. The data for
the DGN package assumes a board layout that follows the
PowerPAD layout guidelines referenced above and
detailed in the PowerPAD application notes in the
Additional Reference Material section at the end of the
data sheet.
6. The top-side solder mask should leave the terminals
of the package and the thermal pad area with its five
holes exposed. The bottom-side solder mask should
cover the five holes of the thermal pad area. This
prevents solder from being pulled away from the
thermal pad area during the reflow process.
3.5
8-Pin DGN Package
3
2.5
2
7. Apply solder paste to the exposed thermal pad area
and all of the IC terminals.
8-Pin D Package
1.5
1
8. With these preparatory steps in place, the IC is simply
placed in position and run through the solder reflow
operation as any standard surface-mount
component. This results in a part that is properly
installed.
0.5
0
−40
−20
0
20
40
60
80
T
− Ambient Temperature − °C
A
θ
θ
Τ
= 170°C/W for 8-Pin SOIC (D)
= 58.4°C/W for 8-Pin MSOP (DGN)
= 150°C, No Airflow
JA
JA
J
POWER DISSIPATION AND THERMAL
CONSIDERATIONS
Figure 117. Maximum Power Dissipation vs
Ambient Temperature
The THS4500 family of devices does not incorporate
automatic thermal shutoff protection, so the designer must
take care to ensure that the design does not violate the
absolute maximum junction temperature of the device.
Failure may result if the absolute maximum junction
temperature of 150°C is exceeded. For best performance,
design for a maximum junction temperature of 125°C.
Between 125°C and 150°C, damage does not occur, but
the performance of the amplifier begins to degrade.
When determining whether or not the device satisfies the
maximum power dissipation requirement, it is important to
not only consider quiescent power dissipation, but also
dynamic power dissipation. Often times, this is difficult to
quantify because the signal pattern is inconsistent, but an
estimate of the RMS power dissipation can provide
visibility into a possible problem.
31
ꢀ ꢁꢂꢃ ꢄ ꢅ ꢅ
ꢅ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
DRIVING CAPACITIVE LOADS
EVALUATION FIXTURES, SPICE MODELS,
AND APPLICATIONS SUPPORT
High-speed amplifiers are typically not well-suited for
driving large capacitive loads. If necessary, however, the
load capacitance should be isolated by two isolation
resistors in series with the output. The requisite isolation
resistor size depends on the value of the capacitance, but
10 to 25 Ω is a good place to begin the optimization
process. Larger isolation resistors decrease the amount of
peaking in the frequency response induced by the
capacitive load, but this comes at the expense of larger
voltage drop across the resistors, increasing the output
swing requirements of the system.
Texas Instruments is committed to providing its customers
with the highest quality of applications support. To support
this goal, an evaluation board has been developed for the
THS4500 family of fully differential amplifiers. The
evaluation board can be obtained by ordering through the
Texas Instruments web site, www.ti.com, or through your
local Texas Instruments sales representative. Schematic
for the evaluation board is shown below with the default
component values. Unpopulated footprints are shown to
provide insight into design flexibility.
R
f
C4
C0805
R4
V
S
R
R
R
R0805
PD
g
S
iso
V
S
+
U1
THS450X
4
−
J2
J3
J1
C5
V
J2
J3
S
3
_
C
R
C1
C0805
L
R6
C0805
T
R2
7
1
8
+
−
R0805
R0805
R0805
C7
C0805
R0805
R1
R
C2
iso
R1206
C0805
−V
+
5
S
R3
6
Riso = 10 − 25 Ω
R7
2
PwrPad
C6
C0805
−V
S
R
f
V
OCM
R5 R0805
C3
R
g
C0805
Use of Isolation Resistors With a Capacitive Load.
J2
J4
R8
4
5
3
1
R0805
Figure 118
R9
R11
R1206
J3
R0805
R0805
6
R9
T1
Simplified Schematic of the Evaluation Board. Power
POWER SUPPLY DECOUPLING
TECHNIQUES AND RECOMMENDATIONS
Supply Decoupling, V
Not Shown
and Power Down Circuitry
OCM,
Power supply decoupling is a critical aspect of any
high-performance amplifier design process. Careful
decoupling provides higher quality ac performance (most
notably improved distortion performance). The following
guidelines ensure the highest level of performance.
Figure 119
Computer simulation of circuit performance using SPICE
is often useful when analyzing the performance of analog
circuits and systems. This is particularly true for video and
RF amplifier circuits where parasitic capacitance and
inductance can have a major effect on circuit performance.
A SPICE model for the THS4500 family of devices is
available through either the Texas Instruments web site
(www.ti.com) or as one model on a disk from the Texas
1. Place decoupling capacitors as close to the power
supply inputs as possible, with the goal of minimizing
the inductance of the path from ground to the power
supply.
2. Placement priority should be as follows: smaller
capacitors should be closer to the device.
Instruments
Product
Information
Center
(1−800−548−6132).The PIC is also available for design
assistance and detailed product information at this
number. These models do a good job of predicting
small-signal ac and transient performance under a wide
variety of operating conditions. They are not intended to
model the distortion characteristics of the amplifier, nor do
they attempt to distinguish between the package types in
their small-signal ac performance. Detailed information
about what is and is not modeled is contained in the model
file itself.
3. Use of solid power and ground planes is
recommended to reduce the inductance along power
supply return current paths.
4. Recommended values for power supply decoupling
include 10-µF and 0.1-µF capacitors for each supply.
A 1000-pF capacitor can be used across the supplies
as well for extremely high frequency return currents,
but often is not required.
32
ꢀꢁ ꢂ ꢃꢄ ꢅꢅ
ꢀꢁ ꢂ ꢃꢄ ꢅꢆ
www.ti.com
SLOS350D − APRIL 2002 − REVISED JANUARY 2004
ADDITIONAL REFERENCE MATERIAL
D
D
D
D
PowerPAD Made Easy, application brief, Texas Instruments Literature Number SLMA004.
PowerPAD Thermally Enhanced Package, technical brief, Texas Instruments Literature Number SLMA002.
Karki, James. Fully Differential Amplifiers. application report, Texas Instruments Literature Number SLOA054D.
Karki, James. Fully Differential Amplifiers Applications: Line Termination, Driving High−Speed ADCs, and Differential
Transmission Lines. Texas Instruments Analog Applications Journal, February 2001.
D
D
D
Carter, Bruce. A Differential Op-Amp Circuit Collection. application report, Texas Instruments Literature Number
SLOA064.
Carter, Bruce. Differential Op-Amp Single-Supply Design Technique, application report, Texas Instruments Literature
Number SLOA072.
Karki, James. Designing for Low Distortion with High-Speed Op Amps. Texas Instruments Analog Applications
Journal, July 2001.
33
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
相关型号：
THS4501CDGKRG4
IC OP-AMP, 0 uV OFFSET-MAX, 300 MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MSOP-8, Operational Amplifier
TI
©2020 ICPDF网 联系我们和版权申明