THS4541IRUNT [TI]
高速差动 I/O 放大器 | RUN | 10 | -40 to 125;
| 型号： | THS4541IRUNT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 高速差动 I/O 放大器 | RUN | 10 | -40 to 125 放大器 |
| 文件： | 总64页 (文件大小：2299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
THS4541 负轨输入、轨到轨输出、高精度、850MHz
完全差分放大器
1 特性
3 说明
1
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完全差分放大器 (FDA) 架构
THS4541 是一款低功耗、电压反馈、完全差分放大器
(FDA)，输入共模范围低于负轨和轨到轨输出。 其设计
用于低功耗数据采集系统，其中高密度对于高性能
ADC 或 DAC 接口设计至关重要。
带宽：500MHz (G = 2V/V)
增益带宽产品：850MHz
转换率：1500V/μs
HD2：10MHz 时为 –95dBc（2 VPP，RL = 500Ω）
HD3：10MHz 时为 –90dBc（2 VPP，RL = 500Ω）
输入电压噪声：2.2nV/Hz(f > 100kHz)
低偏移漂移：±0.5µV/°C（典型值）
负轨输入 (NRI)
THS4541 提供了连接直流耦合地居中源信号所需的负
轨输入。 此负轨输入搭配轨到轨输出，只需使用一个
+2.7V 到 +5.4V 的电源即可轻松将单端接地基准双极
信号源与各种逐次逼近寄存器 (SAR)、Δ-Σ 或流水线
ADC 相连接。
轨到轨输出 (RRO)
THS4541 的额定运行温度介于 –40°C 与 125°C 之
间，并且采用 16 引脚超薄四方扁平无引线 (VQFN) 封
装和 10 引脚超薄四方扁平无引线 (WQFN) 封装。
Rload ≥ 50Ω 时仍可稳定运行
输出共模控制
电源：
器件信息(1)
–
–
–
单电源电压范围：2.7V 到 5.4V
分离电源电压范围：±1.35V 到 ±2.7V
静态电流：10.1mA（5V 电源）
部件号
THS4541
封装
VQFN (16)
WQFN (10)
封装尺寸（标称值）
3.00mm x 3.00mm
2.00mm x 2.00mm
•
断电能力：2µA（典型值）
(1) 要了解所有可用封装，请参见数据表末尾的封装选项附录。
2 应用
•
低功耗高性能模数转换器 (ADC) 驱动器
SAR、ΔΣ 和流水线
–
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低功耗、高性能
（直流耦合或交流耦合）
–
–
单端到差分放大器
差分到差分放大器
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•
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差分有源滤波器
数模转换器 (DAC) 输出的差分互阻抗
ADC3xxx 系列低功耗、高性能 ADC 的直流耦合或
交流耦合接口
•
与 ADA4932-1 (VQFN-16) 引脚兼容
简化电路原理图
单端到差分增益为 2，2 VPP 输出
-50
THS4541 Wideband,
HD2
HD3
Fully-Differential Amplifier
50-ꢀꢀInput Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
-60
-70
Rf1
402 ꢀ
-80
C1
100 nF
Vcc
Rg1
191 ꢀ
-90
50-ꢀꢀ
Source
±
-100
-110
-120
-130
-140
Output
Measurement
Point
+
Rload
500 ꢀ
Rt
60.2 ꢀ
Vocm
FDA
±
+
PD
Rg2
221 ꢀ
Vcc
C2
Rf2
402 ꢀ
0.1
1
10
50
100 nF
Frequency (MHz)
D013
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SLOS375
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
目录
8.5 Noise Analysis......................................................... 30
8.6 Factors Influencing Harmonic Distortion................. 31
8.7 Driving Capacitive Loads ........................................ 32
8.8 Thermal Analysis..................................................... 32
Detailed Description ............................................ 33
9.1 Overview ................................................................. 33
9.2 Functional Block Diagram ....................................... 34
9.3 Feature Description................................................. 35
9.4 Device Functional Modes........................................ 36
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Family Comparison................................... 3
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4
7.2 Handling Ratings....................................................... 4
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information.................................................. 4
7.5 Electrical Characteristics: Vs+ – Vs– = 5 V ............. 5
7.6 Electrical Characteristics: Vs+ – Vs– = 3 V ............. 8
7.7 Typical Characteristics: 5-V Single Supply ............. 11
7.8 Typical Characteristics: 3-V Single Supply ............. 14
7.9 Typical Characteristics: 3-V to 5-V Supply Range.. 17
Parameter Measurement Information ................ 21
8.1 Example Characterization Circuits.......................... 21
8.2 Frequency-Response Shape Factors ..................... 23
8.3 I/O Headroom Considerations ................................ 26
9
10 Application And Implementation....................... 44
10.1 Application Information.......................................... 44
10.2 Typical Applications .............................................. 44
11 Power-Supply Recommendations ..................... 49
12 Layout................................................................... 49
12.1 Layout Guidelines ................................................. 49
12.2 Layout Example .................................................... 50
13 器件和文档支持 ..................................................... 51
13.1 器件支持................................................................ 51
13.2 商标....................................................................... 51
13.3 静电放电警告......................................................... 51
13.4 术语表 ................................................................... 51
14 机械封装和可订购信息 .......................................... 51
8
8.4 Output DC Error and Drift Calculations and the Effect
of Resistor Imbalances ............................................ 28
4 修订历史记录
Changes from Original (August 2014) to Revision A
Page
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•
•
•
Added clarifying text to note 1 in Pin Functions table. ........................................................................................................... 3
Changed "Vcm" to "Vicm" in first paragraph ........................................................................................................................ 29
Changed 0.9 V to 0.91 V in second paragraph of Overview section ................................................................................... 33
Changed 0.9 V to 0.91 V in first paragraph of AC-Coupled Signal Path Considerations for Single-Ended Input to
Differential Output Conversion section................................................................................................................................. 36
•
•
•
•
Changed "single" to "signal" in first paragraph of Application Information section ............................................................. 44
Changed "usually" to "always" in fourth sentence of Detailed Design Procedure section ................................................... 44
Added "(in Hz)" to second paragraph of this page............................................................................................................... 45
Added "ΔΣ" to second paragraph of Detailed Design Procedure section ........................................................................... 47
2
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
5 Device Family Comparison
INPUT NOISE
DEVICE
THS4531A
THS4521
THS4520
BW (MHz)
36
IQ (mA)
0.25
THD (dBc) 2 VPP AT 100 kHz
(nV/√Hz)
RAIL-TO-RAIL
–104
–102
–107
10
Out
Out
Out
145
0.95
4.6
620
14.2
2.0
6 Pin Configuration and Functions
RGT Package
VQFN-16
RUN Package
WQFN-10
(Top View)
(Top View)
Vs+
10
16
15
14 13
OUT–
9
8
7
6
OUT+
NC
1
2
3
4
12 PD
FB–
IN+
1
2
3
4
NC
11 OUT–
Vocm
IN–
PD
IN–
10
9
OUT+
Vocm
IN+
5
FB+
Vs–
5
6
7
8
Pin Functions
PIN
NO.
NAME
RGT(1)
RUN
—
—
4
I/O
DESCRIPTION
FB+
FB–
IN+
4
O
O
I
Noninverted (positive) output feedback
Inverted (negative) output feedback
Noninverting (positive) amplifier input
Inverting (negative) amplifier input
No internal connection
1
2
IN–
3
6
I
NC
—
2, 8
9
—
O
O
I
OUT+
OUT–
PD
10
Noninverted (positive) amplifier output
Inverted (negative) amplifier output
11
12
1
3
Power down. PD = logic low = power off mode; PD = logic high = normal operation.
Common-mode voltage input
Vocm
Vs+
9
7
I
5, 6, 7, 8
10
I
Positive power-supply input
13, 14, 15,
16
Vs–
5
I
Negative power-supply input
(1) Solder the exposed thermal pad (RGT package) to a heat-spreading power or ground plane. This pad is electrically isolated from the
die, but must be connected to a power or ground plane and not floated.
Copyright © 2014, Texas Instruments Incorporated
3
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
5.5
UNIT
V
Supply voltage, Vs+ – Vs–
Voltage
Input/output voltage range
Differential input voltage
(Vs–) – 0.5
(Vs+) + 0.5
±1
V
V
Continuous input current
±20
mA
mA
Current
Continuous output current
Continuous power dissipation
Maximum junction temperature
Operating free-air temperature range
±80
See Thermal Information table and Thermal Analysis section
150
125
°C
°C
Temperature
–40
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 Handling Ratings
MIN
–65
MAX
150
UNIT
Tstg
Storage temperature range
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
°C
–2000
–500
–150
2000
500
Electrostatic
discharge
V(ESD)
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2)
Machine model(2)
V
150
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
UNIT
Vs+
TA
Single-supply voltage
Ambient temperature
5.4
V
–40
25
125
°C
7.4 Thermal Information
THS4541
THERMAL METRIC(1)
RGT (VQFN)
RUN (WQFN)
UNIT
16 PINS
52
10 PINS
146
75
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
69
25
39
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
2.7
14
ψJB
25
105
47
RθJC(bot)
9.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
4
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
7.5 Electrical Characteristics: Vs+ – Vs– = 5 V
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Vout = 100 mVPP, G = 1
620
500
210
125
850
340
100
1500
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
C
Vout = 100 mVPP, G = 2 (see Figure 61)
Vout = 100 mVPP, G = 5
Small-signal bandwidth
Vout = 100 mVPP, G = 10
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(2)
Vout = 100 mVPP, G = 20
Vout = 2 VPP, G = 2 (see Figure 61)
Vout = 2 VPP, G = 2 (see Figure 61)
Vout = 2-VPP, FPBW (see Figure 61)
Vout = 2-V step, G = 2 input ≤ 0.3 ns tr
(see Figure 63)
Rise/fall time
1.4
4
ns
ns
ns
C
C
C
C
To 1%, Vout = 2-V step, tr = 2 ns, G = 2
(seeFigure 63)
Settling time
To 0.1%,Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 63)
8
Vout = 2-V step G = 2, input ≤ 0.3 ns tr
(see Figure 63)
Overshoot and undershoot
100-kHz harmonic distortion
10%
Vout = 2 VPP, G = 2, HD2 (see Figure 61)
Vout = 2 VPP, G = 2, HD3 (see Figure 61)
Vout = 2 VPP, G = 2, HD2 (see Figure 61)
Vout = 2 VPP, G = 2, HD3 (see Figure 61)
f = 10 MHz, 100-kHz tone spacing,
–140
–140
–95
dBc
dBc
dBc
dBc
C
C
C
C
10-MHz harmonic distortion
–90
2nd-order intermodulation distortion
–90
–85
dBc
dBc
C
C
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)
f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)
3rd-order intermodulation distortion
Input voltage noise
f > 100 kHz
2.2
1.9
20
nV/√Hz
pA/√Hz
ns
C
C
C
C
Input current noise
f > 1 MHz
Overdrive recovery time
Closed-loop output impedance
2X output overdrive, either polarity
f = 10 MHz (differential)
0.1
Ω
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C; over temperature limits by characterization
and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB
.
Copyright © 2014, Texas Instruments Incorporated
5
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
Electrical Characteristics: Vs+ – Vs– = 5 V (continued)
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
DC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift(3)
100
–450
–600
–700
–850
–2.4
4.3
119
±100
±100
±100
±100
±0.5
10
dB
µV
A
A
B
B
B
B
A
B
B
B
B
A
B
B
B
B
TA = 25°C
450
600
700
850
2.4
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
µV
µV
µV
µV/°C
µA
13
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
4.3
11
13.5
14
µA
Input bias current
(positive out of node)
4.3
12
µA
4.3
12
14.5
15
µA
Input bias current drift(3)
Input offset current
6
nA/°C
nA
–500
–550
–580
–620
–1.3
±150
±150
±150
±150
±0.3
500
550
580
620
1.3
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
nA
nA
nA
Input offset current drift(3)
nA/°C
INPUT
< 3-dB degradation in TA = 25°C
CMRR from
midsupply
Vs– – 0.2 Vs– – 0.1
V
V
V
V
A
B
A
B
Common-mode input low
Common-mode input high
TA = –40°C to 125°C
Vs– – 0.1
Vs+ –1.2
Vs–
< 3-dB degradation in TA = +25°C
CMRR from
Vs+ – 1.3
Vs+ – 1.3
85
TA = –40°C to 125°C
midsupply
Common-mode rejection ratio
Input pins at (Vs+ – Vs–) / 2
Input pins at (Vs+ – Vs–) / 2
100
dB
A
C
Input impedance differential mode
110 || 0.85
kΩ || pF
OUTPUT
Vs– +
0.25
TA = 25°C
Vs– + 0.2
Vs– + 0.2
Vs+ – 0.2
V
V
V
V
A
B
A
B
Output voltage low
Vs– +
0.25
TA = –40°C to 125°C
TA = 25°C
Vs+ –
0.25
Output voltage high
Output current drive
Vs+ –
0.25
TA = –40°C to 125°C
Vs+ – 0.2
±100
TA = 25°C
±75
±75
mA
mA
A
B
TA = –40°C to 125°C
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum
drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
6
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
Electrical Characteristics: Vs+ – Vs– = 5 V (continued)
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Specified operating voltage
Quiescent operating current
Power-supply rejection ratio
2.7
9.7
9.4
85
5.0
10.1
10.1
100
5.4
10.5
11
V
B
A
B
A
TA = +25°C, Vs+ = 5.0 V
mA
mA
dB
TA = –40°C to 125°C
±PSRR
POWER DOWN
Enable voltage threshold
Either supply pin to differential Vout
Vs– + 1.7
V
A
A
B
A
A
Disable voltage threshold
Disable pin bias current
Vs– + 0.7
V
PD = Vs– → Vs+
PD = Vs– + 0.7 V
PD = Vs–
20
6
50
30
8
nA
µA
µA
Power-down quiescent current
2
Time from PD = low to Vout = 90% of final
value
Turn-on time delay
Turn-off time delay
100
60
ns
ns
C
C
Time from PD = low to Vout = 10% of final
value
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth
Slew rate(2)
Vocm = 100 mVPP
150
400
MHz
V/µs
C
C
A
A
C
Vocm = 2-V step
Gain
0.975
–0.7
0.982
0.1
0.995
0.7
V/V
Input bias current
Input impedance
Considered positive out of node
µA
Vocm input driven to (Vs+ – Vs–) / 2
47 || 1.2
kΩ || pF
Default voltage offset from
(Vs+ – Vs–) / 2
Vocm pin open
TA = 25°C
–40
±8
40
mV
A
–5
–6
±2
±2
±2
±2
5
5.8
mV
mV
mV
mV
A
B
B
B
TA = 0°C to 70°C
Vocm input driven to
(Vs+ – Vs–) / 2
CM Vos
Common-mode offset voltage
TA = –40°C to 85°C
TA = –40°C to 125°C
–6.2
–7.0
6.2
7.08
Common-mode offset voltage
drift(3)
Vocm input driven to (Vs+ – Vs–) / 2
TA = 25°C
–20
±4
+20
µV/°C
B
0.88
0.91
0.94
0.94
1.1
V
V
V
V
V
V
V
V
A
B
B
B
A
B
B
B
TA = 0°C to 70°C
Common-mode loop supply
headroom to negative supply
< ±12-mV shift from
midsupply CM Vos
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
1.15
1.2
Common-mode loop supply
headroom to positive supply
< ±12-mV shift from
midsupply CM Vos
1.2
(4) Specifications are from the input Vocm pin to the differential output average voltage.
Copyright © 2014, Texas Instruments Incorporated
7
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
7.6 Electrical Characteristics: Vs+ – Vs– = 3 V
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Vout = 100 mVPP, G = 1
600
500
200
120
850
300
90
MHz
MHz
MHz
MHz
MHz
MHz
MHz
V/µs
C
C
C
C
C
C
C
C
Vout = 100 mVPP, G = 2 (see Figure 61)
Vout = 100 mVPP, G = 5
Small-signal bandwidth
Vout = 100 mVPP, G = 10
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
Slew rate(2)
Vout = 100 mVPP, G = 20
Vout = 2 VPP, G = 2 (see Figure 61)
Vout = 2 VPP, G = 2 (see Figure 61)
Vout = 2-V step, FPBW (see Figure 61)
1300
Vout = 2-V step, G = 2, input ≤ 0.3 ns tr
(see Figure 63)
Rise/fall time
1.8
5
ns
ns
ns
C
C
C
C
To 1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 63)
Settling time
To 0.1%, Vout = 2-V step, tr = 2 ns, G = 2
(see Figure 63)
8
Vout = 2-V step G = 2, input ≤ 0.3 ns tr
(see Figure 63)
Overshoot and undershoot
100-kHz harmonic distortion
10%
Vout = 2 VPP, G = 2, HD2 (see Figure 61)
Vout = 2 VPP, G = 2, HD3 (see Figure 61)
Vout = 2 VPP, G = 2, HD2 (see Figure 61)
Vout = 2 VPP, G = 2, HD3 (see Figure 61)
f = 10 MHz, 100-kHz tone spacing,
–140
–140
–92
dBc
dBc
dBc
dBc
C
C
C
C
10-MHz harmonic distortion
–89
2nd-order intermodulation distortion
–89
–87
dBc
dBc
C
C
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)
f = 10 MHz, 100-kHz tone spacing,
Vout envelope = 2 VPP (1 VPP per tone)
(see Figure 61)
3rd-order intermodulation distortion
Input voltage noise
f > 100 kHz
2.2
1.9
20
nV/√Hz
pA/√Hz
ns
C
C
C
C
Input current noise
f > 1 MHz
Overdrive recovery time
Closed-loop output impedance
2X output overdrive, either polarity
f = 10 MHz (differential)
0.1
Ω
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈ 25°C; over temperature limits by characterization
and simulation. (B) Not tested in production; limits set by characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VP / √2) · 2π · f–3dB
.
8
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Electrical Characteristics: Vs+ – Vs– = 3 V (continued)
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
DC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
AOL
Open-loop voltage gain
Input-referred offset voltage
Input offset voltage drift(3)
100
–450
–600
–700
–850
–2.4
4.1
119
±100
±100
±100
±100
±0.5
9
dB
µV
A
A
B
B
B
B
A
B
B
B
B
A
B
B
B
B
TA = 25°C
400
600
700
850
2.4
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
µV
µV
µV
µV/°C
µA
12
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
TA = 25°C
4.1
9
12.5
13
µA
Input bias current
(positive out of node)
4.1
9
µA
4.1
9
13.5
15
µA
Input bias current drift(3)
Input offset current
–5
nA/°C
nA
–500
–550
–580
–620
–1.3
±150
±150
±150
±150
±0.3
500
550
580
620
1.3
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = –40°C to 125°C
nA
nA
nA
Input offset current drift(3)
nA/°C
INPUT
< 3-dB degradation in TA = 25°C
CMRR from
midsupply
Vs– – 0.2 Vs– – 0.1
V
V
V
V
A
B
A
B
Common-mode input low
Common-mode input high
TA = –40°C to 125°C
Vs– – 0.1
Vs+ –1.2
Vs–
< 3-dB degradation in TA = +25°C
CMRR from
Vs+ – 1.3
Vs+ – 1.3
85
TA = –40°C to 125°C
midsupply
Common-mode rejection ratio
Input pins at (Vs+ – Vs–) / 2
Input pins at (Vs+ – Vs–) / 2
100
dB
A
C
Input impedance differential mode
110 || 0.85
kΩ || pF
OUTPUT
Vs– +
0.25
TA = 25°C
Vs– + 0.2
Vs– + 0.2
Vs+ – 0.2
V
V
V
V
A
B
A
B
Output voltage low
Vs– +
0.25
TA = –40°C to 125°C
TA = 25°C
Vs+ –
0.25
Output voltage high
Output current drive
Vs+ –
0.25
TA = –40°C to 125°C
Vs+ – 0.2
±60
TA = 25°C
±55
±55
mA
mA
A
B
TA = –40°C to 125°C
(3) Input offset voltage drift, input bias current drift, input offset current drift, and Vocm drift are average values calculated by taking data at
the at the maximum-range ambient-temperature end points, computing the difference, and dividing by the temperature range. Maximum
drift set by distribution of a large sampling of devices. Drift is not specified by test or QA sample test.
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Electrical Characteristics: Vs+ – Vs– = 3 V (continued)
At TA ≈ 25°C, Vocm = open (defaults midsupply), VOUT = 2 VPP, Rf = 402 Ω, Rload = 499 Ω, 50-Ω input match, G = 2 V/V,
single-ended input, differential output, and PD = +Vs, unless otherwise noted. See Figure 61 for an ac-coupled gain of a
2-V/V test circuit, and Figure 63 for a dc-coupled gain of a 2-V/V test circuit.
TEST
PARAMETER
POWER SUPPLY
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
Specified operating voltage
Quiescent operating current
Power-supply rejection ratio
2.7
9.3
9.0
85
3.0
9.7
9.7
100
5.4
10.1
10.6
V
B
A
B
A
TA = +25°C, Vs+ = 3.0 V
mA
mA
dB
TA = –40°C to 125°C
±PSRR
POWER DOWN
Enable voltage threshold
Either supply pin to differential Vout
Vs– + 1.7
V
A
A
B
A
A
Disable voltage threshold
Disable pin bias current
Vs– + 0.7
V
PD = Vs– → Vs+
PD = Vs– + 0.7 V
PD = Vs–
20
2
50
30
nA
µA
µA
Power-down quiescent current
1.0
8.0
Time from PD = low to Vout = 90% of final
value
Turn-on time delay
Turn-off time delay
100
60
ns
ns
C
C
Time from PD = low to Vout = 10% of final
value
OUTPUT COMMON-MODE VOLTAGE CONTROL(4)
Small-signal bandwidth
Slew rate(2)
Vocm = 100 mVPP
140
350
MHz
V/µs
C
C
A
A
C
Vocm = 1-V step
Gain
0.975
–0.7
0.987
0.1
0.990
0.7
V/V
Input bias current
Input impedance
Considered positive out of node
µA
Vocm input driven to (Vs+ – Vs–) / 2
47 || 1.2
kΩ || pF
Default voltage offset from
(Vs+ – Vs–) / 2
Vocm pin open
TA = 25°C
–40
±10
40
mV
A
–5
–5.8
–6.2
–7.0
±2
±2
±2
±2
5
5.8
6.2
7.0
mV
mV
mV
mV
A
B
B
B
TA = 0°C to 70°C
Vocm input driven to
(Vs+ – Vs–) / 2
CM Vos
Common-mode offset voltage
TA = –40°C to 85°C
TA = –40°C to 125°C
Common-mode offset voltage
drift(3)
Vocm input driven to (Vs+ – Vs–) / 2
TA = 25°C
–20
±4
20
µV/°C
B
0.88
0.91
0.94
0.94
1.1
V
V
V
V
V
V
V
V
A
B
B
B
A
B
B
B
TA = 0°C to 70°C
Common-mode loop supply
headroom to negative supply
< ±12-mV shift from
midsupply CM Vos
TA = –40°C to 85°C
TA = –40°C to 125°C
TA = 25°C
TA = 0°C to 70°C
TA = –40°C to 85°C
TA = –40°C to 125°C
1.15
1.2
Common-mode loop supply
headroom to positive supply
< ±12-mV shift from
midsupply CM Vos
1.2
(4) Specifications are from input Vocm pin to differential output average voltage.
10
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7.7 Typical Characteristics: 5-V Single Supply
At Vs+ = 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
9
6
9
6
G=0.1
G=1
G=2
G=5
G=10
3
3
0
0
-3
-6
-9
-12
-3
-6
-9
Vo=100 mVpp
Vo=500 mVpp
Vo=1 Vpp
Vo=2 Vpp
Vo=5 Vpp
1
10
100
Frequency (MHz)
1000
10
100
1000
Frequency (MHz)
D001
D002
Rf = 402 Ω, see Figure 61 and Table 6 for resistor values
See Figure 61
Figure 1. Small-Signal Frequency Response vs Gain
Figure 2. Frequency Response vs Vopp
9
9
8
7
6
5
4
3
Vocm=1.0 V
Vocm=1.5 V
Vocm=2.0 V
Vocm=2.5 V
Vocm=3.0 V
Vocm=3.5 V
RL=50 :
RL=100 :
RL=200 :
RL=500 :
RL=1000 :
8
7
6
5
4
3
10
100
1000
10
100
1000
Frequency (MHz)
Frequency (MHz)
D003
D004
Vout = 100 mVPP , see Figure 61 with Vocm adjusted
Vout = 100 mVPP, see Figure 61 with RL adjusted
Figure 3. Small-Signal Frequency Response vs Vocm
Figure 4. Small-Signal Frequency Response vs Rload (RL)
9
40
Cload=10 pF, Ro = 24.9 :
Cload=22 pF, Ro = 16 :
Cload=51 pF, Ro = 9.1 :
Cload=100 pF, Ro = 5.4 :
Av=2
Av=4
Av=10
35
30
25
20
15
10
5
8
7
6
5
4
3
0
10
100
Frequency (MHz)
1000
1
10
100
Cload (pF)
D005
D006
100 mVPP at load, Av = 2 (see Figure 71), two series Ro added at
output before Cload
Ro is two series output resistors to a differential Cload in parallel
with 500 Ω, see Figure 71 and Table 6
Figure 5. Small-Signal Frequency Response vs Cload
Figure 6. Recommended Ro vs Cload
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Typical Characteristics: 5-V Single Supply (continued)
At Vs+ = 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
2.5
0.5
0.4
0.3
0.2
0.1
0
4 Vpp
2 Vpp
0.5 Vpp
Ro=17 :
Ro=0 :
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
6
8
10 12 14 16 18 20 22 24 26 28 30
Time (ns)
8
10
12
14
16
Time (ns)
18
20
22
24
D007
D008
50-MHz input, 0.3-ns input edge rate, single-ended to differential
output, dc coupled, see Figure 63
Av = 2 , 500-mVPP output into 22-pF Cload, see Figure 71
Figure 7. Small- and Large-Signal Step Response
Figure 8. Step Response into Capacitive Load
2.5
0.5
4 Vpp
2 Vpp
0.5 Vpp
Ro=0 :
Ro=7.5 :
2
0.45
1.5
0.4
0.35
0.3
1
0.5
0
0.25
0.2
-0.5
-1
0.15
0.1
-1.5
-2
0.05
0
-2.5
6
8
10 12 14 16 18 20 22 24 26 28 30
Time (ns)
8
10
12
14
16
Time (ns)
18
20
22
24
D009
D010
G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended
input to differential output, see Figure 63
G = 5 V/V, 500-mVPP output into 22-pF Cload, see Figure 71 and
Table 6
Figure 9. Small- and Large-Signal Step Response
Figure 10. Step Response into Capacitive Load
0.2
15
0.5 V step
Output
2 V step
Input
0.15
0.1
10
5
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-5
-10
-15
0
5
10
15
20
0
20
40
60
80
100
Time ' from 50% of Input Edge (ns)
Time (ns)
D011
D012
Simulated with 2-ns input transition time, see Figure 63
Single-ended to differential gain of 2 (see Figure 63), 2X input
overdrive
Figure 12. Overdrive Recovery Performance
Figure 11. Small- and Large-Signal Step Settling Time
12
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Typical Characteristics: 5-V Single Supply (continued)
At Vs+ = 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
-50
-70
HD2
HD3
HD2
HD3
-75
-60
-80
-70
-85
-80
-90
-90
-95
-100
-110
-120
-130
-140
-100
-105
-110
-115
-120
0.1
1
10
50
0.1
1
10
Frequency (MHz)
Differential Output Voltage (Vpp)
D013
D014
2-VPP output, see Figure 61
10 MHz, see Figure 61
Figure 13. Harmonic Distortion Over Frequency
Figure 14. Harmonic Distortion vs Output Swing
-60
-70
-70
-75
Avg IMD3
Avg IMD2
HD2
HD3
-80
-80
-90
-100
-110
-120
-130
-140
-85
-90
-95
-100
0.1
1
10
50
10
100
1000
Center of Two Input Test Frequencies (MHz)
Differential Load Resistance (:)
D015
D016
1 VPP each tone, see Figure 61
f = 10 MHz, see Figure 61 with Rload adjusted
Figure 15. IMD2 and IM3 Over Frequency
Figure 16. Harmonic Distortion vs Rload
-80
-85
-70
-75
HD2
HD3
HD2
HD3
-80
-90
-85
-90
-95
-95
-100
-100
0.5
1
1.5
2
2.5
3
3.5
4
1
10
Vocm Control Voltage (V)
Gain (V/V)
D017
D018
f = 10 MHz, 2-VPP output, see Figure 63 with Vocm adjusted
Figure 17. Harmonic Distortion vs Vocm
10 MHz, 2-VPP output, see Figure 61 and Table 6 for gain setting
Figure 18. Harmonic Distortion vs Gain
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7.8 Typical Characteristics: 3-V Single Supply
At Vs+ = 3 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
9
6
9
6
G=0.1
G=1
G=2
G=5
G=10
3
3
0
0
-3
-6
-9
-12
-3
-6
-9
-12
Vo=100 mVpp
Vo=500 mVpp
Vo=1 Vpp
Vo=2 Vpp
Vo=5 Vpp
1
10
100
Frequency (MHz)
1000
10
100
1000
Frequency (MHz)
D019
D020
Rf = 402 Ω, Vout = 100 mVPP, see Figure 61 and Table 6 for
See Figure 61 with VCC = 3 V and Vocm = 1.5 V
resistor values
Figure 19. Small-Signal Frequency Response vs Gain
Figure 20. Frequency Response vs Vopp
9
9
8
7
6
5
4
3
Vocm=1.0 V
Vocm=1.5 V
Vocm=1.8 V
RL=50 :
RL=100 :
RL=200 :
RL=500 :
RL=1000 :
8
7
6
5
4
3
10
100
1000
10
100
1000
Frequency (MHz)
Frequency (MHz)
D021
D022
Vout = 100 mVPP, see Figure 61 with Vocm adjusted
Vout = 100 mVPP, see Figure 61 with the Rload adjusted
Figure 21. Small-Signal Frequency response vs Vocm
Figure 22. Small-Signal Frequency Response vs Rload (RL)
9
40
Cload=10 pF, Ro=27 :
Cload=22 pF, Ro=18 :
Cload=51 pF, Ro=10 :
Cload=100 pF, Ro=5.4 :
Av=2
Av=4
Av=10
35
30
25
20
15
10
5
8
7
6
5
4
3
0
10
100
Frequency (MHz)
1000
1
10
100
Differential Cload (pF)
D023
D024
100 mVPP at load, Av = 2 (see Figure 71), two series Ro added at
output before Cload
Two Ro at output to differential Cload in parallel with 500 Ω, see
Figure 71 and Table 6
Figure 23. Small-Signal Frequency Response vs Cload
Figure 24. Recommended Ro vs Cload
14
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Typical Characteristics: 3-V Single Supply (continued)
At Vs+ = 3 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
3
2.5
2
0.5
0.4
0.3
0.2
0.1
0
4 Vpp
2 Vpp
0.5 Vpp
Ro=13.7 :
Ro=0 :
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
-3
6
8
10 12 14 16 18 20 22 24 26 28 30
Time (ns)
8
10
12
14
16
Time (ns)
18
20
22
24
D025
D026
50-MHz input, 0.3-ns input edge rate, single-ended input to
differential output, dc coupled, see Figure 63
500-mVPP output into 22-pF Cload, see Figure 71 with Vs+ = 3 V
and Vocm = 1.5 V
Figure 25. Small- and Large-Signal Step Response
Figure 26. Step Response into Capacitive Load
2.5
0.5
4 Vpp
2 Vpp
0.5 Vpp
Ro=7.5 :
Ro=0 :
2
0.45
1.5
0.4
0.35
0.3
1
0.5
0
0.25
0.2
-0.5
-1
0.15
0.1
-1.5
-2
0.05
0
-2.5
6
8
10 12 14 16 18 20 22 24 26 28 30
Time (ns)
8
10
12
14
16
Time (ns)
18
20
22
24
D027
D028
G = 5 V/V, 50-MHz input, 0.3-ns input edge rate, single-ended
input to differential output, see Figure 61
G = 5 V/V, 500-mVpp output into 22-pF Cload, see Figure 71 and
Table 6
Figure 27. Small- and Large-Signal Step Response
Figure 28. Step Response into Capacitive Load
0.2
6
0.5 V step
Output
2 V step
Input
0.15
0.1
4
2
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-2
-4
-6
0
5
10
15
20
0
20
40
60
80
100
Time ' from 50% of Input Edge (ns)
Time (ns)
D029
D030
Simulated with 2-ns input transition time, see Figure 63
Single-ended to differential gain of 2 (see Figure 63), > 2X input
overdrive
Figure 30. Overdrive Recovery Performance
Figure 29. Small- and Large-Signal Step Settling Time
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Typical Characteristics: 3-V Single Supply (continued)
At Vs+ = 3 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω, and TA
≈ 25°C (unless otherwise noted).
-50
-70
HD2
HD3
HD2
HD3
-75
-60
-80
-70
-85
-80
-90
-90
-95
-100
-110
-120
-130
-140
-100
-105
-110
-115
-120
0.1
1
10
50
0.1
1
10
Frequency (kHz)
Differential Output Voltage (Vpp)
D031
D032
2-VPP output, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V
f = 10 MHz, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V
Figure 31. Harmonic Distortion Over Frequency
Figure 32. Harmonic Distortion vs Output Swing
-60
-70
Avg IMD3
HD2
Avg IMD2
HD3
-70
-80
-75
-80
-85
-90
-100
-110
-120
-130
-140
-90
-95
-100
0.1
1
10
50
10
100
1000
Center of Two Input Test Frequencies (MHz)
Differential Load Resistance (:)
D033
D034
1 VPP each tone, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V
f = 10 MHz, see Figure 61 with Vs+ = 3.0 V, Vocm = 1.5 V
Figure 33. IMD2 and IM3 Over Frequency
Figure 34. Harmonic Distortion vs Rload
-80
-70
HD2
HD3
HD2
HD3
-75
-85
-90
-80
-85
-90
-95
-95
-100
-105
-100
0.5
1
1.5
2
2.5
1
10
Vocm Control Voltage (V)
Gain (V/V)
D035
D036
f = 10 MHz, 2-VPP output, see Figure 63 with Vocm adjusted
f = 10 MHz, 2-VPP output, see Figure 61 and Table 6 for gain
setting
Figure 36. Harmonic Distortion vs Gain
Figure 35. Harmonic Distortion vs Vocm
16
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7.9 Typical Characteristics: 3-V to 5-V Supply Range
At Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω,
and TA ≈ 25°C (unless otherwise noted).
10
1
130
100
70
0
Gain=2, +3 V
Gain=2, +5 V
Gain=5, +3 V
Gain=5, +5 V
Aol Gain
Aol Phase
-50
0.1
-100
-150
-200
-250
0.01
0.001
0.0001
40
10
-20
100
1k
10k
100k
1M
10M
100M
1G
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D037
D038
Single-ended input to differential output, simulated differential
output impedance, (closed-loop) gain of 2 and 5, see Figure 61
Figure 38. Closed-Loop Output Impedance
Figure 37. Main Amplifier Differential Open-Loop Gain and
Phase vs Frequency
-50
50
+3 V supply
+5 V supply
+5 V En
+5 V In
+3 V En
+3 V In
-55
-60
-65
-70
-75
-80
10
1
1k
10k
100k
1M
10M
1k
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D039
D040
Single-ended input to differential output, gain of 2 (see Figure 61),
simulated with 1% resistor, worst-case mismatch
Figure 40. Output Balance Error Over Frequency
Figure 39. Input Spot Noise Over Frequency
110
100
90
90
+3 V +Vs
+5 V +Vs
+3 V -Vs
+5 V -Vs
85
80
75
70
65
60
55
50
45
40
80
70
60
50
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
Frequency (Hz)
Frequency (Hz)
D041
D042
Common-mode in to differential out, gain of 2 simulation
Single-ended to differential, gain of 2 (see Figure 61) PSRR
simulated to differential output
Figure 42. PSRR Over Frequency
Figure 41. CMRR Over Frequency
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Typical Characteristics: 3-V to 5-V Supply Range (continued)
At Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω,
and TA ≈ 25°C (unless otherwise noted).
1
0.5
0
3
2.75
2.5
2.25
2
+5 V, 100 mVpp
+5 V, 1 Vpp
+3 V, 100 mVpp
+3 V, 1 Vpp
5 V Large Signal
-0.5
-1
5 V Small Signal
-1.5
-2
1.75
1.5
1.25
1
3 V Large Signal
-2.5
-3
-3.5
-4
3 V Small Signal
1
10
100
Frequency (MHz)
1000
25
35
45
55
65
Time (ns)
75
85
95
D043
D044
Figure 43. Common-Mode, Small- and Large-Signal
Response (Vocm pin driven)
Figure 44. Common-Mode, Small- and Large-Step Response
(Vocm pin driven)
1000
100
10
10
+5 V Vocm driven
+5 V Vocm floating
+3 V Vocm driven
+3 V Vocm floating
+5 V supply
+3 V supply
8
6
4
2
0
-2
-4
-6
-8
-10
1
100
1k
10k
100k
1M
10M
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
Frequency (Hz)
Vocm Input Voltage (V)
D045
D046
Vocm input either driven to midsupply by low impedance source,
or allowed to float and default to midsupply
Average Vocm output offset of 37 units,
Standard deviation < 2.5 mV, see Figure 63
Figure 45. Output Common-Mode Noise
Figure 46. Vocm Offset vs Vocm Setting
100
100
+3 V supply
+5 V supply
95
95
90
85
80
75
70
90
85
80
75
70
+3 V supply
+5 V supply
0.85
1.35
1.85
2.35
2.85
3.35
3.85
0.85
1.35
1.85
2.35
2.85
3.35
3.85
Vocm (V)
Vocm (V)
D047
D048
Single-ended to differential gain of 2 (see Figure 61), PSRR for
negative supply to differential output (1-kHz simulation)
Single-ended to differential gain of 2 (see Figure 61), PSRR for
positive supply to differential output (1-kHz simulation)
Figure 47. –PSRR vs Vocm Approaching Vs–
Figure 48. +PSRR vs Vocm Approaching Vs+
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Typical Characteristics: 3-V to 5-V Supply Range (continued)
At Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω,
and TA ≈ 25°C (unless otherwise noted).
600
500
400
300
200
100
0
900
800
700
600
500
400
300
200
100
0
+5 V supply
+3 V supply
+5 V supply
+3 V supply
D049
D050
Input Offset Voltage (PV)
Input Offset Current (nA)
3 lots, total of 2962 units trimmed at 5-V supply
3 lots, total of 2962 units
Figure 49. Input Offset Voltage
Figure 50. Input Offset Current
100
75
250
200
150
100
50
50
25
0
0
-50
-25
-50
-75
-100
-100
-150
-200
-250
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Ambient Temperature (°C)
D051
D052
5-V and 3-V delta from 25°C VIO, 25 units
5-V and 3-V over temperature IOS, 25 units
Figure 51. Input Offset Voltage Over Temperature
Figure 52. Input Offset Current Over Temperature
14
12
10
8
12
10
8
+5 V supply
+3 V supply
+5 V supply
+3 V supply
6
6
4
4
2
2
0
0
D053
D054
Offset Drift (µV/qC)
Offset Current Drift (nA/°C)
–40°C to 125°C endpoint drift, 3 lots, total of 68 units
–40°C to 125°C endpoint drift, 3 lots, total of 68 units
Figure 53. Input Offset Voltage Drift
Figure 54. Input Offset Current Drift
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Typical Characteristics: 3-V to 5-V Supply Range (continued)
At Vs+ = 3 V and 5 V, Vs– = GND, Vocm is open, 50-Ω single-ended input to differential output, gain = 2 V/V, Rload = 500 Ω,
and TA ≈ 25°C (unless otherwise noted).
10
9
8
7
6
5
4
3
2
1
0
11
10.5
10
9.5
9
5 V supply
3 V supply
5 V supply
3 V supply
8.5
8
7.5
7
10
100
1000
0
1
2
3
4
5
Differential Load (:)
Disable Pin Voltage (PD) Volts
D055
D056
Maximum differential output swing, Vocm at midsupply
Figure 55. Maximum Vopp vs Rload
Figure 56. Supply Current vs PD Voltage
1400
600
500
400
300
200
100
0
5 V data
3 V data
5 V data
3 V data
1200
1000
800
600
400
200
0
Vocm Offset Voltage (mV)
D057
D058
Vocm Offset Voltage (mV)
Vocm input floating, 3 lots, total of 2962 units
Input driven midsupply, 3 lots, total of 2962 units
Figure 58. Common-Mode Output Offset from Driven Vocm
Figure 57. Common-Mode Output Offset from Vs+ / 2
Default Value
5
4
5
PD 3 V
Out 3 V
Out 5 V
PD 5 V
PD 3 V
4
3
PD 5 V
3
3-V Supply
5-V Supply
2
2
1
1
0
0
-1
-2
-1
-2
0.04
0.06
0.08
0.1
0.12
0.14
0.16
0.18
0.28
0.3
0.32
0.34
0.36
Time (µs)
Time (µs)
D059
D060
10 MHz, 1-Vpp input single to differential gain of 2, see Figure 63
10 MHz, 1-VPP input single to differential gain of 2, see Figure 63
Figure 59. PD Turn On Waveform
Figure 60. PD Turn Off Waveform
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8 Parameter Measurement Information
8.1 Example Characterization Circuits
The THS4541 offers the advantages of a fully differential amplifier (FDA) design, with the trimmed input offset
voltage of a precision op amp. The FDA is an extremely flexible device that provides a purely differential output
signal centered on a settable output common-mode level. The primary options revolve around the choices of
single-ended or differential inputs, ac-coupled or dc-coupled signal paths, gain targets, and resistor-value
selections. The characterizations shown in Figure 1 to Figure 36 focus on single-ended-to-differential designs as
the more challenging application requirement. Differential sources can certainly be supported and are often
simpler to both implement and analyze.
Because most lab equipment is single-ended, the characterization circuits typically operate with a single-ended,
matched, 50-Ω input termination to a differential output at the FDA output pins. That output is then translated
back to single-ended through a variety of baluns (or transformers) depending on the test and frequency range.
DC-coupled, step-response testing uses two 50-Ω scope inputs with trace math. The starting point for any single-
ended-to-differential, ac-coupled characterization plot is shown in Figure 61.
THS4541 Wideband,
Fully-Differential Amplifier
50-ꢀꢀInput Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
Rf1
402 ꢀ
C1
100 nF
Vcc
Rg1
191 ꢀ
50-ꢀꢀ
Source
±
Output
Measurement
Point
+
Rload
500 ꢀ
Rt
60.2 ꢀ
Vocm
FDA
±
+
PD
Rg2
Vcc
221 ꢀ
C2
100 nF
Rf2
402 ꢀ
Figure 61. AC-Coupled, Single-Ended Source to a Differential Gain of a 2-V/V Test Circuit
Most characterization plots fix the Rf (Rf1 = Rf2) value at 402 Ω, as shown in Figure 61. This element value is
completely flexible in application, but the 402 Ω provides a good compromise for the parasitic issues linked to
this value, specifically:
•
•
•
Added output loading. The FDA appears like an inverting op amp design with both feedback resistors as an
added load across the outputs (approximate total differential load in Figure 61 is 500 Ω || 804 Ω = 308 Ω).
Noise contributions because of the resistor values. The resistors contribute both a 4kTR term and provide
gain for the input current noise (see the Noise Analysis section).
Parasitic feedback pole at the input summing nodes. This pole created by the feedback R value and the
0.85-pF differential input capacitance (as well as any board layout parasitic) introduces a zero in the noise
gain, decreasing the phase margin in most situations. This effect must be managed for best frequency
response flatness or step response overshoot. The 402-Ω value selected does degrade the phase margin
slightly over a lower value, but does not decrease the loading significantly from the nominal 500-Ω value
across the output pins.
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Example Characterization Circuits (continued)
The frequency domain characterization curves start with the selections of Figure 61. Then, various elements are
modified to show their impact over a range of design targets, specifically:
•
•
•
Gain setting is changed by adjusting Rt and the 2 – Rg elements (holding a 50-Ω input match).
Output loading, including both resistive and capacitive load testing.
Power-supply settings. Most often, a single +5-V test uses a ±2.5-V supply, and a +3-V test uses ±1.5-V
supplies.
•
The disable control pin is tied to Vs+ for any active channel test.
Because most network and spectrum analyzers are a single-ended input, the output network on the THS4541
characterization tests typically show the desired load connected through a balun to a single-ended, 50-Ω load,
while presenting a 50-Ω source from the balun output back into the balun. For instance, Figure 62 shows a
wideband MA/Com balun used for Figure 61. This network shows a 500-Ω differential load to the THS4541, but
an ac-coupled, 50-Ω source to the network analyzer. Distortion testing typically uses a lower-frequency, dc-
isolated balun (such as the TT1-6T) that is rotated 90° from the wider band interface of Figure 62.
C10
100 nF
Ro1
237 ꢀ
ETC1-1-13
50-ꢀꢀLoad
N1
500-ꢀꢀ
Differential
Load
THS4541
Output
R9
56.2 ꢀ
Ro2
237 ꢀ
N2
C9
100 nF
Figure 62. Example 500-Ω Load to a Single-Ended, Doubly-Terminated, AC-Coupled, 50-Ω Interface
This approach allows a higher differential load, but with a wideband 50-Ω output match at the cost of
considerable signal-path insertion loss. This loss is acceptable for characterization, and is normalized out to
show the characterization curves.
For time-domain or dc-coupled testing, the circuit of Figure 63 is used as a starting point, where the gain of a
5-V/V setting used in Figure 9 and Figure 27 are illustrated.
THS4541 Wideband,
Fully-Differential Amplifier
50-ꢀꢀInput Match,
Gain of 5 V/V from Rt,
Single-Ended Source to
Rf1
402 ꢀ
Differential Step-Response Test
Vcc
Rg1
68.1 ꢀ
50-ꢀ
±
Source
Output
Measurement
Point
+
R1
500 ꢀ
Rt
80.6 ꢀ
Vocm
FDA
±
+
PD
Rg2
Vcc
100 ꢀ
Rf2
402 ꢀ
Figure 63. DC-Coupled, Single-Ended-to-Differential, Basic Test Circuit Set for a Gain of 5 V/V
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Example Characterization Circuits (continued)
In this case, the input is dc-coupled, showing a 50-Ω input match to the source, gain of 5 V/V to a differential
output, again driving a nominal 500-Ω load. Using a single supply, the Vocm control input can either be floated
(defaulting to midsupply) or be driven within the allowed range for the Vocm loop (see the headroom limits on
Vocm in the Electrical Characteristics tables). To use this circuit for step-response measurements, load each of
the two outputs with a 250-Ω network, translating to a 50-Ω source impedance driving into two 50-Ω scope
inputs. Then, difference the scope inputs to generate the step responses of Figure 9 and Figure 27. Figure 64
shows the output interface circuit. This grounded interface pulls a dc load current from the output Vocm voltage
for single-supply operation. Running this test with balanced bipolar power supplies eliminates this dc load current
and gives similar waveform results.
Ro1
221 ꢀ
50-ꢀ
Scope
Rm1
64.9 ꢀ
THS4541
Output
Rm1
Ro2
64.9 ꢀ
221 ꢀ
50-ꢀ
Scope
Figure 64. Example 500-Ω Load to Differential, Doubly-Terminated, DC-Coupled 50-Ω Scope Interface
8.2 Frequency-Response Shape Factors
Figure 1 illustrates the small-signal response shape versus gain using a fixed 402-Ω feedback resistor in the
circuit of Figure 61. Being a voltage-feedback based FDA, the THS4541 shows a response shape that varies
with gain setting, largely determined by the loop-gain crossover frequency and phase margin at the crossover.
This loop-gain crossover frequency is where the open-loop response and the noise gain intersect (where the loop
gain drops to 1). The noise gain is the inverse of the voltage divider from the outputs back to the differential
inputs; use a balanced divider ratio on each feedback path. In general, the noise gain (NG) does not equal the
signal gain for designs providing an input match from a source impedance. NG is given by 1 + Rf / (total
impedance from the inverting summing junction to ground). Using the resistor values computed in the gain sweep
of Table 6, and repeating that sweep showing the NG gives Table 1, where only the exact R solutions are
shown.
Table 1. Resistor Values and Noise Gain for Swept Gain with Rf = 402 Ω(1)
SIGNAL GAIN
Rt, EXACT (Ω)
55.2
Rg1, EXACT (Ω)
399
Rg2, EXACT (Ω)
425
NOISE GAIN
1.94
1
2
60.1
191
218
2.85
3
65.6
124
153
3.63
4
72.0
89.7
119
4.37
5
79.7
67.8
98.3
5.09
6
89.1
54.2
86.5
5.65
7
101
43.2
76.6
6.25
8
117
35.2
70.1
6.74
9
138
29.0
65.8
7.11
10
11
12
13
14
170
23.6
62.5
7.44
220
18.7
59.3
7.78
313
14.6
57.7
7.97
545
10.8
56.6
8.11
2209
7.26
56.1
8.16
(1) Rf = 402 Ω, Rs = 50 Ω, and AvMAX = 14.32 V/V.
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NG is critically important for bandwidth and all output error terms (such as dc offset and noise). For lower-speed
devices, normally only the dc noise gain is considered. However, for the THS4541, with loop gain crossover at
greater than 300 MHz, the feedback network produces a parasitic pole to the differential summing junctions that
causes the noise gain to increase with frequency. This pole causes a lower crossover frequency than might be
expected with added phase shift around the loop. Consider the feedback network (single-ended) of Figure 65,
showing a parasitic 0.2 pF on the feedback 402-Ω resistor. The 0.85-pF differential input capacitance of the
THS4541 is converted to single-ended as a 1.7-pF parasitic for this single-sided analysis circuit (the Rg shown is
Rg2 in Figure 61).
Cf
200 fF
Vin
Rf
402 ꢀ
Rg
221 ꢀ
Cin
1.7 pF
FDA
Output
Pin
+
Vout
±
Figure 65. Feedback Network for the Gain of 2 Configuration Using 402 Ω and Matching to a 50-Ω Source
The response shape from Vout to Vin in Figure 65 has a pole and then a zero. To describe NG, invert the
Laplace transform of Vin and Vout from Figure 65 to provide the frequency-dependent NG response of
Equation 1, where a zero comes in first and then a pole.
Rf
1ꢂ
Rg
s ꢂ
Rf Cf ꢂ Cin
ꢀ
ꢁ
Cin
Cf
§
·
NG 1ꢂ
¨
¸
¹
1
©
s ꢂ
Rf Cf
(1)
The zero location is key. Using the gain of 2 values of Figure 65, the estimated zero in the NG is 588 MHz.
Limiting the parasitic capacitance at the summing junctions, either differentially or signal-ended, to a ground or
power plane is critical in board layouts.
Using this feedback model, and the open-loop gain and phase data for the THS4541, allows the Aol and NG
curves over frequency to be drawn, as shown in Figure 66, where the peaking in the noise gain pulls the
intersection point back in frequency.
40
Aol Gain
Gain = 0.1
Gain = 1
Gain = 2
35
30
25
20
15
10
5
0
10M
100M
1G
Frequency (Hz)
D062
Figure 66. Aol and Noise Gain Plots for the Lower Gains of Figure 61
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To assess closed-loop bandwidth and peaking, the noise-gain phase must be subtracted from the THS4541 Aol
phase to obtain the total phase around the loop, as shown in Figure 67.
-90
-100
-110
-120
-130
-140
-150
Aol Phase
Gain = 0.1
Gain = 1
-160
-170
-180
Gain = 2
10M
100M
1G
Frequency (Hz)
D063
Figure 67. Loop-Gain Phase for the Three Lower Gains of Figure 1
From Figure 66 and Figure 67, using Table 2, tabulate the loop-gain crossover frequency and phase margin at
these crossovers to explain the response shapes of Figure 1.
Table 2. Estimated Crossover Frequency and Phase Margin for Gains of 0.1, 1, and 2 in Figure 1
GAIN
0.1
1
DC NG (V/V)
1.1
0-dB LG (MHz)
PHASE MARGIN (°)
457
380
302
18
41
59
1.94
2
2.85
From these crossover (or 0-dB loop gain) frequencies, a good approximation for the resulting f–3dB is to multiply
the crossover frequencies by 1.6 when the phase margin is less than 65°. Ideally, a 65° phase margin at loop-
gain crossover provides a flat Butterworth closed-loop response. The 59° phase margin for the gain of 2 setting
explains the nearly flat response for this condition with 1.6 × 302 MHz = 483 MHz, estimated with f–3dB closely
matching the measured 500-MHz SSBW.
The very low phase margin in the attenuator setting at 0.1 V/V explains the highly peaked response in Figure 1.
This peaking can be easily compensated, as shown in the Designing Attenuators section, using feedback
capacitors and a differential capacitor across the inputs.
Considering the noise gain zero as part of the loop-gain analysis shows the importance of using relatively-low,
feedback-resistor values and minimizing layout parasitic capacitance on the input pins of the THS4541 to reduce
the effects of this feedback pole. The TINA model does a good job of predicting these issues (the model includes
the 0.85-pF differential internal capacitance); add any estimated external parasitic capacitance on the summing
junctions in simulation to predict the response shape more accurately.
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8.3 I/O Headroom Considerations
The starting point for most designs is usually to assign an output common-mode voltage. For ac-coupled signal
paths, this voltage is often the default midsupply voltage, in order to retain the most available output swing
around the centered Vocm. For dc-coupled designs, set this voltage with consideration for the required minimum
headroom to the supplies shown in the specifications for the Vocm control. From the target output Vocm, the
next step is to verify that the desired output differential VPP stays within the supplies. For any desired differential
Vopp, check that the absolute maximum output pin swings with Equation 2 and Equation 3, and confirm they are
within the supply rails for this rail-to-rail (RR) output device.
Vopp
Vomin Vocm ꢀ
4
(2)
Vopp
4
Vomax Vocm ꢀ
(3)
For instance, driving the ADC3223 with its 0.95 Vcm control using a single 3.3-V supply, the maximum output
swing is set by the negative-going signal from 0.95 Vcm to +0.2 V above ground. This 0.75-V, single-sided swing
becomes an available 4 × 0.75 V = 3 VPP differential around the nominal 0.95 Vcm output common mode. On the
high side, the maximum output is 0.95 + 0.75 = 1.7 V. This result is well within the allowed maximum of 3.3 V –
0.2 V = 3.1 V. This 3 VPP is also well beyond the maximum required 2-VPP full-scale differential input for this
ADC. However, having this extra swing range is useful if an interstage filter to the ADC adds insertion loss.
With the output headrooms confirmed, the input junctions must also stay within their operating range. The input
range extends to the negative supply voltage (over the full temperature range); therefore, input range limitations
usually appear only approaching the positive supply, where a maximum 1.3-V headroom is required over the full
temperature range.
The input pins operate at voltages set by the external circuit design, the required output Vocm, and the input
signal characteristics. For differential-to-differential designs where the input Vicm voltage does not move with the
input signal, there are two configurations to consider:
•
AC-coupled, differential-input designs have a Vicm equal to the output Vocm. The input Vicm requires
approximately a 1.3-V headroom to the positive supply; therefore, the maximum Vocm to that value reduces
from the Vocm positive headroom requirement of 1.2 V to the 1.3 V required on the input pins. The lower limit
on the output Vocm is approximately 0.95 V to the negative supply over the full temperature range, and well
within the 0-V minimum headroom on the input Vicm.
•
DC-coupled, differential-input designs, check the voltage divider from the source Vcm to the THS4541 Vocm
setting to confirm the resulting voltage divider solves to an input Vicm within the allowed range. If the source
Vcm can vary over some voltage range, this result must be validated over that range.
For single-ended input to differential output designs, there is a dc Vicm voltage set by the external configuration
with a small-signal related swing around that. The two conditions to consider are:
•
AC-coupled, single-ended input to differential designs place an average input Vicm equal to the output Vocm
voltage with an ac-coupled swing around that Vocm following the input voltage.
•
DC-coupled, single-ended input to differential designs get a nominal input Vicm set by the source-signal
common mode and the output Vocm setting with a small, signal-related swing around the dc Vicm level set by
the voltage divider.
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I/O Headroom Considerations (continued)
One method of deriving the voltage range for Vicm for any single-ended input to differential output design is to
determine the voltage swing on the nonsignal-input side of the FDA outputs and simply take its divider back to
the input pin to ground or the dc reference used on that side. An example analysis is shown in Figure 68, where
the circuit of Figure 61 is simplified to show just a Thevenized source impedance.
C1
100 nF
Rth
27.3 ꢀ
Rg1
191 ꢀ
Rf1
402 ꢀ
Vocm
Vcc
Vcc
+
+
+
Vcm
2.5 V
Vs1
5 V
Vs
±
±
±
±
+
THS4541
Vocm
FDA
±
+
PD
C2
100 nF
Rg2
221 ꢀ
Vcc
Rf2
402 ꢀ
Figure 68. Input Swing Analysis Circuit from Figure 61 with Thevenized Source
For this ac-coupled input analysis, the nominal dc input Vicm is simply the output Vocm (2.5 V in this example
design). Then, considering the lower side of the feedback networks, any desired maximum output differential VPP
generates a known ac VPP at the junction of Rg2 and Rf2. For instance, if the design intends a maximum 4-VPP
differential output, each FDA output pin is ±1 V around the Vocm (= 2.5 V), and then back to the Vicm, which
produces a ±1 V × 221 / (221 + 402) = ±0.355 V around the dc setting of Vocm. This simple approach to
assessing the input Vicm range for a single-ended to differential design can be applied to any design using an
FDA by reducing the input side circuits to a divider to either the signal source and ground or voltage reference on
the nonsignal input side.
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8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
The THS4541 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to 125°C
operating range. This offset voltage combines with several other error contribution terms to produce an initial
25°C differential offset error band, and then a drift over temperature. For each error term, a gain must be
assigned to that term. For this analysis, only dc-coupled signal paths are considered. One new source of output
error (versus typical op amp analysis) arises from the effect that mismatched resistor values and ratios can have
on the two sides of the FDA. Any common-mode voltage or drift creates a differential output error through the
slight mismatches arising from the external feedback and gain-setting resistor tolerances, and the approximation
(or snap) to standard value.
The error terms (25°C and drift), along with the gain to the output differential voltage, include:
•
Input offset voltage—this voltage has a gain equal to the noise gain or 1 + Rf / Rg, where Rg is the total dc
impedance from the input pins back to the source, or a dc reference (typically ground).
•
Input offset current—this current has a gain to the differential output through the average feedback resistor
value.
The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the
mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias
current creating a differential output offset because of Rf mismatch. For simplicity, the upper Rf and Rg values
are called Rf1 and Rg1 with a ratio of Rf1 / Rg1 ≡ G1. The lower elements are defined as Rf2 and Rg2 with a
ratio of Rf2 / Rg2 ≡ G2. To compute worst-case contributions, a maximum variation in the design resistor
tolerance is used in the absolute and ratio mismatches. For instance, ±1% tolerance resistors are assumed,
giving a worst-case G1 that is 2% higher than nominal and a G2 that is 2% lower than nominal, with a worst-case
Rf value mismatch of 2% as well. For matched impedance designs with Rt and Rg1 on a single-ended to
differential stage, the standard value snap imposes a fixed mismatch in the initial feedback ratios with the resistor
tolerance adding a mismatch to this initial ratio mismatch. Define the selected external resistor tolerance as ±T
(so for 1% tolerance resistors, T = 0.01).
•
Total gain for bias current error is ±2 × T × Rfnom
Anything that generates an output common-mode level or shift over temperature also generates an output
differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in
the output common-mode is overridden by the common-mode control loop, where any feedback ratio mismatch
creates a balanced, differential error around the Vocm output.
The terms that create a differential error from a common-mode term and feedback ratio mismatch include the
desired Vocm voltage, any source common-mode voltage, any drift on the reference bias to the Vocm control
pin, and any internal offset and drift in the Vocm control path.
Considering just the output common-mode control and the source common-mode voltage (Vicm), their
conversion to output differential offsets is done by using Equation 4:
Vocm G1ꢂ G2 ꢂ Vicm G1ꢂ G2
ꢀ
ꢁ
ꢀ
ꢁ
Vod
G1ꢃ G2
1ꢃ
(4)
Neglecting any G1 and G2 mismatch because of standard values snap, the conversion gain for these two terms
can be recast in terms of the nominal Rf / Rg ≡ G, and tolerance T, as shown in Equation 5. As G increases, this
conversion gain approaches 4T, as a worst-case gain for these terms to output differential offset.
Vod
G
4T
(1ꢁ T 2)
Vocm (1ꢀ G)
(5)
28
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Output DC Error and Drift Calculations and the Effect of Resistor Imbalances (continued)
This conversion gain to differential output error is applied to two error terms: Vocm, assuming the input control
pin is driven and not floating, and the source Vicm voltage. The source common-mode voltage is assumed to be
0 V in this example. If not, apply this gain to the source common-mode value or range in the intended
application.
As a full example of using these terms to estimate the worst-case output 25°C error band, and then the worst-
case drift (by adding all the error terms together independently), use the gain of 2 V/V configuration of Figure 63
with Rf = 402 Ω, and assume ±1% tolerance on the resistors with the standard values used in Figure 69.
50-ꢀꢀInput-Matched,
Gain of 2 V/V from Rt,
Single-Ended to Differential,
DC-Coupled, Single Supply
THS4541 Wideband,
Fully-Differential Amplifier
Rf1
402 ꢀ
Vcc
Rs
50 ꢀ
Rg1
191 ꢀ
Vcc
Vocm
±
+
R1
500 ꢀ
+
+
+
+
Vcc
5 V
Vocm
2.5 V
Vocm
FDA
Rt
60.2 ꢀ
VM1
Vs
±
±
±
±
±
+
PD
Rg2
221 ꢀ
Vcc
Rf2
402 ꢀ
Figure 69. DC-Coupled Gain of 2 with Rf = 402 Ω and a Single-Ended to Differential Matched Input 50-Ω
Impedance
The standard value snap on the signal-input side actually produces added G mismatch along with the resistor
tolerances. For Figure 69, G2 = 402 / 221 = 1.819; and G1 = 402 / 218.3 = 1.837 nominally, with a ±2%
tolerance around this initial mismatch for G2 and G1, if 1% resistors are used.
Using the maximum 25°C error terms, and a nominal 2.5-V input to the Vocm control pin, gives Table 3 with the
error terms, the gains to the output differential error (Vod), and then the summed output error band at 25°C.
Table 3. Worst-Case Output Vod Error Band
ERROR TERM
25°C MAXIMUM VALUE
GAIN TO Vod
2.85 V/V
402 Ω
OUTPUT ERROR
±1.2825 mV
±0.201 mV
Input Vio
Input Ios
±0.45 mV
±0.5 µA
13 µA
Input Ibcm, Rf mismatch
Vocm input, G mismatch
±8.04 Ω
±0.105 mV
2.5 V
±0.0322
±80.5 mV
Total
±82.09 mV
The 0.03222 conversion gain for the G ratio mismatch is the worst case, starting from the initially higher G1 value
because of standard value snap, and using a ±1% tolerance on the Rf and Rg elements of that ratio. The actual
Vocm conversion gain range is not symmetric, but is shown that way here. The initial 25°C worst-case error band
is dominated by the Vocm conversion to Vod through the feedback resistor ratio mismatch. Improve this G match
and tolerances to reduce this term.
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Normally, the expected drift in the output Vod is of more interest than an initial error band. Table 4 shows these
terms and the summed results, adding all the terms independently to obtain a worst-case drift.
Table 4. Worst-Case Output Vod Drift Band
ERROR TERM
DRIFT MAXIMUM VALUE
±2.4 µV/°C
GAIN TO Vod
2.85 V/V
402 Ω
OUTPUT ERROR
±6.84 µV/°C
Input Vio
Input Ios
±1.3 nA/°C
±0.522 µV/°C
±0.121 µV/°C
±0.386 µV/°C
±7.86 µV/°C
Input Ibcm, Rf mismatch
Vocm input, G mismatch
15 nA/°C
±8.04 Ω
±12 µV/°C
±0.0322
Total
In this calculation, the input offset voltage drift dominates the output differential offset drift. For the last term, the
drift for the Vocm path is just for the internal offset drift of the common-mode path. Make sure to also consider
the added external drift on the source of the Vocm input.
The absolute accuracy and drift for the THS4541 are exceptionally good. Mismatched resistor feedback ratios
combined with a high drift in the Vocm control input can actually dominate the output Vod drift. Where the output
differential precision is more important than the input matching accuracy, consider matching the networks on the
two input sides to achieve improved nominal G1 to G2 match. The gains for the input bias current error terms are
relatively low in this example design using 402-Ω feedback values. Higher Rf values give these terms more gain.
A less conservative estimate of output drift considers the terms to be uncorrelated and RMS half of each terms
worst-case span shown in Table 4. Performing this calculation for this example estimates a less conservative
output offset drift of ±3.42 µV/°C; essentially, half the worst-case span of the input offset drift term. Follow these
steps to estimate the output differential offset and drift for any external configuration.
8.5 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to its simplest form with equal
feedback and gain setting elements to ground, as shown in Figure 70, with the FDA and resistor noise terms to
be considered.
2
2
enRg
enRf
Rf
Rg
2
In+
+
2
eno
±
2
In±
2
eni
2
2
enRg
enRf
Rg
Rf
Figure 70. FDA Noise-Analysis Circuit
The noise powers are shown for each term. When the Rf and Rg terms are matched on each side, the total
differential output noise is the RSS of these separate terms. Using NG ≡ 1 + Rf / Rg, the total output noise is
given by Equation 6. Each resistor noise term is a 4kTR power.
2
2
eno
e NG ꢂ 2 i Rf ꢂ 2 4kTRfNG
ꢀ n ꢁ
ꢀ
ꢁ
ꢁ
ꢀ
ni
(6)
30
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Noise Analysis (continued)
The first term is simply the differential input spot noise times the noise gain. The second term is the input current
noise terms times the feedback resistor (and because there are two terms, the power is two times one of the
terms). The last term is the output noise resulting from both the Rf and Rg resistors, again times two, for the
output noise power of each side added together. Using the exact values for a 50-Ω, matched, single-ended to
differential gain, sweep with a fixed Rf = 402 Ω (see Table 6) and the intrinsic noise eni = 2.2 nV and In = 1.9 pA
for the THS4541, gives an output spot noise from Equation 6. Then, dividing by the signal gain (Av) gives the
input-referred, spot-noise voltage (ei) shown in Table 5.
Table 5. Swept Gain Output and Input-Referred, Spot-Noise Calculations(1)
Av
1
Rt, EXACT (Ω)
55.2
Rg1, EXACT (Ω)
399
Rg2, EXACT (Ω)
425
NOISE GAIN
1.94
eno (nV/√Hz)
6.64
ei (nV/√Hz)
6.64
2
60.1
191
218
2.85
8.71
4.36
3
65.6
124
153
3.63
10.7
3.56
4
72.0
89.7
119
4.37
12.1
3.03
5
79.7
67.8
98.3
5.09
13.7
2.74
6
89.1
54.2
86.5
5.65
15.4
2.56
7
101
43.2
76.6
6.25
16.7
2.39
8
117
35.2
70.1
6.74
17.3
2.16
9
138
29.0
65.8
7.11
18.6
2.06
10
11
12
13
14
170
23.6
62.5
7.44
18.9
1.89
220
18.7
59.3
7.78
19.6
1.78
313
14.6
57.7
7.97
20.0
1.66
545
10.8
56.6
8.11
20.3
1.56
2209
7.26
56.1
8.16
21.1
1.50
(1) Rf = 402 Ω.
Notice that the input-referred ei is less than 2.2 nV/√Hz for just the THS4541 above a gain of 7 V/V. This result is
because NG is less than Av when the source impedance is included in the NG calculation.
8.6 Factors Influencing Harmonic Distortion
As shown in the swept frequency harmonic distortion plots, the THS4541 provides extremely low distortion at
lower frequencies. In general, FDA output harmonic distortion mainly relates to the open-loop linearity in the
output stage corrected by the loop gain at the fundamental frequency. As the total load impedance decreases
(including the effect of the feedback resistor elements in parallel for loading purposes), the output-stage, open-
loop linearity degrades, increasing the harmonic distortion, as illustrated in Figure 16 and Figure 34. As the
output voltage swings increase, very fine-scale, open-loop, output-stage nonlinearities increase, also degrading
the harmonic distortion, as illustrated in Figure 14 and Figure 32. Conversely, decreasing the target output
voltage swings drops the distortion terms rapidly. For harmonic-distortion testing, 2 VPP is used as a nominal
swing because this value represents a typical ADC, full-scale, differential input range.
Increasing the gain acts to decrease the loop gain, resulting in the increasing harmonic distortion terms, as
illustrated in Figure 18 and Figure 36. One advantage to the capacitive compensation for the attenuator design
(described in the Designing Attenuators typical application example) is that the noise gain is shaped up with
frequency to achieve a crossover at an acceptable phase margin at higher frequencies. This compensation holds
the loop gain high at frequencies lower than the noise-gain zero, improving distortion in these lower bands.
Anything that moves the output pin voltage swings close to clipping into the supplies rapidly degrades harmonic
distortion. Output clipping can occur from either absolute differential swing, or the swing can be moved closer to
the supplies with the common-mode control. This effect is illustrated in Figure 17 and Figure 35.
The THS4541 does an exceptional job of converting from single-ended inputs to differential outputs with very low
harmonic distortions. External resistors of 1% tolerance are used in characterization with good results.
Imbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert
common-mode inputs to differential mode at the outputs with the gain described in the Output DC Error and Drift
Calculations and the Effect of Resistor Imbalances section.
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8.7 Driving Capacitive Loads
A very common requirement is driving the capacitive load of an ADC or some other next stage device. Directly
driving a capacitive load with a closed-loop amplifier such as the THS4541 can lead to an unstable response, as
shown in the step response plots into a capacitive load (see Figure 8 and Figure 26). One typical remedy for this
instability is to add two small series resistors (Ro in Figure 71) at the outputs of the THS4541. Figure 6 and
Figure 24 provide parametric plots of recommended Ro values versus differential capacitive load values and
gain.
THS4541 Wideband,
Fully-Differential Amplifier
50-ꢀꢀInput Match,
Gain of 2 V/V from Rt,
Single-Ended Source to
Differential Output
Rf1
402 ꢀ
Vcc
Rg1
Ro1
191 ꢀ
17 ꢀ
50-ꢀꢀ
Source
±
Output
Measurement
Point
+
Rload
500 ꢀ
Cload
22 pF
Ro2
17 ꢀ
Rt
Vocm
FDA
±
60.2 ꢀ
+
PD
Rg2
Vcc
191 ꢀ
Rf2
402 ꢀ
Figure 71. Including Ro when Driving Capacitive Loads
Operating at higher gains requires lower Ro values to achieve a ±0.5-dB flat response for the same capacitive
load. Some direct parasitic loading is acceptable with no series Ro that increases with gain setting, as illustrated
in Figure 6 and Figure 24 where the Ro value is 0 Ω. Even when these plots suggest no series Ro is required,
good practice is to include a place for the Ro elements in the board layout (0-Ω load initially) for later adjustment,
in case the response appears unacceptable. The TINA simulation model does a good job of predicting this effect
and showing the impact for different choices of capacitive load isolating resistors (Ro).
8.8 Thermal Analysis
The relatively low internal quiescent power dissipation for the THS4541, combined with the excellent thermal
impedance of the 16-pin VQFN package (RGT), limits the possibility of excessively-high, internal-junction
temperatures. Because the 10-pin WQFN (RUN) package has a much higher junction-to-ambient thermal
impedance (θJA = 146°C/W), a more detailed analysis may be warranted.
To estimate the internal junction temperature (TJ), an estimate of the maximum internal power dissipation (PD) is
first required. There are two pieces to the internal power dissipation: quiescent current power and the power
used in the output stage to deliver load current. To simplify the latter, the worst-case, output-stage power is
driving a dc differential voltage across a load using half the total supply voltage. As an example:
1. Assume a worst-case, 5% high 5-V supply. This 5.25-V supply with a maximum ICC of 11 mA gives a
quiescent power term = 58 mW.
2. Assume a 100-Ω differential load with a static 2.5-V differential voltage established across it. This 25 mA of
dc load current generates a maximum output stage power of (5.25 V – 2.5 V) × 25 mA = 69 mW.
3. From this total worst-case internal PD = 127 mW, multiply times the 146°C/W thermal impedance for the
very-small, 10-pin WQFN package to get a 19°C rise from ambient.
Even for this extreme condition and the maximum rated ambient temperature of 125°C, the junction temperature
is a maximum 144°C (less than than the rated absolute maximum of 150°C). Follow this same calculation
sequence for the exact application and package selected to predict the maximum TJ.
32
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9 Detailed Description
9.1 Overview
The THS4541 is a voltage-feedback (VFA) based, fully-differential amplifier (FDA) offering greater than 500-MHz,
small-signal bandwidth at a gain of 2 V/V with trimmed supply current and input offset voltage. The core
differential amplifier is a slightly decompensated voltage-feedback design with a high slew-rate, precision input
stage. This design gives the 500-MHz gain of 2-V/V small-signal bandwidth shown in the characterization curves,
with a 1500-V/µs slew rate, yielding approximately a 340-MHz, 2-VPP, large-signal bandwidth in the same circuit
configuration.
The outputs offer near rail-to-rail output swing (0.2-V headroom to either supply), while the device inputs are
negative rail inputs with approximately 1.2 V of headroom required to the positive supply. This negative rail input
directly supports a bipolar input around ground in a dc-coupled, single-supply design (see Figure 63). Similar to
all FDA devices, the output average voltage (common-mode) is controlled by a separate common-mode loop.
The target for this output average is set by the Vocm input pin that can be either floated to default near
midsupply or driven to a desired output common-mode voltage. The Vocm range extends from a very low 0.91 V
above the negative supply to 1.1 V below the positive supply, supporting a wide range of modern analog-to-
digital converter (ADC) input common-mode requirements using a single 2.7-V to 5.4-V supply range for the
THS4541.
A power-down pin (PD) is included. Pull the PD pin voltage to the negative supply to turn the device off, putting
the THS4541 into a very-low quiescent current state. For normal operation, the PD pin must be asserted high.
When the device is disabled, remember that the signal path is still present through the passive external resistors.
Input signals applied to a disabled THS4541 still appear at the outputs at some level through this passive resistor
path as they would for any disabled FDA device.
9.1.1 Terminology and Application Assumptions
Like all widely-used devices, numerous common terms have developed that are unique to this type of device.
These terms include:
•
Fully differential amplifier (FDA)—In this document, this term is restricted to devices offering what appears
similar to a differential inverting op amp design element that requires an input resistor (not high-impedance
input) and includes a second internal control-loop setting the output average voltage (Vocm) to a default or
set point. This second loop interacts with the differential loop in some configurations.
•
•
The desired output signal at the two output pins is a differential signal swinging symmetrically around a
common-mode voltage where that is the average voltage for the two outputs.
Single-ended to differential—always use the outputs differentially in an FDA; however, the source signal can
be either a single-ended source or differential, with a variety of implementation details for either. When the
FDA operation is single-ended to differential, only one of the two input resistors receives the source signal
with the other input resistor connected to a dc reference (often ground) or through a capacitor to ground.
To simplify, several features in the application of the THS4541 are not explicitly stated, but are necessary for
correct operation. These requirements include:
•
Good power-supply decoupling is required. Minimize the distance (< 0.1") from the power-supply pins to high-
frequency, 0.1-μF decoupling capacitors. Often a larger capacitor (2.2 µF is typical) is used along with a high-
frequency, 0.1-µF supply decoupling capacitor at the device supply pins (share this capacitor for the four
supply pins in the RGT package). For single-supply operation, only the positive supply has these capacitors.
When a split supply is used, use these capacitors for each supply to ground. If necessary, place the larger
capacitors somewhat farther from the device and share these capacitors among several devices in the same
area of the PCB. For each THS4541, attach a separate 0.1-µF capacitor to a nearby ground plane. With
cascaded or multiple parallel channels, including ferrite beads from the larger capacitor is often useful to the
local high-frequency decoupling capacitor.
•
Minimize the distance (< 0.1") from the power-supply pins to high-frequency, 0.1-μF decoupling capacitors. At
the device pins, the ground and power plane layout should not be in close proximity to the signal I/O pins.
Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling
capacitors. The power-supply connections (on pins 4 and 7) should always be decoupled with these
capacitors. An optional supply decoupling capacitor across the two power supplies (for bipolar operation)
improves 2nd-harmonic distortion performance. Larger (2.2μF to 6.8μF) decoupling capacitors, effective at
lower frequency, should also be used on the main supply pins. These can be placed somewhat farther from
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Overview (continued)
the device and may be shared among several devices in the same area of the PCB.
•
•
Although not always stated, make sure to tie the power disable pin to the positive supply when only an
enabled channel is desired.
Virtually all ac characterization equipment expects a 50-Ω termination from the 50-Ω source, and a 50-Ω
single-ended source impedance from the device outputs to the 50-Ω sensing termination. This termination is
achieved in all characterizations (often with some insertion loss), but is not necessary for most applications.
Matching impedance is most often required when transmitting over longer distances. Tight layouts from a
source, through the THS4541, and on to an ADC input do not require doubly-terminated lines or filter designs;
the exception is if the source requires a defined termination impedance for correct operation (for example, a
SAW filter source).
•
•
The amplifier signal path is flexible for single or split-supply operation. Most applications are intended to be
single supply, but any split-supply design can be used, as long as the total supply across the TH4541 is less
than 5.5 V and the required input, output, and common-mode pin headrooms to each supply are observed.
Left open, the Vocm pin defaults to near midsupply for any combination of split or single supplies used. The
disable pin is negative-rail referenced. Using a negative supply requires the disable pin to be pulled down to
within 0.7 V of the negative supply to disable the amplifier.
External element values are normally assumed to be accurate and matched. In an FDA, match the feedback
resistor values and also match the (dc and ac) impedance from the summing junctions to the source on one
side and the reference or ground on the other side. Unbalancing these values introduces nonidealities in the
signal path. For the signal path, imbalanced resistor ratios on the two sides create a common-mode to
differential conversion. Also, mismatched Rf values and feedback ratios create some added differential output
error terms from any common-mode dc, ac signal, or noise terms. Snapping to standard 1% resistor values is
a typical approach and generally leads to some nominal feedback ratio mismatch. Mismatched resistors or
ratios do not in themselves degrade harmonic distortion. If there is meaningful CM noise or distortion coming
in, those errors are converted to a differential error through element or ratio mismatch.
9.2 Functional Block Diagram
Vs+
(RGT Package) FB+
OUT+
±
IN±
2.5 kꢀ
2.5 kꢀ
High-Aol
Differential I/O
Amplifier
+
±
IN+
+
OUT±
(RGT Package) FB±
Vs+
100 kꢀ
±
Vcm
Error
Amplifier
+
Vocm
CMOS
Buffer
PD
100 kꢀ
Vs±
34
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9.3 Feature Description
9.3.1 Differential I/O
The THS4541 combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage with a dominant pole at
approximately 900 Hz. This voltage feedback structure projects a single-pole, unity-gain Aol at 850 MHz (gain
bandwidth product). The high-speed differential outputs include an internal averaging resistor network to sense
the output common-mode voltage. This voltage is compared by a separate Vcm error amplifier to the voltage on
the Vocm pin. If floated, this reference is at half the total supply voltage across the device using two 100-kΩ
resistors. This Vcm error amplifier transmits a correction signal into the main amplifier to force the output average
voltage to meet the target voltage on the Vocm pin. The bandwidth of this error amplifier is approximately the
same bandwidth as the main differential I/O amplifier.
The differential outputs are collector outputs to obtain the rail-to-rail output swing. These outputs are relatively
high-impedance, open-loop sources; however, closing the loop provides a very low output impedance for load
driving. No output current limit or thermal shutdown features are provided in this lower-power device. The
differential inputs are PNP inputs to provide a negative-rail input range.
To operate the THS4541 for the RGT package, connect external resistors from the FB– pin to the IN+ pins, and
the FB+ pin to the IN– pins. For the RUN package, connect the OUT– pin to the IN+ pin through an Rf, and the
OUT+ pin to the IN– pin through the same value of Rf. Bring in the inputs through additional resistors to the IN+
and IN– pins. The differential I/O op amp operates similarly to an inverting op amp structure where the source
must drive the input resistor and the gain is the ratio of the feedback to the input resistor.
9.3.2 Power-Down Control Pin (PD)
The THS4541 includes a power-down control pin, PD. This pin must be asserted high for correct amplifier
operation. The PD pin cannot be floated because there is no internal pullup or pulldown resistor on this pin to
reduce disabled power consumption. Asserting this pin low (within 0.7 V of the negative supply) puts the
THS4541 into a very low quiescent state (approximately 2 µA). Switches in the default Vocm resistor string open
to eliminate the fixed bias current (25 µA) across the supply in this 200-kΩ voltage divider to midsupply.
9.3.2.1 Operating the Power Shutdown Feature
Assert this CMOS input pin to the desired voltage for operation. For applications that require the device to only
be powered on when the supplies are present, tie the PD pin to the positive supply voltage.
When the PD pin is somewhat below the positive supply pin, slightly more quiescent current is drawn; see
Figure 56. For the minimum-on power, assert this pin to the positive supply.
The disable operation is referenced from the negative supply; normally, ground. For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the THS4541 off
when the negative supply exceeds –0.7 V.
For single-supply operation, a minimum of 1.7 V above the negative supply (ground, in this case) is required to
assure operation. This minimum logic-high level allows for direct operation from 1.8-V supply logic.
9.3.3 Input Overdrive Operation
The THS4541 input stage architecture is intrinsically robust to input overdrives with the series input resistor
required by all applications. High input overdrives cause the outputs to limit into their maximum swings with the
remaining input current through the Rg resistors absorbed by internal, back-to-back protection diodes across the
two inputs. These diodes are normally off in application, and only turn on to absorb the currents that a large input
overdrive might produce through the source impedance and or the series Rg elements required by all designs.
Figure 12 and Figure 30 illustrate the exceptional output limiting and short recovery time for an input overdrive
that is attempting to drive the outputs to two times the available swing.
The internal input diodes can safely absorb up to ±15 mA in an overdrive condition. For designs that require
more current to be absorbed, consider adding an external protection diode such as the BAV99 device used in the
example ADC interface design of Figure 80.
Copyright © 2014, Texas Instruments Incorporated
35
THS4541
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www.ti.com.cn
9.4 Device Functional Modes
This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than Vs– + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops correct amplifier operation. The signal path is still present for the source
signal through the external resistors.
The Vocm control pin sets the output average voltage. Left open, Vocm defaults to an internal midsupply value.
Driving this high-impedance input with a voltage reference within its valid range sets a target for the internal Vcm
error amplifier.
9.4.1 Operation from Single-Ended Sources to Differential Outputs
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. While the output side is relatively
straightforward, the device input pins move in a common-mode sense with the input signal. This common-mode
voltage at the input pins moving with the input signal acts to increase the apparent input impedance to be greater
than the Rg value. This input active impedance issue applies to both ac- and dc-coupled designs, and requires
somewhat more complex solutions for the resistors to account for this active impedance, as shown in the
following subsections.
9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
When the signal path can be ac coupled, the dc biasing for the THS4541 becomes a relatively simple task. In all
designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the
input and output sides of an FDA design. The input can be ac coupled and the output dc coupled, or the output
can be ac coupled and the input dc coupled, or they can both be ac coupled. One situation where the output
might be dc coupled (for an ac-coupled input), is when driving directly into an ADC where the Vocm control
voltage uses the ADC common-mode reference to directly bias the FDA output common-mode to the required
ADC input common-mode. In any case, the design starts by setting the desired Vocm. When an ac-coupled path
follows the output pins, the best linearity is achieved by operating Vocm at midsupply. The Vocm voltage must be
within the linear range for the common-mode loop, as specified in the headroom specifications (approximately
0.91 V greater than the negative supply and 1.1 V less than the positive supply). If the output path is also ac
coupled, simply letting the Vocm control pin float is usually preferred in order to get a midsupply default Vocm
bias with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the Vocm pin to ground.
After Vocm is defined, check the target output voltage swing to ensure that the Vocm plus the positive or
negative output swing on each side does not clip into the supplies. If the desired output differential swing is
defined as Vopp, divide by 4 to obtain the ±Vp swing around Vocm at each of the two output pins (each pin
operates 180° out of phase with the other). Check that Vocm ±Vp does not exceed the absolute supply rails for
this rail-to-rail output (RRO) device.
Going to the device input pins side, because both the source and balancing resistor on the nonsignal input side
are dc blocked (see Figure 61), no common-mode current flows from the output common-mode voltage, thus
setting the input common-mode equal to the output common-mode voltage.
This input headroom also sets a limit for higher Vocm voltages. Because the input Vicm is the output Vocm for
ac-coupled sources, the 1.2-V minimum headroom for the input pins to the positive supply overrides the 1.1-V
headroom limit for the output Vocm. Also, the input signal moves this input Vicm around the dc bias point, as
described in the Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA section.
9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
The output considerations remain the same as for the ac-coupled design. Again, the input can be dc coupled
while the output is ac coupled. A dc-coupled input with an ac-coupled output might have some advantages to
move the input Vicm down if the source is ground referenced. When the source is dc coupled into the THS4541
(see Figure 63), both sides of the input circuit must be dc coupled to retain differential balance. Normally, the
nonsignal input side has an Rg element biased to whatever the source midrange is expected to be. Providing this
midscale reference gives a balanced differential swing around Vocm at the outputs. Often, Rg2 is simply
36
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THS4541
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ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
Device Functional Modes (continued)
grounded for dc-coupled, bipolar-input applications. This configuration gives a balanced differential output if the
source is swinging around ground. If the source swings from ground to some positive voltage, grounding Rg2
gives a unipolar output differential swing from both outputs at Vocm (when the input is at ground) to one polarity
of swing. Biasing Rg2 to an expected midpoint for the input signal creates a differential output swing around
Vocm.
One significant consideration for a dc-coupled input is that Vocm sets up a common-mode bias current from the
output back through Rf and Rg to the source on both sides of the feedback. Without input balancing networks,
the source must sink or source this dc current. After the input signal range and biasing on the other Rg element
is set, check that the voltage divider from Vocm to Vin through Rf and Rg (and possibly Rs) establishes an input
Vicm at the device input pins that is in range. If the average source is at ground, the negative rail input stage for
the THS4541 is in range for applications using a single positive supply and a positive output Vocm setting
because this dc current lifts the average FDA input summing junctions up off of ground to a positive voltage (the
average of the V+ and V– input pin voltages on the FDA).
9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
The design equations for setting the resistors around an FDA to convert from a single-ended input signal to
differential output can be approached from several directions. Here, several critical assumptions are made to
simplify the results:
•
•
The feedback resistors are selected first and set equal on the two sides.
The dc and ac impedances from the summing junctions back to the signal source and ground (or a bias
voltage on the nonsignal input side) are set equal to retain feedback divider balance on each side of the FDA
Both of these assumptions are typical and aimed to delivering the best dynamic range through the FDA signal
path.
After the feedback resistor values are chosen, the aim is to solve for the Rt (a termination resistor to ground on
the signal input side), Rg1 (the input gain resistor for the signal path), and Rg2 (the matching gain resistor on the
nonsignal input side); see Figure 61 and Figure 63. The same resistor solutions can be applied to either ac- or
dc-coupled paths. Adding blocking capacitors in the input-signal chain is a simple option. Adding these blocking
capacitors after the Rt element (as shown in Figure 61) has the advantage of removing any dc currents in the
feedback path from the output Vocm to ground.
Earlier approaches to the solutions for Rt and Rg1 (when the input must be matched to a source impedance, Rs)
follow an iterative approach. This complexity arises from the active input impedance at the Rg1 input. When the
FDA is used to convert a single-ended signal to differential, the common-mode input voltage at the FDA inputs
must move with the input signal to generate the inverted output signal as a current in the Rg2 element. A more
recent solution is shown as Equation 7, where a quadratic in Rt can be solved for an exact required value. This
quadratic emerges from the simultaneous solution for a matched input impedance and target gain. The only
inputs required are:
1. The selected Rf value.
2. The target voltage gain (Av) from the input of Rt to the differential output voltage.
3. The desired input impedance at the junction of Rt and Rg1 to match Rs.
Solving this quadratic for Rt starts the solution sequence, as shown in Equation 7.
Rs
2
§
©
·
¹
2Rs 2Rf ꢂ
Av2
2RfRs2Av
¨
¸
Rt2 ꢃ Rt
ꢃ
0
2Rf 2 ꢂ Av ꢃ RsAv(4 ꢂ Av) 2Rf 2 ꢂ Av ꢃ RsAv(4 ꢂ Av)
(7)
Being a quadratic, there are limits to the range of solutions. Specifically, after Rf and Rs are chosen, there is
physically a maximum gain beyond which Equation 7 starts to solve for negative Rt values (if input matching is a
requirement). With Rf selected, use Equation 8 to verify that the maximum gain is greater than the desired gain.
ª
«
º
»
»
»
Rf
4
Rf
Rs
ꢀ 2)2
«
Avmax ꢀ
ꢀ 2ꢁ 1ꢁ 1ꢁ
Rf
Rs
«
(
«
¬
»
¼
Rs
(8)
37
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THS4541
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www.ti.com.cn
Device Functional Modes (continued)
If the achievable Avmax is less than desired, increase the Rf value. After Rt is derived from Equation 7, the Rg1
element is given by Equation 9:
Rf
2
ꢀ Rs
Av
Rg1
Rs
Rt
1ꢁ
(9)
Then, the simplest approach is to use a single Rg2 = Rt || Rs + Rg1 on the nonsignal input side. Often, this
approach is shown as the separate Rg1 and Rs elements. Using these separate elements provides a better
divider match on the two feedback paths, but a single Rg2 is often acceptable. A direct solution for Rg2 is given
as Equation 10:
Rf
2
Av
Rg2
Rs
1ꢀ
Rt
(10)
This design proceeds from a target input impedance matched to Rs, signal gain Av from the matched input to the
differential output voltage, and a selected Rf value. The nominal Rf value chosen for the THS4541
characterization is 402 Ω. As discussed previously, going lower improves noise and phase margin, but reduces
the total output load impedance possibly degrading harmonic distortion. Going higher increases the output noise,
and might reduce the loop-phase margin because of the feedback pole to the input capacitance, but reduces the
total loading on the outputs. Using Equation 8 to Equation 10 to sweep the target gain from 1 to Avmax < 14.3 V/V
gives Table 6, which shows exact values for Rt, Rg1, and Rg2, where a 50-Ω source must be matched while
setting the two feedback resistors to 402 Ω. One possible solution for 1% standard values is shown, and the
resulting actual input impedance and gain with % errors to the targets are also shown in Table 6.
Table 6. Required Resistors for a Single-Ended to Differential FDA Design Stepping Gain from
1 V/V to 14 V/V(1)
Rg1,
EXACT
(Ω)
Rg2,
EXACT
(Ω)
Rt, EXACT
ACTUAL
ZIN
%ERR TO
Rs
ACTUAL
GAIN
%ERR TO
Av
Av
1
(Ω)
Rt 1%
54.9
60.4
64.9
71.5
80.6
88.7
102
Rg1 1%
392
Rg2 1%
422
55.2
60.1
65.6
72.0
79.7
89.1
101
395
193
421
220
49.731
50.171
49.572
49.704
50.451
49.909
50.179
50.246
49.605
50.009
49.815
50.051
49.926
50.079
–0.54%
0.34%
–0.86%
–0.59%
0.90%
–0.18%
0.36%
0.49%
–0.79%
0.02%
–0.37%
0.10%
–0.15%
0.16%
1.006
2.014
2.983
4.005
5.014
6.008
7.029
7.974
9.016
9.961
11.024
11.995
12.967
13.986
0.62%
0.72%
–0.57%
0.14%
0.28%
0.14%
0.42%
–0.32%
0.18%
–0.39%
0.22%
–0.04%
–0.25%
–0.10%
2
191
221
3
123
124
151
150
4
88.9
68.4
53.7
43.5
35.5
28.8
23.5
18.8
14.7
10.9
7.26
88.7
68.1
53.6
43.2
35.7
28.7
23.7
18.7
14.7
11.0
7.32
118
118
5
99.2
85.7
77.1
70.6
65.4
62.0
59.6
57.9
56.7
56.2
100
6
86.6
76.8
69.8
64.9
61.9
59.0
57.6
56.2
56.2
7
8
117
118
9
138
137
10
11
12
13
14
170
169
220
221
313
316
545
549
2209
2210
(1) Rf = 402 Ω, Rs = 50 Ω, and AvMAX = 14.32 V/V.
38
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THS4541
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ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
These equations and design flow apply to any FDA. Using the feedback resistor value as a starting point is
particularly useful for current-feedback-based FDAs such as the LMH6554, where the value of these feedback
resistors determines the frequency response flatness. Similar tables can be built using the equations provided
here for other source impedances, Rf values, and gain ranges.
Note the extremely low Rg1 values at the higher gains. For instance, at a gain of 14 V/V, that 7.32-Ω standard
value is transformed by the action of the common-mode loop moving the input common-mode voltage to appear
like a 50-Ω input match. This active input impedance provides an improved input-referred noise at higher gains;
see the Noise Analysis section. The TINA model correctly shows this actively-set input impedance in the single-
ended to differential configuration, and is a good tool to validate the gains, input impedances, response shapes,
and noise issues.
9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
The designs so far have included a source impedance, Rs, that must be matched by Rt and Rg1. The total
impedance at the junction of Rt and Rg1 for the circuit of Figure 63 is the parallel combination of Rt to ground,
and the ZA (active impedance) presented by Rg1. The expression for ZA, assuming Rg2 is set to obtain the
differential divider balance, is given by Equation 11:
§
¨
©
·§
¸¨
¹©
·
¸
¹
Rg1
Rg2
Rf
1ꢀ
1ꢀ
Rg1
ZA Rg1
Rf
2 ꢀ
Rg2
(11)
For designs that do not need impedance matching, but instead come from the low impedance output of another
amplifier for instance, Rg1 = Rg2 is the single-to-differential design used without an Rt to ground. Setting Rg1 =
Rg2 = Rg in Equation 11 gives the input impedance of a simple input FDA driving from a low-impedance, single-
ended source to a differential output as shown in Equation 12:
Rf
1ꢀ
Rg
ZA 2Rg
Rf
2 ꢀ
Rg
(12)
In this case, setting a target gain as Rf / Rg ≡ α, and then setting the desired input impedance, allows the Rg
element to be resolved first, and then the required Rf to get the gain. For example, targeting an input impedance
of 200 Ω with a gain of 4 V/V, Equation 13 gives the physical Rg element. Multiplying this required Rg value by a
gain of 4 gives the Rf value and the design of Figure 72.
2 ꢂ
2 1ꢂ
D
D
Rg ZA
(13)
THS4541 Wideband,
Fully-Differential Amplifier
Rf1
480 ꢀ
200-ꢀꢀInput Impedance,
Gain of 4 V/V Design
Vcc
Rg1
120 ꢀ
±
Output
Measurement
Point
+
R1
500 ꢀ
+
Vocm
FDA
Vs
±
±
+
PD
Rg2
Vcc
120 ꢀ
Rf2
480 ꢀ
Figure 72. 200-Ω Input Impedance, Single-Ended to Differential DC-Coupled Design with Gain of 4 V/V
Copyright © 2014, Texas Instruments Incorporated
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THS4541
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www.ti.com.cn
After being designed, this circuit can also be ac coupled by adding blocking caps in series with the two 120-Ω Rg
resistors. This active input impedance has the advantage of increasing the apparent load to the prior stage using
lower resistors values, leading to lower output noise for a given gain target.
9.4.2 Differential-Input to Differential-Output Operation
In many ways, this method is a much simpler way to operate the FDA from a design equations perspective.
Again, assuming the two sides of the circuit are balanced with equal Rf and Rg elements, the differential input
impedance is now just the sum of the two Rg elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal, but must be
dc biased in the allowable range for the input pins with consideration given to the voltage headroom required
from each supply. Slightly different considerations apply to ac- or dc-coupled, differential-in to differential-out
designs, as described in the following sections.
9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
There are two typical ways to use the THS4541 with an ac-coupled differential source. In the first method, the
source is differential and can be coupled in through two blocking capacitors. The second method uses either a
single-ended or a differential source and couples in through a transformer (or balun). Figure 73 shows a typical
blocking capacitor approach to a differential input. An optional input differential termination resistor (Rm) is
included in this design. This Rm element allows the input Rg resistors to be scaled up while still delivering lower
differential input impedance to the source. In this example, the Rg elements sum to show a 200-Ω differential
impedance, while the Rm element combines in parallel to give a net 100-Ω, ac-coupled, differential impedance to
the source. Again, the design proceeds ideally by selecting the Rf element values, then the Rg to set the
differential gain, then an Rm element (if needed) to achieve a target input impedance. Alternatively, the Rm
element can be eliminated, the Rg elements set to the desired input impedance, and Rf set to the get the
differential gain (= Rf / Rg).
THS4541 Wideband,
Fully-Differential Amplifier
Rf1
402 ꢀ
C1
100 nF
Vcc
Rg1
100 ꢀ
±
Output
Measurement
Point
+
R1
500 ꢀ
Vocm
FDA
±
Downconverter
Differential
Output
Rm
200 ꢀ
Rg2
100 ꢀ
+
PD
C2
100 nF
Vcc
Rf2
402 ꢀ
Figure 73. Example Down-Converting Mixer Delivering an AC-Coupled Differential Signal to the THS4541
The dc biasing here is very simple. The output Vocm is set by the input control voltage and, because there is no
dc current path for the output common-mode voltage, that dc bias also sets the input pins common-mode
operating points.
40
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THS4541
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Transformer input coupling allows either a single-ended or differential source to be coupled into the THS4541;
possibly also improving the input-referred noise figure. These designs assume a source impedance that must be
matched in the balun interface. The simplest approach is shown in Figure 74, where an example 1:2 turns ratio
step-up transformer is used from a 50-Ω source.
THS4541 Wideband,
Fully-Differential Amplifier
Rf1
402 ꢀ
Pulse
CX2047LNL
1:2 Turns Ratio
Vcc
Balun
Rg1
100 ꢀ
C1
100 nF
Rs
50 ꢀ
M1
90.4 ꢁH
±
Output
Measurement
Point
+
R1
500 ꢀ
Vocm
FDA
±
+
+
PD
VG1
N1
N2
±
Rg2
Vcc
100 ꢀ
Rf2
402 ꢀ
Figure 74. Input Balun Interface Delivers a Differential Input to the THS4541
In this example, this 1:2 turns ratio step-up transformer provides a source and load match from the 50-Ω source
if the secondary is terminated in 200 Ω (turns-ratio squared is the impedance ratio across a balun). The two Rg
elements provide that termination as they sum to the differential virtual ground at the FDA summing junctions.
The input blocking cap (C1) is optional and included only to eliminate dc shorts to ground from the source. This
solution often improves the input-referred noise figure more so than just the FDA using this passive (zero power
dissipation) input balun. Defining a few ratios allows a noise figure expression to be written as Equation 14:
2
2
§
¨
¨
·
¸
¸
¸
¸
n i Rs
§
¨
©
·
¸
¹
ꢀ
ꢁ
eni
1
2
1
1
2
§
·
¹
n
ꢂ
ꢂ
¨
©
¸
(1ꢂ E2
)
8
DE2
4
E2
E
n
D
NF 10 Log 1ꢂ
ꢂ
ꢂ
ꢂ
2
¨
E2
(
DE)
kTRs
¨
¨
¸
©
¹
where
•
•
•
•
n ≡ turns ratio (the ohms ratio is then n2)
α ≡ differential gain in the FDA = Rf / Rg
β ≡ transformer insertion loss in V/V (from a dB insertion loss, convert to linear attenuation = β)
kT = 4e-21J at 290 K (17°C)
(14)
One way to use Equation 14 is to fix the input balun selection, and then sweep the FDA gain by stepping up the
Rf value. The lowest-noise method uses just the two Rg elements for termination matching (no Rm element,
such as in Figure 74) and sweep the Rf values up to assess the resulting input-referred noise figure. While this
method can be used with all FDAs and a wide range of input baluns, relatively low-frequency input baluns are an
appropriate choice here because the THS4541 holds exceptional SFDR for less than 40-MHz applications. Two
representative selections, with their typical measured spans and resulting model elements, are shown in Table 7.
For these two selections, the critical inputs for the noise figures are the turns ratio and the insertion loss (the 0.2
dB for the CX2014LNL becomes a β = 0.977 in the NF expression).
Table 7. Example Input Step-Up Baluns and Associated Parameters
–1-dB
FREQUENCY
(MHz)
–3-dB
FREQUENCY
(MHz)
NO. OF DECADES
–1-dB –3-dB
MODEL ELEMENTS
PART
INSERTION
LOSS (dB)
TURNS
RATIO
NUMBER
Rs (Ω)
50
MIN
0.1
MAX
463
MFR
POINTS POINTS
MIN
0.05
MAX
825
L1 (µH)
L2 (µH)
k
M (µH)
ADT2-1T
0.3
0.2
MiniCircuits
Pulse Eng
3.67
3.51
4.22
3.93
1.41
2
79.57747 158.50797
90.42894 361.71578
0.99988
0.99976
112.19064
180.81512
CX2047LNL
50
0.083
270
0.044
372
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Using the typical input referred noise terms for the THS4541 (eni = 2.2 nV and in = 1.9 pA) and sweeping the total
gain from the input of the balun to the differential output over a 10-dB to 24-dB span, gives the input noise figure
shown in Figure 75.
14
ADT2-1T
CX2047LNL
13
12
11
10
9
8
7
10
12
14
16
18
20
22
24
Total Gain (dB)
D061
Figure 75. Noise Figure versus Total Gain with the Two Input Baluns of Table 7
The 50-Ω referred noise figure estimates show a decreasing input-referred noise for either balun as the gain
increases through 24 dB. The only elements changing in these sweeps are the feedback-resistor values, in order
to achieve the total target gain after the step up from the input balun. The example of Figure 74 is a gain of
7.86 V/V, or a 17.9-dB gain where a 9.0-dB input noise figure is predicted from Figure 75. Another advantage for
this method is that the effective noise gain (NG) is reduced by the source impedance appearing as part of the
total Rg element in the design. The example of Figure 74 operates with a NG = 1 + 402 / (100 + 100) = 3 V/V,
giving greater than 300-MHz SSBW in the THS4541 portion of the design. Combining that with the 372 MHz in
the balun itself gives greater than 200 MHz in this 18-dB gain stage; or an equivalent greater than 1.6-GHz gain
bandwidth product in a low-power, high dynamic range interface.
Added features and considerations for the balun input of Figure 74 include:
•
Many of these baluns offer a secondary centertap. Leave the centertap unconnected for the best HD2
suppression and dc biasing (do not include a capacitor from this centertap to ground).
•
With a floating secondary centertap, the input pins common-mode voltage again equals the output Vocm
setting because there is no dc path for the output common-mode voltage to create a common-mode current
(ICM).
42
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the THS4541 with a dc-coupled differential input source is very simple and only requires that the input
pins stay in range of the dc common-mode operating voltage. One example is a dc-to-50-MHz quadrature down-
converter output. These outputs typically sit on a dc level with some internal source impedance to the external
loads. The example of Figure 76 shows a design using the THS4541 with a simple, passive RLC filter to the
inputs (the Rg elements act as the differential termination for the filter design). From the original source behind
the internal 250-Ω outputs, this circuit is a gain of 1 to the THS4541 output pins. The dc common-mode operating
voltage level shifts from the 1.2-V internal, to the mixer, to an output at the ADC Vcm voltage of 0.95 V. In this
case, a simple average of the two dc voltages in the gain of 1 stage gives a 1.08-V input pin common-mode
result that is well within range.
THS4541 Wideband,
Fully-Differential Amplifier
Quadrature Downconverter
Third-Order
DC Bias and
Rf1
499 ꢀ
50-MHz, 0.2-dB Ripple,
Chebychev, DC-Coupled
Low-Pass Filter
Output Impedance
100-MHz,
Single-RC
Pole
Vcc
R2
250 ꢀ
Rg1
250 ꢀ
R1
22 ꢀ
L1
920 nH
VG1
Low-Power
±
ADC3224
+
C3
30 pF
Vocm
R4
22 ꢀ
12-Bit, Dual,
125-MSPS
FDA
±
C1
C2
7.5 pF
Rg2
250 ꢀ
+
PD
ADC
7.5 pF
R3
250 ꢀ
Vcc
L2
920 nH
VG2
Rf2
499 ꢀ
+
VS2
1.2 V
ADC Vcm
0.95-V Output
±
Figure 76. Example DC-Coupled, Differential I/O Design from a Quadrature Mixer to an ADC
Copyright © 2014, Texas Instruments Incorporated
43
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
10 Application And Implementation
10.1 Application Information
The THS4541 offers an effective solution over a broad range of applications. Two examples are developed here.
First, an attenuator stage that directly receives a higher input signal voltage and translates it to a lower
differential swing on a fixed common-mode is shown. This design requires some attention to frequency-response
flatness issues, and one approach to managing these issues is shown. The second example is a gain of 2 V/V,
matched input of 50 Ω to an output set to 0.95 V common-mode followed by a third-order Bessel filter with
approximately 20 MHz of bandwidth feeding into the ADC34J22, a low-power, 12-bit, quad 50-MSPS JESD 204B
ADC.
10.2 Typical Applications
10.2.1 Designing Attenuators
THS4541 Wideband,
Fully-Differential Amplifier
Gain of 0.1 V/V from Rg1,
Single-Ended to Differential,
DC-Coupled, Single Supply
Rf1
402 ꢀ
Vcc
Rg1
4.02 kꢀ
Vcc
Vcm
±
+
R1
500 ꢀ
+
+
+
+
Vcc
5 V
Vcm
2.5 V
Vocm
FDA
VM1
VG1
±
±
±
±
±
+
PD
Rg2
4.02 kꢀ
Vcc
Rf2
402 ꢀ
Figure 77. Divide-by-10 Attenuator Application for the THS4541
10.2.1.1 Design Requirements
In this design, the aim is to:
1. Present a 4-kΩ input impedance to a ±40-V input signal (maximum ±10 mA from the prior stage).
2. Attenuate that swing by a factor 1/10 (–20 dB) to a differential output swing.
3. Place that swing on a 2.5-V common-mode voltage at the THS4541 outputs.
4. Operate on a single +5-V supply and ground.
5. Tune the frequency response to a flat Butterworth response with external capacitors.
10.2.1.2 Detailed Design Procedure
Operating the THS4541 at a low dc noise gain, or with higher feedback resistors, can cause a lower phase
margin to exist, giving the response peaking shown in Figure 1 for the gain of 0.1 (a 1/10 attenuator) condition.
Although it is often useful operating the THS4541 as an attenuator (taking a large input range to a purely
differential signal around a controlled-output, common-mode voltage), the response peaking illustrated in
Figure 1 is usually undesirable. Several methods can be used to reduce or eliminate this peaking; usually, at the
cost of higher output noise. Using dc techniques always increases the output noise broadband, while using an ac
noise-gain-shaping technique peaks the noise, but only at higher frequencies that can then be filtered off with the
typical passive filters often used after this stage. Figure 77 shows a simplified schematic for the gain of 0.1 V/V
test from Figure 61.
44
Copyright © 2014, Texas Instruments Incorporated
THS4541
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ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
Typical Applications (continued)
This configuration shows a nominal 18° phase margin (from Table 2); therefore, a very highly-peaked response is
illustrated in Figure 1. This peaking can be eliminated by placing two feedback capacitors across the Rf elements
and a differential input capacitor. Adding these capacitors provides a transition from a resistively set noise gain
(NG1 here; 1.1 in Table 2) to a capacitive divider at high-frequency flattening out to a higher noise gain (NG2
here). The key for this approach is to target a Zo, where the noise gain begins to peak up. Using only the
following terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence for Zo and
then the capacitor values.
1. Gain bandwidth product in Hz (850 MHz for the THS4541)
2. Low frequency noise gain, NG1 ( = 1.1 in the attenuator gain of 0.1 V/V design)
3. Target high-frequency noise gain selected to be higher than NG1 (NG2 = 3.1 V/V is selected for this design)
4. Feedback resistor value, Rf (assumed balanced for this differential design = 402 Ω for this design example)
From these elements, for any decompensated voltage-feedback op amp or FDA, solve for Zo (in Hz) using
Equation 15:
§
·
GBP
NG1
NG2
NG1
NG2
Zo
1ꢀ
ꢀ 1ꢀ 2
¨
¨
¸
¸
2
NG1
©
¹
(15)
From this target zero frequency in the noise gain, solve for the feedback capacitors using Equation 16:
1
Cf
2S Rf Zo NG2
(16)
The next step is to resolve the input capacitance on the summing junction. Equation 17 is for a single-ended op
amp (for example, OPA847) where that capacitor goes to ground. To use Equation 17 for a voltage-feedback
FDA, cut the target value in half, and place the result across the two inputs (reducing the external value by the
specified internal differential capacitance).
Cs NG2 ꢂ 1 Cf
(17)
Setting the external compensation elements using Equation 15 to Equation 17 allows an estimate of the resulting
flat bandwidth f–3dB frequency, as shown in Equation 18:
fꢀ3dB
| GBP Zo
(18)
Running through these steps for the THS4541 in the attenuator circuit of Figure 77 gives the proposed
compensation of Figure 78 where Equation 18 estimates a bandwidth of 252 MHz (Zo target is 74.7 MHz).
C1
1.7 pF
THS4541 Wideband,
Fully-Differential Amplifier
Gain of 0.1 V/V from Rg1,
Single-Ended to Differential,
DC-Coupled, Single Supply
Rf1
402 ꢀ
Vcc
Rg1
4.02 kꢀ
Vcc
Vcm
±
+
R1
500 ꢀ
+
+
+
+
C3
1 pF
Vocm
FDA
Vcc
5 V
Vcm
2.5 V
VM1
VG1
±
±
±
±
±
+
PD
Vcc
Rg2
4.02 kꢀ
Rf2
402 ꢀ
C2
1.7 pF
Figure 78. Compensated Attenuator Circuit Using the THS4541
Copyright © 2014, Texas Instruments Incorporated
45
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
Typical Applications (continued)
The 1 pF across the inputs is really a total 1.85 pF, including the internal differential capacitance, and a Cs =
3.7 pF for a single-ended design from Equation 17.
These two designs (with and without the capacitors) were both bench tested and simulated using the THS4541
TINA model giving the results of Figure 79.
This method does a good job of flattening the response for what starts out as a low phase-margin attenuator
application. The simulation model does a very good job of predicting the peaking and showing the same
improvement with the external capacitors; both giving a flat, approximately 250-MHz, closed-loop bandwidth for
this gain of a 0.1-V/V design. In this example, the output noise begins to peak up (as a result of the noise-gain
shaping of the capacitors) above 70 MHz. Use postfiltering to minimize any increase in the integrated noise using
this technique. Using this solution to deliver an 8-VPP differential output to a successive approximation register
(SAR) ADC (using the 2.5-V Vocm shown), the circuit accepts up to ±40-V inputs, where the 4-kΩ input Rg1
draws ±10 mA from the source.
10.2.1.3 Application Curve
-11
Bench without caps
Bench with caps
Sim without caps
-14
Sim with caps
-17
-20
-23
-26
-29
-32
1M
10M
100M
Frequency (Hz)
1G
D064
Figure 79. Attenuator Response Shapes with and without External Compensation
46
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
Typical Applications (continued)
10.2.2 Interfacing to High-Performance ADCs
Vcc
R9
499 ꢀ
D1
BAV99
Vcc
C1
0.2 ꢁF
50-ꢀ
Source
R12
35.7 ꢀ
R16
6.2 ꢀ
L2
250 nH
ADC
Input
R7
205 ꢀ
R4
59 ꢀ
±
+
R15
442 ꢀ
C5
33 pF
C6
180 pF
R6
205 ꢀ
Vocm
FDA
±
R13
35.7 ꢀ
R17
6.2 ꢀ
+
L3
250 nH
PD
ADC
Input
Vcc
R8
499 ꢀ
R1
49.9 ꢀ
R5
59 ꢀ
2
0.95 V
ADC Vcm
Output
3
1
2-to-3 for
ac-coupled Vin
2-to-1 for
dc-coupled Vin
R11
100 ꢀ
Vcc
JP1
C7
1 ꢁF
C3
10 nF
Figure 80. DC-Coupled, Bipolar Input Gain of 2 V/V Single-Ended to Differential Interface to ADC
10.2.2.1 Design Requirements
In this example design, an impedance matched input assuming a 50-Ω source is implemented with a dc-coupled
gain of 2 V/V to the ADC. This configuration effectively reduces the required full-scale input to ±0.5 V for a 2-VPP
full-scale input ADC. Add a low insertion-loss interstage filter to the ADC to control the broadband noise where
the goal is to show minimal SNR reduction in the FFT, as well as minimal degradation in SFDR performance.
10.2.2.2 Detailed Design Procedure
The THS4541 provides a very flexible element for interfacing from a variety of sources to a wide range of ADCs.
Because all precision and high-speed ADCs require a differential input on a common-mode voltage, this design
is the primary application for the THS4541.
The THS4541 provides a simple interface to a wide variety of precision SAR, ΔΣ, or higher-speed pipeline ADCs.
To deliver the exceptional distortion at the output pins, considerably wider bandwidth than typically required in
the signal path to the ADC inputs is provided by the THS4541. For instance, the gain of 2 single-ended to
differential design example provides approximately a 500-MHz, small-signal bandwidth. Even if the source signal
is Nyquist bandlimited, this broad bandwidth can possibly integrate enough THS4541 noise to degrade the SNR
through the ADC if the broadband noise is not bandlimited between the amplifier and ADC.
Figure 80 shows an example dc-coupled, gain of 2 interface with a controlled, interstage-bandwidth filter
implemented on the demonstration board for the JESD digital-output interface, ADC34J22 (a 50-MSPS, quad,
12-bit ADC). This board is called the DEV-ADC34J22 ADC HSMC MODULE with complete documentation at
http://dallaslogic.com/prod_dev-adc34j/.
Designed for a dc-coupled 50Ω input match, this design starts with a 499-Ω feedback resistor, and provides a
gain of 2.35V/V to the THS4541 output pins. The third-order interstage, low-pass filter provides a 20-MHz Bessel
response with a 0.85 V/V insertion loss to the ADC, providing a net gain of 2 V/V from board edge to the ADC
inputs. Although the THS4541 can absorb overdrives, an external protection element is added using the BAV99
low-capacitance device, shown in Figure 80. For dc-coupled testing, pins 1 and 2 are jumpered together. When
the source is an ac-coupled, 50-Ω source, pins 2 and 3 are jumpered to maintain differential balance. FFT testing
normally uses a bandpass filter into the board; an ac-coupled source. A typical 5-MHz, full-scale, single-tone FFT
Copyright © 2014, Texas Instruments Incorporated
47
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
Typical Applications (continued)
is shown in Figure 81, where the jumper is placed from pins 2 to 3. The reported SNR of 70.09 dBFs is only a
slight reduction from the tested ADC-only performance of 70.42 dBFs, showing the value of the interstage noise
bandwidth limiting filter. The exceptionally low harmonic distortion for the THS4541 also shows up in the very low
SFDR and THD shown in Figure 81. This 96-dB SFDR and 92.83-dB THD are comparable to the ADC-only test
results.
10.2.2.3 Application Curve
0
SNR = 70.1 dBFS
SFDR = 96 dBFS
THD = 92.83 dBFS
ENOB = 11.35 bits
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
0
5
10
15
20
25
Frequency (MHz)
D066
Figure 81. 5-MHz FFT, 50-MSPS Test for the Gain of 2 Interface in Figure 80
48
Copyright © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
11 Power-Supply Recommendations
The THS4541 is principally intended to operate with a nominal single-supply voltage of +3 V to +5 V. Supply-
voltage tolerances are supported with the specified operating range of 2.7 V (10% low on a 3-V nominal supply)
and 5.4 V (8% high on a 5-V nominal supply). Supply decoupling is required, as described in the Terminology
and Application Assumptions section. Split (or bipolar) supplies can be used with the THS4541, as long as the
total value across the device remains less than 5.5 V (absolute maximum). The thermal pad on the RGT
package is electrically isolated; connect the thermal pad to any power or ground plane for heat spreading.
Using a negative supply to deliver a true swing to ground output in driving SAR ADCs may be desired. While the
THS4541 quotes a rail-to-rail output, linear operation requires approximately a 200-mV headroom to the supply
rails. One easy option for extending the linear output swing to ground is to provide the small negative supply
voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed negative-
supply generator accepts the 3-V to 5-V positive supply input used by the THS4541 and provides a –230-mV
supply for the negative rail. Using the LM7705 provides an effective solution, as shown in the TI Designs
TIDU187, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts.
12 Layout
12.1 Layout Guidelines
Similar to all high-speed devices, best system performance is achieved with a close attention to board layout.
The THS4541 evaluation module (EVM) shows a good example of high frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed, signal-path layout suggestions include:
•
Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, open up both ground and power planes around the capacitive sensitive input and output device
pins. After the signal is sent into a resistor, parasitic capacitance becomes more of a bandlimiting issue and
less of a stability issue.
•
Use good, high-frequency decoupling capacitors (0.1 µF) on the ground plane at the device power pins.
Higher value capacitors (2.2 µF) are required, but may be placed further from the device power pins and
shared among devices. For best high-frequency decoupling, consider X2Y supply-decoupling capacitors that
offer a much higher self-resonance frequency over standard capacitors.
•
•
When using differential signal routing over any appreciable distance, use microstrip layout techniques with
matched impedance traces.
Higher-speed FDAs, such as the THS4541, include a duplicate of the output pins on the input feedback side
of the larger 16-pin VQFN (RGT) package. This duplication is intended to allow the external feedback
resistors to be connected with virtually no trace length on the input side of the package. Use this layout
approach with no extra trace length on this critical feedback path. The smaller 10-pin, WQFN (RUN) package
lines up the outputs and the required inputs on the same side of the package where the feedback (Rf)
resistors are placed immediately adjacent to the package with minimal trace length.
•
The input summing junctions are very sensitive to parasitic capacitance. Connect any Rg elements into the
summing junction with minimal trace length to the device pin side of the resistor. The other side of the Rg
elements can have more trace length if needed to the source or to ground.
Copyright © 2014, Texas Instruments Incorporated
49
THS4541
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
www.ti.com.cn
12.2 Layout Example
Figure 82. Layout Example
50
版权 © 2014, Texas Instruments Incorporated
THS4541
www.ti.com.cn
ZHCS230A –AUGUST 2014–REVISED SEPTEMBER 2014
13 器件和文档支持
13.1 器件支持
13.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.1.2 开发支持
13.1.2.1 TINA 仿真模型特性
器件模型作为 TINA 模型库的一部分提供。 此模型包含多种功能，旨在帮助设计人员加快设计过程，从而满足各类
应用需求。 下面列出了模型中所包含的性能参数：
•
采用任意外部电路时的小信号响应波形：
–
–
–
差分开环增益和相位
寄生输入电容
开环差分输出阻抗
•
•
对于噪声仿真：
–
–
输入差分点电压噪声和 100kHz 1/f 转角频率
每个输入上的输入电流噪声与 1MHz 1/f 转角频率
对于时域阶跃响应仿真：
–
–
–
差分转换率
用于预测削波的 I/O 余量模型
精密的直流精度术语：
–
–
电源抑制比 (PSRR)
共模抑制比 (CMRR)
典型特性曲线所呈现的信息比宏观模型提供的更为详细；其中一些非模型化的特性包括：
•
•
谐波失真
直流误差方面的温度漂移（VIO 和 IOS
）
13.2 商标
All trademarks are the property of their respective owners.
13.3 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
13.4 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、首字母缩略词和定义。
14 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2014, Texas Instruments Incorporated
51
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS4541IRGTR
THS4541IRGTT
THS4541IRUNR
THS4541IRUNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VQFN
VQFN
QFN
RGT
RGT
RUN
RUN
16
16
10
10
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
Call TI | NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
HS4541
NIPDAU
NIPDAU
NIPDAU
HS4541
4541
QFN
4541
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF THS4541 :
Automotive : THS4541-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4541IRGTR
THS4541IRGTT
THS4541IRUNR
THS4541IRUNT
VQFN
VQFN
QFN
RGT
RGT
RUN
RUN
16
16
10
10
3000
250
330.0
180.0
180.0
180.0
12.4
12.4
8.4
3.3
3.3
2.3
2.3
3.3
3.3
2.3
2.3
1.1
1.1
8.0
8.0
4.0
4.0
12.0
12.0
8.0
Q2
Q2
Q2
Q2
3000
250
1.15
1.15
QFN
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4541IRGTR
THS4541IRGTT
THS4541IRUNR
THS4541IRUNT
VQFN
VQFN
QFN
RGT
RGT
RUN
RUN
16
16
10
10
3000
250
346.0
210.0
210.0
210.0
346.0
185.0
185.0
185.0
33.0
35.0
35.0
35.0
3000
250
QFN
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016A
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.45 0.1
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4219032/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Reference JEDEC registration MO-220
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.45)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
17
(2.8)
(0.475)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.475) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219032/A 02/2017
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
6. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.34)
13
16
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
86% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219032/A 02/2017
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
RUN 10
2 X 2, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228249/A
www.ti.com
PACKAGE OUTLINE
RUN0010A
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4220470/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220470/A 05/2020
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4220470/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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Copyright © 2023，德州仪器 (TI) 公司
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