THS4551IRUNT [TI]
低噪声精密 150MHz 全差分放大器 | RUN | 10 | -40 to 125;
| 型号： | THS4551IRUNT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 低噪声精密 150MHz 全差分放大器 | RUN | 10 | -40 to 125 放大器 |
| 文件： | 总82页 (文件大小：4211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4551
ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
THS4551
低噪声精密150MHz 全差分放大器
1 特性
3 描述
• 带宽：150MHz (G = 1V/V)
• 差分输出压摆率：220V/µs
• 增益带宽积：135MHz
• 负轨输入(NRI)，
轨到轨输出(RRO)
• 宽输出共模控制范围
• 单电源工作电压范围：2.7V 至5.4V
• 修整后的电源电流：在5 V 时为1.37 mA
• 25°C 输入失调电压：±175µV（最大值）
• 输入失调电压漂移：±1.8µV/°C（最大值）
• 差分输入电压噪声：3.3nV/√Hz
• HD2：-128dBc（2VPP、100kHz 时）
• HD3：-139dBc（2VPP、100kHz 时）
• 短于50ns 的稳定时间：4V 阶跃，容限为0.01%
• 18 位稳定时间：4V 阶跃，小于500ns
THS4551 全差分放大器可在单端源与差分输出之间提
供一个简单的接口，从而满足各类高精度模数转换器
(ADC) 的需求。此器件兼具优异的直流精度、低噪声
以及稳健的容性负载驱动能力，非常适用于具有高精度
要求的数据采集系统；同时在放大器与 ADC 协同作用
下，可获得出色的信噪比 (SNR) 与无杂散动态范围
(SFDR)。
THS4551 具有所需的负电源轨输入，可用于将直流耦
合、以接地为中心的源信号连接到单电源差分输入
ADC。该器件具有超低直流误差和漂移，能够满足新
兴的 16 至 20 位逐次逼近寄存器 (SAR) 输入要求。在
0.7V 至 3.0V 以上的 ADC 共模输入要求下，宽范围输
出共模控制支持ADC 在1.8V 至5V 电源下运行。
THS4551 器件可在 –40°C 至 +125°C 的宽温度范围
内额定运行， 并且提供 8 引脚超薄小外形尺寸
(VSSOP) 封装、16 引脚超薄四方扁平无引线 (VQFN)
封装以及10 引脚超薄四方扁平无引线(WQFN) 封装。
2 应用
• 24 位Δ-Σ模数转换器(ADC) 驱动器
• 16 位至20 位差分高速逐次逼近寄存器(SAR) 驱动
器
• 差分有源滤波器
• 差分互阻抗放大器
器件信息(1)
器件型号
封装
封装尺寸（标称值）
3.00mm × 3.00mm
2.00mm x 2.00mm
3.00mm × 3.00mm
THS4551
VSSOP (8)
WQFN (10)
VQFN (16)
• 引脚兼容性升级至THS4521（仅限VSSOP-8）
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1.2 kꢀ
270 pF
3 V
1.2 kꢀ
330 ꢀ
1 nF
5 ꢀ
10 ꢀ
10 ꢀ
AINN
AINP
+
œ
ADS127L01
THS4551
22 nF
470 pF
+
œ
1.2 kꢀ
330 ꢀ
5 ꢀ
270 pF
1.2 kꢀ
Copyright © 2016, Texas Instruments Incorporated
简化版原理图：1V/V 增益，单端输入转差分输出，500kHz，ADS127L01 多反馈滤波器接口
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBOS778
THS4551
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
Table of Contents
8.7 Terminology and Application Assumptions............... 28
9 Detailed Description......................................................30
9.1 Overview...................................................................30
9.2 Functional Block Diagram.........................................30
9.3 Feature Description...................................................31
9.4 Device Functional Modes..........................................40
10 Application and Implementation................................44
10.1 Application Information........................................... 44
10.2 Typical Applications................................................ 51
11 Power Supply Recommendations..............................57
11.1 Thermal Analysis.....................................................58
12 Layout...........................................................................59
12.1 Layout Guidelines................................................... 59
12.2 Layout Example...................................................... 60
12.3 EVM Board..............................................................61
13 Device and Documentation Support..........................63
13.1 Device Support....................................................... 63
13.2 Documentation Support.......................................... 65
13.3 接收文档更新通知................................................... 66
13.4 支持资源..................................................................66
13.5 Trademarks.............................................................66
13.6 静电放电警告.......................................................... 66
13.7 术语表..................................................................... 66
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 描述................................................................................... 1
4 Revision History.............................................................. 2
5 Companion Devices........................................................ 4
6 Pin Configuration and Functions...................................5
7 Specifications.................................................................. 6
7.1 Absolute Maximum Ratings........................................ 6
7.2 ESD Ratings............................................................... 6
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics: (VS+) –(VS–) = 5 V..........7
7.6 Electrical Characteristics: (VS+) –(VS–) = 3 V........ 11
7.7 Typical Characteristics: (VS+) –(VS–) = 5 V........... 14
7.8 Typical Characteristics: (VS+) –(VS–) = 3 V........... 17
7.9 Typical Characteristics: 3-V to 5-V Supply Range.... 20
8 Parameter Measurement Information..........................24
8.1 Example Characterization Circuits............................24
8.2 Output Interface Circuit for DC-Coupled
Differential Testing.......................................................26
8.3 Output Common-Mode Measurements.....................26
8.4 Differential Amplifier Noise Measurements...............27
8.5 Balanced Split-Supply Versus Single-Supply
Characterization.......................................................... 27
8.6 Simulated Characterization Curves.......................... 27
Information.................................................................... 66
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision C (July 2017) to Revision D (April 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• 向说明部分添加了器件信息表...........................................................................................................................1
• Moved the Low-Power ADCs Supported by the THS4551 table to the Device Comparison section................. 4
• Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical
Characteristics: (VS+) –(VS–) = 5 V section.....................................................................................................7
• Removed the IIB input bias current (positive current out-of-node) minimum limits in the Electrical
Characteristics: (VS+) –(VS–) = 3 V section................................................................................................... 11
Changes from Revision B (November 2016) to Revision C (July 2017)
Page
• 将节7.6 表中的47kΩ，1.3pF 更改为150kΩ，7pF..........................................................................................1
Changes from Revision A (August 2016) to Revision B (November 2016)
Page
• Added second row and footnote 2 to Voltage parameter of Absolute Maximum Ratings table..........................6
• Added package differences and footnote 3 to ESD Ratings table......................................................................6
• Changed footnotes 1 and 2 in 5-V Electrical Characteristics table.....................................................................7
• Added test conditions to AOL parameter in 5-V Electrical Characteristics table................................................. 7
• Changed Input offset voltage drift parameter .................................................................................................... 7
• Changed IIB parameter minimum and maximum specifications in last three rows ............................................ 7
• Changed Input bias current drift parameter test conditions and specifications ................................................. 7
• Added Input offset current drift parameter test conditions, minimum and maximum specifications, and test
level value to second row................................................................................................................................... 7
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• Changed test conditions of Common-mode input, low and Common-mode input, high parameters .................7
• Changed test conditions of Continuous output current and Linear output current parameters ......................... 7
• Changed test conditions of Enable voltage threshold and Disable voltage threshold parameters.....................7
• Changed specifications of Power-down quiescent current parameter ...............................................................7
• Changed Common-mode loop supply headroom to negative supply parameter test conditions........................7
• Changed test conditions and maximum specifications of Common-mode loop supply headroom to positive
supply parameter................................................................................................................................................7
• Added test conditions to DC Performance, AOL parameter...............................................................................11
• Changed Input offset voltage drift parameter test conditions in first row, added second row........................... 11
• Changed minimum and maximum specifications in last three rows of IIB parameter........................................11
• Changed Input bias current drift parameter test conditions.............................................................................. 11
• Added second row to Input offset current drift parameter ................................................................................11
• Changed test conditions of Common-mode input, low and Common-mode input, high parameters................11
• Changed test conditions of Continuous output current and Linear output current parameters ........................11
• Changed test conditions of Enable voltage threshold and Disable voltage threshold parameters................... 11
• Changed IQ(PD) parameter specifications..........................................................................................................11
• Changed Common-mode loop supply headroom to negative supply parameter test conditions......................11
• Changed Common-mode loop supply headroom to positive supply parameter test conditions and maximum
specifications ....................................................................................................................................................11
• Changed conditions of 图7-49 to 图7-54 ....................................................................................................... 20
• Changed Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit figure.........................................24
• Changed main Device Functional Modes section: changed value of PD pin voltage ......................................40
• Changed the minimum value for single-supply operation in the Operating the Power Shutdown Feature
section.............................................................................................................................................................. 47
• Added SBOS476, SBOC466, SBOC463, SBOC467, SBOS460, SBOC477, SBOC472, SLOC341, SBOC469,
SBOC462, SBOC461, SBOC465, SBOC464, SBOC475, SBOC474, SBOC471, SBOC459, SBOC470,
SBOC468, and SBOC473 to Related Documentation section ........................................................................ 65
Changes from Revision * (April 2016) to Revision A (August 2016)
Page
• 已投入量产..........................................................................................................................................................1
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5 Companion Devices
Low-Power ADCs Supported by the THS4551
PART NUMBER
ADS127L01
ADC TYPE
RESOLUTION, SPEED
Delta sigma
24 bits, 0.512 MSPS
18 bits, 1 MSPS
18 bits, 2 MSPS
14 bits, 25 MSPS
ADS8881
ADS9110
ADC3241
SAR
SAR
Pipeline
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6 Pin Configuration and Functions
VS+
10
IN-
IN+
1
2
3
4
8
7
6
5
OUT–
NC
9
8
7
6
OUT+
NC
1
2
3
4
VOCM
PD
VOCM
IN–
PD
VS+
VS-
OUT-
IN+
OUT+
5
VS–
图6-1. DGK Package 8-Pin VSSOP Top View
图6-2. RUN Package 10-Pin WQFN Top View
16
15
14 13
12 PD
FB–
IN+
1
2
3
4
11 OUT–
IN–
10
9
OUT+
FB+
VOCM
5
6
7
8
图6-3. RGT Package 16-Pin VQFN With Exposed Thermal Pad Top View
表6-1. Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
RGT(1)
RUN
DGK
1
4
3
2
O
O
I
Inverting (negative) output feedback
FB–
FB+
—
—
6
—
—
1
Noninverting (positive) output feedback
Inverting (negative) amplifier input
Noninverting (positive) amplifier input
No internal connection
IN–
IN+
4
8
I
NC
2, 8
1
—
11
10
—
5
—
O
O
Inverting (negative) amplifier output
Noninverting (positive) amplifier output
OUT–
OUT+
9
4
Power down. PD = logic low = power off mode; PD = logic high = normal
operation.
PD
12
3
7
I
VOCM
VS–
VS+
9
7
5
2
6
3
I
I
I
Common-mode voltage input
Negative power-supply input
Positive power-supply input
13-16
5, 6, 7, 8
10
(1) Solder the exposed thermal pad (RGT package) to a heat-spreading power or ground plane. This pad is electrically isolated from the
die, but it must be connected to a power or ground plane and not floated.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
5.5
UNIT
V
Supply voltage, (VS+) –(VS–
)
Supply turn-on/off maximum dV/dT(2)
Input/output voltage range
Differential input voltage
±1
V/µs
Voltage
(VS+) + 0.5
±1
(VS–) –0.5
V
Continuous input current
±10
mA
Continuous output current(3)
±20
Current
See the 节7.4 and
节11.1 sections
Continuous power dissipation
Maximum junction
Operating free-air, TA
Storage, Tstg
150
125
150
Temperature
–40
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Staying below this ± supply turn-on edge rate ensures that the edge-triggered ESD absorption device across the supply pins remains
off.
(3) Long-term continuous current for electro-migration limits.
7.2 ESD Ratings
VALUE
UNIT
A. THS4551 in DGK, RUN Pacakges
V(ESD) Electrostatic discharge
B. THS4551 in RGT Package
V(ESD) Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±2500
±1250
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) (3)
±1000
±1250
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
(3) ESD limit of ±1000 V for any pin to thermal pad. Pin-to-pin HBM ESD specifications are rated at ±2500 V.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
NOM
5
MAX
5.4
UNIT
VS+
TA
Single-supply positive voltage
Ambient temperature
V
25
125
°C
–40
7.4 Thermal Information
THS4551
RGT(2)
(VQFN)
RUN
(WQFN)
DGK
THERMAL METRIC(1)
UNIT
(VSSOP)
8 PINS
185
16 PINS
54
10 PINS
142
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
72
78
76
28
97
106
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THS4551
RGT(2)
(VQFN)
RUN
(WQFN)
DGK
(VSSOP)
THERMAL METRIC(1)
UNIT
16 PINS
3.2
10 PINS
9.7
8 PINS
13
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
°C/W
°C/W
°C/W
ψJT
28
97
105
ψJB
RθJC(bot)
12
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal impedance for RGT reported with backside thermal pad soldered to heat spreading plane.
7.5 Electrical Characteristics: (VS+) –(VS–) = 5 V
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB)
VOUT = 20 mVPP, G = 2
150
75
C
C
C
C
C
C
SSBW Small-signal bandwidth
MHz
VOUT = 20 mVPP, G = 10
VOUT = 20 mVPP, G = 100
VOUT = 2 VPP, G = 1
15
GBP
Gain-bandwidth product
135
37
MHz
MHz
MHz
LSBW Large-signal bandwidth
Bandwidth for 0.1-dB flatness
VOUT = 2 VPP, G = 1
15
VOUT = 4 VPP, full-power bandwidth (FPBW),
RL = 1 kΩ
SR
Slew rate(2)
220
V/µs
ns
C
tR, tF
Rise and fall time
VOUT = 0.5-V step, G = 1, input tR = 2 ns
To 0.1%, VOUT = 0.5-V step, input tR = 2 ns, G = 1
To 0.01%,VOUT = 0.5-V step, input tR = 2 ns, G = 1
VOUT = 0.5-V step G = 1, input tR = 2 ns
f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 8 VPP, G = 1, RL = 1 kΩ
f > 500 Hz, 1/f < 150 Hz
6
30
C
C
C
C
C
C
C
C
C
C
C
C
tSETTLE Settling time
Overshoot and undershoot
ns
50
8%
–128
–124
–139
–131
3.3
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
Input voltage noise
nV/√Hz
pA/√Hz
ns
Input current noise
f > 20 kHz, 1/f <10 kHz
0.5
Overdrive recovery time
Closed-loop output impedance
G = 2, 2X output overdrive, dc coupled
f = 100 kHz (differential), G = 1
50
0.02
Ω
DC PERFORMANCE(5)
AOL Open-loop voltage gain
105
3.0
125
3.5
10
dB
A
A
B
A
B
A
B
B
B
B
B
B
±3-V differential-to-differential, 1-kΩload
TA = 25°C, RGT only (pins 11-1, 10-4)
TA = –40°C to +125°C, temperature drift
TA = 25°C, RGT only (pins 11-1, 10-4)(6)
4.7
1
Ω
Internal feedback trace resistance
mΩ/°C
0.05
50
–1
Ω
Internal feedback trace resistance
mismatch
TA = –40°C to +125°C, temperature drift
TA = 25°C
µΩ/°C
±50
175
265
295
375
2.0
–175
–225
–295
–295
–2.0
–1.7
–1.8
TA = 0°C to +70°C
VIO
Input-referred offset voltage
Input offset voltage drift(3)
µV
TA = –40°C to +85°C
TA = –40°C to +125°C
±0.45
±0.4
±0.4
TA = –40°C to +125°C (DGK package)
TA = –40°C to +125°C (RUN package)
TA = –40°C to +125°C (RGT package)
1.7 µV/°C
1.8
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7.5 Electrical Characteristics: (VS+) –(VS–) = 5 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
TA = 25°C
1.0
1.5
A
B
B
B
B
A
B
B
B
B
B
TA = 0°C to +70°C
1.73
Input bias current
(positive current out of node)
IIB
µA
1.80
TA = –40°C to +85°C
2.0
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = 25°C
Input bias current drift(3)
Input offset current
2
–50
3.3
5.0 nA/°C
50
±10
TA = 0°C to +70°C
63
nA
67
–57
IOS
TA = –40°C to +85°C
–68
78
TA = –40°C to +125°C
TA = –40°C to +125°C (DGK package)
TA = –40°C to +125°C (RGT and RUN package)
–68
±70
±20
280
pA/°C
120
–280
–120
Input offset current drift(3)
INPUT
(VS–) –
(VS–) –
TA = 25°C
A
B
A
B
0.2
0.1
> 90-dB CMRR at input
range limits
Common-mode input, low
Common-mode input, high
V
V
(VS–) –
VS–
TA = –40°C to +125°C
0.1
(VS+) –
(VS+) –
TA = 25°C
1.2
1.1
> 90-dB CMRR at input
range limits
(VS+) –
(VS+) –
TA = –40°C to +125°C
1.3
1.2
CMRR Common-mode rejection ratio
Input impedance differential mode
OUTPUT
93
110
dB
A
C
Input pins at [(VS+) –(VS–)] / 2
Input pins at [(VS+) –(VS–)] / 2
100 || 1.2
kΩ|| pF
(VS–) +
0.23
(VS–) +
TA = 25°C
A
B
A
B
A
0.2
Output voltage, low
Output voltage, high
V
V
(VS–) +
0.2
(VS–) +
0.22
TA = –40°C to +125°C
TA = 25°C
(VS+) –
(VS+) –
0.23
0.2
(VS+) –
(VS+) –
TA = –40°C to +125°C
0.22
0.2
TA = 25°C, ±2.5 V, RL= 40 Ω,
VOCM offset < ±20 mV
±60
±65
±45
Continuous output current
Linear output current
mA
mA
TA = –40°C to +125°C, ±2.1 V, RL= 40 Ω,
VOCM offset < ±20 mV
±50
±40
±30
B
A
B
TA = 25°C, ±2.1 V, RL= 50 Ω, AOL > 80 dB
TA = –40°C to +125°C, ±1.6 V, RL= 50 Ω,
AOL > 80 dB
POWER SUPPLY
Specified operating voltage
2.7
1.28
0.97
5
5.4
1.44
1.92
V
B
A
B
TA ≈25°C(7), VS+ = 5 V
1.37
IQ
Quiescent operating current
mA
TA = –40°C to +125°C, VS+ = 5 V
Quiescent current temperature
coefficient
dIQ/dT
VS+ = 5 V
2.4
93
3.9
5.4 µA/°C
dB
B
A
±PSRR Power-supply rejection ratio
POWER-DOWN
Either supply pin to differential VOUT
110
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Specified on above (VS–) + 1.15 V
Specified off below (VS–) + 0.55 V
PD = VS– →VS+
(VS–) + 1.15
V
A
A
B
(VS–) + 0.55
100
V
±10
nA
–100
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.5 Electrical Characteristics: (VS+) –(VS–) = 5 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
Power-down quiescent current
Turn-on time delay
1
700
100
5
µA
ns
ns
A
C
C
–2
tON
Time from PD = low to VOUT = 90% of final value
Time from PD = low to VOUT = 10% of final value
tOFF
Turn-off time delay
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.5 Electrical Characteristics: (VS+) –(VS–) = 5 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (See 图8-5)
SSBW Small-signal bandwidth
LSBW Large-signal bandwidth
VOCM = 100 mVPP at the control pin
VOCM = 1 VPP at the control pin
From 1-VPP LSBW
40
8
MHz
MHz
V/µs
C
C
C
SR
Slew rate(2)
18
Output common-mode noise
(≥2 kHz)
VOCM pin driven from low impedance
15
C
nV/√Hz
VOCM control pin input to output average voltage
(see 图8-5)
Gain
0.997
0.999
±10
85
1.001
100
V/V
nA
A
A
C
Input bias current
–100
DC output balance (differential
mode to common-mode output)
VOUT = ±1 V
dB
VOUT = 100 mVPP (output balance drops –3 dB
from the 85-dB dc level)
SSBW
Output balance
300
300
C
C
C
kHz
VOUT = 2 VPP (output balance drops –3 dB from the
85-dB dc level)
LSBW
Input impedance
(VOCM pin input)
150 || 7
kΩ|| pF
VOCM pin open
±2
35
12
mV
A
B
–12
Default voltage offset from
[(VS+) –(VS–)] / 2
15
55 µA/°C
VOCM pin open, TA = –40°C to +125°C
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL (continued)
TA = 25°C
±1
±2
5.0
A
B
B
B
–5.0
–5.25
–5.7
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
5.5
mV
5.6
VOCM pin driven to [(VS+
–(VS–)] / 2
)
CM VOS Common-mode offset voltage
6.0
–5.7
Common-mode offset voltage
drift(3)
10 µV/°C
B
TA = –40°C to +125°C
–10
TA = 25°C
0.55
A
B
B
B
A
B
B
B
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 25°C
0.6
0.65
0.7
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from
midsupply CM VOS
V
V
1.2
TA = 0°C to 70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
1.25
1.3
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from
midsupply CM VOS
1.3
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈25°C. (B) Not tested in production; limits set by
characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the sinusoidal large-signal bandwidth as: (VP / √2) × 2π×
f–3dB
.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking
measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature
range. Maximum drift specifications are set by mean ±4 σon the device distributions tested over a –40°
temperature range. Drift is not specified by final ATE testing or QA sample test.
̊C to +125°C̊ ambient
(4) Specifications are from the input VOCM pin to the differential output average voltage.
(5) Currents out of pin are treated as a positive polarity (with the exception of the power-supply pins).
(6) Trace mismatch measurement is dominated by the variation in contactor resistance. Internal mismatch is less than 0.1 Ω.
(7) TA = 25°C and ICC ≈1.37 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C ICC temperature
coefficient considered; see 图11-1.
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.6 Electrical Characteristics: (VS+) –(VS–) = 3 V
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
AC PERFORMANCE
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
VOUT = 20 mVPP, G = 1, peaking (< 1.0 dB)
VOUT = 20 mVPP, G = 2
150
80
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
SSBW Small-signal bandwidth
MHz
VOUT = 20 mVPP, G = 10
14
GPB
Gain-bandwidth product
VOUT = 20 mVPP, G = 100
130
45
MHz
MHz
MHz
V/µs
ns
LSBW Large-signal bandwidth
Bandwidth for 0.1-dB flatness
VOUT = 1 VPP, G = 1
VOUT = 1 VPP, G = 1
14
SR
Slew rate(2)
VOUT = 1 VPP, FPBW, G = 1
110
7.0
tR, tF
Rise and fall time
VOUT = 0.5-V step, G = 1, input tR = 4 ns
To 0.1%, VOUT = 0.5-V step, input tR = 4 ns, G = 1
To 0.01%, VOUT = 0.5-V step, input tR = 4 ns, G = 1
VOUT = 0.5-V step, G = 1, input tR = 4 ns
f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 2 VPP, G = 1, RL = 1 kΩ
f = 100 kHz, VOUT = 4 VPP, G = 1, RL = 1 kΩ
f > 500 Hz, 1/f < 150 Hz
35
tSETTLE Settling time
Overshoot and undershoot
ns
55
7%
–128
–127
–139
–125
3.4
HD2
HD3
Second-order harmonic distortion
Third-order harmonic distortion
dBc
dBc
Input voltage noise
nV/√Hz
pA/√Hz
ns
Input current noise
f > 20 kHz, 1/f < 10 kHz
0.5
Overdrive recovery time
Closed-loop output impedance
G = 2, 2X output overdrive, dc coupled
f = 100 kHz (differential), G = 1
100
0.02
Ω
DC PERFORMANCE(5)
AOL Open-loop voltage gain
100
3.0
120
3.45
50
dB
A
A
B
A
B
A
B
B
B
B
B
B
A
B
B
B
B
A
B
B
B
B
B
±2-V differential to 1-kΩdifferential load
TA = 25°C, RGT only (pins 11-1, 10-4)
TA = –40°C to +125°C, temperature drift
TA = 25°C, RGT only (pins 11-1, 10-4)(6)
4.7
1
Ω
Internal feedback trace resistance
mΩ/°C
0.05
50
–1
Ω
Internal feedback trace resistance
mismatch
TA = –40°C to +125°C, temperature drift
TA = 25°C
µΩ/°C
±40
175
265
295
375
2.0
–175
–225
–295
–295
–2.0
–1.7
–1.8
TA = 0°C to +70°C
VIO
Input-referred offset voltage
Input offset voltage drift(3)
µV
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C (DGK package)
TA = –40°C to +125°C (RUN package)
TA = –40°C to +125°C (RGT package)
TA = 25°C
±0.45
±0.4
±0.4
1.0
1.7 µV/°C
1.8
1.5
TA = 0°C to +70°C
1.73
Input bias current
(positive current out of node)
IIB
µA
1.80
2.0
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = –40°C to +125°C
TA = 25°C
Input bias current drift(3)
Input offset current
2
–50
3.3
5.5 nA/°C
50
±10
TA = 0°C to +70°C
63
nA
67
–57
IOS
TA = –40°C to +85°C
–68
78
TA = –40°C to +125°C
–68
±70
±20
280
TA = –40°C to +125°C (DGK package)
TA = –40°C to +125°C (RGT and RUN package)
–280
–120
Input offset current drift(3)
pA/°C
120
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.6 Electrical Characteristics: (VS+) –(VS–) = 3 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
LEVEL(1)
INPUT
(VS–) –
(VS–) –
TA = 25°C
A
B
A
B
0.2
0.1
> 87-dB CMRR at input
range limits
Common-mode input, low
Common-mode input, high
V
V
(VS–) –
VS–
TA = –40°C to +125°C
TA = 25°C
0.1
(VS+) –
(VS+) –1.1
(VS+) –1.2
1.2
> 87-dB CMRR at input
range limits
(VS+) –
TA = –40°C to +125°C
1.3
CMRR Common-mode rejection ratio
Input impedance differential mode
OUTPUT
90
110
dB
A
C
Input pins at [(VS+) –(VS–)] / 2
Input pins at [(VS+) –(VS–)] / 2
100 || 1.2
kΩ|| pF
(VS–) +
0.2
(VS–) +
0.21
TA = 25°C
A
B
A
B
A
B
A
B
VOL
Output voltage, low
V
V
(VS–) +
0.2
(VS–) +
0.22
TA = –40°C to +125°C
TA = 25°C
(VS+) –
(VS+) –
0.21
0.2
VOH
Output voltage, high
Continuous output current
Linear output current
(VS+) –
(VS+) –
TA = –40°C to +125°C
±1.5 V, RL = 40 Ω,
0.22
0.2
TA = 25°C
±35
±30
±28
±20
±40
±35
VOCM offset < ±20 mV
mA
mA
±1.3 V, RL = 40 Ω,
VOCM offset < ±20 mV
TA = –40°C to +125°C
TA = 25°C
±1.5 V, RL = 50 Ω,
AOL > 80 dB
±1.1 V, RL = 50 Ω,
AOL > 80 dB
TA = –40°C to +125°C
POWER SUPPLY
Specified operating voltage
2.7
1.24
0.96
3
5.4
1.40
1.84
V
B
A
B
TA ≈25°C(7), VS+ = 3 V
1.31
IQ
Quiescent operating current
mA
TA = –40°C to +125°C, VS+ = 3 V
VS+ = 3 V
Quiescent current temperature
coefficient
dIQ/dT
2.0
90
3.4
5.0 µA/°C
dB
B
A
±PSRR Power-supply rejection ratio
POWER-DOWN
Either supply pin to differential VOUT
105
Enable voltage threshold
Disable voltage threshold
Disable pin bias current
Specified on above (VS–) + 1.15 V
Specified off below (VS–) + 0.55 V
PD = VS– →VS+
(VS–) + 1.15
V
A
A
B
A
C
C
(VS–) + 0.55
V
±10
1
100
5
nA
µA
ns
ns
–100
–2
IQ(PD)
tON
Power-down quiescent current
Turn-on time delay
Time from PD = low to VOUT = 90% of final value
Time from PD = low to VOUT = 10% of final value
750
150
tOFF
Turn-off time delay
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(4) (See 图8-5)
SSBW Small-signal bandwidth
LSBW Large-signal bandwidth
VOCM = 100 mVPP at the control pin
VOCM = 1 VPP at the control pin
From 1-VPP LSBW
40
8
MHz
MHz
C
C
C
SR
Slew rate(2)
12
15
V/µs
Output common-mode noise
VOCM pin driven from low impedance, f ≥2 kHz
nV/√Hz
VOCM control pin input to output average voltage
(see 图8-5)
Gain
0.997
0.999
1.001
V/V
A
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.6 Electrical Characteristics: (VS+) –(VS–) = 3 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
TEST
PARAMETER
TEST CONDITIONS
MIN
TYP
85
MAX UNIT
LEVEL(1)
DC output balance (differential
mode to common-mode output)
VOUT = ±1 V
dB
C
VOUT = 100 mVPP (output balance drops –3 dB
from the 85-dB dc level)
SSBW
Output balance
300
300
C
C
kHz
VOUT = 1 VPP (output balance drops –3 dB from the
85-dB dc level)
LSBW
Input bias current
Input impedance
±10
150 || 7
±2
100
12
nA
kΩ|| pF
mV
A
C
A
B
–100
VOCM pin open
–12
Default voltage offset from
[(VS+) –(VS–)] / 2
15
35
55 µA/°C
VOCM pin open, TA = –40°C to +125°C
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL (continued)
TA = 25°C
±1
±2
5.0
A
B
B
B
–5.0
–5.25
–5.7
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
5.5
mV
5.6
VOCM input driven to [(VS+
CM VOS Common-mode offset voltage
–(VS–)] / 2
)
6.0
–5.7
Common-mode offset voltage
10 µV/°C
B
VOCM input driven to [(VS+) –(VS–)] / 2
–10
drift(3)
TA = 25°C
0.55
A
B
B
B
A
B
B
B
TA = 0°C to +70°C
0.6
0.65
0.7
Common-mode loop supply
headroom to negative supply
< ±15-mV shift from
midsupply CM VOS
V
V
TA = –40°C to +85°C
TA = –40°C to +125°C
TA = 25°C
1.2
TA = 0°C to +70°C
TA = –40°C to +85°C
TA = –40°C to +125°C
1.25
1.3
Common-mode loop supply
headroom to positive supply
< ±15-mV shift from
midsupply CM VOS
1.3
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at TA ≈25°C. (B) Not tested in production; limits set by
characterization and simulation. (C) Typical value only for information.
(2) This slew rate is the average of the rising and falling time estimated from the large-signal bandwidth as: (VPP / √2) × 2π× f–3dB
.
(3) Input offset voltage drift, input bias current drift, and input offset current drift are the mean ±1-sigma values calculated by taking
measurements at the maximum-range ambient temperature end points, computing the difference, and dividing by the temperature
range. Maximum drift specifications are set by mean ±4 σon the device distributions tested over a –40°
temperature range. Drift is not specified by final ATE testing or QA sample test.
̊C to +125°C̊ ambient
(4) Specifications are from input VOCM pin to differential output average voltage.
(5) Currents out of pin are treated as a positive polarity (with exception of the power-supply pin currents).
(6) Trace mismatch measurement is dominated by the variation in contactor resistance. Internal mismatch is less than 0.1 Ω.
(7) TA = 25°C and ICC ≈1.31 mA. The test limit is expanded for the ATE ambient range of 22°C to 32°C with a 4-µA/°C ICC temperature
coefficient considered; see 图11-1.
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.7 Typical Characteristics: (VS+) –(VS–) = 5 V
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
9
3
2
6
1
0
3
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
VOUT = 20 mVpp
VOUT = 200 mVpp
VOUT = 1 Vpp
VOUT = 2 Vpp
VOUT = 4 Vpp
VOUT = 8 Vpp
-3
-6
-9
G = 0.1 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D001
D002
VOUT = 20 mVPP, see 图8-1 and 表9-1 for resistor values
图7-1. Small-Signal Frequency Response vs Gain
See 图8-1
图7-2. Frequency Response vs VOUT
3
2
6
3
1
0
-1
-2
-3
-4
0
-3
-6
-9
-12
VOCM = 0.8 V
-5
VOCM = 1 V
-6
RL = 50 W
VOCM = 1.5 V
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1000 W
VOCM = 2 V
VOCM = 3 V
VOCM = 3.5 V
-7
-8
-9
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D003
D004
VOUT = 20 mVPP , see 图8-1 with VOCM adjusted
VOUT = 20 mVPP, see 图8-1 with load resistance (RL) adjusted
图7-4. Small-Signal Frequency Response vs RL
图7-3. Small-Signal Frequency Response vs VOCM
3
2
100
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
90
1
80
70
0
-1
-2
-3
-4
60
50
40
30
20
10
0
-5
CL = 10 pF, RO = 97.6 W
-6
CL = 47 pF, RO = 49.9 W
CL = 100 pF, RO = 32.4 W
CL = 470 pF, RO = 10.0 W
CL = 1000 pF, RO = 4.7 W
-7
-8
-9
100k
1M
10M
Frequency (Hz)
100M
1
10
100
1000
D006
Differential CL (pF)
D005
VOUT = 20 mVPP at load, G = 1, two series RO added at output
before capacitive load (CL)
Output resistance (RO) is two series output resistors to a
differential CL in parallel with a 1-kΩload resistance
图7-5. Small-Signal Frequency Response vs CL
图7-6. Recommended RO vs CL
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.7 Typical Characteristics: (VS+) –(VS–) = 5 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
1.2
1
0.5
0.4
0.3
0.2
0.1
0
RO = 0 W
RO = 75 W
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
-0.1
-0.2
-0.3
-0.4
-0.5
0.2-V step, tR = 1 ns
0.5-V step, tR = 2 ns
1-V step, tR = 4 ns
2-V step, tR = 8 ns
-1.2
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
D007
D008
G = 1 V/V, 5-MHz input, single-ended to differential output
G = 1 V/V, VOUT = 500-mV step into 22-pF CL, see 图8-4
图7-8. Step Response Into Capacitive Load
图7-7. Small- and Large-Signal Step Response
1.5
0.5
RO = 0 W
RO = 46.4 W
0.4
1
0.5
0
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
0.2-V step, tR = 1 ns
0.5-V step, tR = 1 ns
1-V step, tR = 2 ns
2-V step, tR = 5 ns
-1
-1.5
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
D009
D010
G = 2 V/V, 5-MHz input, single-ended input to differential
output
G = 2 V/V, VOUT = 500-mV step into 22-pF CL, see 图8-4
图7-10. Step Response Into Capacitive Load
图7-9. Small- and Large-Signal Step Response
0.2
10
0.2-V step, tR = 1 ns
1-V step, tR = 4 ns
2-V step, tR = 8 ns
Input
Output
8
0.15
0.1
6
4
0.05
0
2
0
-2
-4
-6
-8
-10
-0.05
-0.1
-0.15
-0.2
0
10
20
30
40
50
60
70
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
Time D from 50% of Input Edge (ns)
D011
D012
Simulated with G = 1 V/V
Single-ended to differential gain of 2, 2X input overdrive
图7-11. Small- and Large-Signal Step Settling Time
图7-12. Overdrive Recovery Performance
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.7 Typical Characteristics: (VS+) –(VS–) = 5 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
-50
-60
-70
-80
HD2
HD3
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-70
-90
-80
-100
-110
-120
-130
-140
-150
-90
-100
-110
-120
-130
-140
-150
10k
100k
1M
10M
0.1
1
Differential Output Voltage (Vpp)
10
Frequency (Hz)
D013
D014
G = 1 V/V, VOUT = 2 VPP
G = 1 V/V
图7-13. Harmonic Distortion vs Frequency
图7-14. Harmonic Distortion vs Output Swing
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-60
Max IMD3
Max IMD2
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-70
-80
-90
-100
-110
-120
-130
-140
1M
10M
50
100
Differential Load Resistance (W)
1000
Frequency (Hz)
D015
D016
G = 1 V/V, VOUT = 1 VPP each tone
G = 1 V/V, VOUT = 2 VPP, with RL adjusted
图7-15. Intermodulation Distortion (IMD2 and IMD3) vs
图7-16. Harmonic Distortion vs RL
Frequency
-20
-105
-110
-115
-120
-125
-130
-135
-140
-145
HD2, 10 kHz
HD2, 100 kHz
HD2, 1 MHz
HD3, 10 kHz
HD3, 100 kHz
HD3, 1 MHz
HD2, 100 kHz
HD3, 100 kHz
-40
-60
-80
-100
-120
-140
-160
0.5
1.5
2.5
VOCM - (VS-) (V)
3.5
4.5
1
10
Gain (V/V)
D017
D018
G = 1 V/V, VOUT = 2 VPP, with VOCM adjusted
VOUT = 2 VPP, see 表9-1 for gain setting
图7-18. Harmonic Distortion vs Gain
图7-17. Harmonic Distortion vs VOCM
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.8 Typical Characteristics: (VS+) –(VS–) = 3 V
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
9
3
2
6
1
0
3
-1
-2
-3
-4
-5
-6
-7
-8
-9
0
-3
-6
-9
G = 0.1 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
VOUT = 20 mVpp
VOUT = 200 mVpp
VOUT = 1 Vpp
VOUT = 2 Vpp
VOUT = 4 Vpp
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D019
D020
VOUT = 20 mVPP, see 图8-1 and 表9-1 for resistor values
图7-19. Small-Signal Frequency Response vs Gain
See 图8-1
图7-20. Frequency Response vs VOUT
3
2
6
1
3
0
0
-1
-2
-3
-4
-5
-6
-3
-6
RL = 50 W
RL = 100 W
RL = 200 W
RL = 500 W
RL = 1000 W
VOCM = 0.8 V
VOCM = 1 V
VOCM = 1.5 V
-7
-8
-9
-9
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D02013
D022
VOUT = 20 mVPP, see 图8-1 with VOCM adjusted
VOUT = 20 mVPP, see 图8-1 with RL adjusted
图7-21. Small-Signal Frequency Response vs VOCM
图7-22. Small-Signal Frequency Response vs RL
3
2
120
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
110
1
100
90
80
70
60
50
40
30
20
10
0
0
-1
-2
-3
-4
-5
CL = 10 pF, RO = 113 W
-6
CL = 47 pF, RO = 54.9 W
CL = 100 pF, RO = 34.0 W
CL = 470 pF, RO = 10.5 W
CL = 1000 pF, RO = 5.1 W
-7
-8
-9
100k
1M
10M
Frequency (Hz)
100M
1
10
100
1000
Differential CL (pF)
D023
D024
VOUT = 20 mVPP, G = 1 V/V, two series RO added at output
before CL
Two RO at output to differential CL in parallel with a 1-kΩload
resistance
图7-23. Small-Signal Frequency Response vs CL
图7-24. Recommended RO vs CL
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.8 Typical Characteristics: (VS+) –(VS–) = 3 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
1.5
0.5
0.4
0.3
0.2
0.1
0
RO = 0 W
RO = 82.5 W
1
0.5
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1
0.2-V step, tR = 2 ns
0.5-V step, tR = 4 ns
1-V step, tR = 8 ns
2-V step, tR = 12ns
-1.5
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
D025
D026
G = 1 V/V, 5-MHz input, single-ended input to differential
output
G = 1 V/V, VOUT = 500-mV step into 22-pF CL, see 图8-4
图7-26. Step Response Into Capacitive Load
图7-25. Small- and Large-Signal Step Response
1.5
0.5
0.4
0.3
0.2
0.1
0
1
0.5
0
-0.1
-0.2
-0.3
-0.5
0.2-V step, tR = 2 ns
0.5-V step, tR = 2 ns
1-V step, tR = 6 ns
2-V step, tR = 12 ns
-1
RO = 0 W
-0.4
RO = 51.1 W
-1.5
-0.5
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
0
20
40
60
80 100 120 140 160 180 200
Time (ns)
D027
D028
G = 2 V/V, 5-MHz input, single-ended input to differential
output.
G = 2 V/V, VOUT = 500-mV step into 22-pF CL, see 图8-4
图7-28. Step Response Into Capacitive Load
图7-27. Small- and Large-Signal Step Response
0.2
6
0.2-V step, tR = 2 ns
1-V step, tR = 8 ns
2-V step, tR = 12 ns
Input
Output
0.15
0.1
4
2
0
0.05
0
-0.05
-0.1
-0.15
-0.2
-2
-4
-6
0
10
20
30
40
50
60
70
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time (ms)
1
Time D from 50% of Input Edge (ns)
D029
D030
Simulated with G = 1 V/V
Single-ended to differential gain of 2, 2X input overdrive
图7-29. Small- and Large-Signal Step Settling Time
图7-30. Overdrive Recovery Performance
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.8 Typical Characteristics: (VS+) –(VS–) = 3 V (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
-40
-50
-70
-80
HD2
HD3
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-60
-90
-70
-80
-100
-110
-120
-130
-140
-150
-90
-100
-110
-120
-130
-140
-150
10k
100k
1M
10M
0.1
1
Differential Output Voltage (Vpp)
4
Frequency (Hz)
D031
D032
G = 1 V/V, VOUT = 2 VPP
图7-31. Harmonic Distortion vs Frequency
G = 1 V/V
图7-32. Harmonic Distortion vs Output Swing
-40
-60
Max IMD3
Max IMD2
HD2, 100 kHz
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-70
-80
-90
-100
-110
-120
-130
-140
1M
10M
50
100
Differential Load Resistance (W)
1000
D034
Frequency (Hz)
D033
G = 1 V/V, 1 VPP each tone
G = 1 V/V, VOUT = 2-VPP output, with RL adjusted
图7-33. IMD2 and IMD3 vs Frequency
图7-34. Harmonic Distortion vs RL
-30
-50
-110
HD2, 10 kHz
HD2, 100 kHz
HD2, 1 MHz
HD3, 10 kHz
HD3, 100 kHz
HD3, 1 MHz
HD2, 100 kHz
HD3, 100 kHz
-115
-120
-125
-130
-135
-140
-70
-90
-110
-130
-150
0.8
1
1.2
1.4
VOCM - (VS-) (V)
1.6
1.8
2
1
10
Gain (V/V)
D035
D036
VOUT = 2-VPP output, with VOCM adjusted
图7-35. Harmonic Distortion vs VOCM
VOUT = 2-VPP output, see 表9-1 for gain setting
图7-36. Harmonic Distortion vs Gain
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.9 Typical Characteristics: 3-V to 5-V Supply Range
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
130
100
70
0
100
50
+5 V, Gain
+5 V, Phase
+3 V, Gain
+3 V, Phase
+5 V, G = 1 V/V
+5 V, G = 2 V/V
+5 V, G = 5 V/V
+3 V, G = 1 V/V
+3 V, G = 2 V/V
+3 V, G = 5 V/V
20
10
5
-50
2
1
0.5
-100
-150
-200
-250
0.2
0.1
0.05
40
0.02
0.01
0.005
10
0.002
0.001
-20
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
10k
100k
1M
Frequency (Hz)
10M
100M
D038
D037
Simulated closed-loop differential output impedance
Simulated with a 1-kΩdifferential load and 0.6-pF internal
feedback capacitors removed
图7-38. Closed-Loop Output Impedance vs Frequency
图7-37. Main Amplifier Differential Open-Loop Gain and Phase
vs Frequency
20
10
90
85
80
75
70
65
60
1
55
+5 V, En
+5 V, In
+3 V, En
+3 V, In
+5 V, SSOB
+5 V, 2-VPP OB
+3 V, SSOB
50
45
+3 V, 2-VPP OB
40
0.1
10
100
1k 10k
Frequency (Hz)
100k
1M
10k
100k
1M
10M
Frequency (Hz)
D039
D040
.
Differential mode output to common-mode output, simulated
with G = 1 V/V
图7-39. Input Spot Noise vs Frequency
图7-40. Output Balance vs Frequency
120
115
110
105
100
95
120
+5 V
+3 V
110
100
90
80
90
+5 V, VS+
+5 V, VS-
+3 V, VS+
+3 V, VS-
70
85
80
60
1k
10k
100k
Frequency (Hz)
1M
10M
1k
10k
100k
Frequency (Hz)
1M
10M
D041
D042
Common-mode input to differential output, simulated with G =
1 V/V
Single-ended to differential gain of 1, PSRR simulated to
differential output
图7-41. CMRR vs Frequency
图7-42. Power-Supply Rejection Ratio vs Frequency
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7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
3
2
0.6
0.4
0.2
0
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-0.2
-0.4
-0.6
+5 V, 100 mVpp
+5 V, 1 Vpp
+3 V, 100 mVpp
+3 V, 1 Vpp
+5 V, 0.2-V step
+5 V, 1-V step
+3 V, 0.2-V step
+3 V, 1-V step
100k
1M
10M
100M
D043
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Time(ms)
1
Frequency (Hz)
D044
图7-43. Common-Mode Voltage, Small- and Large-Signal
图7-44. Common-Mode Voltage, Small- and Large-Step
Response (VOCM Pin Driven)
Response (VOCM Pin Driven)
1000
3
+3 V, VOCM Pin Driven
+5 V, VOCM Pin Driven
+3 V, VOCM Pin Floating
+5 V, VOCM Pin Floating
+3 V
+5 V
2
1
100
0
10
100
-1
1k
10k 100k
Frequency (Hz)
1M
10M
0
0.5
1
1.5
2
VOCM - (VS-) (V)
2.5
3
3.5
4
D045
D046
The VOCM pin is either driven to midsupply by low-impedance
source or allowed to float and default to midsupply
Average VOCM output offset of 39 units, standard deviation < 2
mV
图7-45. Output Common-Mode Noise vs Frequency
图7-46. VOCM Offset vs VOCM Setting
120
120
+5 V
+3 V
+5 V
+3 V
115
110
105
100
95
115
110
105
100
95
90
90
85
85
80
80
0
1
2
VOCM - (VS-) (V)
3
4
5
0
1
2
VOCM - (VS-) (V)
3
4
5
D047
D048
Simulated with single-ended to differential gain of 1 , PSRR
for negative supply to differential output
Simulated with single-ended to differential gain of 1, PSRR for
positive supply to differential output
图7-47. –PSRR vs VOCM Approaching VS–
图7-48. +PSRR vs VOCM Approaching VS+
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7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
80
72
64
56
48
40
32
24
16
8
60
50
40
30
20
10
0
+5 V
+3 V
+5 V
+3 V
0
Input Offset Current (nA)
D050
Input Offset Voltage (mV)
D049
Total of 234 DGK units trimmed at a 5-V supply
图7-50. Input Offset Current (IOS
Total of 234 DGK units trimmed at a 5-V supply
)
图7-49. Input Offset Voltage (VIO
)
100
80
50
40
60
30
40
20
20
10
0
0
-20
-40
-60
-80
-100
-10
-20
-30
-40
-50
-40
-20
0
20
40
60
80
100
120
-40
-20
0
20
40
60
80
100
120
Ambient Temperature (èC)
Ambient Temperature (èC)
D051
D052
5-V and 3-V delta from 25°C VIO, 50 DGK units
5-V and 3-V delta from 25°C IOS, 50 DGK units
图7-51. Input Offset Voltage vs Temperature
图7-52. Input Offset Current vs Temperature
14
40
+5 V
+3 V
+5 V
+3 V
36
12
32
28
24
20
16
12
8
10
8
6
4
2
4
0
0
D054
D053
Input Offset Voltage Drift (mV/èC)
Input Offset Current Drift (nA/èC)
–40°C to +125°C endpoint drift, total of 62 DGK units
图7-53. Input Offset Voltage Drift Histogram
–40°C to +125°C endpoint drift, total of 62 DGK units
图7-54. Input Offset Current Drift Histogram
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
7.9 Typical Characteristics: 3-V to 5-V Supply Range (continued)
at TA ≈25°C, VOCM pin = open, RF = 1 kΩ, RL = 1 kΩ, VOUT = 2 VPP, 50-Ωinput match, G = 1 V/V, PD = VS+, single-
ended input, differential output, and input and output referenced to default midsupply for ac-coupled tests (unless otherwise
noted); see 图8-1 for a gain of 1-V/V test circuit
2.5
2
1.6
1.4
1.2
1
1.5
1
0.5
0
ê1.5 V, Pos
ê1.5 V, Neg
ê2.5 V, Pos
ê2.5 V, Neg
0.8
0.6
0.4
0.2
0
-0.5
-1
-1.5
-2
+3 V
+5 V
-2.5
50
100
Differential Load Resistance (W)
1000
0
1
2
3
Disable Pin Voltage (V)
4
5
D055
D056
Maximum differential output swing, VOCM at midsupply
.
图7-55. ±Maximum VOUT vs Differential Load Resistance
图7-56. Supply Current vs PD Voltage
200
70
65
60
55
50
45
40
35
30
25
20
15
10
5
+5 V
+3 V
+5 V
+3 V
180
160
140
120
100
80
60
40
20
0
0
Common Mode Offset Voltage (mV)
D057
D058
Common Mode Offset Voltage (mV)
VOCM input floating, total of 240 units
VOCM Input driven to midsupply, total of 240 units
图7-57. Common-Mode Output Offset from VS+ / 2 Default Value
图7-58. Common-Mode Output Offset from Driven VOCM
Histogram
Histogram
7
7
+5 V, PD
+5 V, VOUT
+3 V, PD
+3 V, VOUT
+5 V, PD
6
5
6
5
+5 V, VOUT
+3 V, PD
+3 V, VOUT
4
4
3
3
2
2
1
1
0
0
-1
-2
-1
-2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
Time (ms)
Time (ms)
D059
D060
5 MHz, 2-VPP input, G = 1 V/V, see 图8-1
图7-59. PD Turn-On Waveform
5 MHz, 2-VPP input, G = 1 V/V, see 图8-1
图7-60. PD Turn-Off Waveform
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8 Parameter Measurement Information
8.1 Example Characterization Circuits
The THS4551 offers the advantages of a fully differential amplifier (FDA) design with the trimmed input offset
voltage and very low drift of a precision op amp. The FDA is an extremely flexible device where the main aim is
to provide a purely differential output signal centered on a user-configurable common-mode voltage usually
matched to the input common-mode voltage required by an analog-to-digital converter (ADC) following this
stage. The primary options revolve around the choices of single-ended or differential inputs, ac-coupled or dc-
coupled signal paths, gain targets, and resistor value selections. The characterizations described in this section
focus on single-ended input to differential output designs as the more challenging application requirement.
Differential sources can certainly be supported and are often simpler to both implement and analyze.
The characterization circuits are typically operated with a single-ended, matched, 50-Ω, input termination to a
differential output at the FDA output pins because most lab equipment is single-ended. The FDA differential
output is then translated back to single-ended through a variety of baluns (or transformers), depending on the
test and frequency range. DC-coupled step response testing used two 50-Ω scope inputs with trace math.
Single-supply operation is most common in end equipment designs. However, using split balanced supplies
allows simple ground referenced testing without adding further blocking capacitors in the signal path beyond
those capacitors already within the test equipment. The starting point for any single-ended input to differential
output measurements (such as any of the frequency response curves) is shown in 图8-1 (available as a TINA-TI
™ simulation file).
THS4551 Wideband,
Fully Differential Amplifier
-31.8-dB
Insertion Loss
from VOPP to a
50-ꢀ Load
50-ꢀ Input Match,
Gain of 1 V/V from RT,
Single-Ended Source to
Differential Output
RF1
1 kꢀ
RO1
487 ꢀ
VS+
RG1
1 kꢀ
Network
Analyzer,
50-ꢀ Load
ADTL1-4-75+
N1
Network
Analyzer,
50-ꢀ Source
Impedance
œ
50-ꢀ
Single-Ended
Source
+
RM
52.3 ꢀ
RT1
52.3 ꢀ
VOPP
VOCM
FDA
RO2
487 ꢀ
œ
N2
+
PD
RG2
1 kꢀ
VS+
VS-
1-kꢀ
Differential
Load
50-ꢀ Termination
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
RS1
50 ꢀ
RT2
52.3 ꢀ
图8-1. Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit
Most characterization plots fix the RF (RF1 = RF2) value at 1 kΩ, as shown in 图 8-1. This element value is
completely flexible in application, but 1 kΩ provides a good compromise for the parasitic issues linked to this
value, specifically:
• Added output loading: the FDA functions similarly to an inverting op amp design with both feedback resistors
appearing as an added load across the outputs (the approximate total differential load in 图8-1 is 1 kΩ||
2 kΩ= 667 Ω). The 1-kΩvalue also reduces the power dissipated in the feedback networks.
• Noise contributions resulting from resistor values: these contributions are both the 4kTRF terms and the
current noise times the RF value to the output (see 节10.1.1).
• Parasitic feedback pole at the input summing nodes: this pole is created by the feedback resistor (RF) value
and the 1.2-pF differential input capacitance (as well as any board layout parasitic) and introduces a zero in
the noise gain, thus decreasing the phase margin in most situations. This effect must be managed for best
frequency response flatness or step response overshoot. Internal 0.6-pF feedback capacitors on each side
combine with these external feedback resistors to introduce a zero in the noise gain, thereby reducing the
effect of the feedback pole to the differential input capacitance.
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The frequency domain characterization curves start with the selections of 图 8-1. Some of the features in this
test circuit include:
• The elements on the non-signal input side exactly match the signal input resistors. This feature has the effect
of more closely matching the divider networks on each side of the FDA. The three resistors on the non-signal
input side can be replaced by a single resistor to ground using a standard E96 value of 1.02 kΩwith some
loss in gain balancing between the two sides; see 节9.3.4).
• Translating from a 1-kΩdifferential load to a 50-Ωenvironment introduces considerable insertion loss in the
measurements (–31.8 dB in 图8-1). The measurement path insertion loss is normalized out when reporting
the frequency response curves to show the gain response to the FDA output pins.
• In the pass band for the output balun, the network analyzer 50-Ωload reflects to be in parallel with the 52.3-
Ωshunt termination. These elements combine to show a differential 1-kΩload at the output pins of the
THS4551. The source impedance presented to the balun is a differential 50-Ωsource. 图8-2 and 图8-3
show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response flatness for this
relatively low-frequency balun providing 0.1-dB flatness through 100 MHz.
L1's Inductance : 198.94 uH
L2's Inductance : 198.94 uH
Mutual Inductance : 198.92972 uH
R1 25
R2 25
ADTL1-4-75 Model 198.94u
+
VG1
V
VM1
图8-2. Output Measurement Balun Simulation Circuit in TINA-TI™
-6
-6.01
-6.02
-6.03
-6.04
-6.05
-6.06
-6.07
-6.08
-6.09
-6.1
10
8
6
4
2
0
-2
-4
-6
-8
-10
Gain (dB)
Phase (deg)
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D061
图8-3. Output Measurement Balun Flatness Test
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Starting from the test circuit of 图 8-1, various elements are modified to show the effect of these elements over a
range of design targets, specifically:
• The gain setting is changed by adjusting the RT and the two RG elements to provide a 50-Ωinput match and
setting the feedback resistors to 1 kΩ.
• Output loading of both resistive and capacitive load testing. Changing to lower resistive loads is
accomplished by adding parallel resistors across the output pins in 图8-1. Changing to capacitive loads adds
series output resistors to a differential capacitance before the 1-kΩsense path of 图8-1.
• Power-supply settings. Most often, a single 5-V test uses a ±2.5-V supply and a 3-V test uses ±1.5-V supplies
with the VOCM input control at ground.
• The disable control pin ( PD) is tied to the positive supply (VS+) for any active channel test.
8.2 Output Interface Circuit for DC-Coupled Differential Testing
The pulse response plots were taken using the output circuit of 图 8-4. The two sides of this circuit present a
500-Ω load to ground (for a differential 1-kΩ load) with a 50-Ω source to the two scope inputs. Trace math is
used to combine the two sides into the pulse response plots of 图 7-7 to 图 7-10 and 图 7-25 to 图 7-28. Using
balanced bipolar supplies for this test ensures that the THS4551 outputs deliver a ground-centered differential
swing. This setup produces no dc load currents using the circuit of 图8-4.
RO1
475 ꢀ
50-ꢀ
Scope
Input
RM1
56.2 ꢀ
THS4551
Output
RM1
56.2 ꢀ
RO2
475 ꢀ
50-ꢀ
Scope
Input
Copyright © 2016, Texas Instruments Incorporated
图8-4. Output Interface for DC-Coupled Differential Outputs
8.3 Output Common-Mode Measurements
The circuit of 图8-5 is a typical setup for common-mode measurements.
THS4551 Wideband,
Fully Differential Amplifier
RG1
1 kꢀ
RF1
1 kꢀ
VS+
100 ꢀ
100 ꢀ
50-ꢀ
Measurement
Equipment
RS
49.9 ꢀ
Signal
Source
VOCM
Input
œ
+
FDA
œ
RT
49.9 ꢀ
+
PD
VS+
VS-
RT
1 kꢀ
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图8-5. Output Common-Mode Measurements
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In 图 8-5, the differential path is simply terminated back to ground on the two 1-kΩ input resistors and the VOCM
control input is driven from a 50-Ω matched source for the frequency response and step response curves of 图
7-43 and 图 7-44. The outputs are summed to a center point (to obtain the average, or common-mode, output)
through two 100-Ω resistors. These 100-Ω resistors form an equivalent 50-Ω source to the common-mode
output for measurements. This common-mode test circuit is available as a TINA-TI™ simulation file. 图 7-45
illustrates the common-mode output noise measurements with either a ground on the VOCM input pin or with the
VOCM input pin floating. The higher noise in 图 7-45 for a floated input can be reduced by including a capacitor
to ground at the VOCM control input pin.
8.4 Differential Amplifier Noise Measurements
To extract out the input-referred noise terms from the total output noise, a measurement of the differential output
noise is required under two external conditions to emphasize the different noise terms. A high-gain, low resistor
value condition is used to emphasize the differential input voltage noise and a higher RF at low gains is used to
emphasize the two input current noise terms. The differential output noise must be converted to single-ended
with added gain before being measured by a spectrum analyzer. At low frequencies, a zero 1/f noise, high-gain,
differential to single-ended instrumentation amplifier (such as the INA188) is used. At higher frequencies, a
differential to single-ended balun is used to drive into a high-gain, low-noise, op amp (such as the LMH6629). In
this case, the THS4551 outputs drive 25-Ω resistors into a 1:1 balun where the balun output is terminated
single-endedly at the LMH6629 input with 50 Ω. This termination provides a modest 6-dB insertion loss for the
THS4551 differential output noise that is then followed by a 40-dB gain setting in the very wideband LMH6629.
8.5 Balanced Split-Supply Versus Single-Supply Characterization
Although most end applications use a single-supply implementation, most characterizations are done on a split
balanced supply. Using a split balanced supply keeps the I/O common-mode inputs near midsupply and provides
the most output swing with no dc bias currents for level shifting. These characterizations include the frequency
response, harmonic distortion, and noise plots. The time domain plots are in some cases done via single-supply
characterization to obtain the correct movement of the input common-mode voltage.
8.6 Simulated Characterization Curves
In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario
is the output balance plot of 图 7-40. This plot shows the best-case output balance (output differential signal
versus output common-mode signal) using exact matching on the external resistors in simulation using a single-
ended input to differential output configuration. The actual output balance is set by resistor mismatch at low
frequencies but intersects and follows the high-frequency portion of 图7-40.
The remaining simulated plots include:
• AOL gain and phase, see 图7-37.
• Large- and small-signal settling times, see 图7-11 and 图7-29.
• Closed-loop output impedance versus frequency, see 图7-38.
• CMRR vs frequency, see 图7-41.
• PSRR vs frequency and output common-mode voltage, see 图7-42, 图7-47, and 图7-48.
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8.7 Terminology and Application Assumptions
Numerous common terms that are unique to this type of device exist. This section identifies and explains these
terms.
• Fully differential amplifier (FDA). This term is restricted to devices offering what appears similar to a
differential inverting op amp design element that requires an input resistor (not a high-impedance input) and
includes a second internal control loop that sets the output average voltage (VOCM) to a default or set point.
This second common-mode control loop interacts with the differential loop in certain configurations.
• The desired output signal at the two output pins is a differential signal that swings symmetrically around a
common-mode voltage, which is the average voltage for the two outputs.
• Single-ended to differential. The output must always be used differentially in an FDA; however, the source
signal can be either a single-ended or a differential source with a variety of implementation details for either
source. For an FDA operating in single-ended to differential, only one of the two input signals is applied to
one of the input resistors.
• The common-mode control has limited bandwidth from the input VOCM pin to the common-mode output
voltage. The internal loop bandwidth beyond the input VOCM buffer is a much wider bandwidth than the
reported VOCM bandwidth, but is not directly discernable. A very wide bandwidth in the internal VOCM loop is
required to perform an effective and low-distortion single-ended to differential conversion.
Several features in the application of the THS4551 are not explicitly stated, but are necessary for correct
operation. These features are:
• Good power-supply decoupling is required. Often a larger capacitor (2.2 µF, typical) is used along with a high-
frequency, 0.1-µF supply decoupling capacitor at the device supply pins (share this capacitor with the four
supply pins in the RGT package). For single-supply operation, only the positive supply has these capacitors.
Where a split supply is used, connect these capacitors to ground on both sides with the larger capacitor
placed some distance from the package and shared among multiple channels of the THS4551, if used. A
separate 0.1-µF capacitor must be provided to each device at the device power pins. With cascaded or
multiple parallel channels, including ferrite beads from the larger capacitor to the local high-frequency
decoupling capacitor is often useful.
• Although often not stated, the power disable pin ( PD) is tied to the positive supply when only an enabled
channel is desired.
• Virtually all ac characterization equipment expects a 50-Ωtermination from the 50-Ωsource and a 50-Ω,
single-ended source impedance from the device outputs to the 50-Ωsensing termination. This condition is
achieved in all characterizations (often with some insertion loss) but is not necessary for most applications.
Matching impedance is most often required when transmitting over longer distances. Tight layouts from a
source, through the THS4551, and to an ADC input do not require doubly-terminated lines or filter designs.
The only exception is if the source requires a defined termination impedance for correct operation (for
example, mixer outputs).
• The amplifier signal path is flexible for use as single- or split-supply operation. Most applications are intended
to be single supply, but any split-supply design can be used as long as the total supply voltage across the
TH4551 is less than 5.5 V and the required input, output, and common-mode pin headrooms to each supply
are taken into account. When left open, the VOCM pin defaults to near midsupply for any combination of split
or single supplies used. The disable pin ( PD) is referenced to the negative rail. Using a negative supply
requires that PD be pulled down to within 0.55 V of the negative supply to disable the amplifier.
• External element values are normally assumed to be accurate and matched. In an FDA, this assumption
translates to equal feedback resistor values and a matched impedance from each input summing junction to
either a signal source or a dc bias reference on each side of the inputs. Unbalancing these values introduces
non-idealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides creates a
common-mode to differential conversion. Furthermore, mismatched RF values and feedback ratios create
additional differential output error terms from any common-mode dc or ac signal or noise terms. Using
standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio
mismatch. Modestly mismatched resistors or ratios do not by themselves degrade harmonic distortion. Where
there is a meaningful common-mode noise or distortion coming in that gets converted to differential via an
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element or ratio mismatch. For the best dc precision, use 0.1% accuracy resistors that are readily available in
E96 values (1% steps).
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9 Detailed Description
9.1 Overview
In addition to the core differential I/O voltage feedback gain block, there are two 5.2-kΩ resistors internally
across the outputs to sense the average voltage at the outputs. These resistors feed the average voltage back
into a VCM error amplifier where the voltage is compared to either a default voltage divider across the supplies or
an externally set VOCM target voltage. When the amplifier is disabled, the default midsupply bias string is
disabled to save power.
To achieve the very-low noise at the low power provided by the THS4551, the input stage transistors are
relatively large, thus resulting in a higher differential input capacitance (1.2 pF in the 节 9.2). As a default
compensation for the 1.2-pF differential input capacitance and the 1-kΩ feedback resistors used in
characterization, internal 0.6-pF capacitors are placed between the two output and input pins. Adjust any desired
external feedback capacitor value to account for these 0.6-pF internal elements. When using the 16-pin WQFN
package and the internal feedback traces to the input side of the package, include the nominal trace impedance
of 3.3 Ωin the design. These elements are not included in the TINA-TI™ model and must be added externally to
a design intending to use the RGT package.
9.2 Functional Block Diagram
VS+
3.3 ꢀ
(RGT Package) FB+
0.6 pF
OUT+
œ
INœ
5.2 kꢀ
5.2 kꢀ
High-AOL
Differential I/O
Amplifier
+
1.2 pF
œ
IN+
+
OUTœ
0.6 pF
VS+
3.3 ꢀ
(RGT Package) FBœ
300 kꢀ
VSœ
œ
VCM
Error
Amplifier
+
VOCM
CMOS
Buffer
PD
300 kꢀ
VSœ
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9.3 Feature Description
9.3.1 Differential Open-Loop Gain and Output Impedance
The most important elements to the closed-loop performance are the open-loop gain and open-loop output
impedance. 图 9-1 and 图 9-2 show the simulated differential open-loop gain and phase from the differential
inputs to the differential outputs with no load and with a 100-Ω load. Operating with no load removes any effect
introduced by the open-loop output impedance to a finite load. This AOL simulation removes the 0.6-pF internal
feedback capacitors to isolate the forward path gain and phase (see 图 13-1). The 0.6-pF capacitance becomes
part of the feedback network that sets the noise gain and phase combined with the external elements. The
simulated differential open-loop output impedance is shown in 图9-3.
80
70
60
50
40
30
20
10
0
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
-200
-210
100 W Load
No Load
No Load
100 W Load
-10
-20
100k
1M
10M
Frequency (Hz)
100M
1G
100k
1M
10M
Frequency (Hz)
100M
1G
D064
D063
图9-2. No-Load and 100-ΩAOL Phase
图9-1. No-Load and 100-ΩLoaded AOL Gain
10000
1000
100
10
1
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
D062
图9-3. Differential Open-Loop Output Impedance
This impedance combines with the load to shift the apparent open-loop gain and phase to the output pins when
the load changes. The rail-to-rail output stage shows a very high impedance at low frequencies that reduces with
frequency to a lower midrange value and then peaks again at higher frequencies. The maximum value at low
frequencies is set by the common-mode sensing resistors to be a 10.5-kΩ dc value (see 节 9.2). This high
impedance at a low frequency is significantly reduced in closed-loop operation by the loop gain, as shown in the
closed-loop output impedance of 图7-38. 图9-1 compares the no load AOL gain to the AOL gain driving a 100-Ω
load that shows the effect of the output impedance. The heavier loads pull the AOL gain down faster to lower
crossovers with more phase shift at the lower frequencies.
The much faster phase rolloff for the 100-Ω differential load explains the greater peaked response illustrated in
图7-4 and 图7-22 when the load decreases. This same effect happens for the RC loads common with converter
interface designs. Use the TINA-TI™ model to verify loop phase margin in any design.
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9.3.2 Setting Resistor Values Versus Gain
The THS4551 offers considerable flexibility in the configuration and selection of resistor values. The design
starts with the selection of the feedback resistor value. The 1-kΩ feedback resistor value used for the
characterization curves is a good compromise between power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired
gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance
that is the sum of the two input resistors. Single-ended input to differential output designs present a more
complicated input impedance. Most characteristic curves implement the single-ended to differential design as the
more challenging requirement over differential-to-differential I/O.
For single-ended, matched, input impedance designs, 表 9-1 illustrates the suggested standard resistors set to
approximately a 1-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a single
resistor on the non-signal input side for gain matching. Better matching is possible using the same three
resistors on the non-signal input side as on the input side. 图 9-4 shows the element values and naming
convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the
differential output.
THS4551 Wideband,
Fully Differential Amplifier
50-ꢀ Input Match,
Gain of 1 V/V from RT,
Single-Ended Source to
Differential Output
RF1
1 kꢀ
50-ꢀ
Source
Impedance
VS+
RS1
50 ꢀ
RG1
1 kꢀ
VOPP
œ
+
RL
1 kꢀ
RT
52.3 ꢀ
VOCM
FDA
œ
+
PD
RG2
1.02 kꢀ
VS+
VS-
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图9-4. Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor Values
Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV),
the required input RT value is given by solving the quadratic of 方程式1.
RS
≈
’
2
2RS 2RF +
AV
2RFRS2AV
∆
÷
2
«
◊
2
RT - RT
-
= 0
2RF 2 + A - R A (4 + A ) 2RF 2 + A - R A (4 + A )
V
S
V
V
V
S
V
V
(1)
When this value is derived, the required input side gain resistor is given by 方程式2 and then the single value for
RG2 on the non-signal input side is given by 方程式3:
RF
2
- RS
AV
RG1
=
RS
RT
1+
(2)
RF
2
AV
RS
RG2
=
1+
RT
(3)
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Using these expressions to generate a swept gain table of values results in 表 9-1, where the best standard 1%
resistor values are shown to minimize input impedance and gain error to target.
表9-1. Swept Gain 50-ΩInput Match with RF = 1-kΩ(±1 Standard Values)
GAIN (V/V)
RF
RG1
10000
976
RT
RG2
10000
1000
523
ZIN
49.66
49.2
48.9
50.2
50.6
AV
0.1
1
1000
1000
1020
1000
1020
49.9
51.1
52.3
59
0.09965
1.0096
1.988
2
499
5
187
215
5.057
10
88.7
69.8
118
10.09
Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without
an additional resistor to ground (remove RT in 图 9-4). This scenario is common when coming from the output of
another single-ended op amp (such as the OPA192). This single-ended to differential stage shows a higher input
impedance than the physical RG as given by the expression for ZA (active input impedance) shown as 方程式4.
≈
∆
«
’≈
÷∆
◊«
’
÷
◊
RG1
RG2
RF
1+
1+
RG1
ZA = RG1
RF
2 +
RG2
(4)
Using 方程式 4 for the gain of 1 V/V with all resistors equal to 1-kΩ shows an input impedance of 1.33 kΩ. The
increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the
same direction as the input signal. The common-mode input voltage must move to create the current in the non-
signal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is
impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent
input impedance in the signal input path.
9.3.3 I/O Headroom Considerations
The starting point for most designs is to assign an output common-mode voltage for the THS4551. For ac-
coupled signal paths, this voltage is often the default midsupply voltage to retain the most available output swing
around the voltage centered at the VOCM voltage. For dc-coupled designs, set this voltage with consideration to
the required minimum headroom to the supplies as described in the specifications of the Electrical
Characteristics table for the VOCM control. For precision ADC drivers, this output VOCM becomes the input VCM to
the ADC. Often, VCM is set to VREF / 2 to center the differential input on the available input when precision ADCs
are being driven.
From the target output VOCM, the next step is to verify that the desired output differential peak-to-peak voltage
(VOPP) stays within the supplies. For any desired differential VOPP, make sure that the absolute maximum
voltage at the output pins swings with 方程式 5 and 方程式 6 and confirm that these expressions are within the
supply rails minus the output headroom required for the RRO device.
VOPP
VOmax = VOCM
+
4
(5)
(6)
VOPP
VOmin = VOCM
-
4
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For instance, when the THS4551 drives the ADC3223 with a 0.95-VCM control using a single 3.0-V supply, the
negative-going signal sets the maximum output swing from 0.95 VCM to 0.2 V above ground. This 0.75-V, single-
sided swing becomes an available 4 × 0.75 V = 3-VPP differential around the nominal 0.95-VCM output common-
mode voltage. On the high side, the maximum output is equal to 1.7 V (0.95 V + 0.75 V), which is well within the
allowed maximum range of 2.8 V (3.0 V – 0.2 V). This available 3-VPP maximum differential output is also well
beyond the maximum value required for the 2-VPP input ADS3223.
With the output headrooms confirmed, the input junctions must also stay within the operating range. The input
range limitations only appear when approaching the positive supply where a maximum 1.3-V headroom is
required over the full temperature range because the input range extends to the negative supply voltage over the
full temperature range.
The input pins operate at voltages set by the external circuit design, the required output VOCM, and the input
signal characteristics. For differential-to-differential designs where there is no signal-related movement in the
input VICM voltages, ac-coupled differential input designs have a VICM equal to the output VOCM. Going towards
the positive supply, the output common-mode can be set to within 1.2 V of the supply. AC-coupled input designs
violate the required 1.3-V headroom on the input pins in this case. Going towards the negative supply on the
VOCM setting requires a minimum of 0.55 V above the supply. This extreme is always in range for the input pins
that require a minimum 0-V headroom to the negative supply.
DC-coupled differential input designs must check the voltage divider from the source common-mode input
voltage to the THS4551 VOCM setting. This result must be equal to an input VICM within the specified range. If the
source VCM can vary over some voltage range, validate this result over that range before proceeding.
For single-ended input to differential output designs, the VICM is nominally at a voltage set by the external
configuration with a small swing around the nominal value because of the common-mode loop. An ac-coupled,
single-ended input to differential output design places an average input VICM equal to the output VOCM for the
FDA with an ac-coupled swing around the VOCM voltage following the input voltage. A dc-coupled, single-ended
input to differential design gets a nominal input VICM set by the source signal common-mode level and the VOCM
output voltage with a small signal-related swing around the nominal VICM voltage.
One approach to deriving the VICM voltage range for any single-ended input to differential output design is to
observe the output voltage swing on the non-signal input side of the FDA outputs and simply take the voltage
division on the input pin to ground or to the dc reference used on that side. An example analysis is shown in 图
9-5 using a Thevenized version of the gain of 2 values listed in 表 9-1 for a 50-Ω matched impedance, ac-
coupled design.
In this example, a single 3.3-V supply is used with the VOCM defaulted to midsupply or 1.65 V as a common-
mode output voltage. This value is also the common-mode voltage on the input pins for the ac-coupled input to
the FDA. Targeting a 4-VPP differential output swing means each output pin swings ±1 V around this 1.65-V
common-mode voltage. This output swing is in range because the full swing is 0.65 V to 2.65 V relative to
ground, which is well within the 0.2-V output headroom requirements on a single 3.3-V supply.
THS4551 Wideband,
Fully Differential Amplifier
RF1
1.02 kꢀ
Thevinized
Source
VS+
RS1
25.6 ꢀ
RG1
499 ꢀ
1 µF
VS+
VS-
VOUT = 4-VPP
Differential
œ
VOCM
+
RL
1 kꢀ
+
+
FDA
3.3 V
0 V
VIN
= 1.022 V
œ
œ
œ
1 µF
+
PD
VS+
1 µF
VS-
RG2
523 ꢀ
RF2
1.02 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图9-5. Input Swing Analysis Circuit with AC-Coupled, Single-Ended to Differential Signal Path
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The output on the lower side of this design ranges from 0.65 V to 2.65 V. This 2-VPP swing (on just one side, the
other output is an inverted version and gives the 4-VPP differential maximum) is divided back by the RF2 and RG2
divider to the input pins to form a common-mode input swing on top of the 1.65-V input common-mode voltage.
This divider is 0.339 × 2 VPP = 0.678 VPP or ±0.34 V around the 1.65-V input common-mode voltage. The 1.31-V
to 1.99-V common-mode input swing for this design is in range for the 0 V to 2.2 V available input range (the
maximum headroom is 3.3 V – 1.1 V, which is equal to 2.2 V). These voltage swings can be directly observed
using the SBOC460 TINA-TI™ simulation file. Shifting the VOCM down slightly (if allowed by the design
requirements) is a good way to improve the positive-swinging input headroom for this low-voltage design.
Taking a more complex example by using the THS4551 to attenuate a large bipolar input signal in a dc-coupled
design for an ADC is shown in 图9-6. To remove the peaking for this low-noise gain design, the two CF elements
and an input capacitor are added to shape the noise gain at high frequencies to a capacitive divider, as
described in the 节 10.1.6. In this example (including the 1.2-pF internal differential capacitor at the inputs and
the 0.6-pF internal feedback capacitors), the high-frequency noise gain is 3 V/V and a flat frequency response
with approximately 45 MHz of –3-dB BW is delivered.
3.1 pF
THS4551 Wideband,
Fully Differential Amplifier
Gain of 0.2 V/V,
DC-Coupled,
Single-Ended Source to
Differential Output
10 kꢀ
RF1
1 kꢀ
VOCM
VOUT = 7.2 VPP
Differential
+
1 µF
4.096 V
10 kꢀ
œ
VS+
RG1
4.99 kꢀ
œ
A 1-kꢀ load is very
+
RL
1 kꢀ
VOCM
2.6 pF
FDA
important to include because
of high-frequency resonance;
no load may oscillate.
œ
VS
= 18 V
VS+
VS-
+
PD
VS+
+
+
VS-
5 V
0 V
œ
For Attenuator Design:
NG1 = 1.2
NG2 = 3
GBP = 135 MHz
Zo = 14.3 MHz
œ
RF2
1 kꢀ
RG2
4.99 kꢀ
3.1 pF
Copyright © 2016, Texas Instruments Incorporated
图9-6. DC-Coupled, Single-Ended to Differential Attenuator Design
In this example, the output VOCM is 4.096 V / 2, which equals 2.048 V and the source signal VCM is 0 V. These
values set the nominal input pin VICM to 2.048 V × 4.99 kΩ / (4.99 kΩ + 1 kΩ) = 1.71 V. Applying a ±18-V input
at the 4.99-kΩ input resistor produces a 7.2-VPP differential output. That is, a ±1.8-V swing on the lower output
side around the 2.048-V common-mode voltage. This 0.248-V to 3.84-V relative-to-ground swing at the output is
well within the 0.2-V output headrooms to the 0-V to 5-V supplies used in the example in 图 9-6 (with the same
swing inverted on the other output side). That output swing on the lower side produces an attenuated input
common mode swing of (±1.8 V × (4.99 kΩ / (4.99 kΩ + 1 kΩ)) = ±1.5 V around the midscale input bias of
1.71 V. This 0.2-V to 3.2-V input common-mode swing is well within the available 0-V to 3.8-V input range. This
±18-V bipolar input signal is delivered to a SAR ADC with a 7.2-VPP differential output with all I/O nodes
operating in range using a single 5-V supply design. The source must sink the 2.048 V / 5.99 kΩ = 0.34-mA
common-mode level-shifting current to take the input 0-V common-mode voltage up to the midscale 1.71-V VICM
operating voltage. Using the single-ended input impedance of 方程式 4, the source must also drive an apparent
input load of 5.44 kΩ.
Most designs do not run into an input range limit. However, using the approach shown in this section can allow a
quick assessment of the input VICM range under the intended full-scale output condition. The TINA-TI™
simulation file for 图 9-6 can be used to plot the input voltages under the intended swings and application circuit
to verify that there is no limiting from this effect. Driving the I/O nodes out of range in the TINA-TI™ model
results in convergence problems. Increasing the positive and negative supplies slightly in simulation is an easy
way to discover the simulated swings that might be going out of range.
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As a third example of arriving at the input pin voltage swings, use the design of 图 10-17 (the ADC3241 design).
Thevenize the source to just one input resistor to get an expression for the input VICM in terms of the input
voltage to be derived. 图 9-7 shows the gain of 5 V/V, dc-coupled, matched input impedance, single-ended to
differential circuit of 图 10-17 with both sides reduced to a single input resistor. In 图 10-17, the design operates
on a single 3.3-V supply with an output VOCM equal to 0.95 V to directly connect to TI’s line of low-power
ADC3xxx series of 12- and 14-bit ADCs. This family accepts a 2-VPP maximum differential voltage, which (at the
input-terminating resistor of 图 10-17) is a ±0.2-V swing. Going back to the source through the matching resistor
is then a ±0.4-V source swing. Thevenizing that source with the RT element provides the ±0.217 V shown in 图
9-7 and the total R2 as the sum of RG1 and 50 Ω|| 59 Ω.
THS4551 Wideband,
Fully Differential Amplifier
RF1
1 kꢀ
VOUT
VS+
Thevinized
Source
R2
215 ꢀ
1-V Differential Output
Centered on 0.95 VCM
VS+
VOCM
VS-
œ
+
RL
1 kꢀ
+
+
+
VOCM
FDA
VTHEV
0.217 V
0 V
3.3 V
0.95 V
œ
œ
œ
œ
+
PD
R2
215 ꢀ
VS+
VS-
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图9-7. Input VICM Analysis Circuit From the Design of 图10-17
For an input signal (VTHEV) that swings around ground as ±VTHEV, the input pins are within a range given by 方程
式 7, which is a superposition of the output VOCM divided back to the input nodes and half of the input ±VTHEV
signal.
RG
VTHEV
RF
V
= VOCM
ê
ì
ICM
RG + RF
2
RF +RG
(7)
Using the values from the design of 图9-7, the computed input range for the THS4551 input pins is VICM = 0.168
V ± 0.89 mV or 0.079 V to 0.257 V at the input pins. These values are well within range for the negative rail input
available in the THS4551.
A simpler approach to arriving at the input common mode range for this DC coupled single supply design would
be to take the output voltage swing range on the lower side (non – signal input side) and simply divide it back
through its resistor divider to ground on that side.
The output pin voltage swing is 0.95 V ± 0.5 V or 0.45 V to 1.45 V. This swing is divided back to the input VICM by
a 215 / (215 + 1000) = 0.177 ratio. This ratio computes the input pin range as 79 mV to 0.256 V, matching the
input source swing results in 方程式 7. The TINA-TI™ model for 图 9-7 (available as SBOC472) also provides
these input swings as shown in the simplified circuit of 图 9-8. The large centered swing is the differential output
voltage at the THS4551 output pins (which is actually the two outputs swinging ±0.5 V around a 0.95 VCM), the
small centered bipolar swing is the input swing for the thevenized source of 图 9-8, and the smallest VPP swing
on a dc offset is the input VICM voltage at the non-signal side input for the circuit of 图9-8.
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1.2
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1
VIN+
VOUT
VS
-1.2
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
D069
图9-8. I/O Swing Simulation Using the TINA-TI™ Model
9.3.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
The THS4551 offers a trimmed input offset voltage and extremely low offset drift over the full –40°C to +125°C
operating range. This offset voltage combines with several other error contribution terms to produce an initial
25°C output offset error band and then a drift over temperature. For each error term, a gain must be assigned to
that term. For this analysis, only dc-coupled signal paths are considered. One new source of output error (versus
the typical op amp analysis) arises from the effect mismatched resistor values and ratios can have on the two
sides of the FDA. Any common-mode error or drift creates a differential output error through the slight
mismatches arising from the external feedback and gain setting resistor tolerances or standard value constraints.
The error terms (25°C and drift), along with the gain to the output differential voltage, include input offset voltage
and input offset current. Input offset voltage has a gain equal to the noise gain or 1 + RF / RG, where RG is the
total dc impedance from the input pins back to the source or a dc reference (typically ground). Input offset
current has a gain to the differential output through the average feedback resistor value.
The remaining terms arise from an assumed range on both the absolute feedback resistor mismatch and the
mismatch in the divider ratio on each side of the FDA. The first of these resistor mismatch terms is the input bias
current that creates a differential output offset via RF mismatch. For simplicity, the upper RF and RG values are
termed RF1 and RG1 with a ratio of RF1 / RG1 ≡ G1. The lower elements are defined as RF2 and RG2 with a ratio
of RF2 / RG2 ≡G2. To compute worst-case contributions, a maximum variation in the design resistor tolerance is
used in the absolute and ratio mismatches.
For instance, ±1% tolerance resistors are assumed, giving a worst-case G1 that is 2% higher than nominal and a
G2 that is 2% lower than nominal with a worst-case RF value mismatch of 2% as well. Using a 0.1% precision
resistor reduces the gain for the input bias current, but because these precision resistors are usually only
available in 1% value steps, a gain mismatch term may still need to be considered. For matched impedance
designs with RT and RG1 on a single-ended to differential stage, the standard value constraint imposes a fixed
mismatch in the initial feedback ratios with the tolerance of the resistors around the ratio if the non-signal input
side uses a single resistor for RG2
Define the selected external resistor tolerance as ±T (so for 1% tolerance resistors, T = 0.01). Input bias current
times the feedback resistor mismatch gain is ±2 × T × RFnom
.
.
Anything that generates an output common-mode level or shift over temperature also generates an output
differential error term if the two feedback ratios, G1 and G2, are not equal. An error trying to produce a shift in
the output common-mode voltage is overridden by the common-mode control loop where the error becomes a
balanced differential error around the output VOCM
.
The terms that create a differential error from a common-mode term and feedback ratio mismatch include the
desired VOCM voltage, any source common-mode voltage, any drift on the reference bias to the VOCM control pin,
any internal offset and drift in the VOCM control path, and the input average bias current and drift.
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Considering just the output common-mode control and the source common-mode voltage, the conversion to
output differential offsets is through 方程式8.
VOCM G1- G2 - V
G1- G2
(
)
(
)
ICM
VOD
=
G1+ G2
1+
2
(8)
Neglecting any G1 and G2 mismatch because of standard values constraint, the conversion gain for these two
terms can be recast in terms of the nominal RF / RG ≡ G and the tolerance T, as shown in 方程式 9. When G
increases, this conversion gain approaches 4T.
VOD
G
4T
=
•
(1- T 2 )
VOCM
(1+ G)
(9)
This conversion gain to differential output error is applied to two error terms: VOCM and the input bias current and
drift. (The source common-mode voltage is assumed to be 0 V. If not, apply this gain to the source common-
mode voltage and any resulting shift in application.)
The output error is applied to VOCM, assuming that the input control pin is driven and not floating. The input bias
current and drift are multiplied by the average RF value then by the conversion gain to differential output error to
create an added output differential error.
As an example of using these terms to estimate the worst-case output 25°C error band and then the worst-case
drift (by adding all error terms together independently), use the gain of 1-V/V configuration with RF = 1 kΩ and
assume a ±1% tolerance on the resistors with the standard values used in 图9-9.
THS4551 Wideband,
Fully Differential Amplifier
50-ꢀ Input Match,
Gain of 1 V/V from RT,
Single-Ended Source to
Differential Output
RF1
1 kꢀ
50-ꢀ
Source
Impedance
VS+
RS1
50 ꢀ
RG1
1 kꢀ
VOPP
VS+
VS-
VOCM
œ
+
RL
1 kꢀ
RT1
52.3 ꢀ
VOCM
FDA
+
+
+
œ
5 V
0 V
2.5 V
œ
œ
œ
+
PD
RG2
1.02 kꢀ
VS+
VS-
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图9-9. DC-Coupled Gain of 1 with RF = 1 kΩand Single-to-Differential Matched Input 50-ΩImpedance
The standard value constraint on the non-signal input side actually produces more gain mismatch than the
resistor tolerances. For 图9-9, G2 = 1000 / 1020 = 0.9804 and G1 = 1000 / 1025.6 = 0.9751 nominally, then with
a ±2% tolerance around the initial gain mismatch resulting from the standard values available if 1% resistors are
used.
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Using the maximum 25°C error terms and nominal resistor values with an exact 2.5-V input to the VOCM control
pin gives 表9-2, gains to the output differential error (VOD), and then the summed output error band at 25°C. The
output error is clearly dominated by the VOCM voltage and the effect of the nominal feedback dividers being
slightly mismatched. This analysis does not include resistor tolerances but the approach is the same with the
wider error bands on the gain terms. Using 1% tolerance on the resistors setting the gain matching dominates
the output error band through the VOCM input voltage. For the lowest output error, this analysis shows that an
exact match on the feedback dividers with precision resistors is preferred. However, doing so would require
duplicating the exact network on the non-signal input side and the signal input side. Where input impedance
matching is not required, the two RG resistors are simply single equal resistors and the gain mismatch is just
from the tolerance of the resistors.
表9-2. Worst-Case Output VOD Error Band
OUTPUT ERROR
ERROR TERM
25°C MAX VALUE
GAIN TO VOD
GAIN COMMENT
(mV)
±0.346
±0.05
±0.03
±0.004
±6.7
Input VIO
Input IOS
±0.175 mV
±50 nA
1.5 µA
1.9777
1000
Average noise gain
Feedback resistor
Input IBCM
Input IBCM
VOCM input
Feedback resistor mismatch
20 Ω
1.5 µA
Converted to differential by gain mismatch
VOCM to differential by gain mismatch
1 kΩ× 0.00268
0.00268
Total
2.5 V
±7.13
The 0.00268 conversion gain for the gain ratio mismatch is the worst-case ratio starting from the initially lower
G1 value resulting from the standard value constraint and using a ±1% tolerance on the RF and RG elements of
the ratio. Adding in the resistor tolerances to the gain mismatch term greatly increases the contribution of those
terms.
Normally, the expected drift in the output VOD is of more interest than an initial error band. 表 9-3 shows these
terms for the RGT package and the summed results by adding all terms independently to obtain a worst-case
drift.
表9-3. Worst-Case Output VOD Drift Band
OUTPUT ERROR
ERROR TERM
MAX VALUE
GAIN TO VOD
GAIN COMMENT
(µV/°C)
Input VIO
Input IOS
±1.8 µV/°C
±120 pA/°C
5.0 nA/°C
5.0 nA/°C
±10 µV/°C
1.9777
1000
±3.56
Average noise gain
Feedback resistor
±0.12
Input IBCM
Input IBCM
VOCM input
±0.10
Feedback resistor mismatch
20 Ω
±0.013
±0.027
±3.82
Converted to differential by gain mismatch
VOCM to differential by gain mismatch
1 kΩ× 0.00268
0.00268
Total
In 表 9-3, the input offset voltage drift dominates the output drift. For the last term, the drift for the VOCM path is
just for the internal offset drift of the common-mode path with a driven input. Any added external drift on the
source of the VOCM input must also be considered. This type of calculation can be repeated for the exact
application circuit considering each of these terms in the context of a specific design.
The absolute accuracy and drift for the THS4551 are exceptionally good. Mismatched resistor feedback ratios
combined with a high drift in the VOCM control input can actually dominate the output VOD drift. Where the output
differential precision is more important than the input matching accuracy, consider matching the networks on the
two sides of the input to obtain improved nominal G1 to G2 match. The gains for the input bias current error
terms are relatively low when using the 1-kΩ feedback values. Higher RF values provide the input-current-
related drift terms more gain.
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9.4 Device Functional Modes
The wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than (VS–) + 1.15 V, or turned off by asserting PD low (within 0.55 V of the
negative supply). Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation.
The signal path is still present for the source signal through the external resistors, which provides poor signal
isolation from the input to output in power-down mode.
Internal protection diodes remain present across the input pins in both operating and shutdown mode. Large
input signals during disable can turn on the input differential protection diodes, thus producing a load current in
the supply even in shutdown.
The VOCM control pin sets the output average voltage. Left open, VOCM defaults to an internal midsupply
value. Driving this high-impedance input with a voltage reference within the valid range sets a target for the
internal VCM error amplifier. If floated to obtain a default midsupply reference for VOCM, an external decoupling
capacitor is recommended to be added on the VOCM pin to reduce the otherwise high output noise for the
internal high-impedance bias (see 图7-45).
9.4.1 Operation from Single-Ended Sources to Differential Outputs
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. Although the output side is relatively
straightforward, the device input pins move in a common-mode manner with the input signal. The common-mode
voltage at the input pins, which moves with the input signal, increases the apparent input impedance to be
greater than the RG value. The input active impedance issue applies to both ac- and dc-coupled designs, and
requires somewhat more complex solutions for the resistors to account for this active impedance, as discussed
in the 节9.3.2.
9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output
Conversions
When the signal path can be ac-coupled, the dc biasing for the THS4551 becomes a relatively simple task. In all
designs, start by defining the output common-mode voltage. The ac-coupling issue can be separated for the
input and output sides of an FDA design. The input can be ac-coupled and the output dc-coupled, or the output
can be ac-coupled and the input dc-coupled, or both can be ac-coupled. One situation where the output can be
dc-coupled (for an ac-coupled input), is when driving directly into an ADC where the VOCM control voltage uses
the ADC common-mode reference to directly bias the FDA output common-mode voltage to the required ADC
input common-mode voltage. In any case, the design starts by setting the desired VOCM. When an ac-coupled
path follows the output pins, the best linearity is achieved by operating VOCM at midsupply, which can be easily
delivered by floating the VOCM pin. The VOCM voltage must be within the linear range for the common-mode
loop, as specified in the headroom specifications (approximately 0.7 V greater than the negative supply and
1.3 V less than the positive supply for the full –40°C to +125°C operation). If the output path is also ac-coupled,
simply letting the VOCM control pin float is usually preferred in order to obtain a midsupply default VOCM bias
with minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the VOCM control pin to ground.
After VOCM is defined, check the target output voltage swing to ensure that the VOCM plus the positive and
negative output swing on each side does not clip into the supplies. If the desired output differential swing is
defined as VOPP, divide by 4 to obtain the ±VP (peak voltage) swing around VOCM at each of the two output pins
(each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed the absolute supply
rails for the rail-to-rail output (RRO) device. Common-mode current does not flow from the common-mode output
voltage set by the VOCM pin towards the device input pins side, because both the source and balancing resistor
on the non-signal input side are dc blocked (see 图 9-5). The ac-coupled input path sets the input pin common-
mode voltage equal to the output common-mode voltage.
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The input pin positive headroom requirement (1.2 V) is less than the VOCM positive headroom (1.3 V). If the
VOCM is in range, the input pins are also in range for the ac-coupled input configuration. This headroom
requirement functions similarly for when the output VOCM voltage approaches the negative supply. The
approximate minimum headroom of 0.6 V to the negative supply on the VOCM voltage is greater than the input
pin voltage headroom of approximately 0 V for the negative rail input design. The input common-mode voltage is
also in range if the output common-mode voltage is in range and above 0.6 V from the negative supply because
the input common-mode voltage follows the output VOCM setting for ac-coupled input designs.
The input pin voltages move in a common-mode manner with the input signal, as described in 节 9.3.3. Confirm
that the VOCM voltage plus the input VPP common-mode swing also stays in range for the input pins.
9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
The output considerations remain the same as for the ac-coupled design. Again, the input can be dc-coupled
when the output is ac coupled. A dc-coupled input with an ac-coupled output can have some advantages to
move the input VICM down by adjusting the VOCM down if the source is ground referenced. When the source is
dc-coupled into the THS4551 (see 图 9-4), both sides of the input circuit must be dc-coupled to retain differential
balance. Normally, the non-signal input side has an RG element biased to whatever the source midrange is
expected to be, provided that this midscale reference gives a balanced differential swing around VOCM at the
outputs. Often, RG2 is simply grounded for dc-coupled, bipolar-input applications. This configuration provides a
balanced differential output if the source swings around ground. If the source swings from ground to some
positive voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when the
input is at ground) to one polarity of the swing. Biasing RG2 to an expected midpoint for the input signal creates a
differential output swing around VOCM.
One significant consideration for a dc-coupled input is that VOCM sets up a common-mode bias current from the
output back through RF and RG to the source on both sides of the feedback. Without input balancing networks,
the source must sink or source this dc current. After the input signal range and biasing on the other RG element
is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes an input
VICM at the device input pins that is in range. If the average source is at ground, the negative rail input stage for
the THS4551 is in range for applications using a single positive supply and a positive output VOCM setting
because this dc common-mode current lifts the average FDA input summing junctions up off of ground to a
positive voltage (the average of the V+ and V– input pin voltages on the FDA). TINA-TI™ simulations of the
intended circuit offer a good check for input and output pin voltage swings (see 图9-7).
9.4.2 Operation from a Differential Input to a Differential Output
In many ways, this method is a much simpler way to operate the FDA from a design equations perspective.
Again, assuming that the two sides of the circuit are balanced with equal RF and RG elements, the differential
input impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal but must be
dc biased in the design range for the input pins and must take into account the voltage headroom required to
each supply. Slightly different considerations apply to ac- or dc-coupled differential input to differential output
designs, as described in the following sections.
9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
The most common way to use the THS4551 with an ac-coupled differential source is to simply couple the input
into the RG resistors through the blocking capacitors. 图 9-10 shows a typical blocking capacitor approach to a
differential input. An optional input differential termination resistor (RM) is included in this design. The RM element
allows the input RG resistors to be scaled up and still delivers lower differential input impedance to the source. In
this example, the RG elements sum to show a 1-kΩ differential impedance and the RM element combines in
parallel to provide a net 500-Ω ac differential impedance to the source. Again, the design ideally proceeds by
selecting the RF element values, then the RG to set the differential gain, and then an RM element (if needed) to
achieve a target input impedance. Alternatively, the RM element can be eliminated, with the 2 × RG elements set
to the desired input impedance and RF set to obtain the differential gain (equal to RF / RG).
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THS4551 Wideband,
Fully Differential Amplifier
RF1
1.02 kꢀ
Differential I/O
with AC-Coupled
Input
VS+
RG1
499 ꢀ
10 nF
VOUT
VS+
VS-
œ
+
VOCM
RL
1 kꢀ
FDA
+
+
œ
3.3 V
0 V
RF1
1.02 kꢀ
1 µF
+
PD
œ
œ
VIN
VS+
10 nF
VS-
RG2
499 ꢀ
RF2
1.02 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图9-10. Example AC-Coupled Differential Input Design
The dc biasing for an ac-coupled differential input design is very simple. The output VOCM is set by the input
control voltage and, because there is no dc current path for the output common-mode voltage (as long as RM is
only differential and not split and connected to ground for instance), the dc bias also sets the common-mode
operating points for the input pins. For a purely differential input, the voltages on the input pins remain fixed at
the output VOCM setting and do not move with the input signal (unlike the single-ended input configurations
where the input pin common-mode voltages do move with the input signal). The SLOC341 TINA-TI™ simulation
file is available for 图9-10.
9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
Operating the THS4551 with a dc-coupled differential input source is very simple and only requires that the input
pins stay in range for the dc common-mode operating voltage. The example in 图9-11 takes the output of a dual
precision op amp (such as the OPA2192) where a high differential input signal is attenuated by the THS4551
down into the range of an 18-bit SAR ADC such as the 2-MSPS ADS9110. The input stage provides a
differential gain of 21 V/V with a common-mode gain of 1 V/V. This example amplifies a small differential signal
on top of a very-wide range common-mode voltage. The input common-mode voltage appears at the outputs of
the OPA2192. The input common-mode voltage is level shifted by the FDA common-mode control to be at the
required output common-mode voltage to drive the ADS9110 SAR ADC (with a 4.096-V reference, as shown in
图 9-11); the FDA output common-mode voltage must be at the 2.048 V shown in 图 9-11. This design offers a
very high CMRR using the common-mode control loop of the FDA to reset the output common-mode voltage
from that delivered to the inputs of the OPA2192. The actual CMRR from the OPA2192 inputs to the FDA
outputs is dominated by the resistor mismatches in the FDA. The feedback and differential input capacitors are
included to shape the noise gain as described in 节 10.1.6. This full example circuit is available as a TINA-TI™
simulation file.
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Gain of 0.2 V/V,
DC-Coupled,
Differential Input to
Differential Output
THS4551 Wideband,
Fully Differential Amplifier
22 pF
2 kꢀ
VCC
2.048 V
10 kꢀ
RG1
4.99 kꢀ
RF1
1 kꢀ
VOCM
ADS9110
œ
10 ꢀ
+
Inputs
1 µF
4.096 V
10 kꢀ
VIN1
+
œ
VS+
VEE
œ
200 ꢀ
OPA2192
+
12 nF
49 pF
VOCM
FDA
VS+
+
VS-
VCC
VEE
2 kꢀ
œ
+
PD
+
+
+
VCC
œ
5 V
0 V
15 V
-15 V
VS+
œ
œ
œ
œ
VS-
10 ꢀ
VIN2
+
RF2
1 kꢀ
RG2
4.99 kꢀ
VEE
22 pF
Copyright © 2016, Texas Instruments Incorporated
图9-11. Example DC-Coupled Differential I/O Design from a Precision Dual Op Amp to an 18-Bit SAR
9.4.3 Input Overdrive Performance
图 7-12 illustrates a 2X overdrive triangle waveform for the THS4551. The input resistor is driven with a ±9-V
swing for the gain of 2-V/V configuration in the test circuit of 图 8-1 using a single 5-V supply. When the output
maximum swing is reached at approximately the supply values, the increasing input voltage turns on the internal
protection diodes across the two input pins. The internal protection diodes are two diodes in series in both
polarities. This feature clamps the maximum differential voltage across the inputs to approximately 1.5 V when
the output is limited at the supplies but the input exceeds the available range. The input resistors on both sides
limit the current flow in the internal diodes under these conditions.
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
Most applications for the THS4551 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier itself. The following sections detail some of
the design issues with analysis and guidelines for improved performance.
10.1.1 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. 图 10-1 shows the simplest analysis circuit with the FDA and
resistor noise terms to be considered.
2
2
enRg
enRf
RF
RG
2
In+
+
2
eno
œ
2
Inœ
2
eni
2
2
enRg
enRf
RG
RF
图10-1. FDA Noise Analysis Circuit
The noise powers are shown in 图 10-1 for each term. When the RF and RG (or RI) terms are matched on each
side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡ 1 +
RF / RG, the total output noise is given by 方程式 10. Each resistor noise term is a 4kT × R power (4kT =
1.6E-20J at 290K).
eo = e NG 2 + 2 i R 2 + 2 4kTR NG
ni
N
F
F
(10)
The first term is simply the differential input spot noise times the noise gain, the second term is the input current
noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power
is two times one of them), and the last term is the output noise resulting from both the RF and RG resistors, at
again twice the value for the output noise power of each side added together. Running a wide sweep of gains
when holding RF close to 1 kΩ and setting the input up for a 50-Ω match gives the standard values and
resulting noise listed in 表10-1.
Note that when the gain increases, the input-referred noise approaches only the gain of the FDA input voltage
noise term at 3.3 nV/√Hz.
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表10-1. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V)
RF
RG1
10000
976
RT
RG2
10000
1000
523
ZIN
49.66
49.2
48.9
50.2
50.6
AV
EO (nV/√Hz) EI (nV/√Hz)
0.1
1
1000
1000
1020
1000
1020
49.9
51.1
52.3
59
0.09965
1.0096
1.988
7
70
10.4
13.9
23
10.4
6.95
4.6
2
499
5
187
215
5.057
10
88.7
69.8
118
10.09
36.4
3.64
10.1.2 Factors Influencing Harmonic Distortion
As illustrated in the swept frequency harmonic distortion plots (图 7-13 and 图 7-31), the THS4551 provides
extremely low distortion at lower frequencies. In general, an FDA output harmonic distortion mainly relates to the
open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency. When the total
load impedance decreases, including the effect of the feedback resistor elements in parallel for loading
purposes, the output stage open-loop linearity degrades, thus increasing the harmonic distortion; see 图 7-16
and 图 7-34. When the output voltage swings increase, very fine scale open-loop output stage nonlinearities
increase that also degrade the harmonic distortion; see 图 7-14 and 图 7-32. Conversely, decreasing the target
output voltage swings drops the distortion terms rapidly. A nominal swing of 2 VPP is used for harmonic distortion
testing where 图 7-14 illustrates the effect of going up to an 8-VPP differential input that is more common with
SAR converters.
Increasing the noise gain functions to decrease the loop gain resulting in the increasing harmonic distortion
terms; see 图7-18 and 图7-36. One advantage to the capacitive compensation for the attenuator designs is that
the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin at higher
frequencies. This technique (see 节 10.1.6) holds the loop gain high at frequencies lower than the noise gain
zero, thus improving distortion at lower frequencies.
The THS4551 holds nearly constant distortion when the VOCM operating point is moved in the allowed range;
see 图 7-17 and 图 7-35. Clipping into the supplies with any combination of VOCM and VOPP rapidly degrades
distortion performance.
The THS4551 does an exceptional job of converting from single-ended inputs to differential outputs with very low
harmonic distortions. External resistors of 1% tolerance are used in characterization with good results.
Unbalancing the feedback divider ratios does not degrade distortion directly. Imbalanced feedback ratios convert
common-mode inputs to a differential mode at the outputs with the gain described in 节9.3.4.
10.1.3 Driving Capacitive Loads
The capacitive load of an ADC or some other next-stage device is commonly required to be driven. Directly
connecting a capacitive load to the output pins of a closed-loop amplifier such as the THS4551 can lead to an
unstable response; see the step response plots into a capacitive load (图 7-8, 图 7-10, 图 7-26, and 图 7-28).
One typical remedy to this instability is to add two small series resistors (RO) at the outputs of the THS4551
before the capacitive load. 图 7-6 and 图 7-24 illustrate parametric plots of recommended RO values versus
differential capacitor load values and gains. Operating at higher noise gains requires lower RO values to obtain a
±0.5-dB flat response for the same capacitive load. Some direct parasitic loading is acceptable without a series
RO that increases with gain setting (see 图 7-8, 图 7-10, 图 7-26, and 图 7-28 where the RO value is 0 Ω). Even
when these plots suggest that a series RO is not required, good practice is to leave a place for the RO elements
in a board layout (a 0-Ωvalue initially) for later adjustment in case the response appears unacceptable.
The rail-to-rail output stage of the THS4551 has an inductive characteristic in the open-loop output impedance at
higher frequencies; see 图 9-3. This inductive open-loop output impedance introduces added phase shift at the
output pins for direct capacitive loads and feedback capacitors. Larger values of feedback capacitors (greater
than 100 pF) can risk a low phase margin. Including a 10-Ω to 15-Ω series resistor with a feedback capacitor
can be used to reduce this effect.
The TINA-TI™ simulation model does a good job of predicting these issues and illustrating the effect for different
choices of capacitive load isolating resistors (RO) and different feedback capacitor configurations.
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10.1.4 Interfacing to High-Performance Precision ADCs
The THS4551 provides a simple interface to a wide variety of precision SAR and delta-sigma (ΔΣ) ADCs. To
deliver the exceptional distortion at the output pins, considerably wider bandwidth than what is typically required
in the signal path to the ADC inputs is provided by the THS4551. This wide amplifier bandwidth provides the low
broadband, closed-loop output impedance to supply the sampling glitches and to recover quickly for the best
SFDR. A particularly challenging task is to drive the high-frequency modulator sample rates for a precision ΔΣ
converter where the modulator frequency can be far higher than the final output data rate. 图 10-2 shows a
tested example circuit using the THS4551 in a 500-kHz, active multiple feedback (MFB) filter driving the 24-bit
ADS127L01. This filter is designed for FO = 500 kHz and Q = 0.63 to give a linear phase response with the –3-
dB frequency at 443 kHz. This example circuit is available as a TINA-TI™ simulation file.
1.2 kꢀ
270 pF
1.2 kꢀ
330 ꢀ
1 nF
5 ꢀ
10 ꢀ
10 ꢀ
3 V
AINN
AINP
+
œ
ADS127L01
22 nF
THS4551
470 pF
+
œ
1.2 kꢀ
330 ꢀ
5 ꢀ
270 pF
1.2 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图10-2. 500-kHz Low-Pass Active Filter
This 3-V supply example provides a low-power interface to the very low-power ADC. This circuit is available on
the ADS127L01EVM board.
The 5-Ωresistors inside the loop at the output pins and the 1-nF differential capacitor across the FDA input pins
are not part of the filter design. These elements function to improve the loop-phase margin with minimal
interaction with the active filter operation To observe the loop gain and phase margin, use the SBOC461 TINA-TI
™ simulation file. Tested performance with the ADS127L01 at a 4-kHz input shows the exceptional THD and
SNR of –114 dBc and 106 dB, respectively. 图10-3 uses the ADS127L01 at a modulator frequency of 16 MHz.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
20
40
60 80
Frequency (kHz)
100
120
D066
图10-3. 4-kHz FFT Test for the Gain of 1 V/V Interface in 图10-2
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10.1.5 Operating the Power Shutdown Feature
The CMOS input pin must be asserted to the desired voltage for operation. An internal pullup resistor is not
provided on the PD pin so that off-state quiescent current can be minimized. For applications simply requiring
the device to be powered on when the supplies are present, tie the PD pin to the positive supply voltage.
The disable operation is referenced from the negative supply, normally ground. For split-supply operation, with
the negative supply below ground, a disable control voltage below ground is required to turn the THS4551 off. To
assure an off state condition, the disable control pin must be below a voltage within 0.55 V of the negative
supply.
For single-supply operation, a minimum of 1.15 V above the negative supply (ground in this case) is required to
assure on operation. This logic threshold range allows direct operation from a 1.8-V supply logic when the
THS4551 operates with a single positive supply and ground.
10.1.6 Designing Attenuators
Operating the THS4551 at a low-noise gain (or with higher feedback resistors) can cause a lower phase margin
to exist, thus giving the response peaking illustrated in 图 7-1 for the gain of a 0.1 (a 1/10 attenuator) condition.
Although operating the THS4551 as an attenuator is often useful, taking a large input range to a controlled
output common-mode voltage with a purely differential signal around the VOCM voltage, the response peaking
illustrated in 图 7-1 is usually undesirable. Several approaches can be used to reduce or eliminate this peaking,
usually at the cost of higher output noise. DC attenuation at the input usually increases the output noise
broadband, whereas using an ac noise gain shaping technique that peaks the noise gain only at higher
frequencies is more desirable. This peaking output noise can then be filtered off with the typical passive RC
filters often used after this stage. 图10-4 shows a simplified schematic for the gain of 0.1-V/V test from 图7-1.
Gain of 0.1 V/V,
DC-Coupled,
Single-Ended Source to
Differential Output
THS4551 Wideband,
Fully Differential Amplifier
RF1
1 kꢀ
VS+
RG1
10 kꢀ
VOUT
œ
VS+
VS-
VOCM
+
RL
1 kꢀ
FDA
œ
VIN
+
+
2.5 V
-2.5 V
+
PD
œ
œ
VS+
VS-
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
RG2
10 kꢀ
图10-4. Divide-by-10 Attenuator Application for the THS4551
A 5-dB peaked response (see 图 10-6) results from the configuration of 图 10-4, which results from a nominal
32° phase margin. This peaking can be eliminated by placing two feedback capacitors across the RF elements
and a differential input capacitor. Adding these capacitors provides a transition from a resistively set noise gain
(NG1 = 1.1 in 图 10-4) to a capacitive divider at high frequency, and flattening out to a higher noise gain (NG2).
The key for this approach is to target a ZO where the noise gain begins to peak up. Using only the following
terms, and targeting a closed-loop flat (Butterworth) response, gives this solution sequence (from 方程式11 to 方
程式 13) for ZO and then the capacitor values. See the OPA847 data sheet (page 12) for a discussion of this
inverting noise gain shaping technique.
• Gain bandwidth product in Hz (135 MHz for the THS4551)
• Low-frequency noise gain, NG1 (equal to 1.1 in the attenuator gain of a 0.1-V/V design)
• The target high-frequency noise gain is selected to be higher than NG1 (NG2 = 5 V/V) in this example
• Feedback resistor value, RF (is assumed balanced for this differential design = 1 kΩ)
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From these elements, for any voltage feedback op amp or FDA, solve for ZO as shown in 方程式11:
≈
’
GBP
NG1
NG2
NG1
NG2
ZO
=
1-
- 1- 2
∆
∆
÷
÷
2
NG1
«
◊
(11)
From this target zero frequency in the noise gain, the feedback capacitors can be solved as 方程式12:
1
CF
=
2
p • RF • ZO • NG2
(12)
The next step is to resolve the input capacitance on the summing junction. 方程式 13 is for a single-ended op
amp where the capacitor goes to ground. To use the capacitance (CS) resulting from 方程式 13 for a voltage-
feedback FDA, cut the target value in half and place the resulting CS across the two inputs (reducing the external
value by the specified internal differential capacitance).
CS = NG2 - 1 C
F
(13)
Using the computed capacitor values allows for an estimate of the resulting flat response bandwidth f–3dB
frequency, as shown in 方程式14:
f-3dB
ö GBP • ZO
(14)
Running through these steps for the THS4551 in the attenuator circuit of 图 10-4 provides the proposed
compensation of 图 10-5, where 方程式 14 estimates a bandwidth of 22 MHz (the ZO target is 3.5 MHz). The
solutions for CF gives 9 pF, where this value is reduced to 8.4 pF to account for the internal 0.6-pF feedback.
The single-ended solution for CS gives 36 pF, which is reduced to 18 pF to be differential, and is then further
reduced to 16.8 pF to account for the internal 1.2-pF differential input capacitance of the THS4551.
CF1
8.4 pF
Gain of 0.1 V/V,
THS4551 Wideband,
DC-Coupled,
Fully Differential Amplifier
Single-Ended Source to
Differential Output
RF1
1 kꢀ
VS+
VOUT
RG1
10 kꢀ
VS+
VS-
œ
VOCM
+
RL
1 kꢀ
FDA
+
+
œ
Vin
-2.5 V
2.5 V
CS
16.8 pF
œ
œ
+
PD
VS+
VS-
RF2
1 kꢀ
RG2
10 kꢀ
CF2
8.4 pF
Copyright © 2016, Texas Instruments Incorporated
图10-5. Compensated Attenuator Circuit Using the THS4551
The 16.8 pF across the inputs is really a total of 36 pF for a single-ended design from 方程式 13 reduced by half
and then the 1.2-pF internal capacitance is removed.
These two designs (with and without the compensation capacitors) were both bench tested and simulated using
the THS4551 TINA-TI™ model, which resulted in 图 10-6. The TINA-TI™ simulation files used for 图 10-6 are
available both without the compensation capacitors and with the capacitors in place.
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-12
-14
-16
-18
-20
-22
-24
-26
-28
-30
Bench, wo Capacitors
Bench, with Capacitors
TINA-TI≥, wo Capacitors
TINA-TI≥, with Capacitors
1M
10M
Frequency (Hz)
100M
D067
图10-6. Attenuator Response Shapes With and Without External Capacitors
This approach does a good job of flattening the response for what starts out as a low phase margin attenuator
application. The simulation model does a very good job of predicting the peaking and showing the same
improvement with the external capacitors (both give a flat, approximately 24-MHz, closed-loop bandwidth for the
gain of 0.1-V/V design). The output noise starts to peak up (because of the noise gain shaping of the capacitors)
above 3.5 MHz in this example. These stages normally drive the RC filter at the input of a SAR ADC that filters
off the noise peaking above 3.5 MHz.
10.1.7 The Effect of Adding a Feedback Capacitor
Adding a feedback capacitor to band-limit the signal path is very common in lower frequency designs. This
approach is very effective for the signal path gain but does create the potential for high-frequency peaking and
oscillation for a wideband device such as the THS4551. The feedback capacitor by itself takes the noise gain to
1 V/V at high frequencies. Depending on the frequency where the noise gain goes to 1V/V, and what added
phase margin reduction may already be in place resulting from the load RC, the feedback capacitors can cause
instability.
图 10-7 shows the starting point for a typical band-limited design. At lower frequencies, this example delivers a
gain of 10 V/V with an intentional band limit in the feedback RC at 320 kHz. This single 5-V design targets a
midsupply output common-mode voltage with only a noise reduction capacitor on the VOCM input control.
CF1
250 pF
THS4551 Wideband,
Fully Differential Amplifier
High-Gain, Single-Ended
to Differential Output Stage
with Feedback Pole
RF1
2 kꢀ
VS+
RG1
200 ꢀ
10 ꢀ
VS+
VS-
œ
VOCM
+
SAR ADC
Input
10 nF
FDA
+
+
œ
VIN
0 V
5 V
œ
10 nF
œ
+
PD
VS+
VS-
10 ꢀ
RF2
2 kꢀ
RG2
200 ꢀ
CF2
250 pF
Copyright © 2016, Texas Instruments Incorporated
图10-7. Single-Ended to Differential Stage with a Feedback Pole
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The response shape must be probed at the FDA output pins before the added RC pole to the SAR input.
Running a wideband sweep with the THS4551 TINA-TI™ model using the SBOC475 simulation file shows a
resonance at 50 MHz in 图10-8 resulting from the feedback capacitor.
20
15
10
5
200
175
150
125
100
75
Gain (dB)
Phase (deg)
0
-5
-10
-15
-20
-25
-30
50
25
0
-25
-50
100k
1M
10M
Frequency (Hz)
100M
D070
图10-8. Gain and Phase Plot with a Feedback Pole
One approach to increasing the phase margin when there is a feedback capacitor is to include a differential input
capacitor. This approach increases the noise gain at higher frequencies, thus creating a lower-frequency loop
gain equal to a 0-dB crossover with more phase margin. 图 10-9 shows a differential input capacitor equal to the
feedback capacitor in the test circuit. This approach increases the noise gain from 1 V/V at higher frequencies
(with only a feedback capacitor) to a noise gain of 3 V/V at higher frequencies.
CF1
250 pF
THS4551 Wideband,
Fully Differential Amplifier
High-Gain, Single-Ended
to Differential Output Stage
with Feedback Pole
RF1
2 kꢀ
VS+
RG1
200 ꢀ
10 ꢀ
VS+
VS-
œ
VOCM
+
SAR ADC
Input
10 nF
FDA
+
+
œ
VIN
0 V
5 V
œ
250 pF
10 nF
œ
+
PD
VS+
VS-
10 ꢀ
RF2
2 kꢀ
RG2
200 ꢀ
CF2
250 pF
Copyright © 2016, Texas Instruments Incorporated
图10-9. Single-Ended to Differential Stage with a Feedback Pole and Differential Input Capacitor
Re-running the wideband response (using the SBOC474 TINA-TI™ simulation file) simulation illustrates in 图
10-10 that the resonance is greatly reduced with the higher noise gain at the loop gain equal to a 0-dB crossover
at a lower frequency. Although this example is only modestly peaking, good design practice is to include a place
for a differential input capacitor (even if not used) for any design using a feedback capacitor across the feedback
resistors. This recommendation applies to this simple example and to multiple feedback active filter designs.
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20
10
200
Gain (dB)
Phase (deg)
160
120
80
0
-10
-20
-30
-40
-50
-60
40
0
-40
-80
-120
100k
1M
10M
Frequency (Hz)
100M
D071
图10-10. Gain and Phase Plot with a Differential Input Capacitor
10.2 Typical Applications
10.2.1 An MFB Filter Driving an ADC Application
One common application for the THS4551 is to take a single-ended, high VPP voltage swing (from a high-voltage
precision amplifier such as the OPA192) and deliver that swing to precision SAR ADC as a single-ended to
differential conversion with output common-mode control and implement an active 2nd-order multiple feedback
(MFB) filter design. Designing for a 40-VPP maximum input down to an 8-VPP differential swing requires a gain of
0.2 V/V. Targeting a 100-kHz Butterworth response with the RC elements tilted towards low noise gives the
example design of 图10-11. Note that the VCM control is set to half of a 4.096-V reference, which is typical for
5-V differential SAR applications.
THS4551 Wideband,
Fully Differential Amplifier
RF1
592 ꢀ
OPA192 Output
RG1
1.57 kꢀ
910 pF
2.96 kꢀ
VS+
100 pF
VS-
20 ꢀ
10 ꢀ
VS+
+
+
0 V
5 V
VIN
œ
œ
œ
+
8-VPP Differential
SAR ADC Input
VOCM
100 fF
2.2 nF
100 pF
1.5 nF
FDA
œ
+
PD
VOCM
VS+
VS-
+
2.048 V
œ
20 ꢀ
10 ꢀ
RG2
1.57 kꢀ
2.96 kꢀ
910 pF
RF2
592 ꢀ
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图10-11. Example 100-kHz Butterworth Filter
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10.2.1.1 Design Requirements
The requirements for this application are:
• Single-ended to differential conversion
• Attenuation by 0.2-V/V gain
• Active filter set to a Butterworth, 100-kHz response shape
• Output RC elements set by SAR input requirements (not part of the filter design)
• Filter element resistors and capacitors are set to limit added noise over the THS4551 and noise peaking
10.2.1.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note (SBOA114). The process includes:
• Scale the resistor values to not meaningfully contribute to the output noise produced by the THS4551 by itself
• Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design
• Set the output resistor to 10 Ωinto a 2.2-nF differential capacitor
• Add 100-pF common-mode capacitors to the load capacitor to improve common noise filtering
• Inside the loop, add 20-Ωoutput resistors after the filter feedback capacitor to increase the isolation to the
load capacitor
• Include a place for a differential input capacitor (illustrated as 100 fF in 图10-11)
10.2.1.3 Application Curves
Probing the response to the output pins by using the THS4551 SBOC471 TINA-TI™ simulation model (before
the RC filter to the SAR ADC) illustrates the expected response plus some peaking at higher frequencies. Any
signal or noise peaking that appears at the output because of this peaking is rolled off by the RC filter between
the FDA and SAR inputs. A place for a differential input capacitor is illustrated in 图 10-11 (as 0.1 pF) but is not
used for this simulation. This slight peaking is a combination of low phase margin and feedthrough via the
feedback capacitor to the increasing open-loop output impedance of 图 9-3. The loop gain and phase response
are available as a TINA-TI™ simulation file.
Obtaining the SNR to the ADC input pins, and assuming an 8-VPP full scale (2.83 VRMS), gives the result of 图
10-13. The 113-dB SNR shown in 图10-13 does not limit the performance for any SAR application.
0
-20
450
300
150
0
T
150.00
140.00
130.00
120.00
110.00
Gain (dB)
Phase (deg)
-40
-60
-80
-150
-300
-450
-600
-100
-120
-140
10k
100k
1MEG
10MEG
100MEG
Frequency (Hz)
10k
100k
1M
Frequency (Hz)
10M
100M
D072
图10-13. Signal-to-Noise Ratio Plot
图10-12. Gain and Phase Plot for a 100-kHz
Butterworth Filter
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10.2.2 Differential Transimpedance Output to a High-Grade Audio PCM DAC Application
The highest-grade audio digital-to-analog converters (DACs) are a differential current-mode output. These
devices normally suggest a two-amplifier transimpedance stage to hold the DAC output voltages fixed when the
amplifiers produce a differential voltage swing at the outputs. Often, the differential voltage swing is then
converted to single-ended in a differencing amplifier stage to drive headphone loads (see Figure 35 in the
OPA1611). The emerging high-power class D audio amplifiers often require differential inputs. Applying the
THS4551 as a differential transimpedance stage offers a simple solution for very low-distortion, differential-
output audio channels.
Starting with the output specifications for a very high-performance PCM1792A audio DAC, the requirements for
the THS4551 interface can be extracted. The DAC is a current-sourcing device that requires its outputs to be
held at ground when using a transimpedance amplifier. Using the DAC 3.3-V supply and the LM27762 low-noise,
low-dropout (LDO) regulator and inverter provides a ±2.5-V supply to the THS4551. Operating the THS4551 on
±2.5-V supplies places all nodes in range for an input VCM equal to GND (and the DAC output voltages as well)
and an FDA output VOCM also equal to GND.
The center current in 表 10-2 is a fixed 6.2-mA dc current coming out of the DAC outputs regardless of the DAC
code. This dc common-mode current can be absorbed by the –2.5-V supply at the input pins to hold the DAC
compliance voltage and FDA input pins at ground. The FDA controls the output common-mode voltage, set to
ground in this case, whereas the input pin voltage (which does not move with the DAC output differential current)
is controlled with a resistor to the negative supply.
表10-2. PCM1792A Analog Output Specification
ANALOG OUTPUT
TEST CONDITION
MIN
–6
–3
–2
TYP MAX
UNIT
% of FSR
% of FSR
% of FSR
mAPP
Gain error
±2
±0.5
±0.5
7.8
6
3
2
Gain mismatch, channel-to-channel
Bipolar zero (BPZ) error
Output current
At BPZ
Full-scale (0 dB)
At BPZ
Center current
mA
–6.2
This bias is provided by the 402-Ω resistors to –2.5 V, as illustrated in 图 10-14. This design takes the
differential 7.8 mAPP from the DAC and produces a ±1.46-V swing on each output of the THS4551. This
configuration gives a full-scale differential 5.85 VPP available on the ±2.5-V supply design centered at ground at
both the inputs and outputs. Although the LM27762 provides a very-low noise, –2.5-V supply, using 0.1%
resistors in the current sink path to the –2.5-V supply as well as the feedback resistors limits any common-
mode noise on the –2.5-V supply to differential mode conversion at the FDA outputs.
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CF1
2.4 nF
4.4 ꢀ
VS+
VS-
THS4551 Wideband,
Fully Differential Amplifier
VS-
LM27762
RF1
750 ꢀ
+
+
-2.5 V
Supplies
2.5 V
œ
œ
6.2 mA
402 ꢀ
VS+
œ
VOCM
+
FDA
œ
PCM1792A
20 nF
+
PD
Complementary Current
Output DAC
VS+
VS-
RF2
750 ꢀ
402 ꢀ
6.2 mA
4.4 ꢀ
CF2
2.4 nF
VS-
Copyright © 2016, Texas Instruments Incorporated
图10-14. PCM1792A DAC Output Driver
10.2.2.1 Design Requirements
To implement a differential transimpedance output interface to the PCM1792A DAC, the following requirements
must be met:
• The center current of the DAC must be considered to hold the DAC output voltage at ground. Using an FDA
controls the output side common-mode voltage, but the input common-mode voltage must also be controlled
to ground.
• A direct means of sinking the center current is to add a pulldown resistor at the DAC outputs to a negative
supply. Generating a ±2.5-V supply for this current sink requirement and the THS4551 is accomplished with
the LM27762.
• The transimpedance gain can be set using the feedback resistors of the THS4551 FDA. These resistors are
very flexible, but when set, the bandwidth in this stage is set to 88 kHz using a feedback capacitor in parallel
with the resistive gain element.
• When the feedback capacitor is set, a differential input capacitor is added to increase the high-frequency
noise gain for the overall loop gain stability.
• These frequency response control capacitors interact with the inductive open-loop output impedance to form
a high-frequency resonance. Adding a small series resistor to the feedback capacitor paths reduces this
effect.
10.2.2.2 Detailed Design Procedure
Proceed with this design using the techniques described in the Design for Wideband Differential
Transimpedance DAC Output application note (SBAA150):
• Generate the bipolar balanced supplies using the LM27662.
• Set the THS4551 output common-mode voltage at midsupply by grounding the VOCM pin.
• Control the input pin operating voltage by sinking the center current out of the DAC to the –2.5-V supply with
precision 402-Ωresistors.
• Set the gain for the complementary current output signal from the DAC by selecting the feedback resistor to
be 750 Ω. Set this resistor to keep the resulting output swing to be less than the available 9-VPP differential
swing.
• Control the bandwidth in this differential transimpedance stage to 88 kHz using the 2.4-nF feedback capacitor
on each side.
• Increase the high-frequency noise gain to 17.7 V/V by adding a differential input capacitor of 20 nF.
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• Isolate these feedback capacitors with a series 4.4-Ωresistor in series with the feedback capacitors.
10.2.2.3 Application Curves
The bandwidth is controlled to 88 kHz by using the 2.4-nF feedback capacitors. Amplifier stability is controlled by
the 20-nF differential capacitor across the DAC outputs. The added 4.4 Ω in series with the feedback 2.2-nF
capacitor isolates this capacitance from the inductive open-loop output impedance. To observe the effect of
adding these small resistors in series with the feedback capacitors, use the TINA-TI™ loop gain simulation
circuit. Include the DAC source capacitance in any final design analysis. Running the frequency response for this
circuit (available as a TINA-TI™ simulation file) provides this result. The 63.5-dBΩ gain is the 1.5-kΩ
transimpedance gain provided in this design.
70
65
60
55
50
45
40
35
30
25
20
240
200
160
120
80
Gain (dB)
Phase (deg)
40
0
-40
-80
-120
-160
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D074
图10-15. Gain and Phase Plot of DAC Output Driver
Running a full-scale sine wave at 1 kHz with ±1.95 mA on each output from the DAC at 180° out of phase, and
probing each THS4551 output pin separately results in the expected ±1.46 V on each output pin, as shown in 图
10-16. More output swing is available for the RRO device using the ±2.5-V supplies provided by the LM27762 by
simply increasing the feedback resistor values.
2.5
VOUT-
VOUT+
2
1.5
1
0.5
0
-0.5
-1
-1.5
-2
-2.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
Time (ms)
2
D075
图10-16. Output Waveform of the DAC Output Driver
Although this example is on the audio signal generation side, the THS4551 can also be used to convert a single-
ended line input to a differential driver into an audio ADC.
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10.2.3 ADC3k Driver with a 2nd-Order RLC Interstage Filter Application
The THS4551 is well suited to low-power, dc-coupled requirements driving low-power pipeline ADCs (such as
the ADC3241 25-MSPS, 14-bit, dual device). 图10-17 shows an example design taking a bipolar input to a
–1-dBFS swing at the ADC input of 1.8 VPP. In this case, a 50-Ω source and input matching is assumed with a
gain of 5 V/V to the output pins with a 2nd-order interstage filter adding a –1-dB insertion loss. Full-scale
voltage at the input of RT and RG1 is then ±0.2 V. The 0.95-V output common-mode voltage is provided by the
ADC. The output filter provides a noise-power bandwidth limit with a low overshoot step response with no
common-mode level shift from the 0.95-V voltage provided by the ADC.
50-ꢀ Input Match,
Gain of 5 V/V from RT,
Single-Ended Source to
Differential Output
THS4551 Wideband,
Fully Differential Amplifier
VS+
VS-
RF1
1 kꢀ
10-MHz,
Second-Order
Bessel Filter
50-ꢀ Source
Impedance
+
+
0 V
3.3 V
œ
œ
VS+
RS1
50 ꢀ
RG1
187 ꢀ
390 nH
5.6 ꢀ
40.2 ꢀ
VOUT
œ
ADC Output
Common-Mode
Voltage
VOCM
+
ADC3241
RT1
59 ꢀ
360 pF
732 ꢀ
VOCM
FDA
VIN
Inputs
œ
+
+
PD
950 mV
œ
390 nH
RG2
215 ꢀ
VS+
40.2 ꢀ
5.6 ꢀ
VS-
RF2
1 kꢀ
Copyright © 2016, Texas Instruments Incorporated
图10-17. ADC3k Driver with a 2nd-Order RLC Interstage Filter
10.2.3.1 Design Requirements
For this design example, the requirements include:
• Provide a wideband, 50-Ωinput impedance match for a single-ended source centered on ground.
• From the input termination, provide a gain of 5 V/V to the FDA output pins as a differential signal.
• Set the output common-mode operating point using the ADC common-mode output voltage as the VOCM
input to the THS4551 FDA.
• Implement a low-overshoot, noise-band-limiting filter between the FDA and the ADC. Use only differential
shunt elements in the filter to pass the FDA output common-mode voltage to the ADC with no level shifting.
• Design the filter as a –1-dB insertion loss filter with a low series resistor to limit the common-mode level shift
resulting from the ADC input sample-rate-dependent common-mode current.
10.2.3.2 Detailed Design Procedure
The design proceeds as follows:
• Select the feedback resistor to be 1 kΩand use the values from 表9-1 at a gain of 5 V/V to implement a
50-Ωinput match with a gain of 5 V/V.
• Use a 3.3-V power supply and apply the ADC output common-mode voltage to the VOCM input pin of the
THS4551.
• Design a –1-dB insertion loss, 2nd-order RLC filter using the approach described in the RLC Filter Design
for ADC Interface Applications application note (SBAA108).
• Adjust the total resistive load target in the filter design to hit the standard value for the filter inductors.
• Convert the filter design to differential with only differential shunt elements. These elements must not be split
and connected to a center-point ground. This technique passes the output common-mode voltage from the
FDA to the ADC with no level shift error.
• Add a small series resistor at the ADC inputs. This resistor is not part of the filter design but spreads out the
sampling glitch energy to provide improved SFDR.
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• Check the common-mode level shift from the FDA outputs to the ADC resulting from the clock-rate-
dependent common-mode current. This common-mode current into the ADC shifts the common-mode
voltage slightly, but can easily stay in range with a low series resistor in the filter design.
10.2.3.3 Application Curve
Driving a 2-MHz ±0.2-V square wave into this circuit (using a TINA-TI™ simulation file for the circuit of 图 10-17)
gives the response shown in 图 10-18 at the ADC. The red trace is a –1-dBFS, 1.8-VPP square wave at the
ADC input pins. The gray trace is the input signal at the RT termination resistor. The black trace is the common-
mode voltage at the FDA input pins. Note that the input pin voltage swing stays above ground and in range for
this bipolar input, single, 3.3-V supply design.
1.5
1
0.5
0
-0.5
VIN+
VOUT
VIN
-1
-1.5
0
100 200 300 400 500 600 700 800 900 1000
Time (ns)
D076
图10-18. Time-Domain Waveform
Unbuffered pipeline ADCs draw a clock-rate-dependent input common-mode current. For the ADC3241, this
input current is specified as 1.5 µA per MSPS. Operating at 25 MSPS, the common-mode current drops the
common-mode voltage from 0.95 V at the THS4551 outputs by 37.5 µA × 45.8 Ω = 1.7 mV to 0.9483 V. This
value is well within the allowed ±25-mV common-mode deviation from the ADC VCM output. Consider this effect
carefully when using higher resistor values in the interface at the ADC.
11 Power Supply Recommendations
The THS4551 is principally intended to operate with a nominal single-supply voltage of 3 V to 5 V. Supply
voltage tolerances are supported with the specified operating range of 2.7 V (10% low on a 3-V nominal supply)
and 5.4 V (8% high on a 5-V nominal supply). Supply decoupling is required, as described in 节 8.7. Split (or
bipolar) supplies can be used with the THS4551, as long as the total value across the device remains less than
5.5 V (absolute maximum). The thermal pad on the RGT package is electrically isolated form the die; connect
the thermal pad (RGT package only) to any power or ground plane for reduced thermal impedance to the
junction temperature. This pad must be connected to some power or ground plane and not floated.
For the best input offset voltage drift, the THS4551 uses a proportional to absolute temperature (PTAT)
quiescent current biasing scheme. This approach gives a positive over temperature variation in supply current.
图 11-1 shows the 5-V supply current over a wide TJ range for a number of tested units. The Electrical
Characteristics tables report the typical and range on this supply current temperature coefficient for both 5-V and
3-V supply operation.
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1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-45 -30 -15
0
15 30 45 60 75 90 105 120 135
Junction Temperature (èC)
D068
图11-1. Linear Temperature Coefficient for Supply Current
Using a negative supply to deliver a true swing to ground output when driving SAR ADCs can be desired.
Although the THS4551 quotes a rail-to-rail output, linear operation requires approximately 200-mV headroom to
the supply rails. One easy option for extending the linear output swing to ground is to provide the small negative
supply voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed,
negative-supply generator can accept the 3-V to 5-V positive supply input used by the THS4551 and provides a
fixed –230-mV supply for the negative power supply. Using the LM7705 provides an effective solution, as
discussed in the Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts
TI design (TIDU187)
11.1 Thermal Analysis
The very low internal quiescent power dissipation for the THS4551, combined with the excellent thermal
impedance of the 16-pin VQFN package (RGT), limits the possibility of excessively high internal junction
temperatures. A more detailed analysis may be warranted because the 10-pin WQFN (RUN) package has a
much higher junction-to-ambient thermal impedance (θJA = 163°C/W).
To estimate the internal TJ, an estimate of the maximum internal power dissipation is first required. There are two
pieces to the internal power dissipation: quiescent current power and the power used in the output stage to
deliver load current. To simplify the latter, the worst-case output stage power drives a dc differential voltage
across a load using half the total supply voltage. Also assume a maximum ambient temperature of 125°C, giving
the maximum quiescent current as shown in 图11-1. As an example:
• Assume a maximum operating supply voltage of 5.4 V. This 5.4-V supply with a maximum ICC of 1.75 mA
gives a quiescent power term of 9.45 mW.
• Assume a 200-Ωdifferential load with a static 2.7-V differential voltage established across the load. The
1.35 mA of dc load current generates a maximum output stage power of (5.4 V –2.7 V) × 1.35 mA =
3.65 mW.
• From the worst-case total internal PD of 13.1 mW, multiplying the internal PD with a 163°C/W thermal
impedance times the 163°C/W thermal impedance for the very small 10-pin WQFN package results in a
2.1°C rise from ambient.
Even for this extreme condition and the maximum-rated ambient of 125°C, the junction temperature is a
maximum of 127°C, which is less than the rated absolute maximum of 150°C. Follow this same calculation
sequence for the exact application and package selected to predict the maximum TJ.
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12 Layout
12.1 Layout Guidelines
12.1.1 Board Layout Recommendations
Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The
THS4551DGKEVM user guide (SLOU447) shows a good example of high-frequency layout techniques as a
reference. This EVM includes numerous extra elements and features for characterization purposes that may not
apply to some applications. General high-speed signal path layout suggestions include:
• Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, both ground and power planes must be opened up around the capacitive sensitive input and output
device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue
and less of a stability issue.
• Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins.
Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power
pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
• Differential signal routing over any appreciable distance must use microstrip layout techniques with matched
impedance traces.
• Higher-speed FDAs such as the THS4551 include a duplicate of the output pins on the input feedback side of
the larger 16-pin VQFN (RGT) package. This feature is intended to allow the external feedback resistors to
be connected with virtually no trace length on the input side of the package. This internal feedback trace also
provides a second feedback path for connecting a feedback capacitor on the input pin sides for band-limited
or multiple feedback filter designs. This internal trace shows an approximate 3.3-Ωseries resistance that
must be considered in any design using that path. The TINA-TI™ model does not include that element (to be
generally applicable to all package styles) and must be added externally if the RGT package is used. Use this
layout approach without extra trace length on the critical feedback path. The smaller 10-pin WQFN package
lines up the outputs and the required inputs on the same side of the package where the feedback RF resistors
must be placed immediately adjacent to the package with minimal trace length.
• The input summing junctions are very sensitive to parasitic capacitance. Any RG elements must connect into
the summing junction with minimal trace length to the device pin side of the resistor. The other side of the RG
elements can have more trace length if needed to the source or to GND.
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12.2 Layout Example
图12-1. Example Layout
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12.3 EVM Board
图 12-2 and 图 12-3 show the layout of the top and bottom layers of the THS4551DGKEVM evaluation module,
respectively.
图12-2. THS4551DGKEVM Top Layer
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图12-3. THS4551DGKEVM Bottom Layer
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13 Device and Documentation Support
13.1 Device Support
13.1.1 TINA-TI™ Simulation Model Features
The device model is available on the product folder under www.ti.com in a typical application circuit file. The
model includes numerous features intended to speed designer progress over a wide range of application
requirements. The following list shows the performance parameters included in the model:
• For the small-signal response shape with any external circuit:
– Differential open-loop gain and phase
– Parasitic input capacitance
– Open-loop differential output impedance
• For noise simulations:
– Input differential spot voltage noise and a 100-Hz 1/f corner
– Input current noise on each input with a 6-kHz 1/f corner
• For time-domain, step-response simulations:
– Differential slew rate
– I/O headroom models to predict clipping
– Input stage diodes to predict overdrive limiting
• Fine-scale, dc precision terms:
– PSRR
– CMRR
The 节7.9 provides more detail than the macromodels can provide; some of the unmodeled features include:
• Harmonic distortion
• Temperature drift in dc error terms (VIO and IOS
)
• Overdrive recovery time
• Turn-on and turn-off times using the power-down feature
Some unique simulation considerations come with the THS4551 TINA-TI™ model. This device (and model)
include 0.6-pF internal feedback capacitors. These capacitors are intended to improve phase margin when using
higher external feedback resistor values. Higher feedback resistors generate an in-band pole in the feedback
signal with the differential input capacitance, and the internal 0.6 pF capacitors add a zero to the feedback
response shape to shape the noise gain flat at the loop-gain crossover.
In order to generate an accurate open-loop gain and phase simulation, these components must be removed
because they are feedback elements, not forward path elements. 图13-1 illustrates a typical AOL gain and phase
simulation (available as a TINA-TI™ software file) where external –0.6-pF capacitors cancel out the internal
capacitors in the model (TINA-TI™ supports negative value elements). The inductors inside the loop close the
loop for the dc operating point and open the loop immediately for an ac sweep. The input-coupling capacitors are
open at dc, then couple in the differential input immediately on an ac sweep. The somewhat odd values help
reduce numerical chatter in the simulation. When using the internal feedback traces from the outputs to the
inputs on the RGT package, be sure to add the 3.3-Ωtrace impedance to any simulation. This impedance is not
included in the core model.
R1 10 mW
C2 -600 fF
V4
0
V1 2.5
V2 -2.5
C3 9.97 kF
U1 THS4551
+
VIN-
-
+
VOCM
V
+
-
VM1
VIN+
VOCM
-
+
VIN+
VCVS1
+
1
R4
10 MW
C4 9.97 kF
+
-
VG1
C1 -600 fF
-
R5
10 MW
VIN-
R2 10 mW
Copyright
©
2016, Texas Instruments Incorporated
图13-1. Open-Loop Gain and Phase TINA-TI™ Simulation Setup
Copyright © 2021 Texas Instruments Incorporated
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
This test is set up with a very light load to isolate the no load AOL curve. Adding a load brings in the open-loop
OL response to the overall response of the output pins. Running this simulation gives the gain and phase of 图
Z
13-2 that closely matches the plot of 图7-37.
200.00
T
100.00
0.00
-100.00
0.00
-100.00
-200.00
-300.00
-400.00
10.00
100.00
1.00k
10.00k
100.00k
1.00MEG
10.00MEG 100.00MEG 1.00G
Frequency(Hz)
图13-2. Open-Loop Gain and Phase Simulation Result
Copyright © 2021 Texas Instruments Incorporated
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
13.2 Documentation Support
13.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, THS4551 TINA-TI™ model
• Texas Instruments, THS4551DGKEVM User Guide
• Texas Instruments, THS452x Very Low Power, Negative Rail Input, Rail-To-Rail Output, Fully Differential
Amplifier
• Texas Instruments LMH6629 Ultra-Low Noise, High-Speed Operational Amplifier with Shutdown
• Texas Instruments OPA847 Wideband, Ultra-Low Noise, Voltage-Feedback Operational Amplifier with
Shutdown
• Texas Instruments, INA188 Precision, Zero-Drift, Rail-to-Rail Out, High-Voltage Instrumentation Amplifier
• Texas Instruments, OPAx192 36-V, Precision, Rail-to-Rail Input/Output, Low Offset Voltage, Low Input Bias
Current Op Amp with e-trim™
• Texas Instruments, OPA161x SoundPlus™ High-Performance, Bipolar-Input Audio Operational Amplifiers
• Texas Instruments, ADC322x Dual-Channel, 12-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters
• Texas Instruments, ADC324x Dual-Channel, 14-Bit, 25-MSPS to 125-MSPS, Analog-to-Digital Converters
• Texas Instruments, ADS127L01 24-Bit, High-Speed, Wide-Bandwidth Analog-to-Digital Converter
• Texas Instruments, ADS127L01EVM User's Guide
• Texas Instruments, ADS9110 18-Bit, 2-MSPS, 15-mW, SAR ADC with multiSPI™ Interface
• Texas Instruments, REF6025EVM-PDK User's Guide (SBAU258)
• Texas Instruments, 24-Bit, 192-kHz Sampling, Advanced Segment, Audio Stereo Digital-to-Analog Converter
• Texas Instruments, LM27762 Low-Noise Regulated Switched-Capacitor Voltage Inverter
• Texas Instruments, LM7705 Low-Noise Negative Bias Generator
• Texas Instruments, Extending Rail-to-Rail Output Range for Fully Differential Amplifiers to Include True Zero
Volts
• Texas Isntruments, Design Methodology for MFB Filters in ADC Interface Applications
• Texas Instruments, Design for Wideband Differential Transimpedance DAC Output
• Texas Instruments, RLC Filter Design for ADC Interface Applications
• Texas Instruments, TINA-TI Open Loop No Load Response
• Texas Instruments, TINA-TI Basic Gain of 1 Test Circuit
• Texas Instruments, TINA-TI ADTL1-4-75 Model Test
• Texas Instruments, TINA-TI Common Mode Test CKT
• Texas Instruments, TINA-TI AC Coupled Single to Differentiate Gain of 2
• Texas Instruments, TINA-TI Single to Differential Attenuator
• Texas Instruments, TINA-TI Gain of 5 Single to Different Simplified
• Texas Instruments, TINA-TI AC coupled different IO
• Texas Instruments, TINA-TI Differential IO with OPA2192 to FDA to SAR
• Texas Instruments, TINA-TI ADS127L01 MFB Driver
• Texas Instruments, TINA-TI ADS127L01 MFB Driver LG Test
• Texas Instruments, TINA-TI Attenuator With No Caps Gain of 0.1
• Texas Instruments, TINA-TI Attenuator With a Caps Gain of 0.1
• Texas Instruments, TINA-TI High Gain Single to Different with Feedback Pole
• Texas Instruments, TINA-TI High Gain Single to Different with Feedback Pole and Input C
• Texas Instruments, TINA-TI Gain of 0.2 100kHz Butterworth MFB Filter
• Texas Instruments, TINA-TI 100kHz MFB filter LG test
• Texas Instruments, TINA-TI Differential Transimpedance LG Sim
• Texas Instruments, TINA-TI Differential Audio DAC ZT Design
• Texas Instruments, TINA-TI Gain of 5 Single to Different with 10Mhz Bessel
Copyright © 2021 Texas Instruments Incorporated
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ZHCSFB6D –APRIL 2016 –REVISED JUNE 2021
13.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
13.4 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
13.5 Trademarks
TINA-TI™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
13.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
13.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2021 Texas Instruments Incorporated
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS4551IDGKR
THS4551IDGKT
THS4551IRGTR
THS4551IRGTT
THS4551IRUNR
THS4551IRUNT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSSOP
VSSOP
VQFN
VQFN
QFN
DGK
DGK
RGT
RGT
RUN
RUN
8
2500 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAUAG | SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
4551
4551
Samples
Samples
Samples
Samples
Samples
Samples
8
NIPDAUAG | SN
NIPDAU
16
16
10
10
HS4551
HS4551
4551
NIPDAU
NIPDAU
QFN
NIPDAU
4551
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-Aug-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4551IDGKR
THS4551IDGKR
THS4551IDGKT
THS4551IDGKT
THS4551IRGTR
THS4551IRGTT
THS4551IRUNR
THS4551IRUNT
VSSOP
VSSOP
VSSOP
VSSOP
VQFN
VQFN
QFN
DGK
DGK
DGK
DGK
RGT
RGT
RUN
RUN
8
8
2500
2500
250
330.0
330.0
330.0
330.0
330.0
180.0
180.0
180.0
12.4
12.4
12.4
12.4
12.4
12.4
8.4
5.3
5.3
5.3
5.3
3.3
3.3
2.3
2.3
3.4
3.4
3.4
3.4
3.3
3.3
2.3
2.3
1.4
1.4
8.0
8.0
8.0
8.0
8.0
8.0
4.0
4.0
12.0
12.0
12.0
12.0
12.0
12.0
8.0
Q1
Q1
Q1
Q1
Q2
Q2
Q2
Q2
8
1.4
8
250
1.4
16
16
10
10
3000
250
1.1
1.1
3000
250
1.15
1.15
QFN
8.4
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Nov-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4551IDGKR
THS4551IDGKR
THS4551IDGKT
THS4551IDGKT
THS4551IRGTR
THS4551IRGTT
THS4551IRUNR
THS4551IRUNT
VSSOP
VSSOP
VSSOP
VSSOP
VQFN
VQFN
QFN
DGK
DGK
DGK
DGK
RGT
RGT
RUN
RUN
8
8
2500
2500
250
366.0
366.0
366.0
366.0
367.0
210.0
210.0
210.0
364.0
364.0
364.0
364.0
367.0
185.0
185.0
185.0
50.0
50.0
50.0
50.0
35.0
35.0
35.0
35.0
8
8
250
16
16
10
10
3000
250
3000
250
QFN
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RUN 10
2 X 2, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4228249/A
www.ti.com
PACKAGE OUTLINE
RUN0010A
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4220470/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220470/A 05/2020
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4220470/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
1.0
0.8
C
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/D 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/D 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/D 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
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