THS4561_V02 [TI]
THS4561 Low-Power, High Supply Range, 60-MHz, Fully Differential Amplifier;
| 型号： | THS4561_V02 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | THS4561 Low-Power, High Supply Range, 60-MHz, Fully Differential Amplifier |
| 文件： | 总51页 (文件大小：3281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS4561
SBOS874C – AUGUST 2017 – REVISED DECEMBER 2020
THS4561 Low-Power, High Supply Range, 60-MHz, Fully Differential Amplifier
differential output required by precision analog-to-
1 Features
digital converters (ADCs). Designed for a very low,
8-Hz, 1/f voltage noise corner and low, 130-dB total
harmonic distortion (THD) while consuming only a
775-µA quiescent current, the THS4561 is well suited
for power-sensitive data acquisition (DAQ) systems
where high performance is required with the best
signal-to-noise ratio (SNR) and spurious-free dynamic
range (SFDR) through the amplifier and ADC
combination.
•
•
•
•
Bandwidth: 60 MHz (G = 1 V/V)
Slew Rate: 230 V/µs
Gain Bandwidth Product: 68 MHz
Voltage Noise:
– 1/f Voltage Noise Corner: 8 Hz
– Broadband Noise (≥ 500 Hz): 4 nV/√ Hz
Input Offset: ±250 µV (Maximum)
– Drift: ±4 µV/°C (Maximum)
Supply Operating Range: 2.85 V to 12.6 V
Supply Current: 775 µA
Negative Rail Input (NRI)
Rail-to-Rail Output (RRO)
Very Low Harmonic Distortion:
– HD2: –117 dBc at 2 VPP, 100 kHz
– HD3: –124 dBc at 2 VPP, 100 kHz
0.01% Settling (2-V Step): 90 ns
•
The THS4561 features the required negative rail input
when interfacing a DC-coupled, ground-centered,
source signal to a single-supply, differential-input
ADC. Low DC error and drift terms support the
emerging high-speed and high-resolution successive
approximation register (SAR) and delta-sigma (ΔΣ)
ADC input requirements. A 2.85-V to 12.6-V supply
range with a flexible output common-mode setting
with low headroom to the supplies supports a wide
range of ADC input and digital-to-analog converter
(DAC) output requirements.
•
•
•
•
•
•
2 Applications
•
•
•
•
•
•
•
16-bit to 20-bit, Differential, SAR and ΔΣ Drivers
Differential Active Filters
High Output Swing PCM Audio DAC Outputs
Medical Ultrasounds
Battery Testers
Power Analyzers
The THS4561 device is characterized for operation
from –40°C to +125°C.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
2.00 mm × 2.00 mm
3.00 mm × 3.00 mm
VSSOP (8)
THS4561
WQFN (10)
Lower Power Alternate to the THS4551
VQFN (16)(2)
3 Description
(1) For all available packages, see the package option
addendum at the end of the data sheet.
The THS4561 fully differential amplifier (FDA) offers a
simple interface from single-ended sources to the
(2) Preview package.
-20
VS+
VSœ
THS4561
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 8 VPP
Using 5 VS
-30
+
+
-40
+5 V
œ5 V
3.57 kꢀ
œ
œ
-50
-60
HD3, VO = 8 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
330 pF
-70
357 ꢀ
909 ꢀ
-80
VS+
PD
G = 10 V/V
-90
10 nF
10 nF
PCM
Audio DAC
Output
50-kHz MFB
Butterworth
Output Driver
-100
-110
-120
-130
-140
-150
150 pF
FDA
VSœ
357ꢀ
909 ꢀ
330 pF
3.57 kꢀ
10k
100k
1M
10M
Frequency (Hz)
D007
Gain of 10 V/V PCM Audio DAC Output With
Second-Order MFB Filter at 50 kHz
Harmonic Distortion vs Frequency
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS4561
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SBOS874C – AUGUST 2017 – REVISED DECEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Device Comparison Table...............................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings ....................................... 5
7.2 ESD Ratings .............................................................. 5
7.3 Recommended Operating Conditions ........................5
7.4 Thermal Information ...................................................5
7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V .... 6
7.6 Typical Characteristics: (VS+) – (VS–) = 12 V.............. 9
7.7 Typical Characteristics: (VS+) – (VS–) = 5 V.............. 12
7.8 Typical Characteristics: (VS+) – (VS–) = 3 V.............. 15
7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to
12-V Supply Range..................................................... 16
8 Parameter Measurement Information..........................19
8.1 Example Characterization Circuits............................19
8.2 Output Interface Circuit for DC-Coupled
Differential Testing.......................................................21
8.3 Output Common-Mode Measurements.....................21
8.4 Differential Amplifier Noise Measurements...............22
8.5 Balanced Split-Supply Versus Single-Supply
8.6 Simulated Characterization Curves.......................... 22
8.7 Terminology and Application Assumptions............... 23
9 Detailed Description......................................................24
9.1 Overview...................................................................24
9.2 Functional Block Diagram.........................................24
9.3 Feature Description...................................................25
9.4 Device Functional Modes..........................................25
10 Application and Implementation................................28
10.1 Application Information........................................... 28
10.2 Typical Application.................................................. 33
11 Power Supply Recommendations..............................34
12 Layout...........................................................................35
12.1 Layout Guidelines................................................... 35
12.2 Layout Examples.................................................... 35
13 Device and Documentation Support..........................37
13.1 Receiving Notification of Documentation Updates..37
13.2 Support Resources................................................. 37
13.3 Trademarks.............................................................37
13.4 Electrostatic Discharge Caution..............................37
13.5 Glossary..................................................................37
14 Mechanical, Packaging, and Orderable
Information.................................................................... 37
Characterization.......................................................... 22
4 Revision History
Changes from Revision B (August 2020) to Revision C (December 2020)
Page
•
•
Changed the slew rate from 315 V/µs to 230 V/µs in the Features section........................................................1
Updated Gain of 10 V/V PCM Audio DAC Output with Second-Order MFB Filter at 50 kHz in the Features
section................................................................................................................................................................ 1
Releasing the WQFN (10) package for the in the THS4561 device................................................................... 1
Changed the status of the RUN package from preview to production ...............................................................4
Seperated slew rate specification into rising and falling specifications lines...................................................... 5
Changed the VOCM small-signal bandwidth test condition from 100 mVPP to 10 mVPP and the typical value
from 23 MHz to 22 MHz .....................................................................................................................................5
Changed the VOCM large-signal bandwidth typical value from 10 MHz to 1.9 MHz .........................................5
Changed the maximum VOCM drift specification from 300 µV/°C .................................................................... 5
Updated the Common-Mode Voltage, Small-Signal and Large-Signal Response (VOCM Pin Driven) figure in
the Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range section .............................................. 16
Updated the MFB Filter Driving an ADC Application: Example 170-kHz Butterworth Response figure in the
Typical Application section ...............................................................................................................................33
•
•
•
•
•
•
•
•
Changes from Revision A (December 2019) to Revision B (August 2020)
Page
Updated the numbering format for tables, figures, and cross-references throughout the document..................1
Added the VQFN-10 and VQFN-16 Package Outlines.....................................................................................37
•
•
Changes from Revision * (August 2017) to Revision A (December 2019)
Page
•
Changed device status from advance information to production data................................................................1
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SBOS874C – AUGUST 2017 – REVISED DECEMBER 2020
5 Device Comparison Table
IQ, 5 V
(mA)
INPUT NOISE
(nV/√ Hz)
THD (dBc) 2 VPP
DEVICE
THS4561
THS4551
THS4521
THS4531A
THS4541
BW, G = 1 (MHz)
RAIL-TO-RAIL DUAL VERSIONS
AT 10 kHz
Negative in and
60
150
145
36
0.78
1.37
1.14
0.25
10.1
4
–130
—
out
Negative in and
THS4552
out
3.3
5.6
10
–138
–120
–118
–140
Negative in and
THS4522
out
Negative in and
THS4532
out
Negative in and
620
2.2
—
out
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SBOS874C – AUGUST 2017 – REVISED DECEMBER 2020
6 Pin Configuration and Functions
VS+
10
IN-
IN+
1
2
3
4
8
7
6
5
OUT–
NC
9
8
7
6
OUT+
NC
1
2
3
4
VOCM
PD
VS+
VS-
OUT-
VOCM
IN–
PD
OUT+
IN+
5
Figure 6-1. DGK Package 8-Pin VSSOP Top View
VS–
Figure 6-2. RUN Package 10-Pin WQFN Top View
16
15
14 13
12 PD
FB–
IN+
1
2
3
4
11 OUT–
IN–
10
9
OUT+
FB+
VOCM
5
6
7
8
Figure 6-3. RGT Package (Preview) 16-Pin VQFN With Exposed Thermal Pad Top View
Table 6-1. Pin Functions
PIN
TYPE(2)
DESCRIPTION
NAME
FB–
DGK
—
—
1
RUN
—
—
6
RGT(1)
1
4
O
O
I
Inverting (negative) output feedback
FB+
Noninverting (positive) output feedback
Inverting (negative) amplifier input
Noninverting (positive) amplifier input
No internal connection
IN–
3
IN+
8
4
2
I
NC
—
5
2, 8
1
—
11
10
—
O
O
OUT–
OUT+
Inverting (negative) amplifier output
Noninverting (positive) amplifier output
4
9
Power down. PD = logic low = power off mode; PD = logic high = normal
operation.
PD
7
2
6
3
3
7
12
9
I
VOCM
VS–
VS+
I
Common-mode voltage input
Negative power-supply input
Positive power-supply input
13, 14, 15,
16
5
P
P
10
5, 6, 7, 8
(1) Solder the exposed RGT package thermal pad to a heat-spreading power or ground plane. This pad is electrically isolated from the
die, but must be connected to a power or ground plane and not floated.
(2) I = input, O = output, P = power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
13.5
UNIT
V
Total supply voltage, VS = (VS+ – VS–
)
Supply turn-on/off dV/dT(2)
±0.35
(VS+) + 0.5
±1
V/µs
V
Voltage
Input, output, power down and common-mode pin voltage range
Differential input voltage
(VS–) – 0.5
V
Continuous input current
±10
mA
mA
°C
Current
Continuous output current(3)
±20
Junction temperature, TJ
150
Temperature
Operating free-air temperature, TA
Storage temperature, Tstg
–40
–65
125
°C
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These stress-only
ratings do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Staying below this specification ensures that the edge-triggered ESD absorption devices across the supply pins remains off.
(3) Long-term continuous output current for electromigration limits.
7.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1)
±3500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins(2)
±1250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.85
–40
NOM
MAX
12.6
125
UNIT
V
VS
TA
Total supply voltage
Operating free-air temperature
25
°C
7.4 Thermal Information
THS4561
THERMAL METRIC(1)
DGK (VSSOP)
8 PINS
183.1
RUN (WQFN)
10 PINS
134.6
83.6
RGT (VQFN)
UNIT
16 PINS
TBD
RθJA
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
70.3
TBD
104.9
67.7
TBD
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
10.8
7.2
TBD
ΨJB
103.2
67.5
TBD
RθJC(bot)
N/A
N/A
TBD
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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SBOS874C – AUGUST 2017 – REVISED DECEMBER 2020
7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V
at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input
match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output
referenced to midsupply for AC-coupled tests (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
VS = 5 V, VO = 200 mVPP, 2-dB peaking
G = 2 V/V
60
45
SSBW
Small-signal bandwidth
MHz
VS = 5 V, VO = 200 mVPP G = 5 V/V
G = 10 V/V
12.5
6.3
68
GBWP
LSBW
Gain-bandwidth product
Large-signal bandwidth
Bandwidth for 0.1-dB flatness
VO = 200 mVPP, G = 20 V/V, RF = 10 kΩ
VO = 4 VPP
MHz
MHz
MHz
V/µs
V/µs
20
5
Rising
VS = 5 V, VO = 2-V step
Falling
325
230
5%
11%
40
SR
Slew rate (20% – 80%)
VS = 12 V
VS = 5 V
VO = 2-V step,
input tr = 10 ns
Overshoot and undershoot
0.1% settling time
VO = 2-V step, input tr = 10 ns
VO = 2-V step, input tr = 10 ns
VO = 100-mV step, input tr = 2 ns
ns
ns
ns
0.01% settling time
90
Rise and fall time (10% – 90%)
5.7
–117
–110
–124
–106
4
Vo = 2 VPP
Vo = 8 VPP
Vo = 2 VPP
Vo = 8 VPP
HD2
HD3
Second-order harmonic distortion VS = 5 V, f = 100 kHz
dBc
Third-order harmonic distortion
Input differential voltage noise
VS = 5 V, f = 100 kHz
f ≥ 500 Hz
nV/√Hz
Hz
en
in
1/f corner
8
Input current noise, each input
Overdrive recovery time
f ≥ 50 kHz
0.35
pA/√Hz
VS = 5 V, G = 2 V/V,
2x output overdrive, dc-coupled
210
ns
Ω
ZOUT
Closed-loop output impedance
f = 100 kHz (differential)
0.06
DC PERFORMANCE
AOL
VOS
Open-loop voltage gain
Vo = ±2 V
TA = 25°C
104
115
±50
dB
Input offset voltage
–250
250
4
µV
TA = 0°C to 85°C,
TA = –40°C to 125°C
Input offset voltage drift
–4
±0.5
µV/°C
IB+, IB–
Input bias current(3)
Input bias current drift
Input offset current(4)
Input offset current drift
TA = 25°C
370
4.1
±2
600
8
nA
nA/°C
nA
TA = –40°C to 125°C
TA = 25°C
IOS
–20
20
TA = –40°C to 125°C
–200
±40
200 pA/°C
INPUT
TA = –40°C to 125°C, 3-dB AOL
degradation from midsupply VOCM AOL
VICML
Common-mode input low
Common-mode input high
VS– – 0.1
VS+ – 1.1
VS+ – 1.2
VS–
V
V
TA = 25°C
VS+ – 1.2
VS+ – 1.35
95
3-dB AOL degradation
from midsupply
VOCM AOL
VICMH
TA = –40°C to
125°C
Midsupply inputs
110
108
CMRR
Common-mode rejection ratio
Differential input impedance
dB
Midsupply inputs, TA = –40°C to 125°C
Inputs at midsupply
150 || 2.4
kΩ || pF
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7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V (continued)
at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input
match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output
referenced to midsupply for AC-coupled tests (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
OUTPUT
VS = 5 V
VS– + 0.13 VS– + 0.25
VS = 5 V, TA = –40°C to 125°C
VS = 5 V, RL = 10 kΩ
VS = 12 V
VS– + 0.15
VS– + 0.07
VS– + 0.26
VS– + 0.3
Output voltage range low
V
V
VS– + 0.4
VS = 5 V
VS+ – 0.25 VS+ – 0.16
VS+ – 0.3 VS+ – 0.18
VS+ – 0.09
VS = 5 V, TA = –40°C to 125°C
VS = 5 V, RL = 10 kΩ
VS = 12 V
Output voltage range high
VS+ – 0.35
±27
VS+ – 0.2
±31
VO = ±3.6 V, VOCM offset < 15 mV
Continuous output current
Linear output current
mA
mA
TA = –40°C to +125°C, VO = ±2.25 V,
VOCM offset < 15 mV
±17
VS = 5 V, VO = ±2.7 V,, AOL > 80 dB
VS = 12 V, VO = ±4.6 V, AOL > 80 dB
±20
±22
±22
±27
VS = 12 V, TA = –40°C to +125°C,
VO = ±3.1 V, AOL > 80 dB
±15
OUTPUT COMMON-MODE VOLTAGE (VOCM) CONTROL(1)
Small-signal bandwidth
Large-signal bandwidth
Slew rate(2) (20% – 80%)
VOCM = 10 mVPP
VOCM = 1 VPP
22
1.9
4
MHz
MHz
V/µs
VOCM = 0.5-V step
VOCM fixed midsupply,
VOCM/VO (VO = ±1 V)
DC output balance
Output balance
86
dB
Hz
VOCM fixed midsupply,
VOCM/VO (–3-dB from dc)
800
Gain
VOCM = 0 V
0.997
–0.5
72
1
1.003
0.5
V/V
µA
Input bias current
+PSR to VOCM
–PSR to VOCM
Input impedance
Default VOCM offset
–0.1
VOCM = midsupply
VOCM = midsupply
78
dB
70
76
dB
200 || 1.5
kΩ || pF
mV
Relative to midsupply, VOCM pin floating
–40
120
–3.5
–15
8
200
0.25
3
40
Default VOCM offset voltage drift TA = –40℃ to 125℃
600 µV/℃
3.5 mV
15 µV/°C
VOCM offset voltage
VOCM driven to midsupply
TA = –40°C to 125°C
VOCM offset voltage drift
TA = 25°C, < ±4-mV shift from
midsupply offset
VS– + 0.45
VS– + 0.5
VS– + 0.6
VOCM range low
VOCM range high
V
V
TA = –40°C to 125°C, < ±4-mV shift
from midsupply offset
TA = 25°C, < ±4-mV shift from
midsupply offset
VS+ – 1.2
VS+ – 1.3
VS+ – 1.1
TA = –40°C to 125°C, < ±5-mV shift
from midsupply offset
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7.5 Electrical Characteristics: VS+ – VS– = 5 V to 12 V (continued)
at TA ≈ 25°C, VOCM(1) = midsupply, differential output (VO) = VOUT+ – VOUT– = 2 VPP, RF = 1.5 kΩ, RL = 1 kΩ, 50-Ω input
match, differential closed-loop gain (G) = 1 V/V, single-ended input (SE-in), differential output (diff-out), and input and output
referenced to midsupply for AC-coupled tests (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
POWER SUPPLY
Specified operating voltage
Quiescent current
2.85
710
725
12.6
810
825
V
VS = 2.85 V, no load, TA = 25°C
VS = 5 V, no load, TA = 25°C
760
775
VS = 5 V, no load,
TA = –40°C to 125°C
700
770
740
900
880
IQ
µA
VS = 12 V, no load, TA = 25°C
825
VS = 12 V, no load,
TA = –40°C to 125°C
1000
Quiescent current drift
No load, TA = –40°C to 125°C
Either supply to input VOS
0.7
1.3 µA/°C
dB
PSRR
Power-supply rejection ratio
92
110
POWER DOWN
VEN
Enable voltage threshold
PD = VEN, guaranteed on above
PD = VDIS, guaranteed off below
PD = VS+ – 0.5 V (amplifier enabled)
PD = VS– (amplifier disabled)
Switch amplifier on to off
VS+ – 1.2
VS+ – 1.7
1.2
VS+ – 0.5
V
VDIS
Disable voltage threshold
PD pin bias current
VS+ – 1.8
3.5
V
µA
µA
µA
µA
PD pin bias current
–3
3
–1.9
Peak PD pull-down bias current
Power-down quiescent current
175
No load
15
40
Time from PD = high to VO = 90%
of final value
Turnon time delay
Turnoff time delay
600
1.5
ns
µs
Time from PD = low to VO = 10%
of original value
(1) VOCM refers to the voltage at VOCM pin. VOCM = [(VOUT+ + VOUT–)/2] refers to the average output voltage.
(2) Average of the rising and falling slew rate.
(3) Current out of the node is considered positive.
(4) IOS = IB+ – IB–.
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7.6 Typical Characteristics: (VS+) – (VS–) = 12 V
at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-
ended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests
(unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
3
3
0
0
-3
-3
-6
-6
G = 0.5 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
VO = 0.2 VPP
VO = 2 VPP
VO = 4 VPP
VO = 8 VPP
VO = 10 VPP
-9
-9
-12
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D001
D002
VO = 200 mVPP, see Figure 8-1 and Table 10-1 for resistor
values
See Figure 8-1
Figure 7-2. Frequency Response vs VO
Figure 7-1. Small-Signal Frequency Response vs Gain
3
3
0
0
-3
-6
-3
-6
VOCM = 1 V
VOCM = 3 V
VOCM = 6 V
RL = 150 W
RL = 500 W
RL = 1 kW
RL = 2 kW
RL = 10 kW
-9
-9
VOCM = 7.5 V
VOCM = 9 V
-12
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D003
D004
VO = 200 mVPP , see Figure 8-1 with VOCM adjusted
VO = 200 mVPP, see Figure 8-1 with load resistance (RL)
adjusted
Figure 7-3. Small-Signal Frequency Response vs VOCM
Figure 7-4. Small-Signal Frequency Response vs RL
100
10
1
10
0.5
en
in
G = 0.5 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
0.4
0.3
0.2
0.1
0
1
-0.1
-0.2
-0.3
-0.4
-0.5
0.1
100k
1
10
100 1k
Frequency (Hz)
10k
100k
1M
Frequency (Hz)
10M
D050
D072
1/f corners: en = 8 Hz, in = 700 Hz
Figure 7-6. Input Noise Density vs Frequency
VO = 200 mVPP
Figure 7-5. Gain Flatness vs Frequency
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7.6 Typical Characteristics: (VS+) – (VS–) = 12 V (continued)
at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-
ended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests
(unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
-20
-30
-60
-70
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 8 VPP
HD3, VO = 8 VPP
HD2, VO = 10 VPP
HD3, VO = 10 VPP
-40
-50
-80
-60
-70
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-90
-80
-90
-100
-110
-120
-130
-100
-110
-120
-130
-140
-150
10k
100k
1M
10M
2
10
Frequency (Hz)
Output Voltage (VPP)
D007
D008
Figure 7-7. Harmonic Distortion vs Frequency
Figure 7-8. Harmonic Distortion vs VO
-60
-65
-40
-50
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-70
-75
-60
-80
-70
-85
-90
-80
-95
-90
-100
-105
-110
-115
-120
-125
-130
-100
-110
-120
-130
100
1k
Load Resistance, RL (W)
10k
1
10
Gain, G (V/V)
D009
D010
VO = 5 VPP with RL adjusted
VO = 5 VPP, see Table 10-1 for gain setting
Figure 7-9. Harmonic Distortion vs RL
Figure 7-10. Harmonic Distortion vs Gain
-75
-80
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Max IMD2
Max IMD3
-85
-90
HD2, 100 kHz
-95
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-100
-105
-110
-115
-120
-125
-130
-3 -2.5 -2 -1.5 -1 -0.5
0
Common-Mode Voltage, VOCM (V)
0.5
1
1.5
2
2.5
3
1M
Frequency (Hz)
10M
D011
D012
VO = 5 VPP with VOCM adjusted
VO = 2 VPP per tone, ±50-kHz tone spacing
Figure 7-11. Harmonic Distortion vs VOCM
Figure 7-12. Intermodulation Distortion (IMD2 and IMD3) vs
Frequency
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7.6 Typical Characteristics: (VS+) – (VS–) = 12 V (continued)
at TA ≈ 25°C, VOCM pin = midsupply, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-
ended input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests
(unless otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
1.8
1.4
1
6
5
4
3
0.6
0.2
-0.2
-0.6
-1
2
OUT+, TA = -40èC
OUT+, TA = 25èC
OUT+, TA = 85èC
OUT+, TA = 125èC
OUT-, TA = -40èC
OUT-, TA = 25èC
OUT-, TA = 85èC
OUT-, TA = 125èC
1
0
-1
-2
-3
-4
-5
-6
-1.4
-1.8
SE-in, diff-out
Diff-in, diff-out
Time, 15 ns per division
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Output Current (mA)
D015
D065
VO = 2-V step,
VS = 12 V, VOCM at midsupply, average of 30 units
SE-in, diff-out: rising SR = 350 V/µs, falling SR = 200 V/µs,
diff-in, diff-out: rising SR = 285 V/µs, falling SR = 285 V/µs
Figure 7-14. ±Maximum Output Voltage vs Output Current and
Temperature
Figure 7-13. Large-Signal Step Response
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7.7 Typical Characteristics: (VS+) – (VS–) = 5 V
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless
otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
6
3
3
0
0
-3
-3
-6
-9
-12
-6
VO = 0.2 VPP
VO = 1 VPP
VO = 2 VPP
VO = 4 VPP
VO = 8 VPP
G = 0.5 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
-9
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D020
D019
See Figure 8-1
VO = 200 mVPP, see Figure 8-1 and Table 10-1 for resistor
values
Figure 7-16. Frequency Response vs VO
Figure 7-15. Small-Signal Frequency Response vs Gain
3
3
0
0
-3
-6
-3
-6
VOCM = 1 V
VOCM = 2 V
VOCM = 2.5 V
RL = 150 W
RL = 500 W
RL = 1 kW
RL = 2 kW
RL = 10 kW
-9
-9
VOCM = 3 V
VOCM = 3.5 V
-12
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D021
D022
VO = 200 mVPP, see Figure 8-1 with VOCM adjusted
VO = 200 mVPP, see Figure 8-1 with RL adjusted
Figure 7-17. Small-Signal Frequency Response vs VOCM
Figure 7-18. Small-Signal Frequency Response vs RL
100
10
1
10
0.5
en
in
G = 0.5 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
0.4
0.3
0.2
0.1
0
1
-0.1
-0.2
-0.3
-0.4
-0.5
0.1
100k
1
10
100 1k
Frequency (Hz)
10k
100k
1M
Frequency (Hz)
10M
D070
D073
1/f corners: en = 8 Hz, in = 700 Hz
Figure 7-20. Input Noise Density vs Frequency
VO = 200 mVPP
Figure 7-19. Gain Flatness vs Frequency
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7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless
otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
-20
-30
-65
-70
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, VO = 8 VPP
HD3, VO = 8 VPP
-40
-75
-50
-80
-60
-85
-70
-90
-80
-95
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-90
-100
-105
-110
-115
-120
-125
-130
-100
-110
-120
-130
-140
-150
10k
100k
1M
10M
2
10
Frequency (Hz)
Output Voltage (VPP)
D025
D026
Figure 7-21. Harmonic Distortion vs Frequency
Figure 7-22. Harmonic Distortion vs VO
-70
-50
-60
-75
-80
-85
-70
-90
-80
-95
HD2, 100 kHz
-100
-105
-110
-115
-120
-125
-130
-90
HD3, 100 kHz
HD3, 1 MHz
HD2, 1 MHz
-100
-110
-120
-130
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
100
1k
Load Resistance, RL (W)
10k
1
10
Gain, G (V/V)
D027
D028
VO = 5 VPP with RL adjusted
VO = 5 VPP, see Table 10-1 for gain setting
Figure 7-23. Harmonic Distortion vs RL
Figure 7-24. Harmonic Distortion vs Gain
-75
-80
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
Max IMD2
Max IMD3
-85
-90
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-95
-100
-105
-110
-115
-120
-125
-1
-0.75 -0.5 -0.25
0
0.25
0.5
Common-Mode Voltage, VOCM (V)
0.75
1
1M
Frequency (Hz)
10M
D029
D030
VO = 5 VPP with VOCM adjusted
VO = 2 VPP per tone, ±50-kHz tone spacing
Figure 7-25. Harmonic Distortion vs VOCM
Figure 7-26. Intermodulation Distortion (IMD2 and IMD3) vs
Frequency
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7.7 Typical Characteristics: (VS+) – (VS–) = 5 V (continued)
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless
otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
1.8
1.4
1
2.5
2
1.5
1
0.6
0.2
-0.2
-0.6
-1
OUT+, TA = -40èC
OUT+, TA = 25èC
OUT+, TA = 85èC
OUT+, TA = 125èC
OUT-, TA = -40èC
OUT-, TA = 25èC
OUT-, TA = 85èC
OUT-, TA = 125èC
0.5
0
-0.5
-1
-1.5
-2
-1.4
-1.8
SE-in, diff-out
Diff-in, diff-out
-2.5
-5
0
5
10 15 20 25 30 35 40 45 50 55 60 65
Output Current (mA)
Time, 15 ns per division
D033
D075
VO = 2-V step,
VS = 5 V, VOCM at midsupply, average of 30 units
SE-in, diff-out: rising SR = 325 V/µs, falling SR = 230 V/µs,
diff-in, diff-out: rising SR = 305 V/µs, falling SR = 310 V/µs
Figure 7-28. ±Maximum Output Voltage vs Output Current and
Temperature
Figure 7-27. Large-Signal Step Response
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7.8 Typical Characteristics: (VS+) – (VS–) = 3 V
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input (SE-in), differential output (diff-out), and input and output referenced to default midsupply for AC-coupled tests (unless
otherwise noted); see Figure 8-1 for a gain of 1-V/V test circuit.
6
3
3
0
0
-3
-3
-6
-9
-12
-6
G = 0.5 V/V
G = 1 V/V
G = 2 V/V
G = 5 V/V
G = 10 V/V
-9
VO = 0.2 VPP
VO = 1 VPP
VO = 2 VPP
-12
100k
1M
10M
Frequency (Hz)
100M
100k
1M
10M
Frequency (Hz)
100M
D037
D038
VO = 200 mVPP, see Figure 8-1 and Table 10-1 for resistor
values
See Figure 8-1
Figure 7-30. Frequency Response vs VO
Figure 7-29. Small-Signal Frequency Response vs Gain
6
100
10
en
in
3
0
-3
10
1
-6
RL = 150 W
RL = 500 W
RL = 1 kW
RL = 2 kW
RL = 10 kW
-9
-12
1
0.1
100k
1M
10M
Frequency (Hz)
100M
1
10
100 1k
Frequency (Hz)
10k
100k
D039
D071
VO = 200 mVPP, see Figure 8-1 with RL adjusted
1/f corners: en = 9 Hz, in = 700 Hz
Figure 7-31. Small-Signal Frequency Response vs RL
Figure 7-32. Input Noise Density vs Frequency
-20
-60
-70
HD2, VO = 1 VPP
HD3, VO = 1 VPP
HD2, VO = 2 VPP
HD3, VO = 2 VPP
HD2, 100 kHz
HD3, 100 kHz
HD2, 1 MHz
HD3, 1 MHz
-30
-40
-50
-80
-60
-70
-90
-80
-100
-110
-120
-130
-140
-90
-100
-110
-120
-130
-140
-150
100
1k
Load Resistance, RL (W)
10k
100k
Frequency (Hz)
1M
10M
D042
D041
G = 1 V/V, VO = 4 VPP, with RL adjusted
G = 1 V/V
Figure 7-34. Harmonic Distortion vs RL
Figure 7-33. Harmonic Distortion vs Frequency
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7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted);
see Figure 8-1 for a gain of 1-V/V test circuit.
250
225
200
175
150
125
100
75
500
450
400
350
300
250
200
150
100
50
VS = 5 V
VS = 12 V
VS = 5 V
VS = 12 V
50
25
0
0
D059
D059
Input Offset Voltage (mV)
Input Offset Current (nA)
1000 DGK units at each VS
1000 DGK units at each VS
Figure 7-35. Input Offset Voltage (VOS
)
Figure 7-36. Input Offset Current (IOS)
250
200
150
100
50
20
15
10
5
0
0
-50
-5
-100
-150
-200
-250
-10
-15
-20
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (èC)
D061
D062
VS = 12 V, 5 V, and 3 V,
delta from 25°C VOS, 30 DGK units for each VS
VS = 12 V and 5 V,
delta from 25°C IOS, 50 DGK units for each VS
Figure 7-37. Input Offset Voltage vs Temperature
Figure 7-38. Input Offset Current vs Temperature
12
30
VS = 3 V
VS = 5 V
VS = 12 V
VS = 5 V
VS = 12 V
11
27
10
9
8
7
6
5
4
3
2
1
0
24
21
18
15
12
9
6
3
0
D063
D064
Input Offset Voltage Drift (mV/°C)
Input Offset Current Drift (pA/°C)
–40°C to +125°C endpoint drift, 30 DGK units for each VS
–40°C to +125°C endpoint drift, 50 DGK units for each VS
Figure 7-39. Input Offset Voltage Drift Histogram
Figure 7-40. Input Offset Current Drift Histogram
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7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range (continued)
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted);
see Figure 8-1 for a gain of 1-V/V test circuit.
80
65
50
35
20
5
-60
10000
1000
100
-90
-120
-150
-180
-210
-240
-270
-300
-10
-25
-40
Gain, no load
Gain, 100-W load
Phase, no load
Phase, 100-W load
10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
10k
100k
1M 10M
Frequency (Hz)
100M
D103
Simulated
Simulated
Figure 7-42. Open-Loop Output Impedance vs Frequency
Figure 7-41. Main Amplifier Differential Open-Loop Gain and
Phase vs Frequency
100
80
60
VS = 3 V
VS = 5 V
VS = 12 V
40
10
1
20
0
-20
-40
-60
-80
0.1
0.01
VS = 12 V
VS = 5 V
VS = 3 V
-100
40k 100k
1M
Frequency (Hz)
10M
60M
Time, 20 ns per division
D049
D013
.
VO = 100-mV step, tr (10% - 90%) = 5.7 ns
Figure 7-43. Closed-Loop Output Impedance vs Frequency
Figure 7-44. Small-Signal Step Response
1000
975
950
925
900
875
850
825
800
775
5.5
VO
PD
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
IS+, TA = -40èC
IS+, TA = 25èC
IS+, TA = 85èC
IS+, TA = 125èC
750
725
700
675
-0.5
-1
-1.5
5
0
5
0
5
0
Time, 500 ns per division
.25
10
.50
11
.75 .50
12 13
2.7
4.0
5.2
6.5
7.7
9.0
D066
D068
Supply Voltage, VS (V)
5 MHz, 2-VPP input, G = 1 V/V, see Figure 8-1
Figure 7-46. PD Turnon and Turnoff Waveform
Average of 30 units
Figure 7-45. Quiescent Current vs VS
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7.9 Typical Characteristics: (VS+) – (VS–) = 3-V to 12-V Supply Range (continued)
at TA ≈ 25°C, VOCM pin = open, RF = 1.5 kΩ, RL = 1 kΩ, VO = 2 VPP, 50-Ω input match, G = 1 V/V, PD = VS+, single-ended
input, differential output, and input and output referenced to default midsupply for AC-coupled tests (unless otherwise noted);
see Figure 8-1 for a gain of 1-V/V test circuit.
6
5000
VS = 3 V, VOCM floating
VS = 3 V, VOCM driven
VS = 5 V, VOCM floating
VS = 5 V, VOCM driven
VS = 12 V, VOCM floating
VS = 12 V, VOCM driven
3
1000
0
-3
-6
-9
-12
100
VS = 12 V, VO = 10 mVPP
VS = 5 V, VO = 10 mVPP
VS = 3 V, VO = 10 mVPP
VS = 5 V, VO = 0.1 VPP
VS = 12 V, VO = 1 VPP
VS = 5 V, VO = 1 VPP
10
100
100k
1M
Frequency (Hz)
10M
1k
10k 100k
Frequency (Hz)
1M
10M
D057
.
The VOCM pin is either driven to midsupply by low-impedance
source or allowed to float and default to midsupply
Figure 7-47. Common-Mode Voltage, Small-Signal and Large-
Signal Response (VOCM Pin Driven)
Figure 7-48. Output Common-Mode (VOCM) Noise vs Frequency
70
60
50
40
30
20
10
0
0.6
0.5
0.4
0.3
0.2
0.1
0
-10
-20
-30
-0.1
-0.2
-0.3
-40
VS = 3 V
VS = 5 V
VS = 12 V
VS = 3 V
VS = 5 V
VS = 12 V
-0.4
-0.5
-0.6
-50
-60
-70
0
200
400
600
800 1000 1200 1400 1600
Time, 100 ns per division
Time (ns)
D056
D074
VOCM pin driven, 0.1-V VOCM step
VOCM pin driven, 1-V VOCM step
Figure 7-49. Common-Mode Voltage Small-Signal Step
Response
Figure 7-50. Common-Mode Voltage Large-Signal Step
Response
90
150
Small-Signal
Large-Signal, VO = 2 VPP
CMRR
PSRR+
PSRR-
85
80
75
70
65
60
55
50
45
40
35
30
25
20
140
130
120
110
100
90
80
70
60
50
40
30
10
100
1k
10k
Frequency (Hz)
100k
1M
10M
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D051
D053
Simulated
Figure 7-51. Output Balance vs Frequency
Simulated
Figure 7-52. CMRR and PSRR vs Frequency
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8 Parameter Measurement Information
8.1 Example Characterization Circuits
The THS4561 offers the advantages of a fully differential amplifier (FDA) design with the trimmed input offset
voltage and low drift of a precision op amp. The FDA is a flexible device where the main aim is to provide a
purely differential output signal centered on a user-configurable common-mode voltage usually matched to the
input common-mode voltage required by an analog-to-digital converter (ADC) following the FDA stage. The
primary options revolve around the choices of single-ended or differential inputs, AC-coupled or DC-coupled
signal paths, gain targets, and resistor value selections. The characterization circuits described in this section
focus on single-ended input to differential output designs as the more challenging application requirement.
Differential sources are supported and are simple to implement and analyze.
The characterization circuits are typically operated with a single-ended, matched, 50-Ω, input termination to a
differential output at the FDA output pins because most lab equipment is single-ended. The FDA differential
output is then translated back to single-ended through a variety of baluns (or transformers) depending on the
test and frequency range. DC-coupled step response testing uses two 50-Ω scope inputs with trace math to
measure the differential output. Single-supply operation is most common in end equipment designs. However,
using split balanced supplies allows simple ground referenced testing without adding further blocking capacitors
in the signal path beyond those capacitors already within the test equipment. The starting point for any single-
ended input to differential output measurements (such as any of the frequency response curves) is shown in
Figure 8-1.
THS4561 Wideband,
Fully Differential Amplifier
-
31.8-dB
50-ꢀ Input Match,
Gain of 1 V/V from RT,
Single-Ended Source to
Differential Output
Insertion Loss
from VOPP to a
50-ꢀ Load
RF1
1.5 kꢀ
RO1
VS+
RG1
1.5 kꢀ
Network
Analyzer,
50-ꢀ Load
487 ꢀ
ADTL1-4-75+
N1
Network
Analyzer,
50-ꢀ Source
Impedance
œ
50-ꢀ
Single-Ended
Source
+
RM
RT1
VO
FDA
VOCM
52.3 ꢀ
52.3 ꢀ
RO2
œ
N2
487 ꢀ
+
PD
RG2
VS+
VSœ
1-kꢀ
Differential
Load
1.5 kꢀ
50-ꢀ Termination
RF2
1.5 kꢀ
RS1
50 ꢀ
RT2
52.3 ꢀ
Figure 8-1. Single-Ended Source to a Differential Gain of a 1-V/V Test Circuit
Most characterization plots fix the RF (RF1 = RF2) value at 1.5 kΩ, as shown in Figure 8-1. This element value is
flexible in application, but 1.5 kΩ provides a good compromise for the parasitic issues linked to this value,
specifically:
•
Added output loading: The FDA functions similarly to an inverting op amp design with feedback resistors
appearing as an added load across the outputs (the approximate total differential load in Figure 8-1 is 1.5 kΩ
|| 1 kΩ = 857 Ω). The 1.5-kΩ value reduces the power dissipated in the feedback networks.
Noise contributions resulting from resistor values. These contributions are both the 4kTRF terms and the
current noise times the RF term referred to the output (see Section 10.1.3).
Parasitic feedback pole at the input summing nodes. This pole is created by the feedback resistor (RF) value
and the 2.4-pF differential input capacitance (as well as any board layout parasitic) and introduces a zero in
the noise gain, which decreases the phase margin in most situations. This effect must be managed for best
frequency response flatness or step response overshoot.
•
•
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The frequency domain characterization curves start with the circuit and component selections of Figure 8-1.
Some of the features in this test circuit include:
•
The elements on the non-signal input side match the signal input resistors. This feature closely matches the
divider networks on each side of the FDA. The three resistors (RG2, RT2, and RS1) on the non-signal input
side can be replaced by a single resistor to ground using a standard value of 1.5 kΩ with some loss in gain
balancing between the two sides.
•
•
Translating from a 1-kΩ differential load to a 50-Ω environment introduces considerable insertion loss in the
measurements (–31.8 dB in Figure 8-1). The measurement path insertion loss normalizes when reporting the
frequency response curves to show the gain response to the FDA output pins.
In the pass band for the output balun, the 50-Ω load of the network analyzer reflects in parallel with the 52.3-
Ω shunt termination, RM. These elements combine to show a differential 1-kΩ load at the output pins of the
THS4561. The source impedance presented to the balun is a differential 50-Ω source. Figure 8-2 and Figure
8-3 show the TINA-TI™ model (available as a TINA-TI™ simulation file) and resulting response flatness for
this relatively low-frequency balun providing 0.1-dB flatness through 100 MHz.
ADTL1-4-75 Model 198.94µ
R1
25 ꢀ
L1
+
+
VG1
œ
R3
50 ꢀ
VM1
R2
25 ꢀ
L2
L1 Inductance: 198.94 µH
L2 Inductance: 198.94 µH
Mutual Inductance: 198.92972 µH
Figure 8-2. Output Measurement Balun Simulation Circuit in TINA-TI™
-6
-6.01
-6.02
-6.03
-6.04
-6.05
-6.06
-6.07
-6.08
-6.09
-6.1
10
8
6
4
2
0
-2
-4
-6
-8
-10
Gain (dB)
Phase (deg)
1k
10k
100k 1M
Frequency (Hz)
10M
100M
D061
Figure 8-3. Output Measurement Balun Flatness Test
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Starting from the test circuit of Figure 8-1, various elements are modified to show the effect of these elements
over a range of design targets, specifically:
•
The gain setting is changed by adjusting the two RT and the RG resistors to provide a 50-Ω input match and
setting the feedback resistors to 1.5 kΩ.
•
Resistive and capacitive output load testing. Changing to lower resistive loads is accomplished by adding
parallel resistors across the output pins in Figure 8-1. Changing to capacitive loads adds series output
resistors to a differential capacitance before the 1-kΩ sense path of Figure 8-1.
•
•
Power-supply settings. Most often, balanced bipolar supplies are used; a 12-V tests use ±6-V supplies, 5-V
tests use ±2.5-V supplies, and 3-V tests use ±1.5-V supplies with the VOCM input control grounded.
The disable control pin (PD) is tied to the positive supply (VS+) for any active channel test.
8.2 Output Interface Circuit for DC-Coupled Differential Testing
The pulse response plots are measured using the output circuit of Figure 8-4. The two sides of this circuit
present a 500-Ω load to ground (for a differential 1-kΩ load) with a 50-Ω source to the two scope inputs. Trace
math function of the scope combines the two sides to generate the step response plots of Figure 7-13, Figure
7-27, and Figure 7-44. Use balanced bipolar supplies for this test so that the THS4561 outputs deliver a ground-
centered differential swing. This setup produces no DC load currents using the circuit of Figure 8-4.
RO1
50-ꢀ
Scope
Input
475 ꢀ
RM1
56.2 ꢀ
THS4561
Output
RM1
RO2
56.2 ꢀ
475 ꢀ
50-ꢀ
Scope
Input
Figure 8-4. Output Interface for DC-Coupled Differential Outputs
8.3 Output Common-Mode Measurements
The circuit of Figure 8-5 is a typical setup for common-mode measurements.
THS4561 Wideband,
Fully Differential Amplifier
RG1
1.5 kꢀ
RF1
1.5 kꢀ
VS+
100 ꢀ
RS
49.9 ꢀ
œ
VOCM
Input
50-ꢀ
Measurement
Equipment
+
VOCM
Signal
Source
FDA
œ
RT
49.9 ꢀ
+
PD
100 ꢀ
VS+
VSœ
RG2
1.5 kꢀ
RF2
1.5 kꢀ
Figure 8-5. Output Common-Mode Measurements
In Figure 8-5, the differential path is terminated back to ground with the two 1.5-kΩ input resistors and the VOCM
control input is driven from a 50-Ω matched source for the frequency response and step response curves of
Figure 7-47, Figure 7-49, and Figure 7-50. The outputs are summed to a center point (to obtain the average, or
common-mode output, VOCM) through two 100-Ω resistors. These 100-Ω resistors form an equivalent 50-Ω
source to the common-mode output for measurements. Figure 7-48 illustrates the common-mode output noise
measurements with a ground on the VOCM input pin or with the VOCM input pin floating. The higher noise in
Figure 7-48 for a floated input can be reduced by including a capacitor to ground at the VOCM control input pin.
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8.4 Differential Amplifier Noise Measurements
To extract the input-referred noise terms from the total output noise, a measurement of the differential output
noise is required under two external conditions to emphasize the different noise terms. A high-gain, low resistor
value condition is used to emphasize the differential input voltage noise and a higher RF at low gains is used to
emphasize the two input current noise terms. The differential output noise must be converted to single-ended
with added gain before being measured by a spectrum analyzer. At low frequencies, a zero 1/f noise, high-gain,
differential to single-ended instrumentation amplifier (such as the INA188) is used. At higher frequencies, a
differential to single-ended balun is used to drive into a high-gain, low-noise, op amp (such as the LMH6629). In
this case, the THS4561 outputs drive 25-Ω resistors into a 1:1 balun where the balun output is terminated single-
endedly at the LMH6629 input with 50 Ω. This termination provides a modest 6-dB insertion loss for the
THS4561 differential output noise that is then followed by a 40-dB gain setting in the very wideband LMH6629.
8.5 Balanced Split-Supply Versus Single-Supply Characterization
Although most end applications use a single-supply implementation, most characterizations are done on a
bipolar balanced supply. Using a bipolar balanced supply keeps the I/O common-mode inputs near midsupply
and provides the most output swing with no DC bias currents for level shifting. These characterizations include
the frequency response, harmonic distortion, and noise plots. The time domain plots are in some cases done
through single-supply characterization to obtain the correct movement of the input common-mode voltage.
8.6 Simulated Characterization Curves
In some cases, a characteristic curve can only be generated through simulation. A good example of this scenario
is the output balance plot of Figure 7-51. This plot shows the best-case output balance (output differential signal
versus output common-mode signal) using exact matching of the external resistors in simulation using a single-
ended input to differential output configuration. The actual output balance is set by resistor mismatch at low
frequencies but intersects and follows the high-frequency portion of Figure 7-51 at higher frequencies.
The remaining simulated plots include:
•
•
AOL gain and phase; see Figure 7-41.
CMRR and PSRR vs frequency; see Figure 7-52.
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8.7 Terminology and Application Assumptions
There are common terms that are unique to this device. This section identifies and explains these terms.
•
Fully differential amplifier (FDA). This term is restricted to devices offering what is similar to a differential
inverting op amp design element that requires an input resistor (not a high-impedance input) and includes a
second internal control loop that sets the output average voltage (VOCM) to a default or set point. This second
common-mode control loop interacts with the differential loop in certain configurations.
•
•
The desired output signal at the two output pins is a differential signal that swings symmetrically around a
common-mode voltage, VOCM, which is the average voltage of the two outputs.
Single-ended to differential. Generally the output is always used differentially in an FDA; however, the source
signal can be either a single-ended or a differential source. For an FDA operating in single-ended to
differential, the input is applied only to one of the two inputs via input resistors.
•
The common-mode control loop has limited bandwidth from the input VOCM pin to the common-mode output
voltage. The internal loop bandwidth beyond the input VOCM buffer is a much wider bandwidth than the
reported VOCM bandwidth, but is not directly discernable. A very wide bandwidth in the internal VOCM loop
is required to perform an effective and low-distortion single-ended to differential conversion.
Several features in the application of the THS4561 are not explicitly stated, but are necessary for correct
operation. These features are:
•
Although often not stated, the disable pin ( PD) is tied to the positive supply when an enabled channel is
desired.
•
Virtually all ac characterization equipment expects a 50-Ω termination from the 50-Ω source and a 50-Ω,
single-ended source impedance from the device outputs to the 50-Ω sensing termination. This condition is
achieved in all characterizations (often with some insertion loss) but is not necessary for most applications.
Matching impedance is most often required when transmitting over longer distances. Tight layouts from a
source, through the THS4561, and to an ADC input do not require doubly-terminated lines or filter designs.
The only exception is if the source requires a defined termination impedance for correct operation (for
example, mixer outputs).
•
•
The amplifier signal path is flexible for use as single-supply or split-supply operation. Most applications are
intended to be single supply, but any split-supply design can be used as long as the total supply voltage
across the TH4561 is less than 12.6 V and the required input, output, and common-mode pin headrooms to
each supply are taken into account. When left open, the VOCM pin defaults to near midsupply for any
combination of split or single supplies used.
External element values are normally assumed to be accurate and matched. In an FDA, this assumption
translates to equal feedback resistor values and a matched impedance from each input summing junction to
either a signal source or a DC bias reference on each side of the inputs. Unbalancing these values introduces
non-idealities in the signal path. For the signal path, imbalanced resistor ratios on the two sides creates a
common-mode to differential conversion. Furthermore, mismatched RF values and feedback ratios create
additional differential output error terms from any common-mode DC or AC signal or noise terms. Using
standard 1% resistor values is a typical approach and generally leads to some nominal feedback ratio
mismatch. Modestly mismatched resistors or ratios do not by themselves degrade harmonic distortion. Where
there is a meaningful common-mode noise or distortion in the input signal, that gets converted to differential
via an element or ratio mismatch. For the best DC precision, use 0.1% accuracy resistors that are readily
available in E96 values.
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9 Detailed Description
9.1 Overview
The THS4561 is a fully differential amplifier featuring an extremely flexible supply voltage range of 2.85 V to
12.6 V, which makes this device an excellent choice for driving differential ADCs and buffering DAC outputs. This
device features a low-power mode with a unique active-pullup resistor (not a conventional pullup resistor) that
improves EMI reliability of the shutdown pin when left floating. This pin draws very little bias current when
enabled, but increases the bias current as it nears the threshold point of shutdown. The increased current
prevents the pin from unintentionally turning the device off in the presence of EMI on the disable pin. Similar to
other fully differential amplifiers, the THS4561 also includes an output common-mode control pin that can be
used to independently set the output common mode to match that of an ADC or other load circuit.
9.2 Functional Block Diagram
VS+
8.5 ꢀ
(RGT Package) FB+
OUT+
œ
INœ
6 kꢀ
6 kꢀ
High-AOL
Differential I/O
Amplifier
+
2.4 pF
œ
IN+
+
OUTœ
VS+
(RGT Package) FBœ
400 kꢀ
8.5 ꢀ
VSœ
œ
VCM
Error
Amplifier
+
VOCM
CMOS
Buffer
PD
400 kꢀ
VSœ
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9.3 Feature Description
In addition to the core differential I/O voltage feedback gain block, there are two 6-kΩ resistors internally across
the outputs to sense the average voltage at the outputs. These resistors feed the average voltage back into a
VCM error amplifier where the voltage is compared to either a default voltage divider across the supplies or an
externally set VOCM target voltage. When the amplifier is disabled, the default midsupply bias string is disabled
to save power.
To achieve the very-low noise at the low power provided by the THS4561, the input stage transistors are
relatively large, thus resulting in a higher differential input capacitance (2.4 pF in Section 9.2). When using the
16-pin WQFN package and the internal feedback traces to the input side of the package, include the nominal
trace impedance of 8.5 Ω in the design. These elements are not included in the TINA-TI™ model and must be
added externally to a design intending to use the RGT package.
9.4 Device Functional Modes
The wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than (VS+) – 0.5 V, or turned off by asserting PD low (1.8 V below the positive
supply). Disabling the amplifier shuts off the quiescent current and stops correct amplifier operation. The signal
path is still present for the source signal through the external resistors, which provides poor signal isolation from
the input to output in power-down mode.
Internal protection diodes remain present across the input pins in both operating and shutdown mode. Large
input signals during disable can turn on the input differential protection diodes, thus producing a load current in
the supply even in power-down.
The VOCM control pin sets the output average voltage. The VOCM defaults to an internal midsupply value if left
open. Driving this high-impedance input with a voltage reference within the valid range sets a target for the
internal VCM error amplifier. If floated to obtain a default midsupply reference for VOCM, an external decoupling
capacitor is recommended to be added on the VOCM pin to reduce the otherwise high output noise for the
internal high-impedance bias (see Figure 7-48).
9.4.1 Power-Down Mode
The power down ( PD) pin must be asserted to the desired voltage for proper power-down mode operation. A
physical internal pullup resistor is not provided on the PD pin so that if the pin is floated, the device defaults to an
ON state. Tie the PD pin to the positive supply voltage for applications that simply require the device to power on
when the supplies are present. For single-supply operation, a minimum of 0.5 V within the positive supply is
required for operation.
The disable operation is referenced from the positive supply. For an OFF state condition, the disable control pin
must be 1.8 V below the positive supply. The THS4561 has a unique power-down circuit that requires
overcoming the specified peak PD pulldown current when the PD voltage is pulled low. When this current
threshold is overcome, the PD current drops to a very small value. The benefit of the circuit is that the device
stays disabled without having to use an active pullup resistor that wastes crucial power to keep the amplifier
disabled in power-sensitive applications.
9.4.2 Single-Ended Source to Differential Output Mode
One of the most useful features supported by the FDA device is an easy conversion from a single-ended input to
a differential output centered on a user-controlled, common-mode level. Although the output side is relatively
straightforward, the device input pins move in a common-mode manner with the input signal. The common-mode
voltage at the input pins, which moves with the input signal, increases the apparent input impedance to be
greater than the RG value. The input active impedance issue applies to both AC-coupled and DC-coupled
designs, and requires somewhat more complex solutions for the resistors to account for this active impedance,
as discussed in Section 10.1.2.
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9.4.2.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output
Conversions
When the signal path can be AC-coupled, the DC biasing for the THS4561 becomes a relatively simple task. In
all designs, start by defining the output common-mode voltage. The AC-coupling requirement can be separated
for the input and output sides of an FDA design. The input can be AC-coupled and the output DC-coupled, or the
output can be AC-coupled and the input DC-coupled, or both can be AC-coupled. One situation where the output
can be DC-coupled (for an AC-coupled input), is when driving directly into an ADC where the VOCM control
voltage uses the ADC common-mode reference to directly bias the FDA output common-mode voltage to the
required ADC input common-mode voltage. In any case, the design starts by setting the desired VOCM. When an
AC-coupled path follows the output pins, the best linearity is achieved by operating VOCM at midsupply, which
can be easily delivered by floating the VOCM pin. The VOCM voltage must be within the linear range for the
common-mode loop, as specified in the headroom specifications. If the output path is also AC-coupled, simply
letting the VOCM control pin float is usually preferred in order to obtain a midsupply default VOCM bias with
minimal elements. To limit noise, place a 0.1-µF decoupling capacitor on the VOCM control pin to ground.
After VOCM is defined, check the target output voltage swing to make certain that the VOCM plus the positive and
negative output swing on each side does not clip into the supplies. If the desired peak-to-peak output differential
swing is defined as VOPP, divide by 4 to obtain the ±VP (peak voltage) swing around VOCM at each of the two
output pins (each pin operates 180° out of phase with the other). Check that VOCM ±VP does not exceed the
absolute supply rails for the rail-to-rail output (RRO) device. Common-mode current does not flow from the
common-mode output voltage set by the VOCM pin towards the device input pins side, because both the source
and balancing resistor on the non-signal input side are DC blocked. The AC-coupled input path sets the input pin
common-mode voltage equal to the output common-mode voltage. If the VOCM voltage is within the headroom
requirement, then the input pins are also in range for the AC-coupled input configuration. This headroom
requirement functions similarly for when the VOCM voltage approaches the negative supply.
The input pin voltages move in a common-mode manner with the input signal. Confirm that the VOCM voltage
plus the input VPP common-mode swing also stays in the VICM specification range for the input pins.
9.4.2.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversions
The output considerations remain the same as for the AC-coupled design. Again, the input can be DC-coupled
when the output is ac coupled. A DC-coupled input with an AC-coupled output can have some advantages to
move the input VICM down by adjusting the VOCM down if the source is ground referenced. When the source is
DC-coupled into the THS4561 (see Figure 10-3), both sides of the input circuit must be DC-coupled to retain
differential balance. Normally, the non-signal input side has an RG element biased to whatever the source
midrange is expected to be, provided that this midscale reference gives a balanced differential swing around
VOCM at the outputs. Often, RG2 is simply grounded for DC-coupled, bipolar-input applications. This configuration
provides a balanced differential output if the source swings around ground. If the source swings from ground to
some positive voltage, grounding RG2 gives a unipolar output differential swing from both outputs at VOCM (when
the input is at ground) to one polarity of the swing. Biasing RG2 to an expected midpoint for the input signal
creates a differential output swing around VOCM
.
One significant consideration for a DC-coupled input is that VOCM sets up a common-mode bias current from
the output back through RF and RG to the source on both sides of the feedback. Without input balancing
networks, the source must sink or source this dc current. After the input signal range and biasing on the other RG
element is set, check that the voltage divider from VOCM to VIN through RF and RG (and possibly RS) establishes
an input VICM at the device input pins that is within the specification range. If the average source is at ground, the
negative rail input stage for the THS4561 is in range for applications using a single positive supply and a positive
output VOCM setting because this dc common-mode current lifts the average FDA input summing junctions
above ground to a positive voltage (the average of the V+ and V– input pin voltages on the FDA). TINA-TI™
simulations of the intended circuit offer a good check for input and output pin voltage swings.
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9.4.3 Differential Input to a Differential Output Mode
In many ways, this method is a much simpler way to operate the FDA from a design equations perspective.
Again, assuming that the two sides of the circuit are balanced with equal RF and RG elements, the differential
input impedance is now just the sum of the two RG elements to a differential inverting summing junction. In these
designs, the input common-mode voltage at the summing junctions does not move with the signal but must be
dc biased in the design range for the input pins and must take into account the voltage headroom required to
each supply. Slightly different considerations apply to AC-coupled or DC-coupled differential input to differential
output designs, as described in the following sections.
9.4.3.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
The most common way to use the THS4561 with an AC-coupled differential source is to simply couple the input
into the RG resistors through the blocking capacitors. Figure 9-1 shows a typical blocking capacitor approach to
a differential input. An optional input differential termination resistor (RM) is included in this design. The RM
element allows the input RG resistors to be scaled up and still delivers lower differential input impedance to the
source. In this example, the RG elements sum to show a 1-kΩ differential impedance and the RM element
combines in parallel to provide a net 500-Ω ac differential impedance to the source. Again, the design ideally
proceeds by selecting the RF element values, then the RG to set the differential gain, and then an RM element (if
needed) to achieve a target input impedance. Alternatively, the RM element can be eliminated, with the 2 × RG
elements set to the desired input impedance and RF set to obtain the differential gain (equal to RF / RG).
THS4561 Wideband,
Fully Differential Amplifier
RF1
1.5 kꢀ
Differential I/O
with AC-Coupled
Input
VS+
RG1
499 ꢀ
10 nF
œ
VS+
VSœ
+
VOCM
RL
1 kꢀ
FDA
VO
œ
+
+
RM
1 kꢀ
1 µF
+
5 V
0 V
PD
VIN
œ
œ
VS+
VSœ
RG2
499 ꢀ
RF2
1.5 kꢀ
10 nF
Figure 9-1. Example AC-Coupled Differential Input Design
The DC biasing for an AC-coupled differential input design is very simple. The output VOCM is set by the VOCM
input control voltage and, because there is no DC current path for the output common-mode voltage (as long as
RM is only differential and not split and connected to ground for instance), the VOCM DC bias also sets the
common-mode operating points for the input pins. For a purely differential input, the voltages on the input pins
remain fixed at the output VOCM setting and do not move with the input signal (unlike the single-ended input
configurations where the input pin common-mode voltages do move with the input signal).
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10 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
10.1 Application Information
Most applications for the THS4561 strive to deliver the best dynamic range in a design that delivers the desired
signal processing along with adequate phase margin for the amplifier itself. The following sections detail some of
the design issues with analysis and guidelines for improved performance.
10.1.1 Differential Open-Loop Gain and Output Impedance
The most important elements to the closed-loop performance are the open-loop gain and open-loop output
impedance. Figure 10-1 shows the simulated differential open-loop gain and phase from the differential inputs to
the differential outputs with no load and with a 100-Ω load. Operating with no load removes any effect introduced
by the open-loop output impedance to a finite load. Figure 10-2 shows the simulated differential open-loop output
impedance.
80
65
50
35
20
5
-60
10000
1000
100
-90
-120
-150
-180
-210
-240
-270
-300
-10
-25
-40
Gain, no load
Gain, 100-W load
Phase, no load
Phase, 100-W load
10k
100k
1M 10M
Frequency (Hz)
100M
10
10
100
1k
10k
100k
Frequency (Hz)
1M
10M 100M 1G
D103
Figure 10-1. No-Load and 100-Ω Loaded AOL Gain
and Phase
Figure 10-2. Differential Open-Loop Output
Impedance
This open-loop output impedance combines with the load to shift the apparent open-loop gain and phase to the
output pins when the load changes. The rail-to-rail output stage shows a very high impedance at low frequencies
that reduces with frequency to a lower midrange value and then peaks again at higher frequencies. The
maximum value at low frequencies is set by the common-mode sensing resistors to be a 6-kΩ dc value (see
Section 9.2.) This high impedance at a low frequency is significantly reduced in closed-loop operation by the
loop gain, as shown in the closed-loop output impedance of Figure 7-43. Figure 10-1 compares the no load AOL
gain to the AOL gain driving a 100-Ω load that shows the effect of the output impedance. The heavier loads pull
the AOL gain down faster to lower crossovers with more phase shift at the lower frequencies.
The much faster phase rolloff for the 100-Ω differential load explains the greater peaked response illustrated in
Figure 7-4 and Figure 7-18 when the load decreases. This same effect happens for the RC loads common with
converter interface designs. Use the TINA-TI™ model to verify loop phase margin in any design.
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10.1.2 Setting Resistor Values Versus Gain
The THS4561 offers considerable flexibility in the configuration and selection of resistor values. The design
starts with the selection of the feedback resistor value. The 1.5-kΩ feedback resistor value used for the
characterization curves is a good compromise between power, noise, and phase margin considerations. With the
feedback resistor values selected (and set equal on each side) the input resistors are set to obtain the desired
gain with input impedance also set with these input resistors. Differential I/O designs provide an input impedance
that is the sum of the two input resistors. Single-ended input to differential output designs present a more
complicated input impedance. Most characteristic curves implement the single-ended to differential design as the
more challenging requirement over differential-to-differential I/O.
For single-ended, matched, input impedance designs, Table 10-1 illustrates the suggested standard resistors set
to approximately a 1.5-kΩ feedback. This table assumes a 50-Ω source and a 50-Ω input match and uses a
single resistor on the non-signal input side for gain matching. Better matching is possible using the same three
resistors on the non-signal input side as on the input side. Figure 10-3 shows the element values and naming
convention for the gain of 1-V/V configuration where the gain is defined from the matched input at RT to the
differential output.
THS4561 Wideband,
Fully Differential Amplifier
50-ꢀ Input Match,
Gain of 1 V/V from RT,
Single-Ended Source to
Differential Output
RF1
1.5 kꢀ
50-ꢀ
Source
Impedance
VS+
RS1
RG1
1.5 kꢀ
50 ꢀ
œ
+
FDA
VO
RL
RT
VOCM
1 kꢀ
œ
52.3 ꢀ
+
PD
RG2
VS+
VSœ
1.52 kꢀ
RF2
1.5 kꢀ
Figure 10-3. Single-Ended to Differential Gain of 1 V/V with Input Matching Using Standard Resistor
Values
Starting from a target feedback resistor value, the desired input matching impedance, and the target gain (AV),
the required input RT value is given by solving the quadratic of Equation 1.
RS
≈
’
2
2RS 2RF +
AV
2RFRS2AV
∆
÷
2
«
◊
2
RT - RT
-
= 0
2RF 2 + A - R A (4 + A ) 2RF 2 + A - R A (4 + A )
V
S
V
V
V
S
V
V
(1)
When this value is derived, the required input side gain resistor is given by Equation 2 and then the single value
for RG2 on the non-signal input side is given by Equation 3:
RF
2
- RS
AV
RG1
=
RS
RT
1+
(2)
RF
2
AV
RS
RG2
=
1+
RT
(3)
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Using these expressions to generate a swept gain table of values results in Table 10-1, where the best standard
1% resistor values are shown to minimize input impedance and gain error to target.
Table 10-1. Swept Gain 50-Ω Input Match with RF = 1.5-kΩ (±1 Standard Values)
GAIN (V/V)
RF
RG1
15000
1500
750
RT
RG2
15000
1500
768
ZIN
AV
0.1
1
1500
1500
1500
1500
1500
49.9
51.1
52.3
54.9
61.9
49.74
49.82
49.98
49.6
0.09973
0.994
1.978
5.014
10.08
2
5
287
316
10
137
165
50.4
Where an input impedance match is not required, simply set the input resistor to obtain the desired gain without
an additional resistor to ground (remove RT in Figure 10-3). This scenario is common when coming from the
output of another single-ended op amp (such as the OPA810 or OPA192). This single-ended to differential stage
shows a higher input impedance than the physical RG as given by the expression for ZA (active input impedance)
shown as Equation 4.
≈
∆
«
’≈
÷∆
◊«
’
÷
◊
RG1
RG2
RF
1+
1+
RG1
ZA = RG1
RF
2 +
RG2
(4)
Using Equation 4 for the gain of 1 V/V with all resistors equal to 1.5-kΩ shows an input impedance of 2 kΩ. The
increased input impedance comes from the common-mode input voltage at the amplifier pins moving in the
same direction as the input signal. The common-mode input voltage must move to create the current in the non-
signal input RG resistor to produce the inverted output. The current flow into the signal-side input resistor is
impeded because the common-mode input voltage moves with the input signal, thus increasing the apparent
input impedance in the signal input path.
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10.1.3 Noise Analysis
The first step in the output noise analysis is to reduce the application circuit to the simplest form with equal
feedback and gain setting elements to ground. Figure 10-4 shows the simplest analysis circuit with the FDA and
resistor noise terms to be considered.
2
2
enRg
enRf
RF
RG
2
In+
+
2
eno
œ
2
Inœ
2
eni
2
2
enRg
enRf
RG
RF
Figure 10-4. FDA Noise Analysis Circuit
The noise powers are shown in Figure 10-4 for each term. When the RF and RG terms are matched on each
side, the total differential output noise is the root sum squared (RSS) of these separate terms. Using NG ≡ 1 +
RF / RG, the total output noise is given by Equation 5. Each resistor noise term is a 4kT × R power (4kT =
1.6E-20J at 290K).
eo = e NG 2 + 2 i R 2 + 2 4kTR NG
ni
N
F
F
(5)
The first term is simply the differential input spot noise times the noise gain, the second term is the input current
noise terms times the feedback resistor (and because there are two uncorrelated current noise terms, the power
is two times one of them), and the last term is the output noise resulting from both the RF and RG resistors, at
again twice the value for the output noise power of each side added together. Running a wide sweep of gains
when holding RF close to 1.5 kΩ and setting the input up for a 50-Ω match gives the standard values and
resulting noise listed in Table 10-2.
When the gain increases, the input-referred noise approaches only the gain of the FDA input voltage noise term
at 5 nV/√ Hz.
Table 10-2. Swept Gain of the Output- and Input-Referred Spot Noise Calculations
GAIN (V/V)
RF
RG1
15000
1500
750
RT
RG2
15000
1500
768
ZIN
AV
eO (nV/√ Hz) eI (nV/√ Hz)
0.1
1
1500
1500
1500
1500
1500
49.9
51.1
52.3
54.9
61.9
49.74
49.82
49.98
49.6
0.09973
0.994
1.978
5.014
10.08
9.15
14.03
18.99
33.20
55.05
91.53
14.03
9.49
2
5
287
316
6.64
10
137
165
50.4
5.51
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10.1.4 Factors Influencing Harmonic Distortion
As illustrated in the swept frequency harmonic distortion plots (Figure 7-7 and Figure 7-21), the THS4561
provides extremely low distortion at lower frequencies. In general, an FDA output harmonic distortion mainly
relates to the open-loop linearity in the output stage corrected by the loop gain at the fundamental frequency.
When the total load impedance decreases, including the effect of the feedback resistor elements in parallel for
loading purposes, the output stage open-loop linearity degrades, thus increasing the harmonic distortion; see
Figure 7-9 and Figure 7-23. When the output voltage swings increase, very fine scale open-loop output stage
nonlinearities increase that also degrade the harmonic distortion; see Figure 7-8 and Figure 7-22. Conversely,
decreasing the target output voltage swings drops the distortion terms rapidly. Figure 7-8 and Figure 7-22
illustrate the effect of going up to a 10-VPP and 8-VPP differential output, respectively, that is more common with
SAR converters.
Increasing the noise gain functions to decrease the loop gain resulting in the increasing harmonic distortion
terms; see Figure 7-10 and Figure 7-24. One advantage of capacitive compensation that is typical in attenuator
designs is that the noise gain is shaped up with frequency to achieve a crossover at an acceptable phase margin
at higher frequencies. This technique holds the loop gain high at frequencies lower than the noise gain zero,
thus improving distortion at lower frequencies.
The THS4561 does an exceptional job of converting from single-ended inputs to differential outputs with very low
harmonic distortions. External resistors of 1% tolerance are used in characterization with good results.
Unbalancing the feedback divider ratios does not degrade distortion directly. However, imbalanced feedback
ratios convert common-mode inputs to a differential mode at the outputs that can result in increased output
errors.
10.1.5 Input Overdrive Performance
Figure 10-5 and Figure 10-6 show a 2-V and a 2X output overdrive triangular waveform, respectively, for the
THS4561. When the output maximum swing is reached at approximately the supply values, increasing input
voltage beyond this condition turns on the internal protection diodes across the two input pins. The internal
protection diodes are two diodes in series in both polarities. This feature clamps the maximum differential
voltage across the inputs to approximately 1.5 V when the output is limited at the supplies but the input exceeds
the available range. The input resistors on both sides limit the current flow in the internal diodes under these
conditions.
15
12
9
10
7.5
5
Input
Output
Input
Output
6
2.5
0
3
0
-3
-6
-9
-12
-15
-2.5
-5
-7.5
-10
Time, 500 ns per division
Time, 500 ns per division
D016
D034
VS = 12 V, Single-ended to differential gain of 2, 2-V output
overdrive,
VS = 5 V, Single-ended to differential gain of 2, 2x input
overdrive,
overdrive recovery = 250 ns
overdrive recovery = 210 ns
Figure 10-5. Overdrive Recovery Performance
Figure 10-6. Overdrive Recovery Performance
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10.2 Typical Application
One common application for the THS4561 is to take a single-ended, high VPP voltage swing (from a high-voltage
precision amplifier such as the OPA810 or OPA192) and deliver that swing to precision SAR ADC as a single-
ended to differential conversion with output common-mode control and implement an active 2nd-order multiple
feedback (MFB) filter design. Designing for a 16-VPP maximum input down to an 8-VPP differential swing requires
a gain of 0.5 V/V. Targeting a 170-kHz Butterworth response with the RC elements tilted towards low noise gives
the example design of Figure 10-7. The VCM control is set to half of a 4.096-V reference, which is typical for
5-V differential SAR applications. With the high voltage capabilities of the THS4561, the design can be easily
adopted for 20-VPP input swing to the FDA for a full 10-VPP swing into 5-V differential SAR ADC by simply using
wider power supplies for the THS4561 to allow for increased output swing headroom with minimal performance
degradation.
THS4561 Wideband,
Fully Differential Amplifier
RF1
1.5 kꢀ
OPA810 or OPA192
Output
RG1
931 ꢀ
470 pF
100 pF
3.01 kꢀ
680 pF
3.01 kꢀ
VS+
VSœ
20 ꢀ
10 ꢀ
To ADC
VS+
+
+
0 V
5 V
VIN
œ
œ
œ
+
8-VPP Differential
SAR ADC Input
100 fF
2.2 nF
VOCM
FDA
œ
+
PD
VOCM
VS+
VSœ
To ADC
+
2.048 V
20 ꢀ
10 ꢀ
œ
100 pF
RG2
931 ꢀ
470 pF
RF2
1.5 kꢀ
Figure 10-7. MFB Filter Driving an ADC Application:
Example 170-kHz Butterworth Response
10.2.1 Design Requirements
The requirements for this application are:
•
•
•
•
•
Single-ended to differential conversion
Attenuation by 0.5-V/V gain
Active filter set to a Butterworth, 170-kHz response shape
Output RC elements set by SAR input requirements (not part of the filter design)
Filter element resistors and capacitors are set to limit added noise over the THS4561 and noise peaking
10.2.2 Detailed Design Procedure
The design proceeds using the techniques and tools suggested in the Design Methodology for MFB Filters in
ADC Interface Applications application note. The process includes:
•
•
•
•
•
Scale the resistor values to not meaningfully contribute to the output noise produced by the THS4561 by itself
Select the RC ratios to hit the filter targets when reducing the noise gain peaking within the filter design
Set the output resistor to 10 Ω into a 2.2-nF differential capacitor
Add 100-pF common-mode capacitors to the load capacitor to improve common noise filtering
Inside the loop, add 20-Ω output resistors after the filter feedback capacitor to increase the isolation to the
load capacitor
•
Include a place for a differential input capacitor (illustrated as 100 fF in Figure 10-7)
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10.2.3 Application Curves
Figure 10-8 and Figure 10-9 show the gain response and the noise results of the circuit shown in Figure 10-7.
Figure 10-7 shows a place for a differential input capacitor (shown as 100 fF) but is not used for the simulation
results shown in this section. Results in Figure 10-8 illustrate a flat Butterworth filter response at the output
nodes going to the ADC. Obtaining the SNR to the ADC input pins, and assuming an 8-VPP full scale (2.83
VRMS), gives the result of Figure 10-9. The 116-dB SNR and 13-µVRMS total noise shown in Figure 10-9 does not
limit the performance for any SAR application.
0
-6
145
140
135
130
125
120
115
15
12.5
10
7.5
5
SNR
Total Noise
-12
-18
-24
-30
-36
-42
-48
-54
-60
-66
-72
-78
-84
-90
2.5
10k
100k
1M
Frequency (Hz)
10M
0
10M
D101
1k
10k
100k
Frequency (Hz)
1M
Figure 10-8. Gain Plot for a 170-kHz Butterworth
Filter
D102
Figure 10-9. Signal-to-Noise Ratio and Total Noise
Plot
11 Power Supply Recommendations
The THS4561 is principally intended to operate with a nominal single-supply voltage of 3 V to 12 V. Supply
voltage tolerances are supported with the specified operating range of 2.85 V (10% low on a 3-V nominal supply)
and 12.6 V (5% high on a 12-V nominal supply). Supply decoupling is required, as described in Section 8.7. Split
(or bipolar) supplies can be used with the THS4561, as long as the total value across the device remains less
than that specified in Section 7.3.
Using a negative supply to deliver a true swing to ground output when driving SAR ADCs can be desired.
Although the THS4561 quotes a rail-to-rail output, linear operation requires approximately 200-mV headroom to
the supply rails. One easy option for extending the linear output swing to ground is to provide the small negative
supply voltage required using the LM7705 fixed –230-mV, negative-supply generator. This low-cost, fixed,
negative-supply generator can accept a 3-V to 5-V positive supply and provides a fixed –230-mV supply for the
negative power supply. Using the LM7705 provides an effective solution, as discussed in the Extending Rail-to-
Rail Output Range for Fully Differential Amplifiers to Include True Zero Volts reference guide.
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12 Layout
12.1 Layout Guidelines
12.1.1 Board Layout Recommendations
Similar to all high-speed devices, best system performance is achieved with close attention to board layout. The
provides a good example of high-frequency layout techniques as a reference. This EVM includes numerous
extra elements and features for characterization purposes that may not apply to some applications. General
high-speed signal path layout suggestions include:
•
Continuous ground planes are preferred for signal routing with matched impedance traces for longer runs;
however, both ground and power planes must be opened up around the capacitive sensitive input and output
device pins. When the signal goes to a resistor, parasitic capacitance becomes more of a band-limiting issue
and less of a stability issue.
•
Good high-frequency decoupling capacitors (0.1 µF) are required to a ground plane at the device power pins.
Additional higher-value capacitors (2.2 µF) are also required but can be placed further from the device power
pins and shared among devices. For best high-frequency decoupling, consider X2Y supply decoupling
capacitors that offer a much higher self-resonance frequency over standard capacitors.
•
•
Differential signal routing over any appreciable distance must use microstrip layout techniques with matched
impedance traces.
The input summing junctions are very sensitive to parasitic capacitance. Any RG elements must connect into
the summing junction with minimal trace length to the device pin side of the resistor. The other side of the RG
elements can have more trace length if needed to the source or to GND.
12.2 Layout Examples
RGœ
RF+
VIN
RTœ
VS+
CBYP
RO+
œ
+
FDA
VOCM
CL
œ
ROœ
+
PD
VS+
CBYP
VSœ
RG+
RFœ
RS+
RT+
Figure 12-1. Representative Schematic for the Layout in
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RS+
VIN
RT+
RTœ
Remove GND and Power plane
under output and inverting pins to
minimize stray PCB capacitance
1
2
3
4
8
7
6
5
INœ
IN+
Place the feedback resistors, RF , gain
resistors, RG , and the isolation
resistors, RO , as close to the device
pins as possible to minimize parasitics
VOCM
VS+
PD
VSœ
OUT+
OUTœ
Vias to connect supply pins to
CBYP. Place CBYP capacitors on
the other side of the PCB as
close to the vias as possible.
Ground and power plane exist on
inner layers.
CL
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
Figure 12-2. Layout Recommendations
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13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
13.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
13.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
13.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
13.5 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
16
13
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
16
13
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4222419/B 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
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23-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS4561IDGKR
THS4561IDGKT
THS4561IRGTR
ACTIVE
ACTIVE
VSSOP
VSSOP
VQFN
DGK
DGK
RGT
8
8
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
4561
4561
NIPDAUAG
Call TI
PREVIEW
16
3000 RoHS (In work)
& Non-Green
THS4561IRUNR
ACTIVE
QFN
RUN
10
3000 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 125
4561
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Dec-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS4561IDGKR
THS4561IDGKT
THS4561IRUNR
VSSOP
VSSOP
QFN
DGK
DGK
RUN
8
8
2500
250
330.0
330.0
180.0
12.4
12.4
8.4
5.3
5.3
2.3
3.4
3.4
2.3
1.4
1.4
8.0
8.0
4.0
12.0
12.0
8.0
Q1
Q1
Q2
10
3000
1.15
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Dec-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS4561IDGKR
THS4561IDGKT
THS4561IRUNR
VSSOP
VSSOP
QFN
DGK
DGK
RUN
8
8
2500
250
366.0
366.0
210.0
364.0
364.0
185.0
50.0
50.0
35.0
10
3000
Pack Materials-Page 2
PACKAGE OUTLINE
RUN0010A
WQFN - 0.8 mm max height
S
C
A
L
E
5
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
2.1
1.9
0.8
0.7
C
SEATING PLANE
0.08 C
0.05
0.00
SYMM
5
(0.2) TYP
4
6
SYMM
2X 1.5
6X 0.5
9
1
0.3
0.2
10X
10
PIN 1 ID
0.1
C A B
0.6
10X
0.05
0.4
4220470/A 05/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
10
SEE SOLDER MASK
DETAIL
10X (0.7)
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
(1.7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4220470/A 05/2020
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RUN0010A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
10X (0.7)
10
1
10X (0.25)
9
SYMM
(1.7)
6X (0.5)
(R0.05) TYP
6
4
5
SYMM
(1.7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 20X
4220470/A 05/2020
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
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TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
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warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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