THS6212 [TI]

高速差分宽带 PLC/HPLC 线路驱动器放大器;


型号：	THS6212
厂家：	TEXAS INSTRUMENTS
描述：	高速差分宽带 PLC/HPLC 线路驱动器放大器放大器驱动驱动器
文件：	总44页 (文件大小：3093K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THS6212

ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

THS6212 差分宽带PLC 线路驱动器放大器

1 特性

3 说明

• 低功耗：

THS6212 是一款具有电流反馈架构的差分线路驱动器

放大器。该器件专用于宽带电力线通信 (PLC) 线路驱

动器应用，运行速度飞快，足以支持 14.5dBm 线路功

率的传输（在最高30MHz 的频率下）。

– 满偏置模式： 23 mA

– 中偏置模式：17.5 mA

– 低偏置模式：11.9 mA

– 低功耗关断模式

THS6212 采用独特架构，在更大限度降低静态电流的

同时仍能实现超高线性度。满偏置条件下的差分失真在

1MHz 时为 –86-dBc，在 10MHz 时降至仅 –71

dBc。这款放大器具有多种固定偏置设置，对于无需放

大器发挥全部性能的线路驱动器而言，可显著节能。此

外，还可以通过可调电流引脚 (IADJ) 进一步降低偏置

电流，从而实现更为出色的灵活性与节能效果。

– IADJ 引脚，用于调节偏置电流

• 低噪声：

– 电压噪声：2.5 nV/√Hz

– 反相电流噪声：18 pA/√Hz

– 同相电流噪声：1.4 pA/√Hz

• 低失真：

– –86-dBc HD2（1MHz，100Ω

差分负载）

– –101-dBc HD3（1MHz，100Ω差分负载）

• 高输出电流：>665 mA（25Ω负载）

• 宽输出摆幅：

– 49 V_PP(28-V，100Ω差分负载）

• 宽带宽：205 MHz (G_DIFF= 10V/V)

• PSRR：在1MHz 频率下提供>55 dB 的良好隔离

• 宽电源范围：10 V to 28 V

49 V_PP（100Ω 差分负载）的宽输出摆幅搭配 28-V 电

源以及超过 650-mA 的电流驱动能力（25Ω 负载），

使得该器件拥有较宽的动态余量，能够将失真限制在尽

可能低的水平。

THS6212 采用24 引脚VQFN 封装。

器件信息⁽¹⁾

封装尺寸（标称值）

器件型号

THS6212

封装

VQFN (24)

5.00mm × 4.00mm

• 过热保护：175°C（典型值）

• 具有集成共模缓冲器的替代器件：THS6222

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附

录。

2 应用

• 高电压、高电流驱动

• 宽带电力线通信

Vs+

THS6212

100

THS6212

ADJ

Vs-

典型线路驱动器电路，采用THS6212

本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问

www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SBOS758

THS6212

www.ti.com.cn

ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

Table of Contents

7.4 Device Functional Modes..........................................24

8 Application and Implementation..................................25

8.1 Application Information............................................. 25

8.2 Typical Applications.................................................. 25

8.3 What To Do and What Not to Do...............................31

9 Power Supply Recommendations................................31

10 Layout...........................................................................32

10.1 Layout Guidelines................................................... 32

10.2 Layout Example...................................................... 34

11 Device and Documentation Support..........................36

11.1 Documentation Support.......................................... 36

11.2 接收文档更新通知................................................... 36

11.3 支持资源..................................................................36

11.4 Trademarks............................................................. 36

11.5 Electrostatic Discharge Caution..............................36

11.6 术语表..................................................................... 36

12 Mechanical, Packaging, and Orderable

1 特性................................................................................... 1

2 应用................................................................................... 1

3 说明................................................................................... 1

4 Revision History.............................................................. 2

5 Pin Configuration and Functions...................................5

6 Specifications.................................................................. 6

6.1 Absolute Maximum Ratings ....................................... 6

6.2 ESD Ratings .............................................................. 6

6.3 Recommended Operating Conditions ........................6

6.4 Thermal Information ...................................................6

6.5 Electrical Characteristics: V_S= 12 V ..........................7

6.6 Electrical Characteristics: V_S= 28 V ..........................9

6.7 Timing Requirements ...............................................10

6.8 Typical Characteristics: V_S= 12 V.............................11

6.9 Typical Characteristics: V_S= 28 V............................ 17

7 Detailed Description......................................................20

7.1 Overview...................................................................20

7.2 Functional Block Diagram.........................................20

7.3 Feature Description...................................................20

Information.................................................................... 36

4 Revision History

注：以前版本的页码可能与当前版本的页码不同

Changes from Revision D (Novermber 2019) to Revision E (May 2021)

Page

• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1

• 将特性列表中的中偏置模式值从17.7mA 更改为17.5mA..................................................................................1

• 将特性列表中的低偏置模式值从12.2mA 更改为11.9mA.................................................................................. 1

• 将特性列表中的电压噪声值从2.7nV/√Hz 更改为2.5nV/√Hz ........................................................................ 1

• 将特性列表中的反相电流噪声值从17pA/√Hz 更改为18pA/√Hz ................................................................... 1

• 将特性列表中的同相电流噪声值从1.2pA/√Hz 更改为1.4pA/√Hz ................................................................. 1

• 将特性列表中的HD2 失真从-100dBc 更改为-86dBc.......................................................................................1

• 将特性列表中的HD3 失真从-89dBc 更改为-101dBc.......................................................................................1

• 将特性列表中的输出电流从> 416mA 更改为> 665mA.....................................................................................1

• 将特性列表中的输出摆幅从43.2Vpp 更改为49Vpp..........................................................................................1

• 将特性列表中的带宽从150MHz 更改为205MHz.............................................................................................. 1

• 将特性列表中的PSRR 从50dB 更改为> 55dB................................................................................................ 1

• 将特性列表中的过热保护从170°C 更改为175°C..............................................................................................1

• 将差分失真更改为HD2 并更新了说明部分的值.................................................................................................1

• 将说明部分的输出摆幅从43.2Vpp 更改为49Vpp..............................................................................................1

• 将说明部分的电源从±12V 更改为28V..............................................................................................................1

• 将说明部分的电流驱动从416mA 更改为650mA...............................................................................................1

• 从文档中删除了YS 接合焊盘封装...................................................................................................................... 1

• 更改了采用THS6212 的典型线路驱动器电路图................................................................................................1

• Removed YS die package and Bond Pad Functions table.................................................................................5

• Deleted Output current, IO from Absolute Maximum Ratings.............................................................................6

• Added Bias control pin voltage in Absolute Maximum Ratings ..........................................................................6

• Added Input voltage to all pins except VS+, VS-, and BIAS control in Absolute Maximum Ratings ..................6

• Added Input current limit in Absolute Maximum Ratings ................................................................................... 6

• Changed Maximum junction, TJ from 130 C to 125 C in Absolute Maximum Ratings ...................................... 6

• Deleted ESD MM in ESD Ratings ......................................................................................................................6

• Changed Operating junction temperature from 130°C to 125°C in Recommended Operating Conditions........ 6

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ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

• Added Minimum ambient operating air temperature spec in Recommended Operating Conditions .................6

• Changed R_ΘJAfrom 33.2 °C/W to 42.3 °C/W in Thermal Information ...............................................................6

• Changed R_ΘJC(Top)from 31.7 °C/W to 32.8 °C/W in Thermal Information ........................................................ 6

• Changed R_ΘJBfrom 11.3 °C/W to 20.9 °C/W in Thermal Information ...............................................................6

• Changed ψ_JTfrom 0.4 °C/W to 3.8 °C/W in Thermal Information .....................................................................6

• Changed ψ_JBfrom 11.3 °C/W to 20.9 °C/W in Thermal Information .................................................................6

• Changed ψ_JC(bot)from 3.9 °C/W to 9.5 °C/W in Thermal Information ...............................................................6

• Added Electrical Characteristics: V_S= 12V table................................................................................................7

• Deleted Electrical Characteristics: VS = ±6 V table............................................................................................7

• Added Electrical Characteristics: VS = 28V table ..............................................................................................9

• Deleted Deleted Electrical Characteristics: VS = ±12 V table.............................................................................9

• Changed t_ONfrom 1µs to 25ns in Timing Requirements ................................................................................. 10

• Changed t_OFFfrom 1µs to 275ns in Timing Requirements ..............................................................................10

• Added Typical Characteristics: V_S= 12 V.........................................................................................................11

• Deleted Typical Characteristics: V_S= ±6 V (Full Bias)......................................................................................11

• Deleted Typical Characteristics: V_S= ±6 V (Mid Bias)......................................................................................11

• Deleted Typical Characteristics: V_S= ±6 V (Low Bias).....................................................................................11

• Added Typical Characteristics: V_S= 28 V.........................................................................................................17

• Deleted Typical Characteristics: V_S= ±12 V (Full Bias)....................................................................................17

• Deleted Typical Characteristics: V_S= ±12 V (Mid Bias)....................................................................................17

• Deleted Typical Characteristics: V_S= ±12 V (Low Bias)...................................................................................17

• Changed output swing from 43.2 Vpp to 49 Vpp in Overview section..............................................................20

• Changed current drive from 416 mA to 650 mA in Overview section...............................................................20

• Changed thermal protection junction temperature from 170°C to 175°C in Overview section......................... 20

• Deleted Output Current and Voltage section.................................................................................................... 20

• Added Output Voltage and Current Drive section.............................................................................................20

• Changed referenced figures for R_Sversus capacitive load in Driving Capacitive Loads section..................... 21

• Changed ±12-V supplies to 28-V supply in Distortion Performance section.................................................... 22

• Changed ±6-V supplies to 12-V supply in Distortion Performance section...................................................... 22

• Changed noise evaluation from 节8.2.2 to 图8-1 in Differential Noise Performance section......................... 22

• Added R_S= 50 Ωin Differential Noise Performance section........................................................................... 22

• Changed 38.9 nV/√Hz calculation to 53.3 nV/√Hz in Differential Noise Performance section.................... 22

• Changed 7 nV/√Hz calculation to 6.5 nV/√Hz in Differential Noise Performance section........................... 22

• Changed output offset calculation to typical rather than worst case in DC Accuracy and Offset Control section

..........................................................................................................................................................................24

• Changed quiescent current value from 23 mA to 19.5 mA in Wideband Current-Feedback Operation section...

• Changed swing from 1.9 V from either rail to 49 Vpp in Wideband Current-Feedback Operation section.......25

• Changed current drive from 416 mA to 650 mA inWideband Current-Feedback Operation section................25

• Changed ± 6 V supply to 28 V supply inWideband Current-Feedback Operation section............................... 25

• Changed 140 MHz bandwidth to 285 MHz inWideband Current-Feedback Operation section........................25

• Changed Noninverting Differential I/O Amplifierfigure inWideband Current-Feedback Operation section.......25

• Changed Frequency Response and Harmonic Distortion figures in Application Curves section..................... 26

• Changed Dual-Supply Downstream Driver figure.............................................................................................27

• Changed supply voltages to ±14 V in Line Driver Headroom Requirements section....................................... 28

• Changed quiescent current value from 23 mA to 19.5 mA and ±12 V to ±14 V in Computing Total Driver

Power for Line-Driving Applications .................................................................................................................30

• Changed 23 mA to 19.5 mA, 24 V to 28 V and 1003 mW to 11 mW in Computing Total Driver Power for Line-

Driving Applications ......................................................................................................................................... 30

• Changed supply range from "±5 V to ±14 V" to "10 V to 28 V" in Power Supply Recommendations section.. 31

• Changed referenced figures for R_Sversus capacitive load in Driving Capacitive Loads section..................... 32

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ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

• Deleted Wafer and Die Information section......................................................................................................32

• Changed ±12-V to 28-V in Layout Guidelines section......................................................................................32

Changes from Revision C (May 2016) to Revision D (Novermber 2019)

Page

• 添加了最后两个特性要点................................................................................................................................... 1

• Added last paragraph to Overview section ......................................................................................................20

• Changed Dual-Supply Downstream Driver figure.............................................................................................27

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ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

5 Pin Configuration and Functions

D1_IN+

D2_IN+

GND

IADJ

D1_FB

D2_FB

D2_OUT

Thermal

Pad

NC = no internal connection.

图5-1. RHF Package 24-Pin VQFN With Exposed Thermal Pad Top View

表5-1. Pin Functions⁽¹⁾

I/O

DESCRIPTION

NAME

BIAS-1

BIAS-2

D1_FB

D2_FB

D1_IN+

D2_IN+

D1_OUT

D2_OUT

GND⁽²⁾

IADJ

NO.

Bias mode parallel control, LSB

Bias mode parallel control, MSB

Amplifier D1 inverting input

Amplifier D2 inverting input

Amplifier D1 noninverting input

Amplifier D2 noninverting input

Amplifier D1 output

I/O

Amplifier D2 output

Control pin ground reference

Bias current adjustment pin

No internal connection

5-16

—

I/O

Negative power-supply connection

Positive power-supply connection

VS–

VS+

(1) The THS6212 defaults to the shutdown (disable) state if a signal is not present on the bias pins.

(2) The GND pin ranges from VS–to (VS+ –5 V).

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

MIN

MAX UNIT

14.5

Supply voltage, V_S= (V_S+) –(V_S–

)

Bias control pin voltage, referenced to GND pin

All pins except VS+, VS–, and BIAS control

Differential input voltage (each amplifier), V_ID

All input pins, current limit

Voltage

Current

(V_S+) + 0.5

±2

(V_S–) –0.5

±10

Continuous power dissipation⁽²⁾

See Thermal Information table

150

Maximum junction, T_J(under any condition)⁽³⁾

Maximum junction, T_J(continuous operation, long-term reliability)⁽⁴⁾

Storage, T_stg

125

150

Temperature

°C

–65

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under

Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability.

(2) The THS6212 incorporates a thermal pad on the underside of the device. This pad functions as a heatsink and must be connected to a

thermally dissipating plane for proper power dissipation. Failure to do so can result in exceeding the maximum junction temperature,

which can permanently damage the device.

(3) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.

(4) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this

temperature can result in reduced reliability or lifetime of the device

6.2 ESD Ratings

VALUE

±2000

±500

UNIT

Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾

Electrostatic

discharge

V_(ESD)

Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN

NOM

MAX

UNIT

V_S

Supply voltage, V_S= (V_S+) –(V_S–

GND pin voltage

)

GND

T_J

V_S–

V_S+–5

125

Operating junction temperature

Ambient operating air temperature

°C

T_A

–40

6.4 Thermal Information

THS6212

THERMAL METRIC⁽¹⁾

RHF (VQFN)

24 PINS

42.3

UNIT

R_θJA

R_θJC(top)

R_θJB

Ψ_JT

Junction-to-ambient thermal resistance

Junction-to-case (top) thermal resistance

Junction-to-board thermal resistance

°C/W

32.8

20.9

Junction-to-top characterization parameter

Junction-to-board characterization parameter

3.8

Y_JB

20.9

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6.4 Thermal Information (continued)

THS6212

THERMAL METRIC⁽¹⁾

RHF (VQFN)

24 PINS

9.5

UNIT

R_θJC(bot)

Junction-to-case (bottom) thermal resistance

°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.5 Electrical Characteristics: V_S= 12 V

at T_A≈25°C, differential closed-loop gain (A_V) = 10 V/V, differential load (R_L) = 50 Ω, series isolation resistor (R_S) = 2.5 Ω

each, R_F= 1.24 kΩ, R_ADJ= 0 Ω, V_O= D1_OUT –D2_OUT, and full bias (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

AC PERFORMANCE

250

180

A_V= 5 V/V, R_F= 1.5 kΩ, V_O= 2 V_PP

A_V= 10 V/V, R_F= 1.24 kΩ, V_O= 2 V_PP

A_V= 15 V/V, R_F= 1 kΩ, V_O= 2 V_PP

SSBW

Small-signal bandwidth

MHz

165

0.1-dB bandwidth flatness

Large-signal bandwidth

MHz

V/µs

LSBW

V_O= 16 V_PP

195

Slew rate (20% to 80%)

V_O= 16-V step

V_O= 2 V_PP

5500

2.1

Rise and fall time (10% to 90%)

Full bias, f = 1 MHz

Mid bias, f = 1 MHz

–80

–78

–61

–90

–86

–83

–69

–65

–62

2.5

A_V= 10 V/V,

Low bias, f = 1 MHz

V_O= 2 V_PP

HD2

2nd-order harmonic distortion

dBc

Full bias, f = 10 MHz

Mid bias, f = 10 MHz

Low bias, f = 10 MHz

Full bias, f = 1 MHz

Mid bias, f = 1 MHz

Low bias, f = 1 MHz

Full bias, f = 10 MHz

Mid bias, f = 10 MHz

Low bias, f = 10 MHz

R_L= 50 Ω

A_V= 10 V/V,

V_O= 2 V_PP

HD3

3rd-order harmonic distortion

dBc

R_L= 50 Ω

e_n

i_n+

i_n-

Differential input voltage noise

Noninverting input current noise

Inverting input current noise

f ≥1 MHz, input-referred

f ≥1 MHz, each amplifier

nV/√Hz

pA/√Hz

1.4

DC PERFORMANCE

Z_OLOpen-loop transimpedance gain

1300

±12

±16

±11

±1

kΩ

Input offset voltage (each amplifier)

Noninverting input bias current

Inverting input bias current

T_A= –40°C

T_A= 85°C

±1

µA

T_A= –40°C

T_A= 85°C

±1

±8

±7

T_A= –40°C

T_A= 85°C

±4

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6.5 Electrical Characteristics: V_S= 12 V (continued)

at T_A≈25°C, differential closed-loop gain (A_V) = 10 V/V, differential load (R_L) = 50 Ω, series isolation resistor (R_S) = 2.5 Ω

each, R_F= 1.24 kΩ, R_ADJ= 0 Ω, V_O= D1_OUT –D2_OUT, and full bias (unless otherwise noted)

PARAMETER

INPUT CHARACTERISTICS

Common-mode input range

TEST CONDITIONS

MIN

TYP

MAX UNIT

Each input with respect to midsupply

Each input

±3.0

CMRR

Common-mode rejection ratio

T_A= –40°C

T_A= 85°C

Noninverting differential input

resistance

10 || 2

kΩ|| pF

Inverting input resistance

OUTPUT CHARACTERISTICS

±9.7

±9.3

±8.4

R_L= 100 Ω, R_S= 0 Ω

R_L= 50 Ω, R_S= 0 Ω

R_L= 25 Ω, R_S= 0 Ω

V_O

Output voltage swing

R_L= 25 Ω, R_S= 0 Ω, based on

V_Ospecification

I_O

Output current (sourcing and sinking)

±338

Short-circuit output current

±0.81

0.03

Z_O

Closed-loop output impedance

f = 1 MHz, differential

POWER SUPPLY

V_S

Operating voltage

T_A= –40°C to +85°C

GND

GND pin voltage

V_S–

19.5

V_S+–5

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Mid bias (BIAS-1 = 1, BIAS-2 = 0)

Low bias (BIAS-1 = 0, BIAS-2 = 1)

Bias off (BIAS-1 = 1, BIAS-2 = 1)

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Mid bias (BIAS-1 = 1, BIAS-2 = 0)

Low bias (BIAS-1 = 0, BIAS-2 = 1)

Bias off (BIAS-1 = 1, BIAS-2 = 1)

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Differential

I_S+

Quiescent current

10.4

0.8

18.8

14.4

9.6

I_S–

Quiescent current

0.01

0.8

Current through GND pin

+PSRR Positive power-supply rejection ratio

Negative power-supply rejection ratio Differential

–PSRR

BIAS CONTROL

With respect to GND pin,

T_A= –40°C to +85°C

Bias control pin voltage range

3.3

Logic 1, with respect to GND pin,

T_A= –40°C to +85°C

2.1

Bias control pin logic threshold

Bias control pin current⁽¹⁾

Logic 0, with respect to GND pin,

T_A= –40°C to +85°C

0.8

BIAS-1, BIAS-2 = 0.5 V (logic 0)

BIAS-1, BIAS-2 = 3.3 V (logic 1)

Off bias (BIAS-1 = 1, BIAS-2 = 1)

–9.6

0.3

µA

Open-loop output impedance

70 || 5

MΩ|| pF

(1) Current is considered positive out of the pin.

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6.6 Electrical Characteristics: V_S= 28 V

at T_A≈25°C, differential closed-loop gain (A_V) = 10 V/V, differential load (R_L) = 100 Ω, R_F= 1.24 kΩ, R_ADJ= 0 Ω, V_O=

D1_OUT –D2_OUT, and full bias (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

AC PERFORMANCE

285

205

A_V= 5 V/V, R_F= 1.5 kΩ, V_O= 2 V_PP

A_V= 10 V/V, R_F= 1.24 kΩ, V_O= 2 V_PP

SSBW

MHz

Small-signal bandwidth, –3 dB

0.1-dB bandwidth flatness

Large-signal bandwidth

Slew rate (20% to 80% level)

Rise and fall time

MHz

V/µs

LSBW

V_O= 40 V_PP

170

V_O= 40-V step

V_O= 2 V_PP

11,000

Full bias, f = 1 MHz

–86

–79

–71

–63

–101

–88

–80

–65

2.5

A_V= 10 V/V,

Low bias, f = 1 MHz

V_O= 2 V_PP

HD2

HD3

2nd-order harmonic distortion

dBc

Full bias, f = 10 MHz

Low bias, f = 10 MHz

Full bias, f = 1 MHz

Low bias, f = 1 MHz

Full bias, f = 10 MHz

Low bias, f = 10 MHz

R_L= 100 Ω

A_V= 10 V/V,

V_O= 2 V_PP

3rd-order harmonic distortion

Differential input voltage noise

R_L= 100 Ω

e_n

f ≥1 MHz, input-referred

f ≥1 MHz

nV/√Hz

pA/√Hz

Noninverting input current noise (each

amplifier)

i_n+

1.7

Inverting input current noise (each

amplifier)

i_n-

f ≥1 MHz

pA/√Hz

DC PERFORMANCE

Z_OLOpen-loop transimpedance gain

1500

±12

–40

±0.5

±1

kΩ

µV/°C

µA

Input offset voltage

Input offset voltage drift

T_A= –40°C to +85°C

Input offset voltage matching

Noninverting input bias current

Inverting input bias current

Inverting input bias current matching

Amplifier A to B

±6

µA

±8

µA

INPUT CHARACTERISTICS

Common-mode input range

Each input

±9

±10

CMRR

Common-mode rejection ratio

Noninverting input resistance

Inverting input resistance

10 || 2

kΩ|| pF

OUTPUT CHARACTERISTICS

±24.5

±12.3

R_L= 100 Ω

R_L= 25 Ω

V_O

Output voltage swing⁽¹⁾

Output current (sourcing and sinking)

I_O

±580

±665

R_L= 25 Ω, based on V_Ospecification

(1)

Short-circuit output current

Output impedance

Z_O

f = 1 MHz, differential

0.01

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ZHCSEZ1E –MAY 2016 –REVISED MAY 2021

6.6 Electrical Characteristics: V_S= 28 V (continued)

at T_A≈25°C, differential closed-loop gain (A_V) = 10 V/V, differential load (R_L) = 100 Ω, R_F= 1.24 kΩ, R_ADJ= 0 Ω, V_O=

D1_OUT –D2_OUT, and full bias (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX UNIT

POWER SUPPLY

V_S

Operating voltage

Quiescent current

T_A= –40°C to +85°C

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Mid bias (BIAS-1 = 1, BIAS-2 = 0)

Low bias (BIAS-1 = 0, BIAS-2 = 1)

Bias off (BIAS-1 = 1, BIAS-2 = 1)

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Mid bias (BIAS-1 = 1, BIAS-2 = 0)

Low bias (BIAS-1 = 0, BIAS-2 = 1)

Bias off (BIAS-1 = 1, BIAS-2 = 1)

Full bias (BIAS-1 = 0, BIAS-2 = 0)

Differential

17.5

11.9

1.1

I_S+

1.3

16.4

10.8

0.1

I_S–

Quiescent current

0.8

Current through GND pin

+PSRR Positive power-supply rejection ratio

Negative power-supply rejection ratio Differential

–PSRR

BIAS CONTROL

With respect to GND pin,

T_A= –40°C to +85°C

Bias control pin range

3.3

14.5

Logic 1, with respect to GND pin,

T_A= –40°C to +85°C

1.9

Bias control pin logic threshold

Bias control pin current⁽²⁾

Logic 0, with respect to GND pin,

T_A= –40°C to +85°C

0.8

BIAS-1, BIAS-2 = 0.5 V (logic 0)

BIAS-1, BIAS-2 = 3.3 V (logic 1)

–15

–10

µA

0.1

(1) See 节7.3.1 for output voltage vs output current characteristics.

(2) Current is considered positive out of the pin.

6.7 Timing Requirements

MIN

NOM

MAX UNIT

t_ON

Turnon time delay: time for output to start tracking the input

Turnoff time delay: time for output to stop tracking the input

t_OFF

275

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6.8 Typical Characteristics: V_S= 12 V

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

-3

-6

-9

A_V= 5 V/V, R_F= 1.5 kW

A_V= 10 V/V, R_F= 1.24 kW

A_V= 15 V/V, R_F= 1 kW

A_V= 20 V/V, R_F= 850 W

-12

A_V= 10 V/V, R_F= 1.24 kW

A_V= 15 V/V, R_F= 1 kW

-15

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

D001

D040

V_O= 2 V_PP

V_O= 16 V_PP

图6-1. Small-Signal Frequency Response

图6-2. Large-Signal Frequency Response

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

-110

-115

-120

Band 0

Band 1

Band 2

Band 3

T_A= -40èC

T_A= 25èC

T_A= 85èC

10M

2.5

7.5 10 12.5 15 17.5 20 22.5 25

Frequency (MHz)

100M

Frequency (Hz)

D005

SGCC HPLC profiles, crest factor = 5 V/V

A_V= 15 V/V, V_O= 2 V_PP

图6-3. Out-of-Band Suppression

图6-4. Small-Signal Frequency Response vs Temperature

R_F= 100 W

R_F= 250 W

R_F= 500 W

R_F= 909 W

R_F= 1240 W

R_F= 250 W

R_F= 500 W

R_F= 700 W

R_F= 1000 W

10M

100M

Frequency (Hz)

100M

Frequency (Hz)

D039

D004

A_V= 10 V/V, V_O= 2 V_PP

A_V= 15 V/V, V_O= 2 V_PP

图6-5. Small-Signal Frequency Response vs R_F

图6-6. Small-Signal Frequency Response vs R_F

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6.8 Typical Characteristics: V_S= 12 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

20.5

20.4

20.3

20.2

20.1

24.1

23.9

23.8

23.7

23.6

23.5

23.4

23.3

23.2

23.1

19.9

19.8

19.7

19.6

19.5

R_F= 100 W

R_F= 250 W

R_F= 500 W

R_F= 700 W

R_F= 1000 W

R_F= 250 W

R_F= 500 W

R_F= 909 W

R_F= 1240 W

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

D041

D042

A_V= 10 V/V, V_O= 2 V_PP

图6-7. Small-Signal Gain Flatness vs R_F

A_V= 15 V/V, V_O= 2 V_PP

图6-8. Small-Signal Gain Flatness vs R_F

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

A_V= 10 V/V,

_F= 1.24 kW

A_V= 15 V/V,

R_F= 1 kW

-3

-6

-0.1

-0.2

-0.3

-0.4

-0.5

-0.6

-9

C_L= 22 pF, R_S= 0 W

C_L= 33 pF, R_S= 0 W

C_L= 47 pF, R_S= 2 W

C_L= 100 pF, R_S= 5 W

-12

-15

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

D006

D043

V_O= 100 mV_PP

V_O= 16 V_PP

Frequency response is measured at the device output pin

before the isolation resistor.

图6-9. Large-Signal Gain Flatness

图6-10. Small-Signal Frequency Response vs C_LOAD

V_O= 2 V_PP

V_O= 5 V_PP

V_O= 10 V_PP

V_O= 16 V_PP

V_O= 2 V_PP

V_O= 5 V_PP

V_O= 10 V_PP

V_O= 16 V_PP

10M

100M

Frequency (Hz)

100M

Frequency (Hz)

D007

D008

A_V= 10 V/V

A_V= 15 V/V

图6-12. Large-Signal Frequency Response vs V_O

图6-11. Large-Signal Frequency Response vs V_O

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6.8 Typical Characteristics: V_S= 12 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

Full-bias

Mid-bias

Low-bias

Full-bias

Mid-bias

Low-bias

10M

100M

Frequency (Hz)

10M

100M

Frequency (Hz)

D003

D002

A_V= 15 V/V, V_O= 2 V_PP

A_V= 10 V/V, V_O= 2 V_PP

图6-14. Small-Signal Frequency Response vs Bias Modes

图6-13. Small-Signal Frequency Response vs Bias Modes

100

Full-bias

Mid-bias

Low-bias

e_n

i_n+

i_n-

10M

100M

Frequency (Hz)

100

10k 100k

Frequency (Hz)

10M

D047

D018

A_V= 15 V/V, V_O= 16 V_PP

图6-15. Large-Signal Frequency Response vs Bias Modes

图6-16. Input Voltage and Current Noise Density vs Frequency

-45

-75

HD2, R_L= 50W

HD2

HD3

-50

-77

HD3, R_L= 50W

-55

HD2, R_L= 100W

HD3, R_L= 100W

-79

-81

-83

-85

-87

-89

-91

-93

-95

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

10M

Frequency (Hz)

100M

Gain (V/V)

D009

D014

V_O= 2 V_PP

f = 1 MHz, V_O= 2 V_PP

图6-17. Harmonic Distortion vs Frequency

图6-18. Harmonic Distortion vs Gain

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6.8 Typical Characteristics: V_S= 12 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

-30

-40

-50

-60

-70

-80

-90

-100

-10

-20

-30

-40

-50

-60

-70

-80

HD2

HD3

HD2

HD3

0.5

Output Voltage (V_PP

)

Output Voltage (V_PP)

D010

D011

f = 1 MHz, A_V= 10 V/V

f = 10 MHz, A_V= 10 V/V

图6-19. Harmonic Distortion vs V_O

图6-20. Harmonic Distortion vs V_O

-60

-65

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

HD2

HD3

HD2

HD3

-70

-75

-80

-85

-90

-95

-100

-105

100

Load Resistance, R_L(W)

300

100

Load Resistance, R_L(W)

300

D012

D013

f = 1 MHz, V_O= 2 V_PP, A_V= 10 V/V

f = 10 MHz, V_O= 2 V_PP, A_V= 10 V/V

图6-21. Harmonic Distortion vs R_L

图6-22. Harmonic Distortion vs R_L

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

12.5

V_INì 10 gain

V_O(A_V= 10)

IMD2

IMD3

7.5

2.5

-2.5

-5

-7.5

-10

-12.5

-15

10k

100k

Frequency (Hz)

10M

100M

Time, 15 ms per division

D015

D023

±12.2 kHz tone spacing, V_O= 2 V_PPper tone

V_IN= 2.8-V_PPtriangular waveform

图6-23. Intermodulation Distortion vs Frequency

图6-24. Overdrive Recovery

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6.8 Typical Characteristics: V_S= 12 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

1.25

D1_OUT- D2_OUT

D1_OUT

D2_OUT

D1_OUT- D2_OUT

D1_OUT

D2_OUT

0.75

0.5

0.25

-1

-3

-5

-7

-9

-0.25

-0.5

-0.75

-1

-1.25

Time, 25 ns per division

D046

D019

V_Ostep = 16 V_PP

V_Ostep = 2 V_PP

图6-26. Large-Signal Pulse Response

图6-25. Small-Signal Pulse Response

130

120

110

100

Z_OL

Phase

Z_OL

Phase

120

110

100

-15

-30

-45

-60

-75

-90

-105

-120

-135

-150

-165

-180

-105

-120

-135

-150

-165

-180

100

10k

100k 1M

Frequency (Hz)

10M

100M

100

10k

100k 1M

Frequency (Hz)

10M

100M

D016

D036

Full-bias simulation

Mid-bias simulation

图6-27. Open-Loop Transimpedance Gain and Phase vs

图6-28. Open-Loop Transimpedance Gain and Phase vs

Frequency

130

120

110

100

Z_OL

Phase

Full-bias

Mid-bias

Low-bias

-15

100k

10k

-30

Shutdown

-45

-60

-75

-90

-105

-120

-135

-150

-165

-180

100

100k

100

10k

100k 1M

Frequency (Hz)

10M

100M

10M

Frequency (Hz)

100M

D037

D017

Low-bias simulation

Simulation

图6-29. Open-Loop Transimpedance Gain and Phase vs

图6-30. Open-Loop Output Impedance vs Frequency

Frequency

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6.8 Typical Characteristics: V_S= 12 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 50 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

Full Bias

Mid Bias

Low Bias

Power-down

I_CC, T_A= -40°C

I_CC, T_A= 25°C

I_CC, T_A= 85°C

I_EE, T_A= -40°C

I_EE, T_A= 25°C

I_EE, T_A= 85°C

-5

-10

-15

-20

-25

0.5

1.5

2.5

3.5

)

4.5

5.5

10 12 14 16 18 20 22 24 26 28

Single-Supply Voltage, V_S(V)

_ADJ(k

R_L= no load

图6-32. Quiescent Current vs R_ADJ

R_L= no load

图6-31. Quiescent Current vs Single-Supply Voltage

160

PSRR+

PSRR-

CMRR

150

140

130

120

110

100

Full Bias

Mid Bias

Low Bias

Power-down

-40

-25

-10

10k

100k 1M

Frequency (Hz)

10M

100M

Ambient Temperature, T_A( C)

D026

R_L= no load

T_J= 50°C, simulation

图6-33. Quiescent Current vs Temperature

图6-34. PSRR and CMRR vs Frequency

B1, T_A= -40(èC)

B1, T_A= 25(èC)

B1, T_A= 85(èC)

B2, T_A= -40(èC)

B2, T_A= 25(èC)

B2, T_A= 85(èC)

B1, B2

D1_OUT- D2_OUT

D1_OUT

D2_OUT

-1

-2

-3

-4

-5

-6

-7

Bias Pin Voltage (V)

10 11 12

Time, 25 ns per division

D024

D025

B1 = full-bias to mid-bias transition with B2 = GND pin, B2 =

full-bias to low-bias transition with B1 = GND pin, GND pin =

V_S–

图6-36. Full-Bias and Shutdown Mode Transition Timing

图6-35. Mode Transition Voltage Threshold

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6.9 Typical Characteristics: V_S= 28 V

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 100 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

-3

-6

-9

A_V= 5 V/V, R_F= 1.5 kW

A_V= 10 V/V, R_F= 1.24 kW

A_V= 15 V/V, R_F= 1 kW

A_V= 20 V/V, R_F= 850 W

R_F= 500 W

R_F= 909 W

R_F= 1240 W

-12

-15

10M

100M

Frequency (Hz)

100M

Frequency (Hz)

D100

D101

V_O= 2 V_PP

图6-37. Small-Signal Frequency Response

V_O= 2 V_PP

图6-38. Small-Signal Frequency Response vs R_F

V_O= 2 V_PP

V_O= 10 V_PP

V_O= 20 V_PP

V_O= 40 V_PP

V_O= 2 V_PP

V_O= 5 V_PP

V_O= 10 V_PP

V_O= 16 V_PP

10M

100M

Frequency (Hz)

100M

Frequency (Hz)

D103

D104

A_V= 10 V/V

A_V= 15 V/V

图6-39. Large-Signal Frequency Response vs V_O

图6-40. Large-Signal Frequency Response vs V_O

-30

Full-bias

Mid-bias

Low-bias

IMD2

IMD3

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

10M

100M

Frequency (Hz)

10k

100k

Frequency (Hz)

10M

100M

D121

D111

V_O= 40 V_PP

图6-41. Large-Signal Frequency Response vs Bias Modes

图6-42. Intermodulation Distortion vs Frequency

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6.9 Typical Characteristics: V_S= 28 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 100 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

-75

-77

-79

-81

-83

-85

-87

-89

-91

-93

-95

HD2, R_L= 50W

HD3, R_L= 50W

HD2, R_L= 100W

HD3, R_L= 100W

HD2

HD3

10M

Frequency (Hz)

100M

Gain (V/V)

D105

D110

V_O= 2 V_PP

f = 1 MHz, V_O= 2 V_PPR_L= 50 Ω

图6-43. Harmonic Distortion vs Frequency

图6-44. Harmonic Distortion vs Gain

-75

-55

-60

-65

-70

-75

-80

-85

HD2

HD3

HD2

HD3

-80

-85

-90

-95

-100

0.5

Output Voltage (V_PP

)

Output Voltage (V_PP)

D106

D107

f = 1 MHz, R_L= 50 Ω

f = 10 MHz, R_L= 50 Ω

图6-45. Harmonic Distortion vs V_O

图6-46. Harmonic Distortion vs V_O

-60

-65

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

HD2

HD3

HD2

HD3

-70

-75

-80

-85

-90

-95

-100

-105

100

Load Resistance, R_L(W)

300

100

Load Resistance, R_L(W)

300

D108

D109

f = 1 MHz, V_O= 2 V_PP

f = 10 MHz, V_O= 2 V_PP

图6-47. Harmonic Distortion vs R_L

图6-48. Harmonic Distortion vs R_L

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6.9 Typical Characteristics: V_S= 28 V (continued)

At T_A≈25°C, A_V= 10 V/V, R_F= 1.24 kΩ, R_L= 100 Ω, R_S= 2.5 Ω, R_ADJ= 0 Ω, full-bias mode (unless otherwise noted).

1.25

D1_OUT- D2_OUT

D1_OUT

D2_OUT

D1_OUT- D2_OUT

D1_OUT

D2_OUT

0.75

0.5

0.25

-5

-0.25

-0.5

-0.75

-1

-10

-15

-20

-25

-1.25

Time, 25 ns per division

D122

D114

V_Ostep = 40 V_PP

V_Ostep = 2 V_PP

图6-50. Large-Signal Pulse Response

图6-49. Small-Signal Pulse Response

Full Bias

Mid Bias

Low Bias

Power-down

0.5

1.5

2.5

R_ADJ(k

3.5

)

4.5

5.5

图6-51. Quiescent Current vs R_ADJ

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7 Detailed Description

7.1 Overview

The THS6212 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for

use in line-driver applications (such as wide-band power-line communications) and is fast enough to support

transmissions of 14.5-dBm line power up to 30 MHz.

The THS6212 is designed as a single-channel solution that can be a drop-in replacement for dual-channel

footprint packages. The package pinout is compatible with the pinout of the THS6214 dual, differential line driver,

and provides an alternative for systems that only require a single-channel device.

The architecture of the THS6212 is designed to provide maximum flexibility with multiple bias settings that are

selectable based on application performance requirements, and also provides an external current pin (IADJ) to

further adjust the bias current to the device. The wide output swing (49 V_PP) and high current drive (650-mA) of

the THS6212 make the device ideally suited for high-power, line-driving applications.

The THS6212 features thermal protection that typically triggers at a junction temperature of 175°C. The device

behavior is similar to the bias off mode when thermal shutdown is activated. The device resumes normal

operation when the die junction temperature reaches approximately 145°C. The device may go in and out of

thermal shutdown until the overload conditions are removed because of the unpredictable behavior of the

overload and thermal characteristics.

7.2 Functional Block Diagram

VS+

D1 IN+

THS6212

D1 OUT

D1 FB

BIAS-1

BIAS-2

IADJ

BIAS

GND

D2 FB

THS6212

D2 OUT

D2 IN+

VS-

7.3 Feature Description

7.3.1 Output Voltage and Current Drive

The THS6212 provides output voltage and current capabilities that are unsurpassed in a low-cost, monolithic op

amp. The output voltage (under no load at room temperature) typically swings closer than 1.1 V to either supply

rail and typically swings to within 1.1 V of either supply with a 100 Ω differential load. The THS6212 can deliver

over 350 mA of current with a 25 Ωload.

Good thermal design of the system is important, including use of heat sinks and active cooling methods, if the

THS6212 is pushed to the limits of its output drive capabilities. 图 7-1 and 图 7-2 show the output drive of the

THS6212 under two different sets of conditions where T_Ais approximately equal to T_J. In practical applications,

T_Jis often much higher than T_Aand is highly dependent on the device configuration, signal parameters, and

PCB thermal design. In order to represent the full output drive capability of the THS6212 in 图7-1 and 图7-2, T_J

≈T_Ais achieved by pulsing or sweeping the output current for a duration of less than 100 ms.

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0.8

0.6

0.4

0.2

Full-bias

Mid-bias

Low-bias

Sourcing, T_A= -40èC

Sourcing, T_A= 25èC

Sourcing, T_A= 85èC

Sinking, T_A= -40èC

Sinking, T_A= 25èC

Sinking, T_A= 85èC

-1

-2

-3

-4

-5

-6

-0.2

-0.4

-0.6

-0.8

-1

-700 -500 -300 -100 100

300

Output Current (mA)

500

700

900

50 100 150 200 250 300 350 400 450 500 550 600

Output Current (mA)

D045

D022

V_S= 12 V, T_J≈T_A≈25°C

V_S= 12 V, T_J≈T_A

图7-2. Linear Single-Ended Output Voltage vs I_O

图7-1. Slammed Single-Ended Output Voltage vs I_O

and Temperature

In 图 7-1, the output voltages are differentially slammed to the rail and the output current is single-endedly

sourced or sunk using a source measure unit (SMU) for less than 100 ms. The single-ended output voltage of

each output is then measured prior to removing the load current. After removing the load current, the outputs are

brought back to mid-supply before repeating the measurement for different load currents. This entire process is

repeated for each ambient temperature. Under the slammed output voltage condition of 图 7-1, the output

transistors are in saturation and the transistors start going into linear operation as the output swing is backed off

for a given I_O,

In 图 7-2, the inputs are floated and the output voltages are allowed to settle to the mid-supply voltage. The load

current is then single-endedly swept for sourcing (greater than 0 mA) and sinking (less than 0 mA) conditions

and the single-ended output voltage is measured at each current-forcing condition. The current sweep is

completed in a few seconds (approximately 3 to 4 seconds) so as not to significantly raise the junction

temperature (T_J) of the device from the ambient temperature (T_A). The output is not swinging and the output

transistors are in linear operation in 图 7-2 until the current drawn exceeds the device capabilities, at which point

the output voltage starts to deviate quickly from the no load output voltage.

To maintain maximum output stage linearity, output short-circuit protection is not provided. This absence of short-

circuit protection is normally not a problem because most applications include a series-matching resistor at the

output that limits the internal power dissipation if the output side of this resistor is shorted to ground. However,

shorting the output pin directly to the adjacent positive power-supply pin, in most cases, permanently damages

the amplifier.

7.3.2 Driving Capacitive Loads

One of the most demanding and yet very common load conditions for an op amp is capacitive loading. Often, the

capacitive load is the input of an ADC—including additional external capacitance that can be recommended to

improve the ADC linearity. A high-speed, high open-loop gain amplifier such as the THS6212 can be very

susceptible to decreased stability and closed-loop response peaking when a capacitive load is placed directly on

the output pin. When the amplifier open-loop output resistance is considered, this capacitive load introduces an

additional pole in the signal path that can decrease the phase margin. One external solution to this problem is

described in this section.

When the primary considerations are frequency response flatness, pulse response fidelity, and distortion, the

simplest and most effective solution is to isolate the capacitive load from the feedback loop by inserting a series

isolation resistor between the amplifier output and the capacitive load. This series resistor does not eliminate the

pole from the loop response, but shifts the pole and adds a zero at a higher frequency. The additional zero

functions to cancel the phase lag from the capacitive load pole, thus increasing the phase margin and improving

stability.

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The Typical Characteristics sections describe the recommended R_Sversus capacitive load (see 图6-10) and the

resulting frequency response at the load. Parasitic capacitive loads greater than 2 pF can begin to degrade

device performance. Long printed-circuit board (PCB) traces, unmatched cables, and connections to multiple

devices can easily cause this value to be exceeded. Always consider this effect carefully, and add the

recommended series resistor as close as possible to the THS6212 output pin (see the Layout Guidelines

section).

7.3.3 Distortion Performance

The THS6212 provides good distortion performance into a 100-Ω load on a 28-V supply. Relative to alternative

solutions, the amplifier provides exceptional performance into lighter loads and operation on a 12 V supply.

Generally, until the fundamental signal reaches very high frequency or power levels, the second harmonic

dominates the distortion with a negligible third-harmonic component. Focusing then on the second harmonic,

increasing the load impedance improves distortion directly. Remember that the total load includes the feedback

network—in the noninverting configuration (see 图 8-1), this value is the sum of R_F+ R_G, whereas in the

inverting configuration this value is just R_F. Providing an additional supply decoupling capacitor (0.01 µF)

between the supply pins (for bipolar operation) also improves the second-order distortion slightly (from 3 dB to

6 dB).

In most op amps, increasing the output voltage swing directly increases harmonic distortion. The Typical

Characteristics sections illustrate the second harmonic increasing at a little less than the expected 2x rate,

whereas the third harmonic increases at a little less than the expected 3x rate. Where the test power doubles,

the difference between the fundamental power and the second harmonic decreases less than the expected 6 dB,

whereas the difference between the fundamental power and the third harmonic decreases by less than the

expected 12 dB. This difference also appears in the two-tone, third-order intermodulation (IM3) spurious

response curves. The third-order spurious levels are extremely low at low-output power levels. The output stage

continues to hold the third-order spurious levels low even when the fundamental power reaches very high levels.

7.3.4 Differential Noise Performance

The THS6212 is designed to be used as a differential driver in high-performance applications. Therefore,

analyzing the noise in such a configuration is important. 图7-3 shows the op amp noise model for the differential

configuration.

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TI Device

4 kTR

TI Device

4 kTR

图7-3. Differential Op Amp Noise Analysis Model

As a reminder, the differential gain is expressed in 方程式1:

2 ´ R_F

G_D= 1 +

R_G

(1)

(2)

The output noise can be expressed as shown in 方程式2:

E_O=

2 ´ G_D´ e_N²+ (i_N´ R_S)²+ 4 kTR_S+ 2(i_IR_F)²+ 2(4 kTR_FG_D)

Dividing this expression by the differential noise gain [G_D= (1 + 2R_F/ R_G)] gives the equivalent input-referred

spot noise voltage at the noninverting input, as shown in 方程式3.

i_IR_F

G_D

4 kTR_F

G_D

E_O=

2 ´ e_N²+ (i_N´ R_S)²+ 4 kTR_S+ 2

+ 2

(3)

Evaluating these equations for the THS6212 circuit and component values of 图 8-1 with R_S= 50 Ω, gives a

total output spot noise voltage of 53.3 nV/√Hz and a total equivalent input spot noise voltage of 6.5 nV/√Hz.

In order to minimize the output noise as a result of the noninverting input bias current noise, keeping the

noninverting source impedance as low as possible is recommended.

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7.3.5 DC Accuracy and Offset Control

A current-feedback op amp such as the THS6212 provides exceptional bandwidth in high gains, giving fast pulse

settling but only moderate dc accuracy. The Electrical Characteristics tables describe an input offset voltage that

is comparable to high-speed, voltage-feedback amplifiers; however, the two input bias currents are somewhat

higher and are unmatched. Although bias current cancellation techniques are very effective with most voltage-

feedback op amps, these techniques do not generally reduce the output dc offset for wideband current-feedback

op amps. Because the two input bias currents are unrelated in both magnitude and polarity, matching the input

source impedance to reduce error contribution to the output is ineffective. Evaluating the configuration of 图 8-1,

using a typical condition at 25°C input offset voltage and the two input bias currents, gives a typical output offset

range equal to 方程式4:

(4)

where

• NG = noninverting signal gain

7.4 Device Functional Modes

The THS6212 has four different functional modes set by the BIAS-1 and BIAS-2 pins. 表 7-1 shows the truth

table for the device mode pin configuration and the associated description of each mode.

表7-1. BIAS-1 and BIAS-2 Logic Table

BIAS-1

BIAS-2

FUNCTION

DESCRIPTION

Full-bias mode (100%)

Mid-bias mode (75%)

Amplifiers on with lowest distortion possible (default state)

Amplifiers on with power savings and a reduction in distortion performance

Amplifiers on with enhanced power savings and a reduction of overall

performance

Low-bias mode (50%)

Shutdown mode

Amplifiers off and output has high impedance

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8 Application and Implementation

备注

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定

器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

8.1 Application Information

The THS6212 is typically used to drive high output power applications with various load conditions. In the Typical

Applications section, the amplifier is presented in a general-purpose, wideband, current-feedback configuration,

and a more specific 100-Ω twisted pair cable line driver; however, the amplifier is also applicable for many

different general-purpose and specific cable line-driving scenarios beyond what is shown in the Typical

Applications section.

8.2 Typical Applications

8.2.1 Wideband Current-Feedback Operation

The THS6212 provides the exceptional ac performance of a wideband current-feedback op amp with a highly

linear, high-power output stage. Requiring only 19.5 mA of quiescent current, the THS6212 has an output swing

of 49 Vpp (100-Ω load) coupled with over 650 mA current drive (25 Ω load). This low-output headroom

requirement, along with biasing that is independent of the supply voltage, provides a remarkable 28-V supply

operation. The THS6212 delivers greater than 285-MHz bandwidth driving a 2-V_PPoutput into 100 Ω on a 28-V

supply. Previous boosted output stage amplifiers typically suffer from very poor crossover distortion when the

output current goes through zero. The THS6212 achieves a comparable power gain with improved linearity. The

primary advantage of a current-feedback op amp over a voltage-feedback op amp is that ac performance

(bandwidth and distortion) is relatively independent of signal gain. 图 8-1 shows the dc-coupled, gain of 10 V/V,

dual power-supply circuit configuration used as the basis of the 28-V Electrical Characteristics tables and Typical

Characteristics sections.

Vs+

THS6212

1.24 k

OUT

274

1.24 k

THS6212

2 ´ R

OUT

= 1 +

DIFF

Vs-

图8-1. Noninverting Differential I/O Amplifier

8.2.1.1 Design Requirements

The main design requirements for wideband current-feedback operation are to choose power supplies that

satisfy common-mode requirements at the input and output of the device, and also to use a feedback resistor

value that allows for the proper bandwidth when maintaining stability. These requirements and the proper

solutions are described in the Detailed Design Procedure section. Using transformers and split power supplies

can be required for certain applications.

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8.2.1.2 Detailed Design Procedure

For ease of test purposes in this design, the THS6212 input impedance is set to 50 Ω with a resistor to ground

and the output impedance is set to 50 Ω with a series output resistor. Voltage swings reported in the Electrical

Characteristics tables are taken directly at the input and output pins, whereas load powers (dBm) are defined at

a matched 50-Ω load. For the circuit of 图 8-1, the total effective load is 100 Ω || 1.24 kΩ || 1.24 kΩ = 86.1 Ω.

This approach allows a source termination impedance to be set at the input that is independent of the signal

gain. For instance, simple differential filters can be included in the signal path right up to the noninverting inputs

with no interaction with the gain setting. The differential signal gain for the circuit of 图8-1 is given by 方程式5:

R_F

A_D= 1 + 2 ´

R_G

(5)

where

• A_D= differential gain

A value of 274 Ωfor the A_D= 10-V/V design is given by 图8-1. The device bandwidth is primarily controlled with

the feedback resistor value because the THS6212 is a current-feedback (CFB) amplifier; the differential gain,

however, can be adjusted with considerable freedom using just the R_Gresistor. In fact, R_Gcan be reduced by a

reactive network that provides a very isolated shaping to the differential frequency response.

Various combinations of single-supply or ac-coupled gain can also be delivered using the basic circuit of 图 8-1.

Common-mode bias voltages on the two noninverting inputs pass on to the output with a gain of 1 V/V because

an equal dc voltage at each inverting node does not create current through R_G. This circuit does show a

common-mode gain of 1 V/V from the input to output. The source connection must either remove this common-

mode signal if undesired (using an input transformer can provide this function), or the common-mode voltage at

the inputs can be used to set the output common-mode bias. If the low common-mode rejection of this circuit is a

problem, the output interface can also be used to reject that common-mode signal. For instance, most modern

differential input analog-to-digital converters (ADCs) reject common-mode signals very well, and a line-driver

application through a transformer also attenuates the common-mode signal through to the line.

8.2.1.3 Application Curves

图 8-2 and 图 8-3 show the frequency response and distortion performance of the circuit in 图 8-1. The

measurements are made with a load resistor (R_L) of 100 Ω, and at room temperature. 图 8-2 is measured using

the three different device power modes, and the distortion measurements in 图 8-3 are made at an output

voltage level of 2 V_PP

-45

-50

-55

-60

-65

-70

-75

-80

-85

-90

-95

-100

-105

HD2, R_L= 50W

HD3, R_L= 50W

HD2, R_L= 100W

HD3, R_L= 100W

Full-bias

Mid-bias

Low-bias

10M

Frequency (Hz)

100M

Frequency (Hz)

D009

D002

图8-3. Harmonic Distortion

图8-2. Frequency Response

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8.2.2 Dual-Supply Downstream Driver

图 8-4 shows an example of a dual-supply downstream driver with a synthesized output impedance circuit. The

THS6212 is configured as a differential gain stage to provide a signal drive to the primary winding of the

transformer (a step-up transformer with a turns ratio of 1:n is shown in 图 8-4). The main advantage of this

configuration is the cancellation of all even harmonic-distortion products. Another important advantage is that

each amplifier must only swing half of the total output required driving the load.

Vs+

THS6212

0.1 µF

2.2 k

1:1.1

2.9 k

2 k

LINE

V_IN

1.4 k

2.9 k

100

2 k

0.1 µF

2.2 k

THS6212

Vs-

图8-4. Dual-Supply Downstream Driver

The analog front-end (AFE) signal is ac-coupled to the driver, and the noninverting input of each amplifier is

biased to the mid-supply voltage (ground in this case). In addition to providing the proper biasing to the amplifier,

this approach also provides a high-pass filtering with a corner frequency that is set at 5 kHz in this example.

Because the signal bandwidth starts at 26 kHz, this high-pass filter does not generate any problems and has the

advantage of filtering out unwanted lower frequencies.

8.2.2.1 Design Requirements

The main design requirements for 图 8-4 are to match the output impedance correctly, satisfy headroom

requirements, and ensure that the circuit meets power driving requirements. These requirements are described

in the Detailed Design Procedure section and include the required equations to properly implement the design.

The design must be fully worked through before physical implementation because small changes in a single

parameter can often have large effects on performance.

8.2.2.2 Detailed Design Procedure

For 图8-4, the input signal is amplified with a gain set by 方程式6:

2 ´ R_F

G_D= 1 +

R_G

(6)

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The two back-termination resistors (R_M= 10 Ω, each) added at each terminal of the transformer make the

impedance of the amplifier match the impedance of the line, and also provide a means of detecting the received

signal for the receiver. The value of these resistors (R_M) is a function of the line impedance and the transformer

turns ratio (n), given by 方程式7:

Z_LINE

R_M=

2n²

(7)

8.2.2.2.1 Line Driver Headroom Requirements

The first step in a transformer-coupled, twisted-pair driver design is to compute the peak-to-peak output voltage

from the target specifications. This calculation is done using 方程式8 to 方程式11:

V_RMS

P_L= 10 ´ log

(1 mW) ´ R_L

(8)

where

• P_L= power at the load

• V_RMS= voltage at the load

• R_L= load impedance

These values produce the following:

P_L

V_RMS

(1 mW) ´ R_L´ 10

V_P= Crest Factor ´ V_RMS= CF ´ V_RMS

where

(9)

(10)

• V_P= peak voltage at the load

• CF = crest factor

V_LPP= 2 ´ CF ´ V_RMS

(11)

where

• V_LPP= peak-to-peak voltage at the load

Consolidating 方程式 8 to 方程式 11 allows the required peak-to-peak voltage at the load to be expressed as a

function of the crest factor, the load impedance, and the power at the load, as given by 方程式12:

P_L

V_LPP= 2 ´ CF ´

(1 mW) ´ R_L´ 10

(12)

V_LPPis usually computed for a nominal line impedance and can be taken as a fixed design target.

The next step in the design is to compute the individual amplifier output voltage and currents as a function of

peak-to-peak voltage on the line and transformer-turns ratio.

When this turns ratio changes, the minimum allowed supply voltage also changes. The peak current in the

amplifier output is given by 方程式13:

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2 ´ V_LPP

±I_P=

4 R_M

(13)

where

• V_PPis as defined in 方程式12, and

• R_Mis as defined in 方程式7 and 图8-5

2 V

LPP

图8-5. Driver Peak Output Voltage

With the previous information available, a supply voltage and the turns ratio desired for the transformer can now

be selected, and the headroom for the THS6212 can be calculated.

The model shown in 图8-6 can be described with 方程式14 and 方程式15 as:

1. The available output swing:

V_PP= V_CC- (V₁+ V₂) - I_P´ (R₁+ R₂)

(14)

2. Or as the required supply voltage:

V_CC= V_PP+ (V₁+ V₂) + I_P´ (R₁+ R₂)

(15)

The minimum supply voltage for power and load requirements is given by 方程式15.

V₁, V₂, R₁, and R₂are given in 表8-1 for the ±14-V operation.

TI Device

OUT

图8-6. Line Driver Headroom Model

表8-1. Line Driver Headroom Model Values

V_S

V₁

R₁

V₂

R₂

±14 V

1 V

0.6 Ω

1.2 Ω

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When using a synthetic output impedance circuit (see 图 8-4), a significant drop in bandwidth occurs from the

specification provided in the Electrical Characteristics tables. This apparent drop in bandwidth for the differential

signal is a result of the apparent increase in the feedback transimpedance for each amplifier. This feedback

transimpedance equation is given by 方程式16:

R_S

R_L

R_S

R_P

1 + 2 ´

Z_FB= R_F´

R_S

R_P

R_F

R_P

1 + 2 ´

R_L

(16)

To increase the 0.1-dB flatness to the frequency of interest, adding a serial RC in parallel with the gain resistor

may be needed, as shown in 图8-7.

THS6212

LINE

100 W

THS6212

图8-7. 0.1-dB Flatness Compensation Circuit

8.2.2.2.2 Computing Total Driver Power for Line-Driving Applications

The total internal power dissipation for the THS6212 in a line-driver application is the sum of the quiescent power

and the output stage power. The THS6212 holds a relatively constant quiescent current versus supply voltage—

giving a power contribution that is simply the quiescent current times the supply voltage used (the supply voltage

is greater than the solution given in 方程式 15). The total output stage power can be computed with reference to

图8-8.

V_CC

I_P

I_AVG

R_T

图8-8. Output Stage Power Model

The two output stages used to drive the load of 图 8-5 are shown as an H-Bridge in 图 8-8. The average current

drawn from the supply into this H-Bridge and load is the peak current in the load given by 方程式 13 divided by

the crest factor (CF) for the signal modulation. This total power from the supply is then reduced by the power in

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R_T, leaving the power dissipated internal to the drivers in the four output stage transistors. That power is simply

the target line power used in 方程式 8 plus the power lost in the matching elements (R_M). In the following

examples, a perfect match is targeted giving the same power in the matching elements as in the load. The

output stage power is then set by 方程式17.

I_P

P_OUT

´ V_CC- 2P_L

(17)

(18)

The total amplifier power is then given by 方程式18:

I_P

P_TOT= I_Q´ V_CC

´ V_CC- 2P_L

For the example given by 图8-4, the peak current is 159 mA for a signal that requires a crest factor of 5.6 with a

target line power of 20.5 dBm into a 100-Ωload (115 mW).

With a typical quiescent current of 19.5 mA and a nominal supply voltage of ±14 V, the total internal power

dissipation for the solution of 图8-4 is given by 方程式19:

(19)

8.3 What To Do and What Not to Do

8.3.1 What To Do

• Include a thermal design at the beginning of the project.

• Use well-terminated transmission lines for all signals.

• Use solid metal layers for the power supplies.

• Keep signal lines as straight as possible.

• Use split supplies where required.

8.3.2 What Not to Do

• Use a lower supply voltage than necessary.

• Use thin metal traces to supply power.

• Forget about the common-mode response of filters and transmission lines.

9 Power Supply Recommendations

The THS6212 is designed to operate optimally using split power supplies. The device has a very wide supply

range of 10 V to 28 V to accommodate many different application scenarios. Choose power-supply voltages that

allow for adequate swing on both the inputs and outputs of the amplifier to prevent affecting device performance.

The ground pin provides the ground reference for the control pins and must be within V_S–to (V_S+– 5 V) for

proper operation.

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10 Layout

10.1 Layout Guidelines

Achieving optimum performance with a high-frequency amplifier such as the THS6212 requires careful attention

to board layout parasitic and external component types. Recommendations that optimize performance include:

1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance on the output

and inverting input pins can cause instability; on the noninverting input, this capacitance can react with the

source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window around

the signal I/O pins must be opened in all ground and power planes around these pins. Otherwise, ground

and power planes must be unbroken elsewhere on the board.

2. Minimize the distance (less than 0.25 in, or 6.35 mm) from the power-supply pins to high-frequency 0.1-µF

decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity

to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and

the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.

An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves

second-harmonic distortion performance. Larger (2.2 µF to 6.8 µF) decoupling capacitors, effective at lower

frequencies, must also be used on the main supply pins. These capacitors can be placed somewhat farther

from the device and can be shared among several devices in the same area of the PCB.

3. Careful selection and placement of external components preserve the high-frequency performance of the

THS6212. Resistors must be of a very low reactance type. Surface-mount resistors work best and allow a

tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-

frequency performance.

Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-

frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic

capacitance, always position the feedback and series output resistor, if any, as close as possible to the

output pin. Other network components, such as noninverting input termination resistors, must also be placed

close to the package. Where double-side component mounting is allowed, place the feedback resistor

directly under the package on the other side of the board between the output and inverting input pins. The

frequency response is primarily determined by the feedback resistor value as described in the Wideband

Current-Feedback Operation Detailed Design Procedure section. Increasing the value reduces the

bandwidth, whereas decreasing the value leads to a more peaked frequency response. The 1.24-kΩ

feedback resistor used in the Typical Characteristics sections at a gain of 10 V/V on 28-V supplies is a good

starting point for design. Note that a 1.5-kΩfeedback resistor, rather than a direct short, is recommended for

a unity-gain follower application. A current-feedback op amp requires a feedback resistor to control stability

even in the unity-gain follower configuration.

4. Connections to other wideband devices on the board can be made with short direct traces or through

onboard transmission lines. For short connections, consider the trace and the input to the next device as a

lumped capacitive load. Relatively wide traces (50 mils to 100 mils [0.050 in to 0.100 in, or 1.27 mm to 2.54

mm]) must be used, preferably with ground and power planes opened up around them. Estimate the total

capacitive load and set R_Sfrom the recommended R_Sversus capacitive load plots (see 图6-10) . Low

parasitic capacitive loads (less than 5 pF) may not need an isolation resistor because the THS6212 is

nominally compensated to operate with a 2-pF parasitic load. If a long trace is required, and the 6-dB signal

loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched-impedance

transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and

stripline layout techniques). A 50-Ωenvironment is not necessary on board; in fact, a higher impedance

environment improves distortion (see the distortion versus load plots). With a characteristic board trace

impedance defined based on board material and trace dimensions, a matching series resistor into the trace

from the output of the THS6212 is used, as well as a terminating shunt resistor at the input of the destination

device. Remember also that the terminating impedance is the parallel combination of the shunt resistor and

the input impedance of the destination device.

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This total effective impedance must be set to match the trace impedance. The high output voltage and

current capability of the THS6212 allows multiple destination devices to be handled as separate

transmission lines, each with their own series and shunt terminations. If the 6-dB attenuation of a doubly-

terminated transmission line is unacceptable, a long trace can be series-terminated at the source end only.

Treat the trace as a capacitive load in this case and set the series resistor value as shown in the

recommended R_Sversus capacitive load plots. However, this configuration does not preserve signal integrity

as well as a doubly-terminated line. If the input impedance of the destination device is low, there is some

signal attenuation as a result of the voltage divider formed by the series output into the terminating

impedance.

5. Socketing a high-speed part such as the THS6212 is not recommended. The additional lead length and pin-

to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, and can

make achieving a smooth, stable frequency response almost impossible. Best results are obtained by

soldering the THS6212 directly onto the board.

6. Solder the exposed thermal pad to a heat-spreading power or ground plane. This pad is electrically isolated

from the die, but must be connected to a power or ground plane and not floated.

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10.2 Layout Example

Input Signal Routing

Output Signal Routing

图10-1. THS6212EVM Top Layer Example

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Resistors for the optional synthesized

output impedance network.

Closely Located Supply

Decoupling Capacitor

Approximate device footprint is

on the reverse side.

图10-2. THS6212EVM Bottom Layer Example

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation

For related documentation see the following:

• Texas Instruments, THS6214 Dual-Port, Differential, VDSL2 Line Driver Amplifiers data sheet

• Texas Instruments, THS6222 8-V to 32-V, Differential Broadband HPLC Line Driver With Common-Mode

Buffer data sheet

11.2 接收文档更新通知

要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新进行注册，即可每周接收产品信息更

改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 支持资源

TI E2E^™支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解

答或提出自己的问题可获得所需的快速设计帮助。

链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅

TI 的《使用条款》。

11.4 Trademarks

TI E2E^™is a trademark of Texas Instruments.

所有商标均为其各自所有者的财产。

11.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric changes could cause the device not to meet its published

specifications.

11.6 术语表

TI 术语表

本术语表列出并解释了术语、首字母缩略词和定义。

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGE OPTION ADDENDUM

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27-Oct-2021

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan

Lead finish/

Ball material

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

(6)

THS6212IRHFR

THS6212IRHFT

ACTIVE

VQFN

RHF

3000 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

250 RoHS & Green NIPDAU | NIPDAUAG Level-2-260C-1 YEAR

-40 to 85

THS6212

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

⁽³⁾MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6)

Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

27-Oct-2021

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS

TAPE DIMENSIONS

Reel

Diameter

Cavity

A0 Dimension designed to accommodate the component width

B0 Dimension designed to accommodate the component length

K0 Dimension designed to accommodate the component thickness

Overall width of the carrier tape

P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2

Q3 Q4

Q1 Q2

Q3 Q4

User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

THS6212IRHFR

THS6212IRHFT

VQFN

RHF

3000

250

330.0

180.0

12.4

12.5

4.3

5.3

1.1

1.3

1.1

8.0

12.0

250

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

17-Apr-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

THS6212IRHFR

THS6212IRHFT

VQFN

RHF

3000

250

338.0

367.0

210.0

205.0

355.0

367.0

185.0

200.0

50.0

35.0

33.0

250

Pack Materials-Page 2

PACKAGE OUTLINE

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

4.1

3.9

PIN 1 INDEX AREA

0.5

0.3

5.1

4.9

0.30

0.18

DETAIL

OPTIONAL TERMINAL

TYPICAL

1 MAX

SEATING PLANE

0.08 C

0.05

0.00

2.65 0.1

2X 2

(0.1) TYP

EXPOSED

THERMAL PAD

20X 0.5

3.65 0.1

SYMM

SEE TERMINAL

DETAIL

0.30

0.18

24X

0.1

C B A

PIN 1 ID

(OPTIONAL)

SYMM

0.05

0.5

0.3

24X

4219064 /A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

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EXAMPLE BOARD LAYOUT

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

(2.65)

SYMM

24X (0.6)

24X (0.24)

(3.65)

(1.575)

20X (0.5)

SYMM

(4.8)

(0.62)

TYP

(R0.05)

TYP

(

0.2) TYP

VIA

(1.025)

TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE:18X

0.07 MIN

ALL AROUND

0.07 MAX

ALL AROUND

SOLDER MASK

OPENING

METAL

EXPOSED

METAL

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

EXPOSED

METAL

NON SOLDER MASK

DEFINED

SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

4219064 /A 04/2017

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

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EXAMPLE STENCIL DESIGN

RHF0024A

VQFN - 1 mm max height

PLASTIC QUAD FLATPACK - NO LEAD

6X (1.17)

(0.685) TYP

24X (0.6)

24X (0.24)

(1.24)

TYP

20X (0.5)

SYMM

(4.8)

6X (1.04)

(R0.05) TYP

METAL

TYP

SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE:20X

4219064 /A 04/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验

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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE

邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

THS6212 [TI]

相关型号：

THS6212IRHFR

THS6212IRHFT

THS6214

THS6214IPWP

THS6214IPWPR

THS6214IRHFR

THS6214IRHFT

THS6222

THS6222IRGTR

THS6222IRHFR

THS6222IRHFT

THS6222YS