THS6222IRGTR [TI]
THS6222 8 V to 32 V, Differential HPLC Line Driver with Common-Mode Buffer;
| 型号： | THS6222IRGTR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | THS6222 8 V to 32 V, Differential HPLC Line Driver with Common-Mode Buffer |
| 文件： | 总46页 (文件大小：3618K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THS6222
SBOS974C – AUGUST 2019 – REVISED NOVEMBER 2020
THS6222 8 V to 32 V, Differential HPLC Line Driver with Common-Mode Buffer
1 Features
3 Description
•
•
•
•
•
Supply range (VS): 8 V to 32 V
Integrated midsupply common-mode buffer
Large-signal bandwidth: 195 MHz (VO = 16 VPP
Slew rate (16 V step): 5500 V/µs
Low distortion (VS = 12 V, 50 Ω load):
– HD2: –80 dBc (1 MHz)
The THS6222 is a differential line-driver amplifier with
a current-feedback architecture manufactured using
Texas Instruments' proprietary, high-speed, silicon-
germanium (SiGe) process. The device is targeted for
use in broadband, high-speed, power line
communications (HPLC) line driver applications that
require high linearity when driving heavy line loads.
)
– HD3: –90 dBc (1 MHz)
The unique architecture of the THS6222 uses minimal
quiescent current while achieving very high linearity.
The amplifier has an adjustable current pin (IADJ) that
sets the nominal current consumption along with the
multiple bias modes that allow for enhanced power
savings where the full performance of the amplifier is
not required. Shutdown bias mode provides further
power savings during receive mode in time division
multiplexed (TDM) systems while maintaining high
output impedance. The integrated midsupply
•
•
Output current: 338 mA (VS = 12 V, 25 Ω load)
Wide output swing (VS = 12 V):
– 19.4 VPP (100 Ω load)
– 18.6 VPP (50 Ω load)
Adjustable power modes:
– Full-bias mode: 19.5 mA
– Mid-bias mode: 15 mA
– Low-bias mode: 10.4 mA
– Low-power shutdown mode
– IADJ pin for variable bias
•
common-mode
buffer
eliminates
external
components, reducing system cost and board space.
•
•
Integrated overtemperature protection
Pin-compatible with the 24-pin THS6212 VQFN
The wide output swing of 57 VPP (100 Ω load) with
32-V power supplies, coupled with over 650 mA
current drive (25 Ω load), allows for wide dynamic
range that keeps distortion minimal.
2 Applications
•
•
•
•
•
•
SGCC HPLC line drivers
Smart meters
Data concentrators
Power line communications gateways
Home networking PLC
Differential DSL line drivers
The THS6222 is available in a 24-pin VQFN package
with exposed thermal pad and is specified for
operation from –40°C to +85°C ambient temperature.
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
5.00 mm × 4.00 mm
1261.00 µm × 1641.00 µm
3.0 mm × 3.0 mm
VQFN (24)
THS6222
Wafer Sale (19)
VQFN (16)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1-bit power mode control
Full-bias / shutdown
+12 V
THS6222
BIAS
2
BIAS
1
IADJ
VS+
+12 V
AV =
10 V/V
Bias Current Control
100 nF
RS1
2.49 ꢀ
PLC ASIC
D1
IN+
100 nF
+
D1
VS+
OUT
œ
RF1
1.24 kꢀ
1:1
RT1
249 ꢀ
5 kꢀ
CM
Buffer
D1
INt
520 ꢀ
5 kꢀ
Optional
Thermal
Protection
RG
274 ꢀ
50 ꢀ
Power Line
RL
50 ꢀ
VCM
DAC
f
100 nF
+12 V
D2
INt
RT2
249 ꢀ
RF2
1.24 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
RS2
2.49 ꢀ
100 nF
100 nF
D
GND
VSt
GND
GND
Typical Line-Driver Circuit Using the THS6222
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THS6222
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SBOS974C – AUGUST 2019 – REVISED NOVEMBER 2020
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings ....................................... 5
6.2 ESD Ratings .............................................................. 5
6.3 Recommended Operating Conditions ........................5
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics: VS = 12 V ..........................6
6.6 Electrical Characteristics: VS = 32 V ..........................8
6.7 Timing Requirements ...............................................10
6.8 Typical Characteristics: VS = 12 V............................ 10
6.9 Typical Characteristics: VS = 32 V............................ 17
7 Detailed Description......................................................20
7.1 Overview...................................................................20
7.2 Functional Block Diagram.........................................20
7.3 Feature Description...................................................21
7.4 Device Functional Modes..........................................26
8 Application and Implementation..................................26
8.1 Application Information............................................. 26
8.2 Typical Applications.................................................. 26
8.3 What to Do and What Not to Do............................... 29
9 Power Supply Recommendations................................29
10 Layout...........................................................................30
10.1 Layout Guidelines................................................... 30
10.2 Wafer and Die Information...................................... 31
10.3 Layout Examples.................................................... 33
11 Device and Documentation Support..........................34
11.1 Development Support............................................. 34
11.2 Documentation Support.......................................... 34
11.3 Receiving Notification of Documentation Updates..34
11.4 Support Resources................................................. 34
11.5 Trademarks............................................................. 34
11.6 Electrostatic Discharge Caution..............................34
11.7 Glossary..................................................................34
12 Mechanical, Packaging, and Orderable
Information.................................................................... 34
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2020) to Revision C (November 2020)
Page
•
•
•
•
Updated the numbering format for tables, figures, and cross-references throughout the document .................1
Added VQFN (16) Package to the Device Information table.............................................................................. 1
Updated the RHF package in the Pin Configuration and Functions section.......................................................3
Added the RGT package in the Pin Configuration and Functions section..........................................................3
Changes from Revision A (December 2019) to Revision B (April 2020)
Page
•
•
•
•
Added Wafer Sale Package and Body Size (NOM) to the Device Information table .........................................1
Added the YS Die bondpad and functions..........................................................................................................3
Updated Table 1 BIAS-1 and BIAS-2 Logic Table.............................................................................................26
Added Wafer and Die Information section........................................................................................................ 31
Changes from Revision * (August 2019) to Revision A (December 2019)
Page
•
Changed device status from advance information to production data ...............................................................1
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SBOS974C – AUGUST 2019 – REVISED NOVEMBER 2020
5 Pin Configuration and Functions
D1_IN+
D2_IN+
DGND
IADJ
1
2
3
4
5
6
18
17
16
15
14
13
D2_IN–
D2_OUT
NC
D1_IN+
D2_IN+
DGND
IADJ
1
2
3
4
12
11
10
9
D1_OUT
D1_IN–
D2_IN–
D2_OUT
Thermal Pad
Thermal Pad
NC
VCM
NC
NC
NC
Not to scale
Not to scale
NC = no internal connection.
Figure 5-2. RGT Package
Figure 5-1. RHF Package
24-Pin VQFN With Exposed Thermal Pad
Top View
16-Pin VQFN With Exposed Thermal Pad
Top View
Table 5-1. Pin Functions
PIN
RHF
23
24
19
18
1
TYPE(1)
DESCRIPTION
NAME
BIAS-1(2)
BIAS-2(2)
D1_IN–
D2_IN–
D1_IN+
D2_IN+
D1_OUT
D2_OUT
DGND(3)
IADJ
RGT
15
16
11
10
1
I
I
Bias mode control, LSB
Bias mode control, MSB
I
Amplifier D1 inverting input
Amplifier D2 inverting input
Amplifier D1 noninverting input
Amplifier D2 noninverting input
Amplifier D1 output
I
I
2
2
I
20
17
3
12
9
O
O
I
Amplifier D2 output
3
Ground reference for bias control pins
Bias current adjustment pin
No internal connection
4
4
I
NC
6-16
5
6
—
O
P
P
VCM
5
Common-mode buffer output
Negative power-supply connection
Positive power-supply connection
VS–
22
21
7, 14
8, 13
VS+
Electrically connected to die substrate and VS–. Connect to VS– on the printed
circuit board (PCB) for best performance.
Thermal Pad
P
(1) I = input, O = output, and P = power,
(2) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(3) The DGND pin ranges from VS– to (VS+ – 5 V).
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19
18
17
16
15
14
THS6222
13
D1_OUT
12
11
D1_OUT (OPT)
D1_INœ
1
D1_IN+
PAD #1
10
9
D2_INœ
2
3
4
5
D2_IN+
DGND
IADJ
D2_OUT (OPT)
8
7
D2_OUT
VS+
VCM
6
Figure 5-3. YS Die
19-Pad Wafer Sale
Top View
Bond Pad Functions
PAD
Type(1)
DESCRIPTION
NAME
NO.
BIAS-1(2)
BIAS-2(2)
D1_IN–
D2_IN–
D1_IN+
D2_IN+
D1_OUT
18
I
I
Bias mode parallel control, LSB
Bias mode parallel control, MSB
Amplifier D1 inverting input
19
11
I
10
I
Amplifier D2 inverting input
1
I
Amplifier D1 noninverting input
Amplifier D2 noninverting input
2
I
13
O
O
O
O
I
Amplifier D1 output (must be used for D1 output)
D1_OUT (OPT)
D2_OUT
D2_OUT (OPT)
DGND(3)
IADJ
12
Optional amplifier D1 output (pad can be left unconnected or connected to pad 13)
Amplifier D2 output (must be used for D2 output)
Optional amplifier D2 output (can be left unconnected or connected to pad 8)
Ground reference for bias control pins
8
9
3
4
5
I
Bias current adjustment pin
VCM
O
P
P
—
Common-mode buffer output
VS–
6, 16, 17
7, 14, 15
—
Negative power-supply connection
VS+
Positive power-supply connection
Backside
Must be connected to the lowest voltage potential on the die (generally VS–)
(1) I = input, O = output, and P = power.
(2) The THS6222 defaults to the shutdown (disable) state if a signal is not present on the bias pins.
(3) The DGND pin ranges from VS– to (VS+ – 5 V).
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
(2)
Supply voltage, VS = (VS+) – (VS–
)
33
V
V
V
V
Bias control pin voltage, referenced to DGND
Common-mode voltage, VCM
0
16.5
Voltage
See Common-Mode Buffer
(VS–) – 0.5 (VS+) + 0.5
All pins except VS+, VS–, VCM, and BIAS control
Maximum junction, TJ (under any condition)
Maximum junction, TJ (continuous operation, long-term reliability)(3)
Storage, Tstg
150
125
150
Temperature
°C
–65
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent device damage. These are stress ratings only,
which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Refer to Breakdown Supply Voltage for breakdown test results.
(3) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature can result in reduced reliability or lifetime of the device. THS6222 has thermal protection that shuts down the device at
approximately 175°C junction temperature and recovery at approximately 145°C.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per ANSI/ESDA/
JEDEC JS-001, all pins(1)
±3500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
8
NOM
MAX
32
UNIT
V
VS
Supply voltage, VS = (VS+) – (VS–
)
DGND
TA
DGND pin voltage
VS–
–40
VS+ – 5
85
V
Ambient operating air temperature
25
°C
6.4 Thermal Information
THS6222
THERMAL METRIC(1)
RHF (VQFN)
24 PINS
43.4
RGT (VQFN)
16 PINS
48.4
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
35
55.1
21.3
22.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.3
1.6
YJB
21.2
22.6
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THS6222
THERMAL METRIC(1)
RHF (VQFN)
24 PINS
9.3
RGT (VQFN)
16 PINS
8.6
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
6.5 Electrical Characteristics: VS = 12 V
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP
AV = 15 V/V, RF = 1 kΩ, VO = 2 VPP
250
180
165
17
SSBW
Small-signal bandwidth
MHz
0.1-dB bandwidth flatness
Large-signal bandwidth
MHz
MHz
V/µs
ns
LSBW
SR
VO = 16 VPP
195
5500
2.1
Slew rate (20% to 80%)
VO = 16-V step
VO = 2 VPP
Rise and fall time (10% to 90%)
Full bias, f = 1 MHz
Mid bias, f = 1 MHz
–80
–78
–78
–61
–61
–61
–90
–86
–83
–69
–65
–62
AV = 10 V/V,
Low bias, f = 1 MHz
HD2
2nd-order harmonic distortion
VO = 2 VPP
RL = 50 Ω
,
dBc
Full bias, f = 10 MHz
Mid bias, f = 10 MHz
Low bias, f = 10 MHz
Full bias, f = 1 MHz
Mid bias, f = 1 MHz
Low bias, f = 1 MHz
Full bias, f = 10 MHz
Mid bias, f = 10 MHz
Low bias, f = 10 MHz
AV = 10 V/V,
HD3
3rd-order harmonic distortion
Differential input voltage noise
VO = 2 VPP
RL = 50 Ω
,
dBc
f ≥ 1 MHz, input-referred, with and
without 100 nF noise-decoupling
capacitor on VCM pin
en
2.5
nV/√Hz
in+
in-
Noninverting input current noise
Inverting input current noise
f ≥ 1 MHz, each amplifier
f ≥ 1 MHz, each amplifier
1.4
18
pA/√Hz
pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain
1300
±12
±16
±11
±1
kΩ
Input offset voltage (each amplifier)
Noninverting input bias current
Inverting input bias current
TA = –40°C
TA = 85°C
mV
TA = –40°C
TA = 85°C
±1
µA
µA
±1
±8
TA = –40°C
TA = 85°C
±7
±4
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6.5 Electrical Characteristics: VS = 12 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
INPUT CHARACTERISTICS
Common-mode input range
TEST CONDITIONS
MIN
TYP
MAX UNIT
Each input with respect to midsupply
±3.0
64
V
Each input
TA = –40°C
TA = 85°C
CMRR
Common-mode rejection ratio
67
dB
62
Noninverting differential input
resistance
10 || 2
43
kΩ || pF
Ω
Inverting input resistance
COMMON-MODE BUFFER CHARACTERISTICS
Voltage at VCM with respect to
midsupply
±2.5
VCM-OS Common-mode offset voltage
mV
TA = –40°C
TA = 85°C
±5
±1
With and without 100-nF VCM noise-
decoupling capacitor, f ≥ 50 kHz
Common-mode voltage noise
20
nV/√Hz
AC-coupled inputs
f = DC
650
520
Ω
Ω
Common-mode output resistance
DC-coupled inputs
OUTPUT CHARACTERISTICS
RL = 100 Ω, RS = 0 Ω
RL = 50 Ω, RS = 0 Ω
RL = 25 Ω, RS = 0 Ω
±9.7
±9.3
VO
Output voltage swing
V
±8.4
IO
Output current (sourcing and sinking) RL = 25 Ω, RS = 0 Ω, based on VO specification
Short-circuit output current
±338
±0.81
0.03
mA
A
ZO
Closed-loop output impedance
f = 1 MHz, differential
Ω
POWER SUPPLY
8
8
12
32
V
32
VS
Operating voltage
TA = –40°C to +85°C
DGND
DGND pin voltage
VS–
0
19.5
15
VS+ – 5
V
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
Low bias (BIAS-1 = 0, BIAS-2 = 1)
Bias off (BIAS-1 = 1, BIAS-2 = 1)
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
Low bias (BIAS-1 = 0, BIAS-2 = 1)
Bias off (BIAS-1 = 1, BIAS-2 = 1)
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Differential
IS+
Quiescent current
mA
10.4
1.1
18.8
14.4
9.8
IS–
Quiescent current
mA
0.4
Current through DGND pin
0.8
mA
dB
dB
+PSRR Positive power-supply rejection ratio
83
–PSRR Negative power-supply rejection ratio Differential
83
BIAS CONTROL
With respect to DGND,
TA = –40°C to +85°C
Bias control pin voltage range
0
3.3
12
V
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6.5 Electrical Characteristics: VS = 12 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 50 Ω, series isolation resistor (RS) = 2.5 Ω
each, RF = 1.24 kΩ, RADJ = 0 Ω, VCM = open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Logic 1, with respect to DGND,
TA = –40°C to +85°C
2.1
Bias control pin logic threshold
V
Logic 0, with respect to DGND,
TA = –40°C to +85°C
0.8
BIAS-1, BIAS-2 = 0.5 V (logic 0)
BIAS-1, BIAS-2 = 3.3 V (logic 1)
Off bias (BIAS-1 = 1, BIAS-2 = 1)
–9.6
0.3
Bias control pin current(1)
µA
1
Open-loop output impedance
70 || 5
MΩ || pF
(1) Current is considered positive out of the pin.
6.6 Electrical Characteristics: VS = 32 V
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 100 Ω, RF = 1.24 kΩ, RADJ = 0 Ω, VCM
open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
=
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
AC PERFORMANCE
AV = 5 V/V, RF = 1.5 kΩ, VO = 2 VPP
AV = 10 V/V, RF = 1.24 kΩ, VO = 2 VPP
285
205
13
SSBW
Small-signal bandwidth, –3 dB
MHz
0.1-dB bandwidth flatness
Large-signal bandwidth
Slew rate (20% to 80% level)
Rise and fall time
MHz
MHz
V/µs
ns
LSBW
SR
VO = 40 VPP
170
11,000
2
VO = 40-V step
VO = 2 VPP
Full bias, f = 1 MHz
–86
–79
–71
–63
–101
–88
–80
–65
2.5
AV = 10 V/V,
Low bias, f = 1 MHz
HD2
HD3
2nd-order harmonic distortion
VO = 2 VPP
,
dBc
dBc
Full bias, f = 10 MHz
Low bias, f = 10 MHz
Full bias, f = 1 MHz
Low bias, f = 1 MHz
Full bias, f = 10 MHz
Low bias, f = 10 MHz
RL = 100 Ω
AV = 10 V/V,
3rd-order harmonic distortion
Differential input voltage noise
VO = 2 VPP
,
RL = 100 Ω
en
f ≥ 1 MHz, input-referred
f ≥ 1 MHz
nV/√Hz
pA/√Hz
Noninverting input current noise (each
amplifier)
in+
1.7
18
Inverting input current noise (each
amplifier)
in-
f ≥ 1 MHz
pA/√Hz
DC PERFORMANCE
ZOL Open-loop transimpedance gain
1500
±12
–40
±0.5
±1
kΩ
mV
µV/°C
mV
µA
Input offset voltage
Input offset voltage drift
TA = –40°C to +85°C
Amplifier A to B
Input offset voltage matching
Noninverting input bias current
Inverting input bias current
Inverting input bias current matching
±6
µA
±8
µA
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6.6 Electrical Characteristics: VS = 32 V (continued)
at TA ≈ 25°C, differential closed-loop gain (AV) = 10 V/V, differential load (RL) = 100 Ω, RF = 1.24 kΩ, RADJ = 0 Ω, VCM
open, VO = D1_OUT – D2_OUT, and full bias (unless otherwise noted)
=
PARAMETER
INPUT CHARACTERISTICS
Common-mode input range
TEST CONDITIONS
MIN
TYP
MAX UNIT
Each input
±11
53
±12
65
V
dB
CMRR
Common-mode rejection ratio
Noninverting input resistance
Inverting input resistance
Each input
10 || 2
38
kΩ || pF
Ω
COMMON-MODE BUFFER CHARACTERISTICS
Voltage at VCM with respect to
midsupply
VCM-OS Common-mode offset voltage
±3.9
mV
With and without 100-nF VCM noise-
decoupling capacitor, f ≥ 50 kHz
Common-mode voltage noise
21
nV/√Hz
Ω
Common-mode output resistance
f = DC
520
OUTPUT CHARACTERISTICS
RL = 100 Ω
RL = 25 Ω
±28.5
±16.3
VO
Output voltage swing(1)
V
Output current (sourcing and sinking)
IO
RL = 25 Ω, based on VO specification
±580
±665
mA
(1)
Short-circuit output current
Output impedance
1
A
ZO
f = 1 MHz, differential
0.01
Ω
POWER SUPPLY
8
8
12
32
V
32
VS Operating voltage
TA = –40°C to +85°C
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
Low bias (BIAS-1 = 0, BIAS-2 = 1)
Bias off (BIAS-1 = 1, BIAS-2 = 1)
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Mid bias (BIAS-1 = 1, BIAS-2 = 0)
Low bias (BIAS-1 = 0, BIAS-2 = 1)
Bias off (BIAS-1 = 1, BIAS-2 = 1)
Full bias (BIAS-1 = 0, BIAS-2 = 0)
Differential
23
17.7
12.2
1.5
22
IS+
Quiescent current
mA
1.8
16.7
11.2
0.5
1
IS–
Quiescent current
mA
0.8
mA
dB
dB
Current through GND pin
+PSRR Positive power-supply rejection ratio
83
–PSRR Negative power-supply rejection ratio Differential
77
BIAS CONTROL
With respect to DGND,
TA = –40°C to +85°C
Bias control pin range
0
3.3
16.5
V
V
Logic 1, with respect to DGND,
TA = –40°C to +85°C
1.9
Bias control pin logic threshold
Logic 0, with respect to DGND,
TA = –40°C to +85°C
0.8
1
BIAS-1, BIAS-2 = 0.5 V (logic 0)
BIAS-1, BIAS-2 = 3.3 V (logic 1)
–15
–10
0.1
Bias control pin current(2)
µA
(1) See Output Voltage and Current Drive and Figure 6-51 for output voltage vs output current characteristics.
(2) Current is considered positive out of the pin.
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6.7 Timing Requirements
MIN
NOM
25
MAX UNIT
tON
Turnon time delay: time for output to start tracking the input
Turnoff time delay: time for output to stop tracking the input
ns
ns
tOFF
275
6.8 Typical Characteristics: VS = 12 V
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
3
3
0
0
-3
-3
-6
-6
-9
-9
AV = 5 V/V, RF = 1.5 kW
AV = 10 V/V, RF = 1.24 kW
AV = 15 V/V, RF = 1 kW
AV = 20 V/V, RF = 850 W
-12
-12
AV = 10 V/V, RF = 1.24 kW
AV = 15 V/V, RF = 1 kW
-15
-15
10M
100M
Frequency (Hz)
1G
10M
100M
Frequency (Hz)
D001
D040
VO = 2 VPP
VO = 16 VPP
Figure 6-1. Small-Signal Frequency Response
Figure 6-2. Large-Signal Frequency Response
-40
27
Band0
Band1
Band2
Band3
TA = -40èC
-45
-50
TA = 25èC
24
TA = 85èC
-55
-60
-65
-70
21
18
15
12
9
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
6
10M
100M
Frequency (Hz)
1G
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
D005
D030
AV = 15 V/V, VO = 2 VPP
SGCC HPLC profiles, crest factor = 5 V/V, see the Broadband
PLC Line Driving section for more details.
Figure 6-4. Small-Signal Frequency Response vs Temperature
Figure 6-3. Out-of-Band Suppression
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
26
23
20
17
14
11
8
27
24
21
18
15
12
9
RF = 100 W
RF = 250 W
RF = 500 W
RF = 700 W
RF = 1000 W
RF = 250 W
RF = 500 W
RF = 909 W
RF = 1240 W
5
10M
100M
Frequency (Hz)
1G
10M
100M
Frequency (Hz)
1G
D039
D004
AV = 10 V/V, VO = 2 VPP
AV = 15 V/V, VO = 2 VPP
Figure 6-5. Small-Signal Frequency Response vs RF
Figure 6-6. Small-Signal Frequency Response vs RF
20.5
20.4
20.3
20.2
20.1
20
24.1
24
23.9
23.8
23.7
23.6
23.5
23.4
19.9
19.8
RF = 100 W
23.3
RF = 250 W
RF = 250 W
19.7
RF = 500 W
23.2
23.1
23
RF = 500 W
RF = 700 W
RF = 1000 W
RF = 909 W
RF = 1240 W
19.6
19.5
10M
100M
Frequency (Hz)
10M
100M
Frequency (Hz)
1G
D041
D042
AV = 10 V/V, VO = 2 VPP
AV = 15 V/V, VO = 2 VPP
Figure 6-7. Small-Signal Gain Flatness vs RF
Figure 6-8. Small-Signal Gain Flatness vs RF
0.8
3
AV = 10 V/V,
F = 1.24 kW
AV = 15 V/V,
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
R
0
-3
-6
RF = 1 kW
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
-9
CL = 22 pF, RS = 0 W
CL = 33 pF, RS = 0 W
CL = 47 pF, RS = 2 W
CL = 100 pF, RS = 5 W
CL = 100 pF, RS = 5 W
-12
-15
10M
100M
Frequency (Hz)
10M
100M
Frequency (Hz)
D006
D043
VO = 100 mVPP
VO = 16 VPP
Frequency response is measured at the device output pin
before the isolation resistor.
Figure 6-9. Large-Signal Gain Flatness
Figure 6-10. Small-Signal Frequency Response vs CLOAD
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
23
20
17
14
11
8
25
22
19
16
13
10
VO = 2 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
VO = 2 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
5
10M
100M
Frequency (Hz)
10M
100M
Frequency (Hz)
D007
D008
AV = 10 V/V
AV = 15 V/V
Figure 6-11. Large-Signal Frequency Response vs VO
Figure 6-12. Large-Signal Frequency Response vs VO
21
25
Full-bias
Mid-bias
Low-bias
Full-bias
Mid-bias
Low-bias
22
18
15
12
9
19
16
13
10
10M
100M
Frequency (Hz)
10M
100M
Frequency (Hz)
D003
D002
AV = 15 V/V, VO = 2 VPP
AV = 10 V/V, VO = 2 VPP
Figure 6-14. Small-Signal Frequency Response vs Bias Modes
Figure 6-13. Small-Signal Frequency Response vs Bias Modes
26
100
10
1
100
10
1
Full-bias
Mid-bias
Low-bias
en
in+
in-
23
20
17
14
11
8
5
10M
100M
Frequency (Hz)
1G
100
1k
10k 100k
Frequency (Hz)
1M
10M
D047
D018
AV = 15 V/V, VO = 16 VPP
.
Figure 6-15. Large-Signal Frequency Response vs Bias Modes
Figure 6-16. Input Voltage and Current Noise Density vs
Frequency
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-75
-77
-79
-81
-83
-85
-87
-89
-91
-93
-95
HD2, RL = 50W
HD3, RL = 50W
HD2, RL = 100W
HD3, RL = 100W
HD2
HD3
1M
10M
Frequency (Hz)
100M
5
10
Gain (V/V)
20
D009
D014
VO = 2 VPP
f = 1 MHz, VO = 2 VPP
Figure 6-17. Harmonic Distortion vs Frequency
Figure 6-18. Harmonic Distortion vs Gain
-30
-10
-20
-30
-40
-50
-60
-70
-80
HD2
HD3
HD2
HD3
-40
-50
-60
-70
-80
-90
-100
0.5
1
10
20
0.5
1
10
20
Output Voltage (VPP
)
Output Voltage (VPP)
D010
D011
f = 1 MHz, AV = 10 V/V
Figure 6-19. Harmonic Distortion vs VO
f = 10 MHz, AV = 10 V/V
Figure 6-20. Harmonic Distortion vs VO
-60
-65
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD2
HD3
HD2
HD3
-70
-75
-80
-85
-90
-95
-100
-105
10
100
Load Resistance, RL (W)
300
10
100
Load Resistance, RL (W)
300
D012
D013
f = 1 MHz, VO = 2 VPP, AV = 10 V/V
f = 10 MHz, VO = 2 VPP, AV = 10 V/V
Figure 6-21. Harmonic Distortion vs RL
Figure 6-22. Harmonic Distortion vs RL
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
15
12.5
10
VIN ì 10 gain
VO (AV = 10)
IMD2
IMD3
7.5
5
2.5
0
-2.5
-5
-7.5
-10
-12.5
-15
10k
100k
1M
Frequency (Hz)
10M
100M
Time, 15 ms per division
D015
D023
±12.2 kHz tone spacing, VO = 2 VPP per tone
VIN = 2.8-VPP triangular waveform
Figure 6-23. Intermodulation Distortion vs Frequency
Figure 6-24. Overdrive Recovery
1.25
9
7
D1OUT - D2OUT
D1OUT
D2OUT
D1OUT - D2OUT
D1OUT
D2OUT
1
0.75
5
0.5
0.25
0
3
1
-1
-3
-5
-7
-9
-0.25
-0.5
-0.75
-1
-1.25
Time, 25 ns per division
Time, 25 ns per division
D046
D019
VO step = 16 VPP
VO step = 2 VPP
Figure 6-26. Large-Signal Pulse Response
Figure 6-25. Small-Signal Pulse Response
130
120
110
100
90
15
130
120
110
100
90
15
ZOL
Phase
ZOL
Phase
0
0
-15
-15
-30
-30
-45
-45
80
-60
80
-60
70
-75
70
-75
60
-90
60
-90
50
-105
-120
-135
-150
-165
-180
50
-105
-120
-135
-150
-165
-180
40
40
30
30
20
20
10
10
0
0
100
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1G
100
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1G
D016
D036
Full-bias simulation
Mid-bias simulation
Figure 6-27. Open-Loop Transimpedance Gain and Phase vs
Frequency
Figure 6-28. Open-Loop Transimpedance Gain and Phase vs
Frequency
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
130
120
110
100
90
15
1M
100k
10k
1k
ZOL
Phase
Full-bias
Mid-bias
Low-bias
Shutdown
0
-15
-30
-45
80
-60
70
-75
60
-90
50
-105
-120
-135
-150
-165
-180
100
10
40
30
20
10
0
1
100k
100
1k
10k
100k 1M
Frequency (Hz)
10M
100M
1G
1M
10M
Frequency (Hz)
100M
D037
D017
Low-bias simulation
Simulation
Figure 6-29. Open-Loop Transimpedance Gain and Phase vs
Frequency
Figure 6-30. Open-Loop Output Impedance vs Frequency
25
20
15
20
Full-bias
Mid-bias
Low-bias
Power-down
18
16
14
10
ICC, TA = -40èC
5
12
10
8
ICC, TA = 25èC
ICC, TA = 85èC
IEE, TA = -40èC
IEE, TA = 25èC
IEE, TA = 85èC
0
-5
-10
-15
-20
-25
6
4
2
0
4
8
12
16
Single-Supply Voltage, VS (V)
20
24
28
32
0
0.5
1
1.5
2
2.5
RADJ (kW)
3
3.5
4
4.5
5
5.5
6
D021
D020
RL = no load, average of 30 devices
Average of 30 devices
Figure 6-32. Quiescent Current vs RADJ
Figure 6-31. Quiescent Current vs Single-Supply Voltage
22
20
18
16
14
12
10
160
150
140
130
120
110
100
90
PSRR+
PSRR-
CMRR
80
8
6
4
2
0
Full-bias
Mid-bias
Low-bias
Power-down
70
60
50
40
30
-40
-25
-10
5
20
35
50
65
80
1k
10k
100k 1M
Frequency (Hz)
10M
100M
Ambient Temperature, TA (èC)
D044
D026
RL = no load, average of 30 devices
TJ = 50°C, simulation
Figure 6-34. PSRR and CMRR vs Frequency
Figure 6-33. Quiescent Current vs Temperature
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6.8 Typical Characteristics: VS = 12 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 50 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
22
20
18
16
14
12
10
8
8
7
B1, TA = -40(èC)
B1, TA = 25(èC)
B1, TA = 85(èC)
B2, TA = -40(èC)
B2, TA = 25(èC)
B2, TA = 85(èC)
B1, B2
D1OUT - D2OUT
D1OUT
D2OUT
6
5
4
3
2
1
0
-1
-2
-3
-4
-5
-6
-7
0
1
2
3
4
5
6
7
Bias Pin Voltage (V)
8
9
10 11 12
Time, 25 ns per division
D024
D025
B1 = full-bias to mid-bias transition with B2 = DGND, B2 = full-
bias to low-bias transition with B1 = DGND, DGND = VS–
.
Figure 6-36. Full-Bias and Shutdown Mode Transition Timing
Figure 6-35. Mode Transition Voltage Threshold
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6.9 Typical Characteristics: VS = 32 V
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
3
23
20
17
14
11
8
0
-3
-6
-9
AV = 5 V/V, RF = 1.5 kW
AV = 10 V/V, RF = 1.24 kW
AV = 15 V/V, RF = 1 kW
AV = 20 V/V, RF = 850 W
RF = 500 W
RF = 909 W
RF = 1240 W
-12
-15
10M
5
10M
100M
Frequency (Hz)
1G
100M
Frequency (Hz)
1G
D100
D101
VO = 2 VPP
VO = 2 VPP
Figure 6-37. Small-Signal Frequency Response
Figure 6-38. Small-Signal Frequency Response vs RF
23
26
20
17
14
23
20
17
11
14
VO = 2 VPP
VO = 2 VPP
VO = 10 VPP
VO = 20 VPP
VO = 40 VPP
VO = 5 VPP
VO = 10 VPP
VO = 16 VPP
8
11
5
10M
8
10M
100M
Frequency (Hz)
1G
100M
Frequency (Hz)
1G
D103
D104
AV = 10 V/V
AV = 15 V/V
Figure 6-39. Large-Signal Frequency Response vs VO
Figure 6-40. Large-Signal Frequency Response vs VO
23
-30
Full-bias
Mid-bias
Low-bias
IMD2
IMD3
-35
-40
20
17
14
11
8
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
5
10M
100M
Frequency (Hz)
1G
10k
100k
1M
Frequency (Hz)
10M
100M
D121
D111
VO = 40 VPP
.
Figure 6-41. Large-Signal Frequency Response vs Bias Modes
Figure 6-42. Intermodulation Distortion vs Frequency
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6.9 Typical Characteristics: VS = 32 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-75
-77
-79
-81
-83
-85
-87
-89
-91
-93
-95
HD2, RL = 50W
HD3, RL = 50W
HD2, RL = 100W
HD3, RL = 100W
HD2
HD3
1M
10M
Frequency (Hz)
100M
5
10
Gain (V/V)
20
D105
D110
VO = 2 VPP
f = 1 MHz, VO = 2 VPP RL = 50 Ω
Figure 6-43. Harmonic Distortion vs Frequency
Figure 6-44. Harmonic Distortion vs Gain
-75
-55
-60
-65
-70
-75
-80
-85
HD2
HD3
HD2
HD3
-80
-85
-90
-95
-100
0.5
1
10
20
0.5
1
10
20
Output Voltage (VPP
)
Output Voltage (VPP)
D106
D107
f = 1 MHz, RL = 50 Ω
Figure 6-45. Harmonic Distortion vs VO
f = 10 MHz, RL = 50 Ω
Figure 6-46. Harmonic Distortion vs VO
-60
-65
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
HD2
HD3
HD2
HD3
-70
-75
-80
-85
-90
-95
-100
-105
10
100
Load Resistance, RL (W)
300
10
100
Load Resistance, RL (W)
300
D108
D109
f = 1 MHz, VO = 2 VPP
f = 10 MHz, VO = 2 VPP
Figure 6-47. Harmonic Distortion vs RL
Figure 6-48. Harmonic Distortion vs RL
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6.9 Typical Characteristics: VS = 32 V (continued)
At TA ≈ 25°C, AV = 10 V/V, RF = 1.24 kΩ, RL = 100 Ω, RS = 2.5 Ω, RADJ = 0 Ω, full-bias mode, and VCM = open (unless
otherwise noted).
1.25
1
25
20
15
10
5
D1OUT - D2OUT
D1OUT
D2OUT
D1OUT - D2OUT
D1OUT
D2OUT
0.75
0.5
0.25
0
0
-5
-0.25
-0.5
-0.75
-1
-10
-15
-20
-25
-1.25
Time, 25 ns per division
Time, 25 ns per division
D122
D114
VO step = 40 VPP
VO step = 2 VPP
Figure 6-50. Large-Signal Pulse Response
Figure 6-49. Small-Signal Pulse Response
16
24
Full-bias
Mid-bias
Low-bias
Power-down
14
12
10
8
6
4
2
0
-2
-4
22
20
18
16
14
12
10
8
Sourcing, TA
Sourcing, TA = 25
Sourcing, TA = 85
= -40èC
è
C
èC
Sinking, TA
Sinking, TA = 25
Sinking, TA = 85
= -40èC
è
C
èC
-6
-8
6
-10
-12
-14
-16
4
2
0
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
0
0.5
1
1.5
2
2.5
RADJ (kW)
3
3.5
4
4.5
5
5.5
6
D117
D115
Average of 30 devices
Average of 30 devices
Output voltage is slammed and IO is pulsed to maintain TJ as
close to TA as possible.
Figure 6-52. Quiescent Current vs RADJ
Figure 6-51. Single-Ended Output Voltage vs IO and
Temperature
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7 Detailed Description
7.1 Overview
The THS6222 is a differential line-driver amplifier with a current-feedback architecture. The device is targeted for
use in line-driver applications such as narrow-band and broadband power-line communications (PLC) that are
often found in smart metering and home networking applications.
The THS6222 is designed as a single-port differential line driver solution that can be a drop-in replacement for
the THS6212. The integrated common-mode buffer featured in the THS6222 reduces the number of external
components required for level shifting the input common-mode voltage in PLC applications that are often ac
coupled, resulting in space savings on the circuit board and reducing the overall system cost. The THS6222
uses an architecture that does not allow using the two current-feedback amplifiers, D1 and D2, independently;
therefore, these amplifiers must always be driven differentially.
The architecture of the THS6222 is designed to provide maximum flexibility with adjustable power modes that
are selectable based on application performance requirements, and also provides an external current
adjustment pin (IADJ) to further optimize the quiescent power of the device. The wide output swing (18.6 VPP
)
into 50-Ω differential loads with 12-V power supplies and high current drive of the THS6222 make the device
ideally suited for high-power, line-driving applications. By using 32-V power supplies and with good thermal
design that keep the device within the safe operating temperature, the THS6222 is capable of swinging 57 VPP
into 100-Ω loads.
7.2 Functional Block Diagram
THS6222
BIAS
2
BIAS
1
IADJ
VS+
D1
Bias Current Control
D1
IN+
+
D1
OUT
VS+
œ
5 kꢀ
CM
D1
INt
Buffer
520 ꢀ
5 kꢀ
Thermal
Protection
VCM
D2
INt
œ
D2
OUT
VSœ
D2
D2
IN+
+
D
GND
VSt
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7.3 Feature Description
7.3.1 Common-Mode Buffer
The THS6222 is a differential line driver that features an integrated common-mode buffer. Most common line
driving applications for the THS6222 are ac-coupled applications; see Figure 8-2. Therefore, the inputs must be
common-mode shifted to ensure the input signals are within the common-mode specifications of the device. To
maximize the dynamic range, the common-mode voltage is shifted to midsupply in most ac-coupled applications.
With the integrated common-mode buffer, no external components are required to shift the input common-mode
voltage. Often, engineers choose to connect a noise-decoupling capacitor to the VCM pin. However, as shown in
Figure 7-1, assuming the circuit is reasonably shielded from external noise sources, no difference in common-
mode noise is observed with the 100 nF capacitor or without the capacitor.
300
VS = 12 V, no VCM capacitor
VS = 12 V, 100-nF VCM capacitor
VS = 32 V, no VCM capacitor
VS = 32 V, 100-nF VCM capacitor
100
10
1k
10k
100k
Frequency (Hz)
1M
D052
Figure 7-1. Common-Mode Voltage Noise Density vs Frequency
There are ESD protection diodes in series directly at the output of the common-mode buffer between the internal
520 Ω resistor and the common-mode buffer output. These diodes are referenced to midsupply. Any voltage that
is 1.4 V above or below the midsupply applied to the VCM pin forward biases the protection diodes. This biasing
results in either current flowing into or out of the VCM pin. The current is limited by the 520 Ω resistor in series,
but to prevent permanent damage to the device, the current must be limited to the current specifications in the
Absolute Maximum Ratings table.
7.3.2 Thermal Protection and Package Power Dissipation
The THS6222 is designed with thermal protection that automatically puts the device in shutdown mode when the
junction temperature reaches approximately 175°C. In this mode, the device behavior is the same as if the bias
pins are used to power-down the device. The device resumes normal operation when the junction temperature
reaches approximately 145°C. In general, the thermal shutdown condition must be avoided. If and when the
thermal protection triggers, thermal cycling occurs where the device repeatedly goes in and out of thermal
shutdown until the junction temperature stabilizes to a value that prevents thermal shutdown.
A common technique to calculate the maximum power dissipation that a device can withstand is by using the
junction-to-ambient thermal resistance (R θJA), provided in the Thermal Information table. Using the equation
power dissipation = (junction temperature, TJ – ambient temperature, TA) / RθJA, the amount of power a package
can dissipate can be estimated. Figure 7-2 illustrates the package power dissipation based on this equation to
reach junction temperatures of 125°C and 150°C at various ambient temperatures. The RθJA value is determined
using industry standard JEDEC specifications and allows ease of comparing various packages. Power greater
than that in Figure 7-2 can be dissipated in a package by good printed circuit board (PCB) thermal design, using
heat sinks, and or active cooling techniques. See the Thermal Design By Insight, Not Hindsight application report
for an in-depth discussion on thermal design.
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4.5
4.25
4
TJ = 125èC
TJ = 150èC
3.75
3.5
3.25
3
2.75
2.5
2.25
2
1.75
1.5
1.25
1
0.75
0.5
-40 -30 -20 -10
0
10 20 30 40 50 60 70 80 90
Ambient Temperature (èC)
SBOS
Figure 7-2. Package Power Dissipation vs Ambient Temperature
7.3.3 Output Voltage and Current Drive
The THS6222 provides output voltage and current capabilities that are unsurpassed in a low-cost, monolithic op
amp. Under no load at room temperature, the output voltage typically swings closer than 1.1 V to either supply
rail and typically swings to within 1.1 V of either supply with a 100 Ω differential load. The THS6222 can deliver
over 350 mA of current with a 25 Ω load.
Good thermal design of the system is important, including use of heat sinks and active cooling methods, if the
THS6222 is pushed to the limits of its output drive capabilities. Figure 7-3 and Figure 7-4 show the output drive
of the THS6222 under two different sets of conditions where T A is approximately equal to T J. In practical
applications, T J is often much higher than T A and is highly dependent on the device configuration, signal
parameters, and PCB thermal design. In order to represent the full output drive capability of the THS6222 in
Figure 7-3 and Figure 7-4, TJ ≈ TA is achieved by pulsing or sweeping the output current for a duration of less
than 100 ms.
6
5
1
0.8
0.6
0.4
0.2
0
Full-bias
Mid-bias
Low-bias
4
3
2
Sourcing, TA = -40èC
Sourcing, TA = 25èC
Sourcing, TA = 85èC
Sinking, TA = -40èC
Sinking, TA = 25èC
Sinking, TA = 85èC
1
0
-1
-2
-3
-4
-5
-6
-0.2
-0.4
-0.6
-0.8
-1
-700 -500 -300 -100 100
300
Output Current (mA)
500
700
900
0
50 100 150 200 250 300 350 400 450 500 550 600
Output Current (mA)
D045
D022
VS = 12 V, TJ ≈ TA ≈ 25°C
V
S = 12 V, TJ ≈ TA
Figure 7-4. Linear Single-Ended Output Voltage vs
IO and Temperature
Figure 7-3. Slammed Single-Ended Output Voltage
vs IO and Temperature
In Figure 7-3, the output voltages are differentially slammed to the rail and the output current is single-endedly
sourced or sunk using a source measure unit (SMU) for less than 100 ms. The single-ended output voltage of
each output is then measured prior to removing the load current. After removing the load current, the outputs are
brought back to mid-supply before repeating the measurement for different load currents. This entire process is
repeated for each ambient temperature. Under the slammed output voltage condition of Figure 7-3, the output
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transistors are in saturation and the transistors start going into linear operation as the output swing is backed off
for a given IO,
In Figure 7-4, the inputs are floated and the output voltages are allowed to settle to the mid-supply voltage. The
load current is then single-endedly swept for sourcing (greater than 0 mA) and sinking (less than 0 mA)
conditions and the single-ended output voltage is measured at each current-forcing condition. The current sweep
is completed in a few seconds (approximately 3 to 4 seconds) so as not to significantly raise the junction
temperature (TJ) of the device from the ambient temperature (TA). The output is not swinging and the output
transistors are in linear operation in Figure 7-4 until the current drawn exceeds the device capabilities, at which
point the output voltage starts to deviate quickly from the no load output voltage.
To maintain maximum output stage linearity, output short-circuit protection is not provided. This absence of short-
circuit protection is normally not a problem because most applications include a series-matching resistor at the
output that limits the internal power dissipation if the output side of this resistor is shorted to ground. However,
shorting the output pin directly to the adjacent positive power-supply pin, in most cases, permanently damages
the amplifier.
7.3.4 Breakdown Supply Voltage
To estimate the margin beyond the maximum supply voltage specified in the Absolute Maximum Ratings table
and exercise the robustness of the device, several typical units were tested beyond the specifications in the
Absolute Maximum Ratings table. Figure 7-5 shows the configuration used for the test. The supply voltage, VS,
was swept manually and quiescent current was recorded at each 0.5-V supply voltage increment. Figure 7-6
shows the results of the single-supply voltage where the typical units started breaking. Under a similar
configuration as the one shown in Figure 7-5, a unit was subjected to VS = 42 V for 168 hours and tested for
quiescent current at the beginning and at the end of the test. There was no notable difference in the quiescent
current before and after the 168 hours of testing and the device did not show any signs of damage or
abnormality.
The primary objective of these tests was to estimate the margins of robustness for typical devices and does not
imply performance or maximum limits beyond those specified in the Abolute Maximum Ratings and
Recommended Operating Conditions tables.
VS
THS6222
BIAS
2
BIAS
1
IADJ
VS+
Bias Current Control
D1
IN+
+
D1
VS+
OUT
œ
RF1
1.25 kꢀ
5 kꢀ
CM
Buffer
D1
INt
520 ꢀ
5 kꢀ
Thermal
Protection
RG
274 ꢀ
Open
VCM
Open
D2
INt
RF2
1.25 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
D
GND
VSt
Figure 7-5. Breakdown Supply Voltage Test Configuration
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45
Unit 1
Unit 2
Unit 3
Unit 4
Unit 5
40
35
30
25
20
15
10
5
0
D038
Single-Supply Voltage (V)
Figure 7-6. Typical Device Breakdown Supply Voltage (TA = 27°C)
7.3.5 Surge Test Results
Line drivers such as the THS6222 often directly interface with power lines through a transformer and various
protection components in high-speed power line communications (HPLC) smart-meters and digital subscriber
line (DSL) applications. Surge testing is an important requirement for such applications. To validate the
performance and surge survivability of the THS6222, the THS6222 circuit configuration shown in Figure 7-7 was
subjected to a ±4 kV common-mode surge and a ±2 kV differential-mode surge. The common-mode and
differential-mode surge voltages were applied at VCM and VDIFF, respectively, in Figure 7-7. The 1.2/50 µs surge
profile was used per the IEC 61000-4-5 test with REQ = 42 Ω as explained in the TI's IEC 61000-4-x Tests and
Procedures application report. Five devices were tested in full-bias and shutdown modes, and were subjected to
the surge five times for each polarity. No device showed any discernable change in quiescent current after being
subjected to the surge test, and the out-of-band suppression tests did not show any performance deterioration
either, as shown in Figure 7-8 through Figure 7-11 for the state grid corporation of China (SGCC) HPLC bands.
Full-bias /
Shutdown
+12 V
THS6222
BIAS
2
BIAS
1
IADJ
VS+
+12 V
AV
=
Bias Current Control
100 nF
RS1
10 V/V
D1
IN+
100 nF
2.49 ꢀ
+
D1
VS+
OUT
œ
RF1
1:1
RT1
5 kꢀ
CM
Buffer
1.24 kꢀ
VCM
49.9 ꢀ
D1
INt
520 ꢀ
5 kꢀ
Thermal
Protection
RG
VCM
TVS
Varistor
VDIFF
274 ꢀ
+12 V
D2
INt
VCM
RT2
RF2
49.9 ꢀ
1.24 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
RS2
2.49 ꢀ
100 nF
100 nF
D
GND
VSt
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Full-bias /
Shutdown
+12 V
SC00059
BIAS
2
BIAS
1
IADJ
VS+
+12 V
AV
=
Bias Current Control
100 nF
RS1
10 V/V
D1
IN+
100 nF
2.49 ꢀ
+
D1
OUT
VS+
œ
RF1
1:1
RT1
5 kꢀ
CM
Buffer
1.24 kꢀ
VCM
49.9 ꢀ
D1
INt
520 ꢀ
5 kꢀ
Thermal
Protection
RG
VCM
TVS
Varistor
VDIFF
274 ꢀ
+12 V
D2
INt
VCM
RT2
RF2
49.9 ꢀ
1.24 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
RS2
2.49 ꢀ
100 nF
100 nF
D
GND
VSt
Figure 7-7. Surge Test Configuration
-45
-50
-40
Pre-surge
Post-surge
Pre-surge
Post-surge
-45
-50
-55
-55
-60
-60
-65
-65
-70
-70
-75
-80
-85
-90
-75
-80
-85
-95
-90
-100
-105
-110
-115
-120
-95
-100
-105
-110
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
D048
D049
Figure 7-8. China SGCC HPLC Band0 Pre-Surge
and Post-Surge
Figure 7-9. China SGCC HPLC Band1 Pre-Surge
and Post-Surge
-40
-40
Pre-surge
Post-surge
Pre-surge
Post-surge
-45
-50
-45
-50
-55
-60
-55
-60
-65
-70
-65
-70
-75
-80
-75
-80
-85
-90
-85
-90
-95
-95
-100
-105
-110
-115
-120
-100
-105
-110
-115
-120
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
D050
D051
Figure 7-10. China SGCC HPLC Band2 Pre-Surge
and Post-Surge
Figure 7-11. China SGCC HPLC Band3 Pre-Surge
and Post-Surge
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7.4 Device Functional Modes
The THS6222 has four different functional modes set by the BIAS-1 and BIAS-2 pins. Table 7-1 shows the truth
table for the device mode pin configuration and the associated description of each mode.
Table 7-1. BIAS-1 and BIAS-2 Logic Table
BIAS-1
BIAS-2
FUNCTION
DESCRIPTION
0
1
0
0
Full-bias mode (100%)
Mid-bias mode (75%)
Amplifiers on with lowest distortion possible
Amplifiers on with power savings and a reduction in distortion performance
Amplifiers on with enhanced power savings and a reduction of overall
performance
0
1
1
1
Low-bias mode (50%)
Shutdown mode
Amplifiers off and output is high impedance
If the PLC application requires switching the line driver between all four power modes and if the PLC application-
specific integrated circuit (ASIC) has two control bits, then the two control bits can be connected to the bias pins
BIAS-1 and BIAS-2 for switching between any of the four power modes. However, most PLC applications only
require the line driver to switch between one of the three active power modes and the shutdown mode. This type
of 1-bit power mode control is illustrated in Figure 8-1, where the line driver can be switched between the full-
bias and shutdown modes using just one control bit from the PLC ASIC. If switching between the mid-bias or
low-bias modes and the shutdown mode is required for the application, then either the BIAS-1 or BIAS-2 pin can
be connected to ground and the control pin from the PLC ASIC can be connected to the non-grounded BIAS pin.
8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The THS6222 is typically used for high output power line-driving applications with various load conditions, as is
often the case in power line communications (PLC) applications. In the Typical Applications section, the amplifier
is presented in a typical, broadband, current-feedback configuration driving a 50 Ω line load. However, the
amplifier is also applicable for many different general-purpose and specific line-driving applications beyond what
is shown in the Typical Applications section.
8.2 Typical Applications
8.2.1 Broadband PLC Line Driving
The THS6222 provides the exceptional ac performance of a wideband current-feedback op amp with a highly
linear, high-power output stage. The low output headroom requirement and high output current drive capability
makes the THS6222 an excellent choice for 12 V PLC applications. The primary advantage of a current-
feedback op amp such as the THS6222 over a voltage-feedback op amp is that the ac performance (bandwidth
and distortion) is relatively independent of signal gain. Figure 8-1 shows a typical ac-coupled broadband PLC
application circuit where a current-output digital-to-analog converter (DAC) of the PLC application-specific
integrated circuit (ASIC) drives the inputs of the THS6222. Though Figure 8-1 shows the THS6222 interfacing
with a current-output DAC, the THS6222 can just as easily be interfaced with a voltage-output DAC by using
much larger terminating resistors, RT1 and RT2.
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1-bit power mode control
Full-bias / shutdown
+12 V
THS6222
BIAS
2
BIAS
1
IADJ
VS+
+12 V
PLC ASIC
AV =
10 V/V
Bias Current Control
100 nF
RS1
2.49 ꢀ
D1
IN+
100 nF
+
D1
OUT
VS+
œ
RF1
1.24 kꢀ
1:1
RT1
249 ꢀ
5 kꢀ
CM
Buffer
D1
INt
520 ꢀ
5 kꢀ
Optional
Thermal
Protection
RG
274 ꢀ
50 ꢀ
Power Line
RL
50 ꢀ
VCM
DAC f
100 nF
+12 V
D2
INt
RT2
249 ꢀ
RF2
1.24 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
RS2
2.49 ꢀ
100 nF
100 nF
D
GND
VSt
Figure 8-1. Typical Broadband PLC Configuration
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8.2.1.1 Design Requirements
The main design requirements for an ac-coupled wideband current-feedback operation are to choose power
supplies that satisfy the output voltage requirement, and also to use a feedback resistor value that allows for the
proper bandwidth while maintaining stability. Use the design requirements shown in Table 8-1 to design a
broadband PLC application circuit.
Table 8-1. Design Requirements
DESIGN PARAMETER
Power supply
VALUE
12 V, single-supply
Differential gain, AV
10 V/V
Spectrum profile
China SGCC HPLC band0, band1, band2, and band3
In-band power spectral density
Minimum out-of-band suppression
–50 dBm/Hz
35 dB
8.2.1.2 Detailed Design Procedure
The closed-loop gain equation for a differential line driver such as the THS6222 is given as AV = 1 + 2 × (RF /
RG), where RF = RF1 = RF2. The THS6222 is a current-feedback amplifier and thus the bandwidth of the closed-
loop configuration is set by the value of the RF resistor. This advantage of the current-feedback architecture
allows for flexibility in setting the differential gain by choosing the value of the RG resistor without reducing the
bandwidth as is the case with voltage-feedback amplifiers. The THS6222 is designed to provide optimal
bandwidth performance with RF1 = RF2 = 1.24 kΩ. To configure the device in a gain of 10 V/V, the RG resistor is
chosen to be 274 Ω. See the TI Precision Labs for more details on how to choose the RF resistor to optimize the
performance of a current-feedback amplifier.
Often, a key requirement for PLC applications is the out-of-band suppression specifications. The in-band
frequencies carry the encoded data with a certain power level. The line driver must not generate any spurs
beyond a certain power level outside the in-band spectrum. In the design requirements of this application
example, the minimum out-of-band suppression specification of 35 dB means there must be no frequency spurs
in the out-of-band spectrum beyond the –80 dBm/Hz power spectral density, considering the in-band power
spectral density is –50 dBm/Hz.
The circuit shown in Figure 8-2 measures the out-of-band suppression specification. The minor difference in
components between the circuits of Figure 8-1 and Figure 8-2 does not have any significant impact on the out-
of-band suppression results.
+6 V
THS6222
BIAS
2
BIAS
1
IADJ
VS+
AV =
10 V/V
Bias Current Control
100 nF
RS1
2.49 ꢀ
D1
IN+
+
D1
VS+
OUT
œ
RF1
1.24 kꢀ
5 kꢀ
1:1
CM
Buffer
Atten-
uation
100 nF
100 nF
D1
INt
Power
Spectrum
Analyzer
Arbitrary
Waveform
Generator
520 ꢀ
5 kꢀ
Thermal
Protection
RG
274 ꢀ
VCM
Open
D2
INt
RF2
1.24 kꢀ
œ
D2
OUT
VSœ
D2
IN+
+
RS2
2.49 ꢀ
100 nF
D
GND
VSt
œ6 V
Figure 8-2. Measurement Test Circuit for Out-of-Band Suppression
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8.2.1.3 Application Curve
Figure 8-3 shows the out-of-band suppression measurement results of the circuit. Out-of-band suppression is a
good indicator of the linearity performance of the device. The results in Figure 8-3 show over 40 dB of out-of-
band suppression, which is well beyond the 35 dB requirement and indicative of the excellent linearity
performance of the THS6222.
-40
Band0
Band1
Band2
Band3
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
-105
-110
-115
-120
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Frequency (MHz)
D030
Figure 8-3. Out-of-Band Suppression
8.3 What to Do and What Not to Do
8.3.1 Do
•
•
•
•
•
Include a thermal design at the beginning of the project.
Use well-terminated transmission lines for all signals.
Use solid metal layers for the power supplies.
Keep signal lines as straight as possible.
Keep the traces carrying differential signals of the same length.
8.3.2 Do Not
•
•
•
Do not use a lower supply voltage than necessary.
Do not use thin metal traces to supply power.
Do not treat the D1 and D2 amplifiers as independent single-ended amplifiers.
9 Power Supply Recommendations
The THS6222 supports single-supply and split-supply power supplies, and balanced and unbalanced bipolar
supplies. The device has a wide supply range of 8 V (–3 V to +5 V) to 32 V (±16 V). Choose power-supply
voltages that allow for adequate swing on both the inputs and outputs of the amplifier to prevent affecting device
performance. Operating from a single supply can have numerous advantages. With the negative supply at
ground, the errors resulting from the –PSRR term can be minimized. The DGND pin provides the ground
reference for the bias control pins. For applications that use split bipolar supplies, care must be taken to design
within the DGND voltage specifications and must be within VS– to (VS+ – 5 V); the DGND pin must be a minimum
bias of 5 V. Thus, the minimum positive supply that can be used in split-supply applications is VS+ = 5 V. The
negative supply, V S–, can then be set to a voltage anywhere in between –3 V and –27 V, as per the
Recommended Operating Conditions specifications.
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS6222 requires careful attention
to board layout parasitic and external component types. The THS6222RHFEVM can be used as a reference
when designing the circuit board. Recommendations that optimize performance include:
1. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Parasitic capacitance, particularly on
the output and inverting input pins, can cause instability; on the noninverting input, this capacitance can react
with the source impedance to cause unintentional band limiting. To reduce unwanted capacitance, a window
around the signal I/O pins must be opened in all ground and power planes around these pins. Otherwise,
ground and power planes must be unbroken elsewhere on the board.
2. Minimize the distance (less than 0.25 in, or 6.35 mm) from the power-supply pins to high-frequency 0.1 µF
decoupling capacitors. At the device pins, the ground and power plane layout must not be in close proximity
to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and
the decoupling capacitors. The power-supply connections must always be decoupled with these capacitors.
An optional supply decoupling capacitor across the two power supplies (for bipolar operation) improves
second-harmonic distortion performance. Larger (2.2 µF to 6.8 µF) decoupling capacitors, effective at lower
frequencies, must also be used on the main supply pins. These capacitors can be placed somewhat farther
from the device and can be shared among several devices in the same area of the PCB.
3. Careful selection and placement of external components preserves the high-frequency performance of the
THS6222. Resistors must be of a very low reactance type. Surface-mount resistors work best and allow a
tighter overall layout. Metal film and carbon composition, axially-leaded resistors can also provide good high-
frequency performance.
Again, keep leads and PCB trace length as short as possible. Never use wire-wound type resistors in a high-
frequency application. Although the output pin and inverting input pin are the most sensitive to parasitic
capacitance, always position the feedback and series output resistor, if any, as close as possible to the output
pin. Other network components, such as noninverting input termination resistors, must also be placed close
to the package. Where double-side component mounting is required, place the feedback resistor directly
under the package on the other side of the board between the output and inverting input pins. The frequency
response is primarily determined by the feedback resistor value, as described in the Boradband PLC Line
Driving section. Increasing the value reduces the bandwidth, whereas decreasing the value leads to a more
peaked frequency response. The 1.24 kΩ feedback resistor used in the Typical Characteristics: Vs = 12 V is a
good starting point for a gain of 10 V/V design.
4. Connections to other wideband devices on the board can be made with short direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Relatively wide traces (50-mils to 100-mils, 0.050-in to 0.100-In, or 1.27-mm to 2.54-
mm) must be used, preferably with ground and power planes opened up around them.
5. Socketing a high-speed part such as the THS6222 is not recommended. The additional lead length and pin-
to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network, and can
make achieving a smooth, stable frequency response almost impossible. Best results are obtained by
soldering the THS6222 directly onto the board.
6. Use the VS– plane to conduct the heat out of the package. The package attaches the die directly to an
exposed thermal pad on the bottom, and must be soldered to the board. This pad must be connected
electrically to the same voltage plane as the most negative supply voltage (VS–) applied to the THS6222.
Place as many vias as possible on the thermal pad connection and connect the vias to a heat spreading
plane that is at the same potential as VS– on the bottom side of the PCB.
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10.2 Wafer and Die Information
Table 10-1 lists wafer and bond pad information for the YS package.
Table 10-1. Wafer and Bond Pad Information
WAFER BACKSIDE
FINISH
WAFER
THICKNESS
BOND PAD
METALLIZATION
BACKSIDE POTENTIAL
BOND PAD DIMENSIONS (X × Y)
Silicon without
backgrind
Must be connected to the lowest voltage potential on
25 mils
Al
76.0 µm × 76.0 µm
the die (generally VS–
)
19
18
17
16
15
14
THS6222
13
12
11
1
PAD #1
10
9
2
3
4
5
8
7
6
0
38
0
38
1261.0
All dimensions are in micrometers (µm).
Figure 10-1. Die Dimensions
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Table 10-2 lists the bond pad locations for the YS package. All dimensions are in micrometers (µm).
Table 10-2. Bond Pad Locations
PAD
NUMBER
PAD NAME
X MIN
Y MIN
X MAX
Y MAX
DESCRIPTION
1
2
3
4
5
6
7
D1_IN+
D2_IN+
DGND
IADJ
71.050
71.050
878.875
525.125
384.025
267.025
150.025
85.925
147.050
147.050
147.050
147.050
147.050
285.175
1083.475
954.875
601.125
460.025
343.025
226.025
161.925
171.500
Amplifier D1 noninverting input
Amplifier D2 noninverting input
71.050
Ground reference for bias control pins
Bias current adjustment pin
71.050
VCM
71.050
Common-mode buffer output
VS–
209.175
1007.475
Negative power-supply connection
Positive power-supply connection
VS+
95.500
Amplifier D2 output (must be used for D2
output)
8
9
D2_OUT
1007.475
1007.475
222.500
369.900
1083.475
1083.475
298.500
445.900
Optional amplifier D2 output (can be left
unconnected or connected to pad 8)
D2_OUT (OPT)
10
11
D2_IN–
D1_IN–
1007.475
1007.450
487.375
919.375
1083.475
1083.450
563.375
995.375
Amplifier D2 inverting input
Amplifier D1 inverting input
Optional amplifier D1 output (pad can be
left unconnected or connected to pad 13)
12
13
D1_OUT (OPT)
D1_OUT
1007.475
1007.475
1034.100
1181.500
1083.475
1083.475
1110.100
1257.500
Amplifier D1 output (must be used for D1
output)
14
15
16
17
18
19
VS+
VS+
851.675
718.900
557.375
424.600
293.075
159.250
1417.950
1417.950
1417.950
1417.950
1417.750
1417.750
927.675
794.900
633.375
500.600
369.075
235.250
1493.950
1493.950
1493.950
1493.950
1493.750
1493.750
Positive power-supply connection
Positive power-supply connection
Negative power-supply connection
Negative power-supply connection
Bias mode parallel control, LSB
Bias mode parallel control, MSB
VS–
VS–
BIAS-1
BIAS-2
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10.3 Layout Examples
VS+
Bias Control
CBYP
THS6222
BIAS
2
BIAS
1
IADJ
VS+
D1
IN+
D1IN+
RS1
+
D1
OUT
D1OUT
VS+
œ
RF1
5 kꢀ
CM
Buffer
D1
INt
520 ꢀ
5 kꢀ
Thermal
Protection
RG
VCM
Open
D2
INt
RF2
œ
D2
OUT
VSœ
D2OUT
D2
IN+
D2IN+
+
RS2
D
GND
VSt
CBYP
Figure 10-2. Representative Schematic for the Layout in Figure 10-3
Place bypass capacitor
close to power pins
Place the feedback resistors, RF1
and RF2, and the isolation resistors,
RS1 and RS2, as close to the device
pins as possible to minimize parasitics
RS1
D1OUT
Bias
Control
CBYP
CBYP
Considering high power capabilities,
use wide supply traces to the bypass
capacitors to minimize inductance
RF1
RG
D1IN+
D2IN+
1
2
3
4
5
6
7
19
Thermal Pad
Ground and power plane exist on
inner layers.
18
17
16
15
14
13
RF2
RS2
Ground and power plane removed
from inner layers. Ground fill on
outer layers also removed.
D2OUT
Open VCM
Place as many vias as possible under
the thermal pad and connect them to a
heat spreading plane that is at the
same potential as VSœ
Connect the thermal pad to a heat
spreading plane; the plane must be at
the same potential as VSœ
Figure 10-3. Layout Recommendations
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SBOS974C – AUGUST 2019 – REVISED NOVEMBER 2020
11 Device and Documentation Support
11.1 Development Support
TI Precision Labs
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
•
•
•
•
•
Texas Instruments, THS6212 Differential Broadband PLC Line Driver Amplifier data sheet
Texas Instruments, THS6214 Dual-Port, Differential, VDSL2 Line Driver Amplifiers data sheet
Texas Instruments, Thermal Design By Insight, Not Hindsight application report
Texas Instruments, TI's IEC 61000-4-x Tests and Procedures application report
Texas Instruments, THS6222 Evaluation Module user guide
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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22-Nov-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
RGT
RHF
Qty
3000
3000
250
1
(1)
(2)
(3)
(4/5)
(6)
THS6222IRGTR
THS6222IRHFR
THS6222IRHFT
THS6222YS
ACTIVE
VQFN
VQFN
VQFN
16
24
24
0
Green (RoHS
& no Sb/Br)
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
TH6222
ACTIVE
ACTIVE
Green (RoHS
& no Sb/Br)
NIPDAU
NIPDAU
Call TI
THS
6222
RHF
Green (RoHS
& no Sb/Br)
THS
6222
ACTIVE WAFERSALE
YS
TBD
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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22-Nov-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS6222IRGTR
THS6222IRHFR
THS6222IRHFT
VQFN
VQFN
VQFN
RGT
RHF
RHF
16
24
24
3000
3000
250
330.0
330.0
180.0
12.4
12.4
12.4
3.3
4.3
4.3
3.3
5.3
5.3
1.1
1.3
1.3
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Nov-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS6222IRGTR
THS6222IRHFR
THS6222IRHFT
VQFN
VQFN
VQFN
RGT
RHF
RHF
16
24
24
3000
3000
250
367.0
367.0
210.0
367.0
367.0
185.0
35.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
RGT0016C
VQFN - 1 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
C
1 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(0.2) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
1.5
1
12
0.30
16X
0.18
13
16
0.1
C A B
PIN 1 ID
(OPTIONAL)
SYMM
0.05
0.5
0.3
16X
4222419/B 11/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
(0.58) TYP
8
(R0.05)
ALL PAD CORNERS
(2.8)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222419/B 11/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
RGT0016C
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4222419/B 11/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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