THS6226AIRHBR [TI]
门控 H 类双端口 VDSL2 和 PLC 线路驱动器 | RHB | 32 | -40 to 85;
| 型号： | THS6226AIRHBR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 门控 H 类双端口 VDSL2 和 PLC 线路驱动器 | RHB | 32 | -40 to 85 驱动 商用集成电路 驱动器 |
| 文件： | 总33页 (文件大小：2520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
THS6226A 门控 H 类，双端口 VDSL2 线路驱动器
1 特性
3 说明
1
•
数字式可调节静态电流：
9.4mA 至 24.8mA
THS6226A 是一款双端口，H 类，电流反馈架构，差
分线路驱动器放大器系统，此系统非常适合于 xDSL
系统。 该器件旨在应用于超高位速率数字用户线路 2
(VDSL2) 线路驱动器系统，此类系统可启用本地 DTM
信号，同时用良好线性支持高于 20.5dBm 的线路功
率（在高达 8.5MHz 的频率条件下），从而支持
G.993.2 VDSL2 8b 传输模式。 另外，此器件还拥有
足以支持 14.5dBm 线路功率（在高达 30MHz 的频率
下）的中心局传输的高速度。
•
•
•
•
•
偏置电流步长：1.0mA
独立的升压和主线路驱动器禁用
低功率线路端接模式
完全电容器再充电：200µs
低输出电压噪声密度：
6.5nV/√Hz 输入引入电压噪声
•
低多音频功率比 (MTPR) 失真：
70dB 加上 +19.8dBm G.993.2 — 传输模式 8b
此器件的独特架构可实现极小的静态电流，同时仍然实
现超高线性度。 在全偏置条件和 1MHz 频率下，差分
失真为 -91dBc，并在 5MHz 频率下减少为仅有 -
75dBc。 对于并不需要放大器全部性能的线路长度，
放大器的多种固定偏置设定值可提升节能效果。 为了
在所有的系统配置中实现更大的灵活性及节能幅度，以
0.1mA 的偏置电流步长对静态电流进行数字化调节，
调节范围从 7.67mA 至 23mA。 对于那些希望在不传
输时节省更多电能的系统，此器件可在其线路端接模式
中使用，以保持阻抗匹配。
•
•
-83dBc HD3（1MHz，60Ω 差分）
高输出电流：（可向 60Ω 负载输送 383mA 的电
流）
•
宽输出摆幅：40VPP（+12V，100Ω 差分负载和一
个 1:1.4 变压器）
•
•
•
高带宽：97MHz
端口至端口隔离度：1MHz 时大于 90dB
电源抑制比 (PSRR)：在 1MHz 频率下提供了
70dB 的良好隔离
2 应用范围
12V 电源上的宽输出摆幅与出色的电流驱动能力相结
合，可实现宽动态余量，从而将失真保持在尽可能低的
水平。 此器件采用超薄四方扁平无引线 (VQFN)-32
PowerPAD™ 封装。
•
•
非常适合于所有的 VDSL2 传输模式
与 ADSL，ADSL2+ 和 ADSL2++ 系统向后兼容
器件信息(1)
产品型号
THS6226A
封装
VQFN (32)
封装尺寸（标称值）
5.00mm x 5.00mm
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
利用 THS6226A 的一个端口的典型 VDSL2 线路驱动
器电路
1mF
功耗与 Tx 间的关系
850
VLL_CD
+12V
CAPL_CD
FBC
750
650
550
450
350
IND
VIN+
OUTD
1:n
+12V
THS6226A
100kW
RL
RL
33nF
0.2 ×
n2
OUTC
250
150
Single Channel
Dual channel
VIN-
DATA
CLK
INC
FBD
±6
±3
0
3
6
9
12
15
18
21
VHH_CD
CAPH_CD
1mF
Tx Power (dBm)
C009
1
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
English Data Sheet: SBOS643
THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 15
7.5 Programming........................................................... 16
Applications and Implementation ...................... 19
8.1 Application Information............................................ 19
8.2 Typical Application .................................................. 19
8.3 Initialization Set Up ................................................ 21
Power Supply Recommendations...................... 21
1
2
3
4
5
6
特性.......................................................................... 1
应用范围................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 5
6.1 Absolute Maximum Ratings ..................................... 5
6.2 Handling Ratings....................................................... 5
6.3 Recommended Operating Conditions....................... 6
6.4 Thermal Information.................................................. 6
6.5 Electrical Characteristics: VS = +12 V....................... 6
6.6 Timing Characteristics............................................... 8
6.7 Typical Characteristics.............................................. 9
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
8
9
10 Layout................................................................... 22
10.1 Layout Guidelines ................................................. 22
10.2 Layout Example .................................................... 23
11 器件和文档支持 ..................................................... 24
11.1 文档支持................................................................ 24
11.2 Trademarks........................................................... 24
11.3 Electrostatic Discharge Caution............................ 24
11.4 Glossary................................................................ 24
12 机械封装和可订购信息 .......................................... 24
7
4 修订历史记录
Changes from Original (April 2014) to Revision A
Page
•
Changed HBM parameter in Handling Ratings table ............................................................................................................. 5
2
Copyright © 2014, Texas Instruments Incorporated
THS6226A
www.ti.com.cn
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
5 Pin Configuration and Functions
RHB Package(1)(2)
VQFN-32
(Top View)
32 31 30 29 28 27 26 25
GND
1
2
3
4
5
6
7
8
24 OUTD
FB_D
FB_C
IND
INC
23
22
DATA
CLK
INB
21 OUTC
20
19
18
OUTB
FB_B
FB_A
INA
RESET(3)
17 OUTA
9
10 11 12 13 14 15 16
(1) The PowerPAD is electrically isolated from all other pins and can be connected to any potential voltage range from VS– to VS+. Typically,
the PowerPAD is connected to the GND plane because this plane tends to physically be the largest and is able to dissipate the most amount
of heat.
(2) The device defaults to the disabled mode at power-up.
(3) Default is GND (internal pull-down resistor).
Copyright © 2014, Texas Instruments Incorporated
3
THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
Pin Functions
PIN
I/O
DESCRIPTION
NO.
NAME
GND
1, 12, 29
2
—
I
Analog ground
IND
Input D of amplifier CD
3
INC
I
Input C of amplifier CD
4
DATA
I
Serial interface data pin
5
CLK
I
Serial interface CLK pin
6
INB
I
Input B of amplifier AB
7
INA
I
Input A of amplifier AB
8
RESET
VH_ENAB
VLL_AB
CAPL_AB
VSAB
I
Reset the internal register to 00h (startup conditions, state machine may require resetting)
Class H mode control pin for amplifier AB
Amplifier AB low pump supply
9
I
10
11
13, 14
15
16
17
18
19
20
21
22
23
24
25
26
27, 28
30
31
32
—
—
—
—
—
O
I
Amplifier AB negative voltage pump capacitor pin
Amplifier AB supply voltage
CAPH_AB
VHH_AB
OUTA
Amplifier AB positive voltage pump capacitor pin
Amplifier AB high pump supply
Output A of amplifier AB
FB_A
Feedback for active output impedance of amplifier AB
Feedback for active output impedance of amplifier AB
Output B of amplifier AB
FB_B
I
OUTB
O
O
I
OUTC
FB_C
Output C of amplifier CD
Feedback for active output impedance of amplifier CD
Feedback for active output impedance of amplifier CD
Output D of amplifier CD
FB_D
I
OUTD
VHH_CD
CAPH_CD
VSCD
O
—
—
—
—
—
I
Amplifier CD high pump supply
Amplifier CD positive voltage pump capacitor pin
Amplifier CD supply voltage
CAPL_CD
VLL_CD
VH_ENCD
Amplifier CD negative voltage pump capacitor pin
Amplifier CD low pump supply
Class H mode control pin for amplifier CD
The PowerPAD must be connected to any internal PCB ground plane using multiple vias for good thermal
performance.
PowerPAD
—
4
Copyright © 2014, Texas Instruments Incorporated
THS6226A
www.ti.com.cn
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
6 Specifications
6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
16.5
12.8
15
UNIT
V
Class AB only
Supply voltage, GND to VS+
Class H only
V
Input voltage, VI
V
Output current, IO
Static dc(2)
±100
mA
Continuous power dissipation
See Thermal Information table
(3)
Maximum junction, any condition, TJ
150
°C
Temperature
Maximum junction, continuous operation, long-term reliability,
TJ
130
°C
(4)
(1) Stresses above those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute maximum rated conditions for extended periods may degrade device reliability.
(2) The device incorporates a PowerPAD on the underside of the chip, which functions as a heatsink and must be connected to a thermally
dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature, which could
permanently damage the device. See the technical brief PowerPAD™ Thermally Enhanced Package (SLMA002) for more information
about using the PowerPAD thermally-enhanced package. Under high-frequency ac operation (> 10 kHz), the short-term output current
capability is much greater than the continuous dc output current rating. This short-term output current rating is roughly 8.5 times the dc
capability, or approximately ±850 mA.
(3) The absolute maximum junction temperature under any condition is limited by the constraints of the silicon process.
(4) The absolute maximum junction temperature for continuous operation is limited by the package constraints. Operation above this
temperature may result in reduced reliability or lifetime of the device.
6.2 Handling Ratings
MIN
MAX
UNIT
Tstg
Storage temperature range
–65
150
°C
Supply and ground pins with respect to
PowerPad: GND (pins 1, 12, 29), VSAB (pins
13, 14), VSCD (pins 27, 28)
–1.5
1.5
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
kV
V
Electrostatic
discharge
V(ESD)
All other pins
–2
2
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins
–500
500
Copyright © 2014, Texas Instruments Incorporated
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THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
10
NOM
MAX
12.6
15
UNIT
V
Class H
Power-supply voltage range
Class AB
10
V
Operating junction temperature
6.4 Thermal Information
THERMAL METRIC(1)
–40
130
°C
THS6226A
RHB (VQFN)
32 PINS
35.1
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
RθJC(top)
RθJB
22.1
7.0
°C/W
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.3
ψJB
6.9
RθJC(bot)
1.3
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics: VS = +12 V
At TA = 25°C, RMATCH = 10.2 Ω, transformer turn ratio 1:1.4, RL = 100-Ω differential at transformer output, full bias mode, and
active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
TEST
PARAMETER
AC PERFORMANCE
CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
VO = 2 VPP, differential at
OUTCD and OUTAB, gain = 19 V/V
Small-signal bandwidth, –3 dB
97
MHz
C
0.1-dB bandwidth flatness
Large-signal bandwidth
Slew rate (10% to 90% level)
Rise-and-fall time
VO = 2 VPP
30
80
MHz
MHz
V/μs
ns
C
C
C
C
VO = 7.5 VPP
SR
VO = 15-V step, differential
VO = 2 VPP
1750
3.6
Full bias, f = 1 MHz, VO = 2 VPP
RL = 60-Ω differential
,
,
,
,
–87
–73
–83
dBc
dBc
dBc
C
C
C
HD2
Second-harmonic distortion
Full bias, f = 5 MHz, VO = 2 VPP
RL = 60-Ω differential
Full bias, f = 1 MHz, VO = 2 VPP
RL = 60-Ω differential
HD3
Third-harmonic distortion
Full bias, f = 5 MHz, VO = 2 VPP
RL = 60-Ω differential
–71
6.5
dBc
C
C
Differential input voltage noise
f = 1 MHz, input-referred
nV/√Hz
DC PERFORMANCE
Differential gain
Closed-loop configuration
TA = 25°C
19
±1
V/V
C
A
A
B
B
Differential gain error(2)
±8%
±10
±11
15
TA = 25°C
mV
mV
VIO
Input offset voltage
TA = –40°C to 85°C
Input offset voltage drift
μV/°C
Channels 1 to 2 and 3 to 4 only,
TA = 25°C
Input offset voltage matching
±1
±10
mV
A
INPUT CHARACTERISTICS
Noninverting input resistance
Input bias voltage
2 || 2
6
kΩ || pF
C
A
TA = 25°C
5.8
6.2
V
(1) Test levels: (A) 100% tested at 25°C. Overtemperature limits set by characterization and simulation. (B) Limits set by characterization
and simulation. (C) Typical value only for information.
(2) Negative feedback loop only.
6
Copyright © 2014, Texas Instruments Incorporated
THS6226A
www.ti.com.cn
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
Electrical Characteristics: VS = +12 V (continued)
At TA = 25°C, RMATCH = 10.2 Ω, transformer turn ratio 1:1.4, RL = 100-Ω differential at transformer output, full bias mode, and
active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
OUTPUT CHARACTERISTICS
16
–4
17.5
–5.5
V
V
V
V
A
A
B
B
RL = 60-Ω differential, class H
operation(3)(4), each output, TA = 25°C
Voltage swing
15.7
–3.7
Class H
output
TA = –40°C to 85°C(3)(4)
RL = 60-Ω differential, class H operation,
TA = 25°C
±333
±383
mA
A
Current
(sourcing, sinking)
TA = –40°C to 85°C
±323
9.9
mA
V
B
A
A
B
B
RL = 60-Ω differential, normal operation(3)
each output, TA = 25°C
,
10.1
1.9
2.1
V
Voltage swing
9.8
V
Class AB
output
TA = –40°C to 85°C(3)
2.2
V
RL = 60-Ω differential, normal operation,
TA = 25°C
±130
±126
±137
mA
A
Current
(sourcing, sinking)
TA = –40°C to 85°C
mA
A
B
C
C
C
Short-circuit output current
Output impedance
Crosstalk
1
25
zo
f = 1 MHz, differential
Ω
f = 1 MHz, VOUT = 2 VPP, port 1 to port 2
–90
dB
POWER SUPPLY
Class AB, TA = 25°C
TA = –40°C to 85°C
Class H
10
10
10
10
12
12
15
15
V
V
V
V
A
B
B
B
Maximum operating voltage
12.6
12.6
TA = –40°C to 85°C
Per port, bias 15, class H enable
(power supplies connected together),
TA = 25°C
23.4
22.9
22.8
22.3
24.6
24.0
25.8
26.1
25.2
25.7
mA
mA
mA
A
B
A
TA = –40°C to 85°C
Per port, bias 15, class H disable
(power supplies connected together),
TA = 25°C
TA = –40°C to 85°C
Bias current step
mA
mA
B
C
1
Per port, bias 0, class H disable
(power supplies connected together),
TA = 25°C
IQ
Quiescent current (IS+)
8.5
8.0
9.7
10.9
11.4
mA
mA
mA
A
B
C
TA = –40°C to 85°C
Per port, line termination mode
(B9 = B8 = B7 = B6 = 0)
(power supplies connected together)
7.0
1.9
Both ports, main amplifiers and
class H disable
(B9 = B8 = B7 = B6 = 0)
2.4
2.5
mA
A
TA = –40°C to 85°C
mA
dB
dB
B
A
B
PSRR
Power-supply rejection ratio
Differential, from 12 V, GND, TA = 25°C
TA = –40°C to 85°C
60
58
70
(3) Measured at the amplifier outputs (pins 17, 20, 21, and 24).
(4) Capacitor fully charged, no droop.
Copyright © 2014, Texas Instruments Incorporated
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THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
Electrical Characteristics: VS = +12 V (continued)
At TA = 25°C, RMATCH = 10.2 Ω, transformer turn ratio 1:1.4, RL = 100-Ω differential at transformer output, full bias mode, and
active impedance circuit configuration, unless otherwise noted. Each port is tested independently.
TEST
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
LEVEL(1)
LOGIC
Logic 1, with respect to GND(5)
Logic 0, with respect to GND(5)
Logic X = 0.5 V (logic 0), TA = 25°C
TA = –40°C to 85°C
1.9
V
V
C
C
A
B
A
B
C
C
C
Logic threshold
0.8
25
10
66
μA
Logic pin
30
μA
Input Bias current
Input impedance
Logic X = 3.3 V (logic 1), TA = 25°C
TA = –40°C to 85°C
125
130
μA
μA
50 || 1
kΩ || pF
μs
td(on)
td(off)
Turn-on time delay
Turn-off time delay
Time for IS to reach 50% of final value
Time for IS to reach 50% of final value
1
1
μs
(5) The GND pin usable range is from VS– to (VS+ – 5 V).
6.6 Timing Characteristics
PARAMETER
MIN
200
MAX
UNITS
tCL
Clock period
ns
1
2
3
4
5
6
7
8
9
10
11 12
CLK
tCL
DATA
tSETUP
Figure 1. Serial Interface Timing
8
Copyright © 2014, Texas Instruments Incorporated
THS6226A
www.ti.com.cn
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
6.7 Typical Characteristics
At TA = 25°C, 1:1.4 transformer, and 10.2-Ω matching resistance, unless otherwise noted
3
0
3
0
-3
-3
Bias 0
Bias 1
Bias 2
Bias 3
Bias 4
Bias 5
Bias 6
Bias 7
Bias 8
Bias 9
Bias 10
Bias 11
Bias 12
Bias 13
Bias 14
Bias 15
Bias 0
Bias 1
Bias 2
Bias 3
Bias 4
Bias 5
Bias 6
Bias 7
Bias 8
Bias 9
Bias 10
Bias 11
Bias 12
Bias 13
Bias 14
Bias 15
-6
-6
-9
-9
-12
-15
-18
-21
-24
-12
-15
-18
-21
-24
1
10
100
1
10
100
Frequency (MHz)
Frequency (MHz)
C001
C002
VO = 2 VPP
VO = 7.5 VPP
Figure 2. Normalized Small-Signal Frequency Response
Figure 3. Normalized Large-Signal Frequency Response
12
±30
Profile
±40
Adjacent Ch. Disabled
±50
±60
10
8
1 W Internal
Power Limit
±70
±80
±90
6
25 : Load Line
50 : Load Line
100 : Load Line
±100
±110
±120
±130
±140
±150
±160
4
1 W Internal
Power Limit
2
0
-350
-250
-150
-50
50
150
250
350
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Output Current (mA)
Frequency (MHz)
C003
C004
14.5-dBm Tx Power in One Channel
MTPR Measured on Adjacent channel
Bias 11
Figure 4. Output Voltage vs Output Current
Figure 5. Profile 17a Crosstalk
25
24.5
24
12
32
30
28
26
24
22
20
18
16
14
12
10
8
11.5
11
Class H Bias 15
Class AB Bias 15
Class H Bias 0
Class AB Bias 0
23.5
23
10.5
10
22.5
22
9.5
9
Ch. AB Bias 15
Ch. CD Bias 15
Ch. AB Bias 15 Class H
Ch. CD Bias 15 Class H
Ch. AB Bias 0
6
4
2
0
21.5
21
8.5
8
Ch. CD Bias 0
0
5
10
15
±50
±25
0
25
50
75
100
125
Supply Voltage (V)
Temperature (C)
C005
C006
Figure 6. Quiescent Current vs Supply Voltage
Figure 7. Quiescent Current vs Temperature
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THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
Typical Characteristics (continued)
At TA = 25°C, 1:1.4 transformer, and 10.2-Ω matching resistance, unless otherwise noted
±30
700
600
500
400
300
200
100
0
Single Channel
±40
Dual channel (per channel)
±50
±60
±70
±80
Profile
Single Channel
Dual Channel
±90
±100
±110
±120
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
±10
±5
0
5
10
15
20
Frequency (MHz)
Tx Power (dBm)
C008
C007
19.8-dBm Tx Power
Bias 2
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 2
ADSL
Figure 9. ADSL MTPR
Figure 8. ADSL Power Consumption vs Tx Power
±30
±40
850
750
650
550
450
350
250
150
±50
±60
±70
±80
±90
Profile
Single Channel
Dual Channel
±100
±110
±120
Single Channel
Dual channel
0
1
2
3
4
5
6
7
8
±6
±3
0
3
6
9
12
15
18
21
Frequency (MHz)
Tx Power (dBm)
C010
C009
20.5-dBm Tx Power
Bias 7
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
VDSL Profile 8
Bias 7
Figure 11. Profile 8 MTPR
Figure 10. Profile 8 Power Consumption vs Tx Power
±30
±40
500
Profile
Single Channel
Dual Channel
450
400
350
300
250
200
±50
±60
±70
±80
±90
±100
±110
±120
±130
Single Channel
Dual channel
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
±6
±3
0
3
6
9
12
15
Frequency (MHz)
Tx Power (dBm)
C012
C011
14.5-dBm Tx Power
Bias 11
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
VDSL Profile 17
Bias 11
Figure 13. Profile 17 MTPR
Figure 12. Profile 17 Power Consumption vs Tx Power
10
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Typical Characteristics (continued)
At TA = 25°C, 1:1.4 transformer, and 10.2-Ω matching resistance, unless otherwise noted
±30
700
600
500
400
300
200
100
0
Ta = +85C
Ta = +25C
Ta = -40C
±40
±50
±60
±70
Profile
Ta = +85C
Ta = +25C
Ta = -40C
±80
±90
±100
±110
±120
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
±10
±5
0
5
10
15
20
Frequency (MHz)
Tx Power (dBm)
C014
C013
19.8-dBm Tx Power
Bias 2
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 2
ADSL
Figure 15. Single-Channel ADSL MTPR vs Temperature
Figure 14. Single-Channel ADSL Power Consumption
vs Temperature
±30
±40
±50
±60
±70
±80
850
Ta = +85C
Ta = +25C
Ta = -40C
750
650
550
450
350
250
150
Profile
±90
Ta = +85C
Ta = +25C
±100
Ta = -40C
±110
±120
0
1
2
3
4
5
6
7
8
±6
±3
0
3
6
9
12
15
18
21
Frequency (MHz)
Tx Power (dBm)
C016
C015
20.5-dBm Tx Power
Bias 7
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
VDSL Profile 8
Bias 7
Figure 17. Single-Channel Profile 8 MTPR vs Temperature
Figure 16. Single-Channel Profile 8 Power Consumption
vs Temperature
±30
500
Profile
Ta = +85C
Ta = +85C
Ta = +25C
Ta = +25C
Ta = -40C
±40
Ta = -40C
±50
450
400
350
300
250
±60
±70
±80
±90
±100
±110
±120
±130
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
±6
±3
0
3
6
9
12
15
Frequency (MHz)
Tx Power (dBm)
C018
C017
14.5-dBm Tx Power
Bias 11
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
VDSL Profile 17
Bias 11
Figure 19. Single-Channel Profile 17 MTPR vs Temperature
Figure 18. Single-Channel Profile 17 Power Consumption
vs Temperature
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Typical Characteristics (continued)
At TA = 25°C, 1:1.4 transformer, and 10.2-Ω matching resistance, unless otherwise noted
±30
700
600
500
400
300
200
100
0
Ta = +85C
Ta = +25C
Ta = -40C
±40
±50
±60
±70
Profile
Ta = +85C
Ta = +25C
Ta = -40C
±80
±90
±100
±110
±120
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
±10
±5
0
5
10
15
20
Frequency (MHz)
Tx Power (dBm)
C020
C019
19.8-dBm Tx Power
Bias 2
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 2
Per Channel
ADSL
Figure 21. Dual-Channel ADSL MTPR vs Temperature
Figure 20. Dual-Channel ADSL Power Consumption
vs Tx Power
±30
±40
±50
±60
±70
±80
850
Ta = +85C
Ta = +25C
Ta = -40C
750
650
550
450
350
250
150
Profile
±90
Ta = +85C
Ta = +25C
±100
Ta = -40C
±110
±120
0
1
2
3
4
5
6
7
8
±6
±3
0
3
6
9
12
15
18
21
Frequency (MHz)
Tx Power (dBm)
C022
C021
20.5-dBm Tx Power
Bias 7
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 7
Per Channel
VDSL Profile 8
Figure 23. Dual-Channel Profile 8 MTPR vs Temperature
Figure 22. Dual-Channel Profile 8 Power Consumption
vs Temperature
±30
450
Profile
Ta = +85C
Ta = +85C
Ta = +25C
Ta = +25C
Ta = -40C
±40
Ta = -40C
±50
400
350
300
250
200
±60
±70
±80
±90
±100
±110
±120
±130
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
±6
±3
0
3
6
9
12
15
Frequency (MHz)
Tx Power (dBm)
C024
C023
14.5-dBm Tx Power
Bias 11
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 11
VDSL Profile 17
Per Channel
Figure 25. Dual-Channel Profile 17 MTPR vs Temperature
Figure 24. Dual-Channel Profile 17 Power Consumption
vs Temperature
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ZHCSCI0A –APRIL 2014–REVISED MAY 2014
Typical Characteristics (continued)
At TA = 25°C, 1:1.4 transformer, and 10.2-Ω matching resistance, unless otherwise noted
900
800
700
600
500
400
300
200
100
0
2
1.5
1
0.5
0
-0.5
-1
Unit 1
Unit 2
Unit 3
Unit 4
-1.5
-2
±50
±25
0
25
50
75
100
125
Temperature (C)
Input Offset Voltage (mV)
C025
C026
Figure 27. Input Offset Voltage Histogram
Figure 26. Input Offset Voltage vs Temperature
±30
±40
500
450
400
350
300
250
200
Profile
Ta = +85C
Ta = +25C
Ta = -40C
Ta = +85C
Ta = +25C
Ta = -40C
±50
±60
±70
±80
±90
±100
±110
±120
±130
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (MHz)
±6
±3
0
3
6
9
12
15
Tx Power (dBm)
C028
C027
14.5-dBm Tx Power
Bias 15
1:1.4 Transformer into 100 Ω
1:1.4 Transformer into 100 Ω
Bias 15
VDSL Profile 30
Figure 29. Single-Channel Profile 30 MTPR vs Temperature
Figure 28. Single-Channel Profile 30 Power Consumption
vs Temperature
±30
500
Profile
Ta = +85C
Ta = +85C
Ta = +25C
Ta = +25C
Ta = -40C
±40
Ta = -40C
450
400
350
300
250
200
±50
±60
±70
±80
±90
±100
±110
±120
±130
0
2
4
6
8
10 12 14 16 18 20 22 24 26 28 30 32
Frequency (MHz)
±6
±3
0
3
6
9
12
15
Tx Power (dBm)
C030
C029
14.5-dBm Tx Power
Bias 15
1:1.4 Transformer into 100 Ω
Per Channel
Figure 31. Dual-Channel Profile 30 MTPR vs Temperature
Figure 30. Dual-Channel Profile 30 Power Consumption
vs Temperature
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7 Detailed Description
7.1 Overview
The THS6226A class H line driver provides exceptional ac performance in conjunction with wide output voltage
swing. The class H operation allows voltage swings to exceed the power supply for short intervals limited only by
the charge in the capacitor. In class AB mode, the device is capable of driving a 100-Ω load from +1.8 V to
+10.2 V. In class H mode, under the same conditions, the output voltage range becomes an impressive –5.5 V to
+17.5 V, or 46 VPP differentially with the capacitor fully charged.
The Functional Block Diagram section shows a fully-differential, noninverting amplifier configuration with active
impedance. In this configuration, the 10.2-Ω matching resistor appears through the transformer as 100 Ω,
minimizing reflection on the line. This active impedance scheme also minimizes transmission losses, as
compared to passive termination. Device gain is fixed and is equal to 19 V/V from the input to the output of the
amplifier (INAB/CD to OUTAB/CD), not including the transformer-turn ratio or the termination loss.
To simplify the implementation as well as to provide design flexibility, the device contains an integrated mid-
supply buffer that provides the correct biasing to the amplifier core without requiring any external components.
Also present is a two-pin serial interface that provides exceptional design flexibility and allows minimal power
consumption for each xDSL profile.
7.2 Functional Block Diagram
VLL_AB,
VLL_CD
CAPL_AB,
CAPL_CD
Class H Functions
IN_B, IN_D
FB_B, FB_D
OUTB, OUTD
Voltage
Reference
OUTA, OUTC
FB_A, FB_C
IN_A, IN_C
Bias
Class H Functions
RESET DATA
CLK
VHH_AB,
VHH_CD
CAPH_AB,
CAPH_CD
14
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7.3 Feature Description
The device incorporates several hardware and functionality features: a high output current line driver, a charge
pump, a voltage reference, a logic circuit, an active impedance, and a RESET pin. The device has two ports.
Each port consists of a high output current line driver, a charge pump, and a reference voltage. Common circuits
are the RESET feature and the logic circuit.
7.3.1 High Output Current Line Driver
The main purpose for the device is to provide a high output current into a heavy load. For the THS6226A, with its
xDSL application targeted, the load is typically 100 Ω and currents as high as 400 mA are supported with
excellent linearity. The core of the line driver is a class AB amplifier providing both good efficiency and high
current drive capability. The high output line driver is the core of the device and any external circuit interface is
located on both the device inputs and output.
7.3.2 Charge Pump
The class H functionality of the device is brought on by the integration of a charge pump. The charge pump is a
power-supply function to the line driver. The role of the charge pump is to vary the power supply from (12 V /
GND) to (20 V / –8 V) and allow the line driver to support high peak to average ratio (PAR) signals while
minimizing power consumption and maintaining excellent linearity. The charge pump is controlled externally by
the VH_EN pin. A logic high on the VH_EN pin results in the power supply of the class AB line driver going to (20 V /
–8 V), while a logic low on the VH_EN pin results in normal operation under the (12 V / GND) supplies.
7.3.3 Voltage Reference
An internal voltage reference provides the device common-mode input and output voltage.
7.3.4 Logic
The DATA and CLK pins allow access to the internal logic circuit implemented in the device. This logic circuit
allows each channel to either be programmed individually for quiescent current, turn the charge pump on or off,
disable the main amplifier, or select the line termination mode. For more information on programming, refer to the
Programming section.
7.3.5 Active Impedance
The line driver incorporates the positive feedback path to provide the termination to the load. For the device, the
synthesis factor implemented is 5.
7.3.6 RESET Pin
The RESET pin provides a quick and easy way to disable the two ports immediately if a fault condition on the
line occurs.
7.4 Device Functional Modes
There are several functional modes for the device. These functional modes can be accessed with the CLK and
DATA pins. Each main line driver quiescent current can be set to 16 different bias modes: bias 0 through bias
15. Additionally, the line driver and class H feature can be controlled to have the following configuration:
•
Class AB mode is the main line driver by itself. The output voltage is limited by the (12 V / GND) power-
supply rails. The quiescent current is then set by four bits.
•
Class H mode is the main line driver used in conjunction with the class H feature. The output voltage is
limited by the (20 V / –8 V) internally-generated power-supply rails. The quiescent current of the main line
driver is set by four bits, as in class AB mode.
•
•
Line termination mode is the powered-down mode for the line driver. This mode maintains line termination but
has reduced linearity performance.
Disabled mode.
For more information on these mode, refer to the Programming section.
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7.5 Programming
7.5.1 Programming the Device
Programming the device is accomplished through a serial interface (pins 4 and 5) and proceeds in the following
sequence:
•
•
•
•
Two start bits are required (B0 = 0 followed by B1 = 1).
B2 through B9 are used to program the device. (Table 1 lists the bit descriptions.)
B10 (described in Table 2) is the parity bit that controls whether the word is loaded or not.
B11 is the stop bit and must be set to B11 = 1.
Figure 32 shows the required sequence.
Table 1. DATA Sequence
PARAMETER
B0, B1
DESCRIPTION
Start bits
B2, B3
B4, B5
B6-B9
B10
Channel select
Power-down features
Quiescent current setting
Parity bit
B11
Stop bit
Table 2. Parity Bit
B10
0
ODD PARITY BIT
For an odd number of high bits in B2 to B9, set B10 to 0
For an even number of high bits in B2 to B9, set B10 to 1
1
MSB
B0
LSB
B11
DATA
B1
B2
B3
B4
B5
B6
D3
B7
D2
B8
D1
B9
D0
B10
Start
Bit
Start Ch AB Ch CD PD1
Bit Select Select
PD0
Parity Stop
Bit
Figure 32. DATA Description
16
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7.5.2 Quiescent Current
The device quiescent current is dissipated in two main device modules: the class AB and the charge pump. Bits
B4 (PD1) and B5 (PD0) select one of the possible four modes of operation:
1. Class AB mode (charge pump disabled),
2. Class H mode (charge pump enabled),
3. Disable mode, or
4. Line termination mode (maintains line matching, core amplifier at very low bias mode and charge pump
disabled for lowest power consumption possible).
Table 3 lists the details on each bit functionality and the approximate quiescent current. The various power
modes are shown in Table 3. For all modes, when B6 through B9 are not defined, set B9 = B8 = B7 = B6 = 0 to
achieve the lowest power dissipation possible.
Table 3. Power Modes
APPROXIMATE IQ
B4 (PD1)
B5 (PD0)
POWER-DOWN MODE
(mA per Port)
0
0
1
1
0
1
0
1
Power-down (B9 = B8 = B7 = B6 = 0)
0.85
4.4
—
Line termination mode (B9 = B8 = B7 = B6 = 0)
Class AB driver IQ set by B6 to B9, class H disabled
Class AB driver IQ set by B6 to B9, class H enabled
—
The class AB quiescent current is set by bits B6 to B9, using B4 and B5 for the power-down function and B2 and
B3 for channel selection. The approximate quiescent current for the amplifier core is shown in Table 4.
Table 4. Class AB Quiescent Current
QUIESCENT CURRENT APPROXIMATE
BIAS
0
B6 (D3)
B7 (D2)
B8 (D1)
B9 (D0)
SETTING
IQ (mA per Port)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
9.4
1
10.4
2
ADSL2+ mode
11.5
3
12.5
4
13.6
5
14.6
6
15.7
7
Profile 8b mode
Profile 17a mode
16.7
8
17.8
9
18.8
10
11
12
13
14
15
19.8
20.8
21.8
22.8
23.8
24.8
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Channel selection is shown in Table 5. Each channel can be programmed independently, or together if both B2
and B3 are set to 1.
Table 5. Channel Selection
B2 (Channel AB)
B3 (Channel CD)
CHANNEL SELECT
Bits B4 to B9 are ignored
0
0
1
1
0
1
0
1
Channel B programmed with B4 to B9
Channel A programmed with B4 to B9
Channels A and B programmed with B4 to B9
At startup, the internal register is set as shown in Figure 33.
Figure 33. Internal Register
7
6
5
PD1(B4)
W
4
PD0(B5)
W
3
D3 (B6)
W
2
D2 (B7)
W
1
D1 (B8)
W
0
D0 (B9)
W
Ch. AB Select
(B2)
Ch. CD Select
(B3)
W
W
LEGEND: W = Write
In this condition, the total quiescent power dissipation is 10.2 mW per port on a +12-V supply.
18
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8 Applications and Implementation
8.1 Application Information
The device is a dual-port, very-high-bit-rate digital subscriber line (VDSL), class H line driver. Typically, the signal
is generated by a high-speed digital-to-analog converter (DAC). The device drives a twisted pair.
The digital subscriber line (DSL) system is ac-coupled as it transmits information above the audio band. On the
input of the line driver, this ac-coupling translates into the series capacitors to isolate the dc voltage coming from
the DAC output common-mode voltage. On the output, a transformer is used to help isolate the 48V present
between tip and ring of the telephone line.
The transformer can be set to any useful ratio. In practice, the transformer-turn ratio is set between 1:1 and 1:1.4
for the device. As mentioned in the Feature Description section, the active impedance synthesis factor is 5. This
synthesis factor means that the termination resistor is 1/5th of the load impedance reflected to the transformer
secondary. Thus, the correct termination can be selected based on the transformer-turn ratio.
Note that the resulting load detected by the amplifier may affect the amplifier linearity or output voltage swing
capabilities.
8.2 Typical Application
The typical application circuit for this application is shown in Figure 34.
1mF
VLL_CD
+12V
CAPL_CD
FBC
47 W
IND
VIN+
OUTD
1:n
+12V
Device
100kW
RL
RL
33 nF
0.2 ×
n2
OUTC
VIN-
DATA
CLK
INC
47 W
FBD
VHH_CD
CAPH_CD
1mF
Figure 34. Typical VDSL Line Driver Circuit Configuration
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Typical Application (continued)
8.2.1 Design Requirements
Table 6. Design Requirements
DESIGN REQUIREMENT
CONDITION
0.1 µF
AC-coupling capacitors
Synthesis factor
5
Output transformer ratio
Surge protection circuit
1:1.4
Not shown
8.2.2 Detailed Design Procedure
The input capacitor forms a high-pass filter with the device input impedance. This pole must be set at a
frequency low enough to not interfere with the desired signal.
The output transformer can be changed to any transformer-turn ratio. Note that the load is expected to be a
transmission line with 100-Ω characteristic impedance. Referred to the transformer secondary, the load detected
by the amplifier is 1 / n2 with 1:n being the transformer-turn ratio.
Practical limitations force the transformer-turn ratio to be between 1.4:1 and 1:2. At the lighter load detected by
the amplifier (1.4:1), the voltage swing is limited by the class H and the maximum achievable swing of the
amplifier. At the heaviest load (1:2), the voltage swing is limited by the current drive capability of the amplifier. To
satisfy the synthesis impedance factor and the loading, the series resistance (RS) can be set to RS = RL / 5 =
100 Ω / (5 × n2).
For the charge pump, consider the thermal characteristic of the capacitor (X7R, X5R, or Y5V can be used for the
charge pump).
For the power-supply bypass, consider using only X7R or X5R because of the better stability of these materials
over temperature.
For surge protection, consider adding 47-Ω resistors in series on the positive feedback path. The secondary
protection is also normally added after the series resistance on the secondary transformer.
20
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8.2.3 Application Curves
±30
±40
±30
±40
±50
±50
±60
±60
±70
±70
±80
±80
Profile
Single Channel
Dual Channel
±90
±90
Profile
Single Channel
Dual Channel
±100
±110
±120
±100
±110
±120
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
0
1
2
3
4
5
6
7
8
Frequency (MHz)
Frequency (MHz)
C008
C010
19.8-dBm Tx Power
1:1.4 Transformer into 100 Ω
Bias 2
20.5-dBm Tx Power
1:1.4 Transformer into 100 Ω
Bias 7
Figure 35. ADSL MTPR
Figure 36. VDSL 8b MTPR
±30
±40
Profile
Single Channel
Dual Channel
±50
±60
±70
±80
±90
±100
±110
±120
±130
0
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Frequency (MHz)
C012
14.5-dBm Tx Power
Bias 11
1:1.4 Transformer into 100 Ω
Figure 37. VDSL 17a MTPR
8.3 Initialization Set Up
After the initial power-up and prior to sending any words to program the device, TI recommends sending a string
of twelve 1s (111111111111) to ensure that the state machine is initialized.
9 Power Supply Recommendations
As a result of large recharge current flowing in and out of the four charge pump capacitors during charge pump
discharge and recharge events, TI recommends placing bypass capacitors that are at least equal in value to the
charge pump capacitor close to each supply voltage pin. A minimum of 2-µF bypass capacitors for each channel
are required to minimize any transient appearing on the power supply because both positive and negative charge
pump 1-µF bypass capacitors are recharged on the +12-V supply.
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10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the THS6226A requires careful attention
to board layout parasitics and external component types. Recommendations that optimize performance include:
a. Minimize parasitic capacitance to any ac ground for all signal I/O pins. Excessive parasitic capacitance on
the inverting input pin can cause instability. In the line driver application, the parasitic capacitance forms a
pole with the load detected by the amplifier and may reduce the effective bandwidth of the application circuit,
thus leading to degraded performance. To reduce unwanted capacitance, open a window around the signal
I/O pins in all ground and power planes around those pins. Otherwise, make sure that ground and power
planes are unbroken elsewhere on the board.
b. Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1-µF decoupling capacitors.
At the device pins, make sure that the ground and power-plane layout are not in close proximity to the signal
I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and decoupling
capacitors. Always decouple the power-supply connections with these capacitors. An additional low ESR
supply decoupling capacitor (≥ 2 µF, X7R or X5R) to ground is necessary to provide a transient current
during the charge pump capacitors recharge.
c. Careful selection and placement of external components preserves the high-frequency performance
of the device. Use very low reactance type resistors. Surface-mount resistors function best and allow a
tighter overall layout. Metal-film or carbon composition, axially-leaded resistors also provide good high-
frequency performance. Again, keep the leads and printed circuit board traces as short as possible. Never
use wire-wound type resistors in a high-frequency application.
d. Connections to other wideband devices on the board can be made with short, direct traces or through
onboard transmission lines. For short connections, consider the trace and the input to the next device as a
lumped capacitive load. Use relatively wide traces (50 mils to 100 mils), preferably with ground and power
planes opened up around them.
e. Do not socket a high-speed part such as the THS6226A. The additional lead length and pin-to-pin
capacitance introduced by the socket can create an extremely troublesome parasitic network that makes
achieving a smooth, stable frequency response almost impossible. Best results are obtained by soldering the
device onto the board.
22
Copyright © 2014, Texas Instruments Incorporated
THS6226A
www.ti.com.cn
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
10.2 Layout Example
Charge Pump
Capacitor
Charge Pump
Capacitor
GND
Charge Pump
Capacitor
Charge Pump
Capacitor
Charge Pump
Placed to Minimize
Parasitic Series Resistance
Figure 38. Layout Example
Copyright © 2014, Texas Instruments Incorporated
23
THS6226A
ZHCSCI0A –APRIL 2014–REVISED MAY 2014
www.ti.com.cn
11 器件和文档支持
11.1 文档支持
11.1.1 相关文档ꢀ
相关文档如下：
•
《PowerPAD™ 耐热增强型封装》(，SLMA002
11.2 Trademarks
PowerPAD is a trademark of Texas Instruments, Inc.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
12 机械封装和可订购信息
以下页中包括机械封装和可订购信息。 这些信息是针对指定器件可提供的最新数据。 这些数据会在无通知且不对
本文档进行修订的情况下发生改变。 欲获得该数据表的浏览器版本，请查阅左侧的导航栏。
24
Copyright © 2014, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THS6226AIRHBR
THS6226AIRHBT
LIFEBUY
VQFN
VQFN
RHB
32
32
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-3-260C-168 HR
Level-3-260C-168 HR
-40 to 85
-40 to 85
HS6226A
IRHB
LIFEBUY
RHB
NIPDAU
HS6226A
IRHB
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Jun-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THS6226AIRHBR
THS6226AIRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
330.0
180.0
12.4
12.4
5.3
5.3
5.3
5.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THS6226AIRHBR
THS6226AIRHBT
VQFN
VQFN
RHB
RHB
32
32
3000
250
346.0
210.0
346.0
185.0
33.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RHB 32
5 x 5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224745/A
www.ti.com
PACKAGE OUTLINE
RHB0032E
VQFN - 1 mm max height
S
C
A
L
E
3
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
B
A
PIN 1 INDEX AREA
(0.1)
5.1
4.9
SIDE WALL DETAIL
20.000
OPTIONAL METAL THICKNESS
C
1 MAX
SEATING PLANE
0.08 C
0.05
0.00
2X 3.5
(0.2) TYP
3.45 0.1
9
EXPOSED
THERMAL PAD
16
28X 0.5
8
17
SEE SIDE WALL
DETAIL
2X
SYMM
33
3.5
0.3
0.2
32X
24
0.1
C A B
C
1
0.05
32
25
PIN 1 ID
(OPTIONAL)
SYMM
0.5
0.3
32X
4223442/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
3.45)
SYMM
32
25
32X (0.6)
1
24
32X (0.25)
(1.475)
28X (0.5)
33
SYMM
(4.8)
(
0.2) TYP
VIA
8
17
(R0.05)
TYP
9
16
(1.475)
(4.8)
LAND PATTERN EXAMPLE
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223442/B 08/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RHB0032E
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X ( 1.49)
(0.845)
(R0.05) TYP
32
25
32X (0.6)
1
24
32X (0.25)
28X (0.5)
(0.845)
SYMM
33
(4.8)
17
8
METAL
TYP
16
9
SYMM
(4.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 33:
75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4223442/B 08/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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