THVD1400_V02 [TI]
THVD1400, THVD1420 3.3-V to 5-V RS-485 Transceivers in Small Package with ±12-kV IEC ESD Protection;
| 型号： | THVD1400_V02 |
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TEXAS INSTRUMENTS |
| 描述： | THVD1400, THVD1420 3.3-V to 5-V RS-485 Transceivers in Small Package with ±12-kV IEC ESD Protection |
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THVD1400, THVD1420
SLLSF78B – DECEMBER 2020 – REVISED OCTOBER 2021
THVD1400, THVD1420 3.3-V to 5-V RS-485 Transceivers in Small Package
with ±12-kV IEC ESD Protection
1 Features
Description
•
Meets or exceeds the requirements of the TIA/
EIA-485A standard
3-V to 5.5-V Supply voltage
Half-duplex RS-422/RS-485
Data rates
THVD1400 and THVD1420 are robust half-duplex
RS-485 transceivers for industrial applications. The
bus pins are immune to high levels of IEC Contact
Discharge ESD events, eliminating the need for
additional system level protection components.
•
•
•
– THVD1400: 500 kbps
– THVD1420: 12 Mbps
Bus I/O protection
– ±16-kV HBM ESD
The devices operate from a single 3 to 5.5-V supply.
The wide common-mode voltage range and low input
leakage on bus pins make the devices suitable for
multi-point applications over long cable runs.
•
– ±12-kV IEC 61000-4-2 Contact discharge
– ±15-kV IEC 61000-4-2 Air gap discharge
– ±4-kV IEC 61000-4-4 Fast transient burst
– ±16-V bus fault protection (absolute max
voltage on bus pins)
Small, space-saving 8-pin SOT package option
(2.1 mm x 1.2 mm)
– See the layout example for co-layout with
standard SOIC-8 package
THVD1400 and THVD1420 are available in
industry standard, 8-pin SOIC package for drop-in
compatibility as well as in the industry-leading, small
SOT package. The devices are characterized for
ambient temperatures from –40°C to 125°C.
•
•
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
SOT (8)
SOIC (8)
2.1 mm x 1.2 mm
THVD1400
THVD1420
Extended industrial temperature range: -40°C to
125°C
4.90 mm × 3.91 mm
•
•
Large receiver hysteresis for noise rejection
Low power consumption
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
– Low standby supply current: < 1 µA
– Quiescent current during operation: 1.5 mA
(typ)
•
•
•
Glitch-free power-up/down for hot plug-in capability
Open, short, and idle bus failsafe
1/8 Unit load (Up to 256 bus nodes)
1
R
2
7
2 Applications
RE
B
6
•
•
•
•
•
•
•
•
•
Factory automation & control
Building automation
Grid infrastructure
Motor drives
Power delivery
Industrial transport
HVAC systems
3
A
DE
4
D
Simplified Schematic
Video surveillance
Smart meters
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1400, THVD1420
SLLSF78B – DECEMBER 2020 – REVISED OCTOBER 2021
www.ti.com
Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Revision History.............................................................. 2
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 4
5.1 Absolute Maximum Ratings........................................ 4
5.2 ESD Ratings............................................................... 4
5.3 ESD Ratings [IEC]...................................................... 4
5.4 Recommended Operating Conditions.........................5
5.5 Thermal Information....................................................5
5.6 Power Dissipation Characteristics.............................. 5
5.7 Electrical Characteristics.............................................6
5.8 Switching Characteristics (THVD1400).......................7
5.9 Switching Characteristics (THVD1420).......................7
5.10 Typical Characteristics..............................................9
6 Parameter Measurement Information.......................... 11
7 Detailed Description......................................................13
7.1 Overview...................................................................13
7.2 Functional Block Diagrams....................................... 13
7.3 Feature Description...................................................13
7.4 Device Functional Modes..........................................13
8 Application Information Disclaimer.............................15
8.1 Application Information............................................. 15
8.2 Typical Application.................................................... 15
9 Power Supply Recommendations................................19
10 Layout...........................................................................20
10.1 Layout Guidelines................................................... 20
10.2 Layout Example...................................................... 20
11 Device and Documentation Support..........................22
11.1 Device Support........................................................22
11.2 Receiving Notification of Documentation Updates..22
11.3 Support Resources................................................. 22
11.4 Trademarks............................................................. 22
11.5 Electrostatic Discharge Caution..............................22
11.6 Glossary..................................................................22
12 Mechanical, Packaging, and Orderable
Information.................................................................... 22
3 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2021) to Revision B (October 2021)
Page
•
•
•
•
Updated IEC ESD Contact rating from 8 kV to 12 kV in the Features section................................................... 1
Changed HBM rating for non-bus pins from 1kV to 4kV in the ESD Ratings table ...........................................4
Changed the IEC ESD contact rating for bus pins from 8kV to 12kV in the ESD Ratings [IEC] table................4
Updated the VIH max specification for the logic input pins from VCC to 5.5 V in the Recommended Operating
Conditions table..................................................................................................................................................5
Updated IEC ESD Contact rating from 8 kV to 12 kV in the Features Description section.............................. 13
Updated IEC ESD Contact rating from 8 kV to 12 kV in the Transient Protection section................................17
•
•
Changes from Revision * (December 2020) to Revision A (April 2021)
Page
•
•
•
•
•
Added Feature: See the layout example............................................................................................................ 1
Deleted the Advanced Information note from THVD1420 in the Device Information table.................................1
Added Figure 5-7, Figure 5-8 and Figure 5-9. ................................................................................................... 9
Added test conditions for Figure 5-1, Figure 5-2, Figure 5-4 and Figure 5-5. ....................................................9
Added Figure 10-2 ...........................................................................................................................................20
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4 Pin Configuration and Functions
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
GND
Not to scale
Figure 4-1. SOIC-8 (D), SOT-8 (DRL) Package, Top View
Table 4-1. Pin Functions
PIN
I/O
DESCRIPTION
NAME
R
NO.
1
Digital output
Digital input
Digital input
Digital input
Ground
Receive data output
RE
DE
D
2
Receiver enable, active low (internal 2-MΩ pull-up)
Driver enable, active high (internal 2-MΩ pull-down)
Driver data input
3
4
GND
A
5
Device ground
6
Bus input/output
Bus input/output
Power
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
3.3-V to 5-V supply
B
7
VCC
8
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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range, unless otherwise noted (see (1)
)
MIN
–0.5
–0.3
–16
MAX
7
UNIT
V
VCC
VL
Supply voltage
Input voltage at any logic pin (D, DE or RE)
Voltage at A or B inputs
Receiver output current
Junction temperature
5.7
16
V
VA, VB
IO
V
–24
24
mA
°C
°C
TJ
170
150
TSTG
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
5.2 ESD Ratings
VALUE
UNIT
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Bus terminals (A, B) and GND ±16,000
V
All other pins
±4,000
±1,500
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 ESD Ratings [IEC]
VALUE
UNIT
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
IEC 61000-4-2 ESD (Contact Discharge), bus terminals and GND
IEC 61000-4-2 ESD (Air-Gap Discharge), bus terminals and GND
IEC 61000-4-4 EFT (Fast transient or burst), bus terminals and GND
±12,000
±15,000
±4,000
V(ESD)
V
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5.4 Recommended Operating Conditions
MIN
3
NOM
MAX
5.5
12
UNIT
VCC
VID
VI
Supply voltage
5
V
V
V
V
V
Differential input voltage
–12
–7
2
Input voltage at any bus terminal(1)
12
VIH
VIL
High-level input voltage (driver, driver-enable, and receiver-enable inputs)
Low-level input voltage (driver, driver-enable, and receiver-enable inputs)
5.5
0.8
60
0
Driver
–60
–8
54
IO
Output current
Receiver
mA
8
RL
Differential load resistance
60
Ω
kbps
Mbps
°C
1/tUI
1/tUI
TJ
Signaling rate: THVD1400
500
12
Signaling rate: THVD1420
Junction temperature
–40
–40
150
150
125
(2)
TA
Operating ambient temperature
Thermal shutdown threshold (temperature rising)
Thermal shutdown hysteresis
°C
TSHDN
THYS
170
15
°C
°C
(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
(2) Operation is specified for internal (junction) temperatures up to 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shut-down (TSD) circuit which
disables the driver outputs when the junction temperature reaches 170°C.
5.5 Thermal Information
THVD1400, THVD1420
THERMAL METRIC(1)
DRL (SOT)
8 PINS
112.2
28.4
D (SOIC)
8 PINS
126.0
66.2
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
22.1
69.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
1.2
18.7
ψJB
22.0
68.7
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
5.6 Power Dissipation Characteristics
PARAMETER
TEST CONDITIONS
RL = 300 Ω, CL = 50 pF
VALUE
145
UNIT
Power dissipation, driver and
Unterminated
RS-422 load
receiver enabled, VCC = 5.5 V, TA
=
RL = 100 Ω, CL = 50 pF
RL = 54 Ω, CL = 50 pF
175
125°C, 50% duty cycle square-wave
signal at maximum signaling rate
(THVD1400)
mW
RS-485 load
235
PD
Power dissipation, driver and
receiver enabled, VCC = 5.5 V, TA
125°C, 50% duty cycle square-wave
signal at maximum signaling rate
(THVD1420)
Unterminated
RS-422 load
RL = 300 Ω, CL = 50 pF
RL = 100 Ω, CL = 50 pF
175
200
=
mW
RS-485 load
RL = 54 Ω, CL = 50 pF
250
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5.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V
1.5
2.1
2
3
See Figure 6-1
See Figure 6-2
RL = 60 Ω, -7 V ≤ Vtest ≤ 12 V, 4.5 V ≤ Vcc
≤ 5.5 V
Driver differential-output voltage
magnitude
│VOD│
V
RL = 100 Ω, CL = 50 pF
RL = 54 Ω, CL = 50 pF
2
1.5
2.1
2.5
2
RL = 54 Ω, 4.5 V ≤ Vcc ≤ 5.5 V
3
Change in magnitude of driver
differential-output voltage
Δ│VOD
VOC(SS)
ΔVOC
VOC(PP)
VOC(PP)
│IOS
│
–50
1
50
3
mV
V
Steady-state common-mode
output voltage
RL = 54 Ω or 100 Ω, CL = 50 pF
See Figure 6-2
VCC / 2
Change in differential driver
common-mode output voltage
–50
50
mV
mV
mV
mA
Peak-to-peak driver common-
mode output voltage
RL = 54 Ω, CL = 50 pF, VCC = 5 V
RL = 54 Ω, CL = 50 pF, VCC = 3.3 V
See Figure 6-2
See Figure 6-2
520
250
Peak-to-peak driver common-
mode output voltage
Driver short-circuit output
current
│
DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin
-250
–97
250
100
Receiver
VI = 12 V
DE = 0 V, VCC = 0 V or 5.5 V
VI = –7 V
75
Bus input current (driver
disabled)
II
µA
–70
Positive-going receiver
differential-input voltage
threshold
VIT+
–70
–150
50
–45
mV
Negative-going receiver
differential-input voltage
threshold
VIT–
-7 V ≤ VCM ≤ 12 V
–200
mV
mV
Receiver differential-input
voltage threshold hysteresis
(1)
VHYS
30
(VIT+ – VIT–
)
Receiver high-level output
voltage
VOH
VOL
IOZ
IOH = –4 mA
VCC – 0.4
VCC – 0.2
0.2
V
V
Receiver low-level output
voltage
IOL = 4 mA
0.4
1
Receiver high-impedance
output current
VO = 0 V or VCC, RE = VCC
–1
–5
µA
Logic
IIN
Input current (D, DE, RE)
5
µA
Supply
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5.7 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DE = VCC, RE =
0, no load
Both driver and receiver enabled
1500
1800
Driver enabled and receiver
disabled
DE = VCC, RE =
VCC, no load
1000
700
0.1
1500
900
1
VCC = 3.6
V
µA
Driver disabled and receiver
enabled
DE = 0, RE = 0,
no load
DE = 0 , RE =
VCC, no load
Both driver and receiver disabled
Driver and receiver enabled
ICC
Supply current (quiescent)
DE = VCC, RE =
0, no load
1700
1300
800
0.1
3000
2500
1000
1
DE = VCC, RE =
VCC, no load
Driver enabled, receiver disabled
Driver disabled, receiver enabled
Both driver and receiver disabled
VCC = 5.5
V
µA
DE = 0, RE = 0,
no load
DE = 0, RE =
VCC, no load
(1) Under any specific conditions, VIT+ is specified to be at least VHYS higher than VIT–
.
5.8 Switching Characteristics (THVD1400)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Driver differential output rise and fall times
200
400
250
600
500
15
ns
ns
ns
ns
ns
µs
tPHL, tPLH Driver propagation delay
tSK(P) Driver pulse skew, |tPHL – tPLH
See Figure 6-3
|
tPHZ, tPLZ Driver disable time
tPZH, tPZL Driver enable time
Receiver
80
200
4
200
650
10
See Figure
6-4 and Figure 6-5
Receiver enabled
Receiver disabled
tr, tf
tPHL, tPLH Receiver propagation delay time
tSK(P) Receiver pulse skew, |tPHL – tPLH
tPHZ, tPLZ Receiver disable time
tPZL(1)
Receiver output rise and fall times
13
60
20
110
7
ns
ns
ns
ns
ns
See Figure 6-6
|
30
60
60
See Figure 6-7
See Figure 6-8
,
Driver enabled
Driver disabled
150
tPZH(1)
tPZL(2)
tPZH(2)
Receiver enable time
,
4
10
µs
5.9 Switching Characteristics (THVD1420)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Driver differential output rise and fall times
15
20
25
38
3.5
38
70
10
ns
ns
ns
ns
ns
µs
tPHL, tPLH Driver propagation delay
tSK(P) Driver pulse skew, |tPHL – tPLH
See Figure 6-3
|
tPHZ, tPLZ Driver disable time
tPZH, tPZL Driver enable time
Receiver
15
15
4
See Figure
6-4 and Figure 6-5
Receiver enabled
Receiver disabled
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5.9 Switching Characteristics (THVD1420) (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
10
MAX
UNIT
ns
tr, tf
Receiver output rise and fall times
16
75
5
tPHL, tPLH Receiver propagation delay time
tSK(P) Receiver pulse skew, |tPHL – tPLH
tPHZ, tPLZ Receiver disable time
tPZL(1)
See Figure 6-6
40
ns
|
ns
15
25
25
170
ns
See Figure 6-7
,
Driver enabled
Driver disabled
ns
tPZH(1)
tPZL(2)
tPZH(2)
Receiver enable time
,
See Figure 6-8
4
10
µs
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5.10 Typical Characteristics
6
5.5
5
5
4.8
4.6
4.4
4.2
4
VOH (VCC=5V)
VOL (VCC=5V)
VCC = 5 V
4.5
4
3.5
3
3.8
3.6
3.4
3.2
3
2.5
2
1.5
1
2.8
2.6
2.4
0.5
0
0
10
20
30
40
50
Driver Output Current (mA)
60
70
80
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Driver Output Current (mA)
D001
D002
D001_driver_vout_iout.grf
D002_driver_vdiff.grf
DE = VCC
TA = 25°C
DE = VCC
D = 0 V
TA = 25°C
Figure 5-1. Driver Output voltage vs Driver Output Current
Figure 5-2. Driver Differential Output voltage vs Driver Output
Current
66
63
60
57
54
51
48
45
42
39
36
33
350
Fall time (VCC=5V)
Rise time (VCC=5V)
345
340
335
330
325
320
315
310
3
3.25 3.5 3.75
4
4.25 4.5 4.75
Vcc (V)
5
5.25 5.5
-40
-20
0
20
40
60
80
100 120 140
Temperature (èC)
D003
D004
D003_Iout_vcc.grf
D004_rise_fall.grf
RL = 54 Ω
DE = VCC
D = VCC
RL = 54 Ω
spacer
CL = 50 pF
TA = 25°C
Figure 5-3. Driver Output Current vs Supply Voltage
Figure 5-4. Driver Rise or Fall Time vs Temperature (THVD1400)
320
75
tPHL (ns) VCC=5V
tPLH (ns) VCC=5V
VCC=5V
315
310
305
300
295
290
285
280
70
65
60
55
50
-40
-20
0
20
40
60
80
100 120 140
0
50 100 150 200 250 300 350 400 450 500
Signaling Rate (kbps)
Temperature (èC)
D005
D006
D005_prop_delay.grf
D006_Icc_datarate.grf
RL = 54 Ω
CL = 50 pF
RL = 54 Ω
TA = 25 °C
Figure 5-5. Driver Propagation Delay vs Temperature
(THVD1400)
Figure 5-6. Supply Current vs Signal Rate (THVD1400)
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5.10 Typical Characteristics (continued)
11
21
20
19
18
17
16
15
14
13
Rise Time (VCC = 5 V )
Fall Time (VCC = 5 V)
tPHL (VCC = 5 V)
tPLH (VCC = 5 V)
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (C)
Temperature (C)
RL = 54 Ω
CL = 50 pF
RL = 54 Ω
CL = 50 pF
Figure 5-7. Driver Rise and Fall Time vs Temperature
(THVD1420)
Figure 5-8. Driver Propagation Delay vs Temperature
(THVD1420)
65
60
55
50
VCC = 5 V
0
2000
4000
6000
8000
10000
12000
Signaling Rate (kbps)
RL = 54 Ω TA = 25 °C
Figure 5-9. Supply Current vs Signal Rate (THVD1420)
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6 Parameter Measurement Information
Vcc
375 Ω
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
Figure 6-1. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
V
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
OC
Figure 6-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
0 V
Vcc
DE
50%
V
I
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
Input
50 Ω
V
50%
10%
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
Figure 6-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
B
R
=
DE
50 Ω
L
t
PZH
=
C
L
50 pF
110 Ω
V
Input
Generator
OH
90%
V
I
50%
V
O
~
~ 0V
t
PHZ
Figure 6-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
50%
10%
VOL
VI
Generator
50 Ω
Figure 6-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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3 V
0 V
50%
V
I
A
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
VOH
Generator
I
90%
B
CL=15 pF
50%
10%
RE
V
OD
V
OL
tr
t
f
Figure 6-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
Figure 6-7. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
Figure 6-8. Measurement of Receiver Enable Times With Driver Disabled
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7 Detailed Description
7.1 Overview
The THVD1400 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 500 kbps.
The THVD1420 is a low-power, half-duplex RS-485 transceiver suitable for data transmission up to 12 Mbps.
7.2 Functional Block Diagrams
VCC
R
RE
A
B
DE
D
GND
7.3 Feature Description
Internal ESD protection circuits protect the transceiver against Electrostatic Discharges (ESD) according to IEC
61000-4-2 of up to ±12 kV (Contact Discharge), ±15 kV (Air Gap Discharge) and against electrical fast transients
(EFT) according to IEC 61000-4-4 of up to ±4 kV.
7.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case, the differential output voltage defined
as VOD = VA – VB is positive. When D is low, the output states reverse, B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition, the logic state at D is irrelevant. The DE
pin has an internal pull-down resistor to ground; thus, when left open, the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
Table 7-1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is positive and higher than the positive input threshold, VIT+, the receiver output, R,
turns high. When VID is negative and lower than the negative input threshold, VIT-, the receiver output, R, turns
low. If VID is between VIT+ and VIT- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven
(idle bus).
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Table 7-2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VIT+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VIT- < VID < VIT+
VID < VIT-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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8 Application Information Disclaimer
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The THVD1400 is a half-duplex RS-485 transceiver commonly used for asynchronous data transmissions. The
driver and receiver enable pins allow for the configuration of different operating modes.
8.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Figure 8-1. Typical RS-485 Network With Half-Duplex Transceivers
8.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
8.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 300 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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8.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
(1)
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
8.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1
unit load represents a load impedance of approximately 12 kΩ. Because the THVD1400 consists of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
8.2.1.4 Receiver Failsafe
The differential receivers of the THVD1400 are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver
is not indeterminate.
Receiver failsafe is accomplished by offsetting the receiver thresholds such that the input indeterminate range
does not include zero volts differential. To comply with the RS-422 and RS-485 standards, the receiver output
must output a high when the differential input VID is more positive than 200 mV, and must output a low when
VID is more negative than –200 mV. The receiver parameters which determine the failsafe performance are VIT+
,
VIT–, and VHYS (the separation between VIT+ and VIT–). As shown in the Receiver Function Table, differential
signals more negative than –200 mV always causes a low receiver output, and differential signals more positive
than 200 mV always causes a high receiver output.
When the differential input signal is close to zero, it is still above the VIT+ threshold, and the receiver output is
high. Only when the differential input is more than VHYS below VIT+ does the receiver output transition to a low
state. Therefore, the noise immunity of the receiver inputs during a bus fault conditions includes the receiver
hysteresis value, VHYS, as well as the value of VIT+
.
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8.2.1.5 Transient Protection
The bus pins of the THVD1400 transceiver family include on-chip ESD protection against ±16-kV HBM and
±12-kV IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far
more severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge
resistance, R(D), of the IEC model produce significantly higher discharge currents than the HBM model.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
Figure 8-2. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment.
Common discharge events occur because of human contact with connectors and cables. Designers may choose
to implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients
often result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or
the switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
Figure 8-3 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
Figure 8-3. Power Comparison of ESD, EFT, and Surge Transients
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In the event of surge transients, high-energy content is characterized by long pulse duration and slow decaying
pulse power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver
is converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver.
Figure 8-4 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT
pulse train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
Figure 8-4. Comparison of Transient Energies
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8.2.2 Detailed Design Procedure
In order to protect bus nodes against high-energy transients, the implementation of external transient protection
devices is necessary. Figure 8-5 suggests a protection circuit against 1 kV surge (IEC 61000-4-5) transients.
Table 8-1 shows the associated bill of materials.
5V
100nF
100nF
10k
V
CC
R1
R
RxD
TVS
RE
DE
D
A
B
MCU/
UART
DIR
TxD
R2
10k
GND
Figure 8-5. Transient Protection Against Surge Transients for Half-Duplex Devices
Table 8-1. Bill of Materials
DEVICE
XCVR
R1
FUNCTION
ORDER NUMBER
MANUFACTURER
RS-485 transceiver
THVD1400
TI
10-Ω, pulse-proof thick-film resistor
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bourns
R2
TVS
Bidirectional 400-W transient suppressor
8.2.3 Application Curves
Figure 8-6. THVD1400 waveforms at 500 kbps, VCC = 5V
9 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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10 Layout
10.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order
to protect against surge transients that may occur in industrial environments. Since these transients have a
wide frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver, UART
and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in these lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
8. While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-oxide
varistors (MOVs) which reduce the transients to a few hundred volts of clamping voltage, and transient
blocking units (TBUs) that limit transient current to less than 1 mA.
10.2 Layout Example
5
Via to ground
Via to VCC
C
4
R
R
R
6
6
1
R
R
7
R
MCU
5
TVS
5
Figure 10-1. Layout Example for SOIC package
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Figure 10-2. Layout Example for Co-layout of SOIC (D) and SOT (DRL)
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11 Device and Documentation Support
11.1 Device Support
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1400DR
THVD1400DRLR
THVD1420DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOT-5X3
SOIC
D
8
8
8
8
2500 RoHS & Green
4000 RoHS & Green
2500 RoHS & Green
4000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1400
T400
1420
T420
DRL
D
SN
NIPDAU
SN
THVD1420DRLR
SOT-5X3
DRL
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1400DRLR
THVD1420DRLR
SOT-5X3
SOT-5X3
DRL
DRL
8
8
4000
4000
180.0
180.0
8.4
8.4
2.75
2.75
1.9
1.9
0.8
0.8
4.0
4.0
8.0
8.0
Q3
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1400DRLR
THVD1420DRLR
SOT-5X3
SOT-5X3
DRL
DRL
8
8
4000
4000
210.0
210.0
185.0
185.0
35.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DRL0008A
SOT-5X3 - 0.6 mm max height
S
C
A
L
E
8
.
0
0
0
PLASTIC SMALL OUTLINE
1.3
1.1
B
A
PIN 1
ID AREA
1
8
6X 0.5
2.2
2.0
2X 1.5
NOTE 3
5
4
0.27
0.17
8X
1.7
1.5
0.05
0.00
0.1
C A B
0.05
C
0.6 MAX
SEATING PLANE
0.05 C
0.18
0.08
SYMM
0.4
0.2
8X
SYMM
4224486/D 11/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, interlead flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4.Reference JEDEC Registration MO-293, Variation UDAD
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EXAMPLE BOARD LAYOUT
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:30X
0.05 MIN
AROUND
0.05 MAX
AROUND
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDERMASK DETAILS
4224486/D 11/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DRL0008A
SOT-5X3 - 0.6 mm max height
PLASTIC SMALL OUTLINE
8X (0.67)
SYMM
8
8X (0.3)
1
SYMM
6X (0.5)
5
4
(R0.05) TYP
(1.48)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:30X
4224486/D 11/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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