THVD1419DR [TI]
具有浪涌保护功能的 3.3V 至 5V RS-485 收发器 | D | 8 | -40 to 125;
| 型号： | THVD1419DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有浪涌保护功能的 3.3V 至 5V RS-485 收发器 | D | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总31页 (文件大小：1386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1419, THVD1429
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
具有浪涌保护功能的 THVD14x9 3.3V 至 5V RS-485 收发器
1 特性
3 说明
1
•
•
•
满足或超过 TIA/EIA-485A 标准的要求
THVD1419 和 THVD1429 是半双工 RS-485 收发器，
集成了浪涌保护功能。电涌保护是通过在标准 8 引脚
SOIC (D) 封装中集成瞬态电压抑制器 (TVS) 二极管实
现的。此功能大大提高了可靠性，可以更好地抵抗耦合
到数据电缆的噪声瞬变，无需外部保护元件。
3V 至 5.5V 电源电压
总线 I/O 保护
–
–
–
–
–
±16kV HBM ESD
±8kV IEC 61000-4-2 接触放电
±30kV IEC 61000-4-2 气隙放电
±4kV IEC 61000-4-4 电气快速瞬变
±2.5kV IEC 61000-4-5 1.2/50μs 浪涌
每个器件由 3.3V 或 5V 单电源供电。该系列中的器件
具有很宽的共模电压范围，因此非常适合长电缆上的
应用 长线缆。
•
有两种速度等级
THVD1419 和 THVD1429 器件采用行业标准 SOIC 封
装，无需变更 PCB 即可轻松插入。这些器件在自然通
风环境下的额定温度范围为 –40°C 至 125°C。
–
–
THVD1419：250kbps
THVD1429：20Mbps
•
•
扩展环境
温度范围：–40°C 至 125°C
器件信息(1)
扩展运行
共模范围：±12V
器件型号
THVD1419
THVD1429
封装
封装尺寸（标称值）
SOIC (8)
4.90mm × 3.91mm
•
•
用于噪声抑制的接收器迟滞值：30mV
低功耗
(1) 如需了解所有可订购器件，请参阅数据表末尾的可订购产品附
录。
–
–
待机电源电流：< 2µA
运行期间的电流：< 3mA
THVD1419 和 THVD1429 方框图
•
•
•
•
适用于热插拔功能的无干扰加电/断电
开路、短路和空闲总线失效防护
VCC
1/8 单位负载（多达 256 个总线节点）
A
R
采用可实现快插兼容性的行业标准 8 引脚 SOIC
封装
B
RE
DE
D
2 应用
•
•
•
•
•
•
•
•
无线基础设施
楼宇自动化
HVAC 系统
工厂自动化和控制
电网基础设施
智能仪表
GND
过程分析
视频监控
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF32
THVD1419, THVD1429
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
www.ti.com.cn
目录
9.2 Functional Block Diagrams ..................................... 13
9.3 Feature Description................................................. 13
9.4 Device Functional Modes........................................ 16
10 Application and Implementation........................ 17
10.1 Application Information...................................... 17
10.2 Typical Application ............................................... 17
11 Power Supply Recommendations ..................... 20
12 Layout................................................................... 21
12.1 Layout Guidelines ................................................. 21
12.2 Layout Example .................................................... 21
13 器件和文档支持 ..................................................... 22
13.1 器件支持................................................................ 22
13.2 第三方产品免责声明.............................................. 22
13.3 相关链接................................................................ 22
13.4 接收文档更新通知 ................................................. 22
13.5 社区资源................................................................ 22
13.6 商标....................................................................... 22
13.7 静电放电警告......................................................... 22
13.8 术语表 ................................................................... 22
14 机械、封装和可订购信息....................................... 22
1
2
3
4
5
6
7
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Device Comparison Table..................................... 3
Pin Configuration and Functions......................... 4
Specifications......................................................... 5
7.1 Absolute Maximum Ratings ...................................... 5
7.2 ESD Ratings.............................................................. 5
7.3 ESD Ratings [IEC] .................................................... 5
7.4 Recommended Operating Conditions....................... 6
7.5 Thermal Information.................................................. 6
7.6 Power Dissipation ..................................................... 6
7.7 Electrical Characteristics........................................... 7
7.8 Switching Characteristics.......................................... 8
7.9 Typical Characteristics.............................................. 9
Parameter Measurement Information ................ 11
Detailed Description ............................................ 13
9.1 Overview ................................................................. 13
8
9
4 修订历史记录
Changes from Revision B (December 2018) to Revision C
Page
•
•
•
•
•
将 THVD1419 从：“产品预览” 更改为：“生产数据“................................................................................................................ 1
Changed power dissipation numbers of THVD1419 ............................................................................................................. 6
Changed THVD1419 driver switching characteristics ............................................................................................................ 8
Changed THVD1419 receiver switching characteristics......................................................................................................... 8
Added 图 7 to 图 9 ................................................................................................................................................................. 9
Changes from Revision A (December 2018) to Revision B
Page
•
将 THVD1429 从：“预告信息” 更改为：“生产数据”................................................................................................................ 1
2
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1419, THVD1429
www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
5 Device Comparison Table
PART NUMBER
THVD1419
DUPLEX
Half
ENABLES
SIGNALING RATE
up to 250 kbps
up to 20 Mbps
NODES
DE, RE
256
THVD1429
Copyright © 2018–2019, Texas Instruments Incorporated
3
THVD1419, THVD1429
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
www.ti.com.cn
6 Pin Configuration and Functions
THVD1419, THVD1429 Devices
8-Pin D Package (SOIC)
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A
NO.
6
Bus input/output
Bus input/output
Digital input
Digital input
Ground
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
Driver data input
B
7
D
4
DE
GND
R
3
Driver enable, active high (2-MΩ internal pull-down)
Device ground
5
1
Digital output
Power
Receive data output
VCC
RE
8
3.3-V to 5-V supply
2
Digital input
Receiver enable, active low (2-MΩ internal pull-up)
4
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1419, THVD1429
www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
Bus voltage
VCC
-0.5
7
V
Range at any bus pin (A or B) as differential or
common-mode with respect to GND
-15
-0.3
-24
-65
15
5.7
24
V
V
Input voltage
Range at any logic pin (D, DE, or /RE)
Receiver output
current
IO
mA
℃
Storage temperature range
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
VALUE
±16
UNIT
kV
Bus terminals
and GND
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, 2010
V(ESD)
Electrostatic discharge
All other pins
±8
kV
Charged device model (CDM), per
JEDEC JESD22-C101E
All pins
±1.5
kV
7.3 ESD Ratings [IEC]
VALUE
UNIT
Contact Discharge, per IEC 61000- Bus pins and
4-2 GND
±8
kV
V(ESD)
Electrostatic discharge
Air-Gap Discharge, per IEC 61000- Bus pins and
±30
±4
kV
kV
kV
4-2
GND
Bus pins and
GND
V(EFT)
Electrical fast transient
Surge
Per IEC 61000-4-4
Bus pins and
GND
V(surge)
Per IEC 61000-4-5, 1.2/50 μs
±2.5
Copyright © 2018–2019, Texas Instruments Incorporated
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THVD1419, THVD1429
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
www.ti.com.cn
7.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
VCC
VI
Supply voltage
3
5.5
V
Input voltage at any bus terminal
(separately or common mode)
-12
12
VCC
0.8
V
V
V
(1)
High-level input voltage (driver, driver
enable, and receiver enable inputs)
VIH
VIL
2
0
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
VID
IO
Differential input voltage
Output current, driver
-12
-60
-8
12
60
8
V
mA
mA
Ω
IOR
RL
Output current, receiver
Differential load resistance
Signaling rate: THVD1419
Signaling rate: THVD1429
Operating ambient temperature
Junction temperature
54
1/tUI
1/tUI
TA
250
20
kbps
Mbps
℃
-40
-40
125
150
TJ
℃
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
7.5 Thermal Information
THVD14x9
THERMAL METRIC(1)
D (SOIC)
8-PINS
120.7
50.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.5
ΨJB
62.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.6 Power Dissipation
PARAMETER
Description
TEST CONDITIONS
VALUE
230
UNIT
mW
mW
mW
mW
mW
mW
Unterminated: RL = 300 Ω, CL = 50 pF
RS-422 load: RL = 100 Ω, CL = 50 pF
RS-485 load: RL = 54 Ω, CL = 50 pF
Unterminated: RL = 300 Ω, CL = 50 pF
RS-422 load: RL = 100 Ω, CL = 50 pF
RS-485 load: RL = 54 Ω, CL = 50 pF
Driver and receiver enabled, VCC = 5.5 V, TA
= 125 0C, 50% duty cycle square wave at
maximum signaling rate, THVD1419
350
470
PD
350
Driver and receiver enabled, VCC = 5.5 V, TA
= 125 0C, 50% duty cycle square wave at
maximum signaling rate, THVD1429
290
300
6
Copyright © 2018–2019, Texas Instruments Incorporated
THVD1419, THVD1429
www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
7.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
Driver differential output voltage
magnitude
|VOD
|VOD
|VOD
|VOD
|
|
|
|
1.5
2.1
2
3.5
V
V
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, see 图 10
Driver differential output voltage
magnitude
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, 4.5 V ≤ VCC
5.5 V, see 图 10
≤
Driver differential output voltage
magnitude
RL = 100 Ω, see 图 11
RL = 54 Ω, see 图 11
4
V
Driver differential output voltage
magnitude
1.5
-200
1
3.5
V
Change in differential output
voltage
Δ|VOD
|
200
3
mV
V
VCC
/
VOC
Common-mode output voltage
RL = 54 Ω, see 图 11
2
Change in steady-state common-
mode output voltage
ΔVOC(SS)
-200
-250
200
250
mV
mA
IOS
Short-circuit output current
DE = VCC, -7 V ≤ VO ≤ 12 V
Receiver
VI = 12 V
VI = -7 V
VI = -12 V
50
-65
125
µA
µA
µA
II
Bus input current
DE = 0 V, VCC = 0 V or 5.5 V
-100
-150
-100
Positive-going input threshold
voltage
VTH+
VTH-
See(1)
-100
-20
mV
mV
Negative-going input threshold
voltage
Over common-mode range of ±12 V
-200
-130 See(1)
VHYS
CA,B
Input hysteresis
30
mV
pF
Input differential capacitance
Measured between A and B, f = 1 MHz
IOH = -8 mA
220
VCC
0.4
–
VCC
–
VOH
Output high voltage
V
0.3
VOL
Output low voltage
IOL = 8 mA
0.2
0.4
1
V
IOZR
Output high-impedance current
VO = 0 V or VCC, RE = VCC
-1
µA
Logic
IIN
Input current (D, DE, RE)
4.5 V ≤ VCC ≤ 5.5 V
-6.2
6.2
µA
Device
RE = 0 V,
Driver and receiver enabled
DE = VCC
No load
,
2.4
2
3
2.6
mA
mA
µA
RE = VCC
,
Driver enabled, receiver disabled DE = VCC
No load
,
ICC
Supply current (quiescent)
RE = 0 V,
Driver disabled, receiver enabled DE = 0V,
No load
700
960
RE = VCC
DE = 0 V, D
= open, No
load
,
Driver and receiver disabled
0.1
2
µA
TSD
Thermal shutdown temperature
170
℃
(1) Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–
.
Copyright © 2018–2019, Texas Instruments Incorporated
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THVD1419, THVD1429
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
www.ti.com.cn
7.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver: THVD1419
tr, tf
Differential output rise / fall time
Propagation delay
300
200
500
450
40
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF, see 图 12
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
20
60
3
50
RE = 0 V, see 图 13 and 图 14
RE = VCC, see 图 13 and 图 14
250
11
tPZH, tPZL
Enable time
Receiver: THVD1419
tr, tf
Output rise / fall time
14
30
20
50
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1), tPZL(1),
tPZH(2)
tPZL(2)
Driver: THVD1429
Propagation delay
Pulse skew, |tPHL – tPLH
Disable time
CL = 15 pF, see 图 15
|
7
35
80
45
DE = VCC, see 图 16
DE = 0 V, see 图 17
120
,
,
Enable time
5
14
µs
tr, tf
Differential output rise / fall time
Propagation delay
9
16
25
6
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF, see 图 12
12
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
18
16
40
40
11
RE = 0 V, see 图 13 and 图 14
RE = VCC, see 图 13 and 图 14
tPZH, tPZL
Enable time
2.8
Receiver: THVD1429
tr, tf
Output rise / fall time
2
6
45
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1), tPZL(1),
tPZH(2)
tPZL(2)
Propagation delay
Pulse skew, |tPHL – tPLH
Disable time
CL = 15 pF, see 图 15
12
|
6
14
75
28
DE = VCC, see 图 16
DE = 0 V, see 图 17
110
,
,
Enable time
4.8
14
µs
8
版权 © 2018–2019, Texas Instruments Incorporated
THVD1419, THVD1429
www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
7.9 Typical Characteristics
5
4.5
4
5
4.5
4
VOH VCC = 5 V
VOL VCC = 5 V
VOH VCC = 3.3 V
VOL VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
10
20
30
40
50
60
70
80
90
0
10
20
30
40
50
60
70
80
90
IO Driver Output Current (mA)
IO Driver Output Current (mA)
D101
D102
DE = VCC
D = 0 V
DE = VCC
D = 0 V
图 1. Driver Output Voltage vs Driver Output Current
图 2. Driver Differential Output voltage vs Driver Output
Current
70
65
60
55
50
45
40
35
30
25
20
15
10
5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
VCC = 5 V
VCC = 3.3 V
0
-5
8.5
8
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
VCC Supply Voltage (V)
Temperature (0C)
D103
D104
DE = VCC
TA = 25°C
RL = 54 Ω
THVD1429
图 3. Driver Output Current vs Supply Voltage
图 4. Driver Rise or Fall Time vs Temperature
19
18
17
16
15
14
13
12
11
10
90
85
80
75
70
65
60
55
50
45
40
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
-40
THVD1429
图 5. Driver Propagation Delay vs Temperature
-20
0
20
40
60
80
100 120 140
0
2
4
6
8
10
12
14
16
18
20
Temperature (0C)
Signaling Rate (Mbps)
D105
D106
THVD1429
TA = 25°C
RL = 54 Ω
图 6. Supply Current vs Signal Rate
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ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
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Typical Characteristics (接下页)
270
260
250
240
230
220
210
200
190
180
340
VCC = 5V
VCC = 3.3V
VCC = 5 V
VCC = 3.3 V
320
300
280
260
240
220
200
-40
-20
0
20
40
60
80
100 120 140
-40
-20
0
20
40
60
80
100 120 140
Temperature (0C)
Temperature (0C)
D_TH
D_TH
THVD1419
THVD1419
图 8. Driver Propagation Delay vs Temperature
图 7. Driver Rise or Fall Time vs Temperature
85
VCC = 5V
VCC = 3.3V
80
75
70
65
60
55
50
45
40
0
25
THVD1419
图 9. Supply Current vs Signal Rate
50
75 100 125 150 175 200 225 250
Signaling Rate (kbps)
D_TH
TA = 25°C
RL = 54 Ω
10
版权 © 2018–2019, Texas Instruments Incorporated
THVD1419, THVD1429
www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
8 Parameter Measurement Information
375 Ω
Vcc
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
图 10. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
V
OC
图 11. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
Vcc
DE
50%
V
I
0 V
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
50%
10%
Input
50 Ω
V
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
图 12. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
V
B
R
110 Ω
=
DE
50 Ω
L
t
PZH
=
C
L
Input
OH
50 pF
90%
Generator
V
I
50%
V
O
~
~ 0V
t
PHZ
图 13. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
Generator
50%
10%
VOL
VI
50 Ω
图 14. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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Parameter Measurement Information (接下页)
3 V
0 V
VOH
50%
V
I
A
B
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
Generator
I
90%
CL=15 pF
50%
10%
RE
V
OD
V
tr
OL
t
f
图 15. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
图 16. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
0V
Vcc
VI
50%
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
图 17. Measurement of Receiver Enable Times With Driver Disabled
12
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9 Detailed Description
9.1 Overview
THVD1419 and THVD1429 are surge-protected, half duplex RS-485 transceivers available in two speed grades
suitable for data transmission up to 250 kbps and 20 Mbps respectively. Surge protection is achieved by
integrating transient voltage suppresser (TVS) diodes in the standard 8-pin SOIC (D) package.
These devices have active-high driver enables and active-low receiver enables. A standby current of less than 2
µA can be achieved by disabling both driver and receiver.
9.2 Functional Block Diagrams
VCC
A
R
B
RE
DE
D
GND
图 18. THVD1419 and THVD1429 Block Diagram
9.3 Feature Description
9.3.1 Electrostatic Discharge (ESD) Protection
The bus pins of the THVD14x9 transceiver family include on-chip ESD protection against ±16-kV HBM and ±8-kV
IEC 61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more
severe than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance,
R(D), of the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC
61000-4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图 19. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables.
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Feature Description (接下页)
9.3.2 Electrical Fast Transient (EFT) Protection
Inductive loads such as relays, switch contactors, or heavy-duty motors can create high-frequency bursts during
transition. The IEC 61000-4-4 test is intended to simulate the transients created by such switching of inductive
loads on AC power lines. 图 20 shows the voltage waveforms in to 50-Ω termination as defined by the IEC
standard.
1
Time
15 ms at 5 kHz
0.75 ms at 100 kHz
300 ms
1
Time
200 µs at 5 kHz
10 µs at 100 kHz
1
0.5
Time
5 ns
50ns
图 20. EFT Voltage Waveforms
Internal ESD protection circuits of the THVD14x9 protect the transceivers against EFT ±4 kV.
9.3.3 Surge Protection
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and
currents), or the switching of power systems, including load changes and short circuit switching. These transients
are often encountered in industrial environments, such as factory automation and power-grid systems.
图 21 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
14
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Feature Description (接下页)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
0.5-kV Surge
12
4-kV EFT
10
8
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图 21. Power Comparison of ESD, EFT, and Surge Transients
图 22 shows the test setup used to validate THVD14x9 surge performance according to the IEC 61000-4-5
1.2/50-μs surge pulse.
80 ꢀ
A
Surge Generator
2 ꢀ Source Impedance
80 ꢀ
THVD14x9
GND
B
Coupling Network
图 22. THVD14x9 Surge Test Setup
THVD14x9 product family is robust to ±2.5-kV surge transients without the need for any external components.
9.3.4 Failsafe Receiver
The differential receivers of the THVD14x9 family are failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic high state so that the output of the
receiver is not indeterminate.
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9.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor to VCC, thus, when left open while the driver is enabled, output
A turns high and B turns low.
表 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
16
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ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
10 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
THVD14x9 are half-duplex RS-485 transceivers with integrated system-level surge protection. Standard 8-pin
SOIC (D) package allows drop-in replacement into existing systems and eliminate system-level protection
components.
10.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
图 23. Typical RS-485 Network With Half-Duplex Transceivers
10.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
10.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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Typical Application (接下页)
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10000
1000
100
5%, 10%, and 20% Jitter
Conservative
Characteristics
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图 24. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 20 Mbps for the THVD1429) in cases where the interconnect is
short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
10.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in 公式 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
10.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD14x9 devices consist of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible.
18
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Typical Application (接下页)
10.2.2 Detailed Design Procedure
RS-485 transceivers operate in noisy industrial environments typically require surge protection at the bus pins. 图
25 compares 1-kV surge protection implementation with a regular RS-485 transceiver (such as THVD14x0)
against with the THVD14x9. The internal TVS protection of the THVD14x9 achieves ±2.5 kV IEC 61000-4-5
surge protection without any additional external components, reducing system level bill of materials.
System level surge protection implementation
using a typical RS-485 transceiver
3.3V œ 5 V
100nF
VCC
10k 10k
RxD
Pulse-proof,
thick-film resistor
R
/RE
TVS
A
B
DIR
MCU/
UART
DE
D
DIR
TxD
Pulse-proof,
thick-film resistor
THVD14x0
10k
GND
System level surge protection implementation
using THVD14x9 transceiver
3.3V œ 5 V
100nF
VCC
10k 10k
R
RxD
/RE
A
DIR
MCU/
UART
B
DE
DIR
TxD
D
THVD14x9
10k
GND
图 25. Implementation of System-Level Surge Protection Using THVD14x9
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Typical Application (接下页)
10.2.3 Application Curves
VCC = 5 V
54-Ω Termination
TA = 25°C
图 26. THVD1429 Waveforms at 20 Mbps
11 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100-
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
20
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www.ti.com.cn
ZHCSJ05C –NOVEMBER 2018–REVISED MARCH 2019
12 Layout
12.1 Layout Guidelines
Additional external protection components generally are not needed when using THVD14x9 transceivers.
1. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance. Apply 100-nF to 220-nF decoupling capacitors
as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
2. Use at least two vias for VCC and ground connections of decoupling capacitors to minimize effective via-
inductance.
3. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
12.2 Layout Example
2
Via to GND
C
1
R
Via to VCC
3
R
R
MCU
3
R
THVD14x9
2
图 27. Half-Duplex Layout Example
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13 器件和文档支持
13.1 器件支持
13.2 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
13.3 相关链接
下表列出了快速访问链接。类别包括技术文档、支持和社区资源、工具和软件，以及立即订购快速访问。
表 3. 相关链接
器件
产品文件夹
请单击此处
请单击此处
立即订购
请单击此处
请单击此处
技术文档
请单击此处
请单击此处
工具与软件
请单击此处
请单击此处
支持和社区
请单击此处
请单击此处
THVD1419
THVD1429
13.4 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。.
13.5 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.6 商标
E2E is a trademark of Texas Instruments.
13.7 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
13.8 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。
14 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请查阅左侧的导航栏。
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1419DR
THVD1419DT
THVD1429DR
THVD1429DT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500 RoHS & Green
250 RoHS & Green
2500 RoHS & Green
250 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1419
1419
1429
1429
NIPDAUAG
NIPDAUAG
NIPDAUAG
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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10-Dec-2020
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1419DR
THVD1419DT
THVD1429DR
THVD1429DT
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
250
330.0
177.8
330.0
177.8
12.4
12.4
12.4
12.4
6.4
6.4
6.4
6.4
5.2
5.2
5.2
5.2
2.1
2.1
2.1
2.1
8.0
8.0
8.0
8.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
2500
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Sep-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD1419DR
THVD1419DT
THVD1429DR
THVD1429DT
SOIC
SOIC
SOIC
SOIC
D
D
D
D
8
8
8
8
2500
250
346.0
213.0
346.0
213.0
346.0
191.0
346.0
191.0
29.0
35.0
29.0
35.0
2500
250
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
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担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
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