THVD1428DR [TI]
具有浪涌保护功能的 3.3V 至 5V RS-485 收发器 | D | 8 | -40 to 125;
| 型号： | THVD1428DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有浪涌保护功能的 3.3V 至 5V RS-485 收发器 | D | 8 | -40 to 125 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总27页 (文件大小：1240K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1428
SLLSFG3 –MAY 2020
THVD1428 3.3-V to 5-V RS-485 Transceiver with 3-kV Surge Protection
1 Features
3 Description
THVD1428 is a half-duplex RS-485 transceiver with
integrated surge protection. Surge protection is
achieved by integrating transient voltage suppressor
(TVS) diodes in the standard 8-pin SOIC (D)
package. This feature provides a substantial increase
in reliability for better immunity to noise transients
coupled to the data cable, eliminating the need for
external protection components.
1
•
Meets or exceeds the requirements of the
TIA/EIA-485A standard
•
•
3-V to 5.5-V Supply voltage
Bus I/O protection
–
–
–
–
–
± 16 kV HBM ESD
± 4 kV IEC 61000-4-2 Contact discharge
± 8 kV IEC 61000-4-2 Air-gap discharge
± 4 kV IEC 61000-4-4 Electrical fast transient
± 3 kV IEC 61000-4-5 1.2/50-μs Surge
This device operates from a single 3.3-V or 5-V
supply and features a wide common-mode voltage
range which makes it suitable for multi-point
applications over long cable runs.
•
•
Supports 20 Mbps
Extended ambient
The device is available in the industry standard SOIC
package for easy drop-in without any PCB changes.
The device is characterized over ambient free-air
temperatures from –40°C to 125°C.
temperature range: -40°C to 125°C
•
Extended operational
common-mode range: ± 12 V
Device Information(1)
•
•
Receiver hysteresis for noise rejection: 30 mV
Low power consumption
PART NUMBER
PACKAGE
BODY SIZE (NOM)
–
–
Standby supply current: < 2 µA
Current during operation: < 3 mA
THVD1428
SOIC (8)
4.90 mm × 3.91 mm
(1) For all available devices, see the orderable addendum at the
end of the data sheet.
•
Glitch-free power-up/down for hot plug-in
capability
Block Diagram
•
•
•
Open, short, and idle bus fail-safe
1/8 Unit load (Up to 256 bus nodes)
VCC
Industry standard 8-Pin SOIC
for drop-in compatibility
A
R
B
RE
2 Applications
DE
D
•
•
•
•
•
•
•
•
Wireless infrastructure
Building automation
HVAC systems
Factory automation & control
Grid infrastructure
Smart meters
GND
Process analytics
Video surveillance
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
THVD1428
SLLSFG3 –MAY 2020
www.ti.com
Table of Contents
8.2 Functional Block Diagrams ..................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 14
Application and Implementation ........................ 15
9.1 Application Information........................................ 15
9.2 Typical Application ................................................. 15
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 ESD Ratings - IEC Specifications............................. 4
6.4 Recommended Operating Conditions....................... 5
6.5 Thermal Information.................................................. 5
6.6 Power Dissipation ..................................................... 5
6.7 Electrical Characteristics........................................... 6
6.8 Switching Characteristics.......................................... 7
6.9 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
9
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 19
11.1 Layout Guidelines ................................................. 19
11.2 Layout Example .................................................... 19
12 Device and Documentation Support ................. 20
12.1 Device Support...................................................... 20
12.2 Receiving Notification of Documentation Updates 20
12.3 Support Resources ............................................... 20
12.4 Trademarks........................................................... 20
12.5 Electrostatic Discharge Caution............................ 20
12.6 Glossary................................................................ 20
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 20
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
May 2020
*
Initial release.
2
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5 Pin Configuration and Functions
THVD1428 Devices
8-Pin D Package (SOIC)
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
VCC
B
A
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
A
NO.
6
Bus input/output
Bus input/output
Digital input
Digital input
Ground
Bus I/O port, A (complementary to B)
Bus I/O port, B (complementary to A)
Driver data input (2-MΩ internal pull-up)
Driver enable, active high (2-MΩ internal pull-down)
Device ground
B
7
D
4
DE
GND
R
3
5
1
Digital output
Power
Receive data output
VCC
RE
8
3.3-V to 5-V supply
2
Digital input
Receiver enable, active low (2-MΩ internal pull-up)
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
Supply voltage
Bus voltage
VCC
-0.5
7
V
Range at any bus pin (A or B) as differential or
common-mode with respect to GND
-15
-0.3
-24
-65
15
5.7
24
V
Input voltage
Range at any logic pin (D, DE, or /RE)
V
Receiver output
current
IO
mA
℃
Storage temperature range
150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±16
UNIT
kV
Bus terminals
and GND
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, 2010
V(ESD)
Electrostatic discharge
All other pins
±8
kV
Charged device model (CDM), per
JEDEC JESD22-C101E
All pins
±1.5
kV
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
Contact Discharge, per IEC 61000- Bus pins and
±4
kV
4-2
GND
V(ESD)
Electrostatic discharge
Air-Gap Discharge, per IEC 61000- Bus pins and
±8
±4
±3
kV
kV
kV
4-2
GND
Bus pins and
GND
V(EFT)
Electrical fast transient
Surge
Per IEC 61000-4-4
Bus pins and
GND
V(surge)
Per IEC 61000-4-5, 1.2/50 μs
4
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
NOM
MAX
UNIT
VCC
VI
Supply voltage
3
5.5
V
Input voltage at any bus terminal
(separately or common mode)
-12
12
VCC
0.8
V
V
V
(1)
High-level input voltage (driver, driver
enable, and receiver enable inputs)
VIH
VIL
2
0
Low-level input voltage (driver, driver
enable, and receiver enable inputs)
VID
IO
Differential input voltage
Output current, driver
-12
-60
-8
12
60
8
V
mA
mA
Ω
IOR
RL
Output current, receiver
Differential load resistance
Signaling rate: THVD1428
Operating ambient temperature
Junction temperature
54
1/tUI
TA
20
125
150
Mbps
℃
-40
-40
TJ
℃
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.5 Thermal Information
THVD1428
THERMAL METRIC(1)
D (SOIC)
8-PINS
120.7
50.3
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
62.8
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
7.5
ΨJB
62.2
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.6 Power Dissipation
PARAMETER
Description
TEST CONDITIONS
VALUE
350
UNIT
mW
mW
mW
Unterminated: RL = 300 Ω, CL = 50 pF
RS-422 load: RL = 100 Ω, CL = 50 pF
RS-485 load: RL = 54 Ω, CL = 50 pF
Driver and receiver enabled, VCC = 5.5 V, TA
= 125 0C, 50% duty cycle square wave at
maximum signaling rate, THVD1428
PD
290
300
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
Driver differential output voltage
magnitude
|VOD
|VOD
|VOD
|VOD
|
|
|
|
1.5
2.1
2
3.5
V
V
V
V
RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, see Figure 7
Driver differential output voltage RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, 4.5 V ≤
magnitude
VCC ≤ 5.5 V, see Figure 7
Driver differential output voltage
magnitude
RL = 100 Ω, see Figure 8
RL = 54 Ω, see Figure 8
4
Driver differential output voltage
magnitude
1.5
3.5
Change in differential output
voltage
Δ|VOD
|
-200
1
200
3
mV
V
VOC
Common-mode output voltage
RL = 54 Ω, see Figure 8
VCC / 2
Change in steady-state
common-mode output voltage
ΔVOC(SS)
-200
-250
200
250
mV
mA
IOS
Short-circuit output current
DE = VCC, -7 V ≤ VO ≤ 12 V
Receiver
VI = 12 V
VI = -7 V
VI = -12 V
50
-65
125
µA
µA
µA
II
Bus input current
DE = 0 V, VCC = 0 V or 5.5 V
-100
-150
-100
Positive-going input threshold
voltage
VTH+
VTH-
See(1)
-100
-130
-20
mV
mV
Negative-going input threshold
voltage
Over common-mode range of ±12 V
-200
See(1)
VHYS
CA,B
VOH
Input hysteresis
30
mV
pF
V
Input differential capacitance
Output high voltage
Output low voltage
Measured between A and B, f = 1 MHz
IOH = -8 mA
220
VCC – 0.4 VCC – 0.3
VOL
IOL = 8 mA
0.2
0.4
1
V
IOZR
Output high-impedance current VO = 0 V or VCC, RE = VCC
-1
µA
Logic
IIN
Input current (D, DE, RE)
4.5 V ≤ VCC ≤ 5.5 V
-6.2
6.2
µA
Device
RE = 0 V,
Driver and receiver enabled
DE = VCC
No load
,
2.4
2
3
2.6
mA
mA
µA
RE = VCC
DE = VCC
No load
,
Driver enabled, receiver
disabled
,
ICC
Supply current (quiescent)
RE = 0 V,
DE = 0V,
No load
Driver disabled, receiver
enabled
700
960
RE = VCC
DE = 0 V,
D = open,
No load
,
Driver and receiver disabled
0.1
2
µA
TSD
Thermal shutdown temperature
170
℃
(1) Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–
.
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6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver: THVD1428
tr, tf
Differential output rise / fall time
Propagation delay
9
16
25
6
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
RL = 54 Ω, CL = 50 pF, see Figure 9
12
Pulse skew, |tPHL – tPLH
|
tPHZ, tPLZ
Disable time
18
16
40
RE = 0 V, see Figure 10
and Figure 11
40
11
ns
µs
tPZH, tPZL
Enable time
RE = VCC, see Figure 10
and Figure 11
2.8
Receiver: THVD1428
tr, tf
Output rise / fall time
2
6
45
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
tPHZ, tPLZ
tPZH(1), tPZL(1),
tPZH(2)
tPZL(2)
Propagation delay
Pulse skew, |tPHL – tPLH
Disable time
CL = 15 pF, see Figure 12
12
|
6
14
75
28
DE = VCC, see Figure 13
DE = 0 V, see Figure 14
110
,
,
Enable time
4.8
14
µs
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6.9 Typical Characteristics
5
4.5
4
5
4.5
4
VOH VCC = 5 V
VOL VCC = 5 V
VOH VCC = 3.3 V
VOL VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
3.5
3
3.5
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
0
10
20
30
IO Driver Output Current (mA)
40
50
60
70
80
90
0
10
20
30
IO Driver Output Current (mA)
40
50
60
70
80
90
D101
D102
DE = VCC
D = 0 V
DE = VCC
D = 0 V
Figure 1. Driver Output Voltage vs Driver Output Current
Figure 2. Driver Differential Output voltage vs Driver Output
Current
70
65
60
55
50
45
40
35
30
25
20
15
10
5
16
15.5
15
14.5
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
VCC = 5 V
VCC = 3.3 V
0
8.5
8
-5
0
0.5
1
1.5
2
VCC Supply Voltage (V)
2.5
3
3.5
4
4.5
5
5.5
-40
-20
0
20
40
60
80
100 120 140
Temperature (0C)
D103
D104
DE = VCC
TA = 25°C
RL = 54 Ω
Figure 4. Driver Rise or Fall Time vs Temperature
Figure 3. Driver Output Current vs Supply Voltage
19
90
85
80
75
70
65
60
55
50
45
40
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
18
17
16
15
14
13
12
11
10
-40
-20
0
20
40
60
80
100 120 140
0
2
4
6
8
Signaling Rate (Mbps)
10
12
14
16
18
20
Temperature (0C)
D105
D106
Figure 5. Driver Propagation Delay vs Temperature
Figure 6. Supply Current vs Signal Rate
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7 Parameter Measurement Information
375 Ω
Vcc
DE
D
A
B
V
test
VOD
R
0V or V
cc
L
375 Ω
Figure 7. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A
B
R /2
L
B
D
V
B
0V or V
cc
V
OD
V
OC(PP)
R /2
L
ûV
OC(SS)
V
OC
C
L
V
OC
Figure 8. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
V
cc
Vcc
DE
50%
V
I
0 V
A
B
t
t
R =
L
54 Ω
PHL
PLH
D
~
V
2 V
~
C = 50 pF
L
OD
90%
Input
50 Ω
V
50%
10%
I
Generator
V
OD
~ œ 2 V
~
t
r
t
f
Figure 9. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A
V
cc
S1
V
O
D
50%
V
I
0 V
B
R
=
DE
50 Ω
L
t
PZH
=
C
L
50 pF
110 Ω
V
Input
Generator
OH
90%
V
I
50%
V
O
~
~ 0V
t
PHZ
Figure 10. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down
Load
Vcc
Vcc
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0 V
S1
VO
tPLZ
D
Vcc
≈
DE
CL=
50 pF
Input
50%
10%
VOL
VI
Generator
50 Ω
Figure 11. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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Parameter Measurement Information (continued)
3 V
0 V
VOH
50%
V
I
A
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
Generator
I
90%
50%
10%
B
CL=15 pF
RE
V
OD
V
tr
OL
t
f
Figure 12. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
cc
Vcc
DE
Vcc
V
50%
I
0V
V
A
B
tPZH(1)
1 kΩ
tPHZ
D
V
O
R
D at Vcc
S1 to GND
0V or Vcc
S1
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
Generator
D at 0V
S1 to Vcc
V
CC
50 Ω
V
I
V
50%
O
10%
V
OL
Figure 13. Measurement of Receiver Enable/Disable Times With Driver Enabled
Vcc
Vcc
VI
50%
0V
A
B
1 kΩ
tPZH(2)
V or 1.5V
VO
R
S1
VOH
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0V
50%
VO
CL=15 pF
RE
≈ 0V
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
VCC
50 Ω
VI
VO
50%
VOL
Figure 14. Measurement of Receiver Enable Times With Driver Disabled
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8 Detailed Description
8.1 Overview
THVD1428 is surge-protected, half duplex RS-485 transceiver suitable for data transmission up to 20 Mbps.
Surge protection is achieved by integrating transient voltage suppresser (TVS) diodes in the standard 8-pin SOIC
(D) package.
The device has active-high driver enable and active-low receiver enable. A standby current of less than 2 µA can
be achieved by disabling both driver and receiver.
8.2 Functional Block Diagrams
VCC
A
R
B
RE
DE
D
GND
Figure 15. THVD1428 Block Diagram
8.3 Feature Description
8.3.1 Electrostatic Discharge (ESD) Protection
The bus pins of the THVD1428 transceiver includes on-chip ESD protection against ±16-kV HBM and ±4-kV IEC
61000-4-2 contact discharge. The International Electrotechnical Commission (IEC) ESD test is far more severe
than the HBM ESD test. The 50% higher charge capacitance, C(S), and 78% lower discharge resistance, R(D), of
the IEC model produce significantly higher discharge currents than the HBM model. As stated in the IEC 61000-
4-2 standard, contact discharge is the preferred transient protection test method.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
Figure 16. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment. Common
discharge events occur because of human contact with connectors and cables.
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Feature Description (continued)
8.3.2 Electrical Fast Transient (EFT) Protection
Inductive loads such as relays, switch contactors, or heavy-duty motors can create high-frequency bursts during
transition. The IEC 61000-4-4 test is intended to simulate the transients created by such switching of inductive
loads on AC power lines. Figure 17 shows the voltage waveforms in to 50-Ω termination as defined by the IEC
standard.
1
Time
15 ms at 5 kHz
0.75 ms at 100 kHz
300 ms
1
Time
200 µs at 5 kHz
10 µs at 100 kHz
1
0.5
Time
5 ns
50ns
Figure 17. EFT Voltage Waveforms
Internal ESD protection circuits of the THVD1428 protect the transceiver against EFT ±4 kV.
8.3.3 Surge Protection
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and
currents), or the switching of power systems, including load changes and short circuit switching. These transients
are often encountered in industrial environments, such as factory automation and power-grid systems.
Figure 18 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation.
The right hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are most likely to occur in power generation and power-grid systems.
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Feature Description (continued)
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
Time (µs)
0
5
10 15 20 25 30 35 40
Time (µs)
Figure 18. Power Comparison of ESD, EFT, and Surge Transients
Figure 19 shows the test setup used to validate THVD1428 surge performance according to the IEC 61000-4-5
1.2/50-μs surge pulse.
80 ꢀ
A
RS-485
Transceiver
Surge Generator
2 ꢀ Source Impedance
80 ꢀ
B
Coupling Network
GND
Figure 19. THVD1428 Surge Test Setup
THVD1428 is robust to ±3-kV surge transients without the need for any external components.
8.3.4 Failsafe Receiver
The differential receiver of THVD1428 is failsafe to invalid bus states caused by the following:
•
•
•
Open bus conditions, such as a disconnected connector
Shorted bus conditions, such as cable damage shorting the twisted-pair together
Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver outputs a failsafe logic high state so that the output of the receiver
is not indeterminate.
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8.4 Device Functional Modes
When the driver enable pin, DE, is logic high, the differential outputs A and B follow the logic states at data input
D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage defined as
VOD = VA – VB is positive. When D is low, the output states reverse: B turns high, A becomes low, and VOD is
negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant. The DE pin
has an internal pull-down resistor to ground, thus when left open the driver is disabled (high-impedance) by
default. The D pin has an internal pull-up resistor of 2-MΩ to VCC, thus, when left open while the driver is
enabled, output A turns high and B turns low.
Table 1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between VTH+
and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
Table 2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA – VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
THVD1428 is a half-duplex RS-485 transceiver with integrated system-level surge protection. Standard 8-pin
SOIC (D) package allows drop-in replacement into existing systems and eliminate system-level protection
components.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for higher data rates over longer
cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
Figure 20. Typical RS-485 Network With Half-Duplex Transceivers
9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
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Typical Application (continued)
10000
5%, 10%, and 20% Jitter
1000
100
Conservative
Characteristics
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
Figure 21. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 20 Mbps for the THVD1428) in cases where the interconnect is
short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections as the length of the stub increases. As a general guideline, the electrical length, or round-trip delay, of
a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum physical stub length as
shown in Equation 1.
L(STUB) ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s)
v is the signal velocity of the cable or trace as a factor of c
(1)
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to driver 32 unit loads (UL), where 1 unit
load represents a load impedance of approximately 12 kΩ. Because the THVD1428 device consists of 1/8 UL
transceiver, connecting up to 256 receivers to the bus is possible.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
RS-485 transceivers operate in noisy industrial environments typically require surge protection at the bus pins.
Figure 22 compares 1-kV surge protection implementation with a regular RS-485 transceiver (such as
THVD14x0) against with the THVD1428. The internal TVS protection of the THVD1428 achieves ±3 kV IEC
61000-4-5 surge protection without any additional external components, reducing system level bill of materials.
System level surge protection implementation
using a typical RS-485 transceiver
3.3V œ 5 V
100nF
VCC
10k 10k
MOV
TBU
R
RxD
/RE
TVS
A
DIR
MCU/
UART
B
DE
DIR
TBU
D
TxD
RS-485 transceiver
10k
MOV
GND
System level surge protection implementation using
transceiver with integrated surge protection
3.3V œ 5 V
100nF
VCC
10k 10k
R
RxD
/RE
A
B
DIR
MCU/
UART
DE
D
DIR
TxD
10k
RS-485 with surge
protection integrated
GND
Figure 22. Implementation of System-Level Surge Protection Using THVD1428
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Typical Application (continued)
9.2.3 Application Curves
VCC = 5 V
54-Ω Termination
TA = 25°C
Figure 23. THVD1428 Waveforms at 20 Mbps
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100-
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
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11 Layout
11.1 Layout Guidelines
Additional external protection components generally are not needed when using THVD1428 transceivers.
1. Use VCC and ground planes to provide low-inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance. Apply 100-nF to 220-nF decoupling capacitors
as close as possible to the VCC pins of transceiver, UART and/or controller ICs on the board.
2. Use at least two vias for VCC and ground connections of decoupling capacitors to minimize effective via-
inductance.
3. Use 1-kΩ to 10-kΩ pull-up and pull-down resistors for enable lines to limit noise currents in theses lines
during transient events.
11.2 Layout Example
2
Via to GND
C
1
R
Via to VCC
3
R
R
MCU
3
R
THVD1428
2
Figure 24. Half-Duplex Layout Example
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12 Device and Documentation Support
12.1 Device Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1428DR
ACTIVE
SOIC
D
8
2500 RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
1428
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1428DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-May-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 29.0
THVD1428DR
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
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