THVD1505DR [TI]
总线极性借助 IEC-ESD 保护校正 RS-485 收发器 | D | 8 | -40 to 125;
| 型号： | THVD1505DR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 总线极性借助 IEC-ESD 保护校正 RS-485 收发器 | D | 8 | -40 to 125 PC 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总32页 (文件大小：1457K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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THVD1505
ZHCSK86 –SEPTEMBER 2019
具有 IEC-ESD 保护功能的 THVD1505 总线极性校正 RS-485 收发器
1 特性
2 应用
1
•
符合或超出 TIA/EIA-485A 标准和中国国家电网公
司 (SGCC) 第 11 部分串行通信协议 RS-485 标准
的要求
•
•
•
•
电表
HVAC 系统
逆变器
•
•
•
•
•
•
4.5V 至 5.5V 电源电压
半双工 RS-422/RS-485
可在 45ms 内校正总线极性
有无失效防护偏置电阻器均可工作
数据速率：高达 1Mbps
总线 I/O 保护：
视频监控
3 说明
THVD1505 是一款低功耗 RS-485 收发器，具有总线
极性自动校正和瞬态保护功能。热插拔时，此器件在总
线闲置的头 45ms 内检测并校正总线极性。这些总线
引脚可耐受静电放电 (ESD) 事件，具有符合人体放电
模型 (HBM)、IEC 61000-4-2 接触放电和空气间隙放
电规范的高级别保护功能。
–
–
–
–
±16kV HBM ESD
±8kV IEC 61000-4-2 接触放电
±8kV IEC 61000-4-2 空气间隙放电
±2kV IEC 61000-4-4 快速瞬变脉冲
此器件将一个差分驱动器和一个差分接收器组合在一
起，这两个器件由一个 5V 单电源供电。驱动器差分输
出和接收器差分输入在内部连接，构成一个适用于半双
工（两线制总线）通信的总线端口。该器件 具有 宽共
模电压范围，因此适用于长线缆上的 多点 。
•
•
开路、短路和空闲总线失效防护
用于噪声抑制的
较大接收器迟滞值：120mV
•
•
一条总线上多达 256 个节点（1/8 单位负载）
工作温度
范围：–40°C 至 125°C
THVD1505 采用 SOIC-8 封装，在自然通风环境下的
额定温度范围为 –40°C 至 125°C。
•
低功耗
器件信息(1)
–
–
待机电源电流：< 1µA
工作电源电流：< 1.1mA
器件型号
THVD1505
封装
SOIC (8)
封装尺寸（标称值）
•
适用于热插拔功能的无干扰上电/断电
4.90mm × 3.91mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
支持极性纠正 (POLCOR) 的典型网络应用
Cross-wire
fault
5V
M
R
RE
DE
D
R
R
R
1k
A
B
A
B
RE
DE
D
1k
D
D
A
B
A
B
Master
THVD1500
Slave
THVD1505
R
R
D
D
POLCOR
RE DE
POLCOR
RE DE
R
D
R
D
Slave
Slave
THVD1505
THVD1505
Copyright © 2018, Texas Instruments Incorporated
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSF68
THVD1505
ZHCSK86 –SEPTEMBER 2019
www.ti.com.cn
目录
8.1 Overview ................................................................ 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 11
8.4 Device Functional Modes........................................ 15
Application and Implementation ........................ 16
9.1 Application Information............................................ 16
9.2 Typical Application ................................................. 21
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 3
6.3 ESD Ratings [IEC] .................................................... 4
6.4 Recommended Operating Conditions....................... 4
6.5 Thermal Information.................................................. 4
6.6 Electrical Characteristics........................................... 5
6.7 Power Dissipation Characteristics ............................ 6
6.8 Switching Characteristics.......................................... 6
6.9 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
7.1 Driver......................................................................... 8
7.2 Receiver.................................................................... 9
Detailed Description ............................................ 11
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example ................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 器件支持................................................................ 25
12.2 接收文档更新通知 ................................................. 25
12.3 社区资源................................................................ 25
12.4 商标....................................................................... 25
12.5 静电放电警告......................................................... 25
12.6 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
9 月2019 年
*
初始发行版。
2
Copyright © 2019, Texas Instruments Incorporated
THVD1505
www.ti.com.cn
ZHCSK86 –SEPTEMBER 2019
5 Pin Configuration and Functions
D Package
8-Pin SOIC
Top View
R
RE
DE
D
1
2
3
4
8
7
6
5
V
B
A
CC
GND
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
Bus
input/output
A
6
Driver output or receiver input (complementary to B)
Driver output or receiver input (complementary to A)
Bus
input/output
B
7
D
DE
GND
R
4
3
5
1
2
8
Digital input Driver data input (internal 5-MΩ pull-up)
Digital input Driver enable, active high (internal 5-MΩ pull-down)
Ground
Device ground
Digital output Receive data output
RE
VCC
Digital input Receiver enable, active low (internal 5-MΩ pull-up)
Supply
4.5-V to 5.5-V supply
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.3
–18
MAX
7
UNIT
V
VCC
VL
Supply voltage
Input voltage at any logic pin (D, DE or RE)
5.7
18
V
VA, VB Voltage at A or B inputs, as differential or common-mode with respect to GND
V
IO
Receiver output current
Junction temperature
Storage temperature
–24
24
mA
°C
°C
TJ
170
150
TSTG
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditionsbeyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions forextended periods may affect device reliability.
6.2 ESD Ratings
VALUE
±16,000
±4,000
±1,500
±400
UNIT
Bus terminals and GND
All other pins
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
V(ESD)
Electrostatic discharge
V
Machine model (MM), per JEDEC JESD22-A115-A
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 2019, Texas Instruments Incorporated
3
THVD1505
ZHCSK86 –SEPTEMBER 2019
www.ti.com.cn
6.3 ESD Ratings [IEC]
VALUE
±8,000
±8,000
±2,000
UNIT
IEC 61000-4-2 ESD contact discharge, bus terminals and GND
IEC 61000-4-2 ESD air-gap discharge, bus terminals and GND
IEC 61000-4-4 EFT fast transient, bus terminals and GND
V(ESD)
Electrostatic discharge
V
6.4 Recommended Operating Conditions
MIN
4.5
–12
–7
NOM
MAX
UNIT
VCC
VID
VI
Supply voltage
5
5.5
12
V
V
V
V
V
Differential input voltage
Input voltage at any bus terminal(1)
12
VIH
VIL
High-level input voltage (driver, driver-enable, and receiver-enable inputs)
Low-level input voltage (driver, driver-enable, and receiver-enable inputs)
2
VCC
0.8
60
0
Driver
–60
–8
IO
Output current
Receiver
mA
8
RL
Differential load resistance
54
60
Ω
kbps
°C
1/tUI
TJ
Signaling rate
0.3
–40
–40
1000
150
Junction temperature
(2)
TA
Operating ambient temperature (see Thermal Information for additional information)
125
°C
(1) The algebraic convention in which the least positive (most negative) limit is designated as minimum is used in this datasheet.
(2) Operation is specified for internal (junction) temperatures upto 150°C. Self-heating due to internal power dissipation should be
considered for each application. Maximum junction temperature is internally limited by the thermal shutdown (TSD) circuit which disables
the device when the junction temperature reaches 170°C.
6.5 Thermal Information
THVD1505
THERMAL METRIC(1)
D (SOIC)
8 PINS
125.3
67.6
UNIT
RθJA
RθJC(top)
RθJB
ψJT
Junction-to-ambient thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
68.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20.4
ψJB
67.8
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
THVD1505
www.ti.com.cn
ZHCSK86 –SEPTEMBER 2019
6.6 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
Vtest from –7 to +12 V
See 图 7
See 图 8
1.5
1.5
2
2.5
2.5
3
Driver differential-output voltage
magnitude
│VOD
│
RL = 54 Ω (RS-485), CL = 50 pF
RL = 100 Ω (RS-422), CL = 50 pF
V
Change in magnitude of driver
differential-output voltage
Δ│VOD
VOC(SS)
ΔVOC
│
RL = 54 Ω, CL = 50 pF
See 图 8
–50
1
50
3
mV
V
Steady-state common-mode
output voltage
VCC / 2
Change in differential driver
common-mode output voltage
RL = 54 Ω, CL = 50 pF
See 图 8
–50
50
mV
mV
Peak-to-peak driver common-
mode output voltage
VOC(PP)
250
8
DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B
pin
│IOS
│
Driver short-circuit output current
Differential output capacitance
150
110
mA
pF
COD
Receiver
VI = 12 V
75
II
Bus input current (driver disabled) DE = 0 V, VCC = 0 V or 5.5 V
µA
VI = –7 V
–90
96
–70
VA = -7 V, VB = 12 V and VA = 12
RA, RB
VIT+
Bus input impedance
V, VB = -7 V
See 图 12
kΩ
mV
mV
mV
Positive-going receiver
differential-input voltage threshold
60
–60
120
100
Negative-going receiver
differential-input voltage threshold
VIT–
–100
Receiver differential-input voltage
threshold hysteresis (VIT+ – VIT–
(1)
VHYS
40
4
)
VOH
VOL
Receiver high-level output voltage IOH = –8 mA
Receiver low-level output voltage IOL = 8 mA
Receiver high-impedance output
VCC – 0.3
0.2
V
V
0.4
1
IOZ
VO = 0 V or VCC, RE = VCC
–1
–2
µA
current
Receiver output short-circuit
current
IOSR
RE = 0, DE = 0
See 图 13
95
2
mA
Logic
IIN
Input current (D, DE, RE)
Supply current (quiescent)
µA
µA
Supply
DE = VCC, RE = 0,
no load
Driver and receiver enabled
Driver enabled, receiver disabled
Driver disabled, receiver enabled
Driver and receiver disabled
820
520
520
0.03
1100
660
660
1
DE = VCC, RE =
VCC, no load
ICC
DE = 0, RE = 0, no
load
DE = 0, RE = VCC
no load
,
(1) Under any specific conditions, VIT+ is specified to be at least VHYS higher thanVIT–
.
Copyright © 2019, Texas Instruments Incorporated
5
THVD1505
ZHCSK86 –SEPTEMBER 2019
www.ti.com.cn
6.7 Power Dissipation Characteristics
PARAMETER
TEST CONDITIONS
RL = 300 Ω, CL = 50 pF
VALUE
120
UNIT
Unterminated
RS-422 load
RS-485 load
Power dissipation, driver and
receiver enabled, VCC = 5.5 V, TA
125°C, 50% duty cycle square-wave
signal at maximum signaling rate
=
PD
RL = 100 Ω, CL = 50 pF
RL = 54 Ω, CL = 50 pF
160
mW
200
6.8 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
tr, tf
Driver differential output rise and fall times
Driver propagation delay
See 图 9
100
115
90
300
350
40
ns
ns
ns
ns
ns
µs
tPHL, tPLH
tSK(P)
See 图 9
Driver pulse skew, |tPHL – tPLH
|
See 图 9
25
tPHZ, tPLZ
Driver disable time
See 图 10 and 图 11
See 图 10 and 图 11
See 图 10 and 图 11
70
160
400
3
Receiver enabled
Receiver disabled
220
1.5
tPHZ, tPLZ
Driver enable time
Receiver
tr, tf
Receiver output rise and fall times
Receiver propagation delay time
See 图 14
See 图 14
See 图 14
See 图 15
See 图 15
6
80
30
120
7
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
Receiver pulse skew, |tPHL – tPLH
|
2
tPHZ, tPLZ
Receiver disable time
15
30
tPZL(1)
tPZH(1)
tPZL(2)
tPZH(2)
,
Driver enabled
Driver disabled
Driver disabled
180
370
Receiver enable time
Bus fail-safe time
,
See 图 16
See 图 17
1
5
µs
tFS
25
35
45
ms
6
版权 © 2019, Texas Instruments Incorporated
THVD1505
www.ti.com.cn
ZHCSK86 –SEPTEMBER 2019
6.9 Typical Characteristics
4.8
4.5
4.2
3.9
3.6
3.3
3
4.2
3.6
3
VOL
VOH
2.4
1.8
1.2
0.6
0
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
-0.6
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Driver Output Current (mA)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75
Driver Output Current (mA)
D_00
D_00
图 2. Driver Differential Output Voltage vs Driver Output
图 1. Driver Output Voltage vs Driver Output Current
Current
130
65
60
55
50
45
40
35
30
25
20
15
10
5
Rise time
Fall time
128
126
124
122
120
118
116
114
0
0
0.5
1
1.5
2
2.5
3
3.5
4
Supply Voltage (V)
4.5
5
5.5
6
6.5
7
-40
-20
0
20
40
60
80
100 120 140
Temperature (0C)
D_00
D_00
图 3. Driver Output Current vs Supply Voltage
图 4. Driver Rise or Fall Time vs Temperature
91
45.35
45.3
45.25
45.2
45.15
45.1
45.05
45
90.5
90
89.5
89
88.5
88
87.5
87
TPLH
TPHL
44.95
44.9
86.5
86
-40
-20
0
20
40
60
80
100 120 140
0
100 200 300 400 500 600 700 800 900 1000
Signaling Rate (kbps)
Temperature (0C)
D_00
D_00
图 5. Driver Propagation Delay vs Temperature
图 6. Supply Current vs Signaling Rate
版权 © 2019, Texas Instruments Incorporated
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THVD1505
ZHCSK86 –SEPTEMBER 2019
www.ti.com.cn
7 Parameter Measurement Information
7.1 Driver
Vcc
DE
375 Ω
60 Ω
A
B
D
0V or 5 V
VOD
Vtest
375 Ω
图 7. Measurement of Driver Differential-Output Voltage With Common-Mode Load
A
VA
A
B
RL/2
RL/2
B
D
VB
ûVOC(SS)
0V or 5 V
VOD
VOC(PP)
VOC
CL
VOC
图 8. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
5V
Vcc
50%
VI
tPLH
0V
DE
A
B
tPHL
D
CL=
50 pF
54 Ω
≈ 2V
VOD
90%
50%
10%
Input
Generator
50Ω
VI
VOD
≈ -2V
tr
tf
图 9. Measurement of Driver Differential-Output Rise and Fall Times and Propagation Delays
A
B
5V
S1
VO
D
50%
VI
0V
RL=
110 Ω
DE
50Ω
tPZH
CL=
50 pF
VOH
Input
Generator
90%
VI
50%
VO
≈ 0V
tPHZ
图 10. Measurement of Driver Enable and Disable Times With Active-High Output and Pull-Down Load
5V
5V
50%
RL= 110 Ω
VI
tPZL
VO
A
B
0V
S1
D
VO
tPLZ
≈ 5V
DE
50Ω
CL=
50 pF
50%
Input
Generator
10%
VI
VOL
图 11. Measurement of Driver Enable and Disable Times With Active-Low Output and Pull-up Load
8
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THVD1505
www.ti.com.cn
ZHCSK86 –SEPTEMBER 2019
7.2 Receiver
VCC
Source meter to apply
VA/VB and measure IA/IB
=
VX
RE
DE
VCC
A
VA
IA
DI
R
B
VB
IB
GND
图 12. Measurement of Bus Impedance
VCC
RE
DE
VCC
A
DI
R
B
A
GND
图 13. Measurement of Receiver Output Short Circuit Current
5V
50%
VI
tPLH
0V
A
R
VO
tPHL
Input
Generator
50Ω
VI
1.5V
0V
VOH
90%
50%
10%
B
CL= 15 pF
RE
VOD
VOL
tr
tf
图 14. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
5V
Vcc
DE
Vcc
VI
tPZH(1)
VO
50%
0V
A
B
1 kΩ
tPHZ
D
VO
D at 5V
S1 to GND
R
S1
0V or 5 V
VOH
≈ 0V
VCC
VOL
90%
50%
CL= 15 pF
RE
tPZL(1)
tPLZ
D at 0V
S1 to VCC
Input
Generator
50Ω
VI
VO
50%
10%
图 15. Measurement of Receiver Enable and Disable Times With Driver Enabled
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THVD1505
ZHCSK86 –SEPTEMBER 2019
www.ti.com.cn
Receiver (接下页)
5V
Vcc
VI
tPZH(2)
VO
50%
0V
A
1 kΩ
0V or 1.5 V
R
VO
S1
VOH
≈ 0V
VCC
VOL
A at 1.5V
B at 0V
S1 to GND
1.5 V or 0 V
B
50%
CL= 15 pF
RE
tPZL(2)
Input
Generator
A at 0V
B at 1.5V
S1 to VCC
50Ω
VI
VO
50%
图 16. Measurement of Receiver Enable Times With Driver Disabled
2.8V
VI
2.2V
A
R
VO
10 kΩ
Input
Generator
tFS
50Ω
VI
2.5V
0V
B
VCC
RE
(DE = Low)
VO
50%
图 17. Measurement of Receiver Polarity-Correction Time With Driver Disabled
10
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THVD1505
www.ti.com.cn
ZHCSK86 –SEPTEMBER 2019
8 Detailed Description
8.1 Overview
The THVD1505 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 1 Mbps
over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high level of
internal transient protection, making it able to withstand ESD strikes up to ±8 kV (per IEC 61000-4-2) and EFT
transients up to ±2 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of THVD1500 and/or
THVD1505 may share a common RS-485 bus due to the devices' low bus input currents. THVD1505 features
automatic polarity correction, which detects bus mis-wiring and swaps A and B.
8.2 Functional Block Diagram
R
RE
DE
D
Vcc
B
A
GND
Copyright © 2018, Texas Instruments Incorporated
8.3 Feature Description
8.3.1 Bus Polarity Correction
THVD1505 automatically corrects a wrong bus-signal polarity caused by a mis-wire fault. In order to detect the
bus polarity, the following conditions must be met.
•
•
•
A slave node must enable the receiver (RE = low). Driver can be in either enabled or disabled state
A and B signals should be static for longer than fail-safe time (tFS
The absolute value of the differential voltage at the receiver input should be greater than the receiver
thresholds (|VIT+| or |VIT-|)
)
The receiver input voltage can be defined either by using passive fail-safe resistors or by the master node
actively driving the bus.
8.3.1.1 Passive Polarity Definition Using Fail-Safe Biasing Network
图 18 shows a simple point-to-point data link between a master node and a slave node with mis-wire fault.
VS-Master
VS-Master
VS-Slave
VS-Slave
Master
node
Slave
node
VSM
Vdd
Vcc
Vcc
Vdd
R
R
RxD
RxD
RFS
A
B
A
B
MCU
MCU
RE
DE
D
RE
DE
D
RT
(opt.)
RT
(opt.)
DIR
TxD
DIR
TxD
RFS
DGND
GND
GND
DGND
图 18. Passive Polarity Definition
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Feature Description (接下页)
During passive polarity definition, an external fail-safe resistor network (RFS) must be used to ensure fail-safe
operation during an idle bus state. When the bus is not actively driven, the differential receiver inputs could float
allowing the receiver output to assume a random output. A proper fail-safe network forces the receiver inputs to
exceed the VIT threshold, thus forcing the THVD1505 receiver output into the high state.
图 19 shows the timing diagram for passive polarity definition.
Prior to initiating data transmission the master transceiver must idle for a time span that exceeds the maximum
fail-safe time, tFS, of a slave transceiver. This idle time is accomplished by driving the direction control line (the
output of the MCU in 图 19 that is driving DE and RE pins), DIR, low. After a time, t > tFS, the master begins
transmitting data.
Because of the indicated mis-wire fault between master and slave, the slave node receives bus signals with
reversed polarity. Assuming the slave node has just been connected to the bus, the direction-control pin is
pulled-down during power-up and then is actively driven low by the slave MCU. The polarity correction begins as
soon as the slave supply is established and ends after tFS
.
Low due to pull-down
DIRm
Dm
or actively driven
high Z
Master
signals
VAm
0V
VFS
-Vod
+Vid
+Vod
-Vid
VBm
VBs
0V
VFS
VAs
VSs
Slave
signals
Low due to pull-down and then actively driven
DIRs
Rs
tFS
Uncorrected R output:
R is in phase with
wrong V polarity
Corrected R output:
R is reversed to
wrong V polarity
ID
ID
图 19. Polarity Correction Timing With Passive Polarity Definition
Initially, the slave receiver assumes that the correct bus polarity is applied to the inputs and performs no polarity
reversal. Because of the reversed polarity of the bus-failsafe voltage, the output of the slave receiver, RS, turns
low. After tFS has passed and the receiver has detected the wrong bus polarity, the internal POLCOR logic
reverses the input signal and RS turns high.
At this point, all incoming bus data with reversed polarity are polarity corrected within the transceiver. Because
polarity correction is also applied to the transmit path, the data sent by the slave MCU are reversed by the
POLCOR logic and then fed into the driver.
12
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Feature Description (接下页)
The reversed data from the slave MCU are reversed again by the mis-wire fault in the bus, and the correct bus
polarity is reestablished at the master end.
THVD1505 retains the state of the polarity logic as long as VCC is present to the device. However, the device
POLCOR logic powers up in the default no polarity reversal mode at each device power up. POLCOR logic
remains active as long as VCC is applied to the device.
注
Data string durations of consecutive 0s or 1s exceeding the minimum tFS can accidently
trigger a wrong polarity correction and must be avoided.
8.3.1.2 Active Polarity Definition by the Master Node
THVD1505 polarity correction can also work without a fail-safe resistor network. See 图 20.
VS-Master
VS-Master
VS-Slave
VS-Slave
Master
node
Slave
node
Vdd
Vcc
Vcc
Vdd
R
R
RxD
RxD
A
B
A
B
MCU
RE
DE
D
RE
DE
D
MCU
DIR
TxD
RT
RT
DIR
TxD
DGND
GND
GND
DGND
图 20. Active Polarity Definition
In this scenario, the master node drives the bus for longer than tFS. After a time, t > tFS, the master begins
transmitting data. 图 21 shows the timing diagram for active polarity definition. DIR pin refers to the output of the
MCU that is driving DE and RE pins in 图 21.
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Feature Description (接下页)
Driven high
Driven high
DIRm
Dm
Master
signals
VAm
0V
-VOD
+VOD
VFS
VBm
VBs
0V
+VID
-VID
VFS
VAs
VSs
Slave
signals
Low due to pull-down and then actively driven
DIRs
Rs
tFS
Uncorrected R output :
R is in phase with
wrong V polarity
Corrected R output :
R is reversed to
wrong V polarity
ID
ID
图 21. Polarity Correction Timing With Active Polarity Definition
POLCOR logic behavior with active polarity definition is identical to the POLCOR logic behavior with passive
polarity definition.
14
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8.4 Device Functional Modes
表 1. Driver Pin Functions
INPUT
ENABLE
DE
OUTPUTS
DESCRIPTION
D
A
B
NORMAL MODE
H
H
H
L
L
H
Z
Z
L
Actively drives bus high
Actively drives bus low
Driver disabled
L
X
H
L
Z
Z
H
X
OPEN
H
Driver disabled by default
Actively drives bus high
OPEN
POLARITY-CORRECTING MODE
H
H
L
H
Z
Z
L
H
L
Actively drives bus low
Actively drives bus high
Driver disabled
L
X
H
L
Z
Z
H
X
OPEN
H
Driver disabled by default
Actively drives bus low
OPEN
表 2. Receiver Pin Functions
DIFFERENTIAL
INPUT
ENABLE
OUTPUT
DESCRIPTION
VID = VA – VB
RE
DE
R
VID > VIT+
L
X
H
Receive valid bus high
L during tFS
H after tFS
Receive valid bus low if lasting for less than tFS, polarity correcting if lasting for
more than tFS
VIT- > VID
L
X
X
X
H
X
X
Z
Z
Receiver disabled
Receiver disabled
OPEN
Open, short or VIT+
VID > VIT-
>
L
X
H after tFS
Receiver fail-safe high
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
9.1.1 Device Configuration
The THVD1505 is a half-duplex RS-485 transceiver operating from a single 5-V ±10% supply. The driver and
receiver enable pins allow for the configuration of different operating modes.
R
R
R
R
Vcc
B
R
Vcc
B
R
Vcc
B
RE
RE
RE
DE
D
DE
D
DE
D
A
A
A
D
GND
D
GND
D
GND
c) Receiver always on
b) Combined enable signals for
use as directional control pin
a) Independent driver and
receiver enable signals
Copyright © 2018, Texas Instruments Incorporated
图 22. Transceiver Configurations
Using independent enable lines provides the most flexible control as the lines allow for the driver and the
receiver to be turned on and turned off individually. While this configuration requires two control lines, it allows for
selective listening to the bus traffic, whether the driver is transmitting data or not. Only this configuration allows
the THVD1505 to enter low-power standby mode because it allows both the driver and receiver to be disabled
simultaneously.
Combining the enable signals simplifies the interface to the controller by forming a single direction-control signal.
Thus, when the direction-control line is high, the transceiver is configured as a driver, while for a low the device
operates as a receiver.
Tying the receiver enable to ground and controlling only the driver-enable input also uses only one control line. In
this configuration, a node not only receives the data on the bus sent by other nodes but also receives the data
sent on the bus, enabling the node to verify the correct data has been transmitted.
9.1.2 Bus Design
An RS-485 bus consists of multiple transceivers connected in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, allows for relatively high data rates over
long cable length.
Common cables used are unshielded twisted pair (UTP), such as low-cost CAT-5 cable with Z0 = 100 Ω, and RS-
485 cable with Z0 = 120 Ω. Typical cable sizes are AWG 22 and AWG 24.
The maximum bus length is typically given as 4000 ft or 1200 m, and represents the length of an AWG 24 cable
whose cable resistance approaches the value of the termination resistance, thus reducing the bus signal by half
or 6 dB. Actual maximum usable cable length depends on the signaling rate, cable characteristics, and
environmental conditions.
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Application Information (接下页)
9.1.3 Fail-Safe Biasing for Passive Polarity Definition
External biasing resistor network of RFS along with RT define the VFS during the polarity correction time, tFS. See
Passive Polarity Definition Using Fail-Safe Biasing Network for more details.
RFS resistors should be selected such that VFS > |VIT| = 100 mV. The equation below can be used to calculate
RFS. Note that too low of a RFS value increases the bus loading that reduces the number of nodes on the RS-485
bus.
RFS < 0.5 x [(RT x VCC-min) / 0.1 - RT]
(1)
9.1.4 Cable Length Versus Data Rate
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
shorter the cable length; and conversely, the lower the data rate the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, applications such as e-metering often operate at rates of
up to 250 kbps even at distances of 4000 ft and longer. Longer distances are possible by allowing for small
signal jitter of up to 5 or 10%.
10000
5,10,20 % Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100k
1M
10M
100M
DATA RATE - bps
图 23. Cable Length vs Data Rate Characteristic
9.1.5 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. The reason for the short distance is because a stub presents a non-
terminated piece of bus line which can introduce reflections if the distance is too long. As a general guideline, the
electrical length or round-trip delay of a stub should be less than one-tenth of the rise time of the driver, thus
leading to a maximum physical stub length of as shown in 公式 2.
LS ≤ 0.1 × tr × v × c
where
•
•
•
tr is the 10/90 rise time of the driver
c is the speed of light (3 × 108 m/s or 9.8 × 108 ft/s)
v is the signal velocity of the cable (v = 78%) or trace (v = 45%) as a factor of c
(2)
Based on 公式 2, with a minimum rise time of 400 ns, 公式 3 shows the maximum cable-stub length of the
THVD1505.
LS ≤ 0.1 × 400 × 10-9 × 3 108 × 0.78 = 9.4 m (or 30.6 ft)
(3)
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Application Information (接下页)
L
S
A
B
R
R
D
D
RE DE
图 24. Stub Length
9.1.6 Transient Protection
The bus terminals of the THVD1505 transceiver family possess on-chip ESD protection against ±16 kV HBM, ±8
kV IEC 61000-4-2 contact discharge and ±2 kV IEC 61000-4-4 EFT. The International Electrotechnical
Commission (IEC) ESD test is far more severe than the HBM ESD test. The 50% higher charge capacitance, CS,
and 78% lower discharge resistance, RD of the IEC model produce significantly higher discharge currents than
the HBM model.
R
R
D
C
40
35
30
25
20
15
10
5
50M
(1M)
330ꢀ
10kV IEC
(1.5k)
High-Voltage
Pulse
Generator
Device
Under
Test
150pF
C
S
(100pF)
10kV HBM
0
0
50
100
150
200
250
300
Time - ns
Copyright © 2016, Texas Instruments Incorporated
图 25. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD and EFT protection significantly increases the robustness of equipment.
Common discharge events occur because of human contact with connectors and cables. EFTs are generally
caused by relay-contact bounce or the interruption of inductive loads.
Surge transients often result from lightning strikes (direct strike or an indirect strike which induce voltages and
currents), or the switching of power systems, including load changes and short circuit switching. These transients
are often encountered in industrial environments, such as factory automation and power-grid systems.
图 26 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left hand diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which dwarf the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients are
representative of events that may occur in factory environments in industrial and process automation. The right
hand diagram shows the pulse-power of a 6-kV surge transient, relative to the same 0.5-kV surge transient. 6-kV
surge transients are most likely to occur in power generation and power-grid systems.
Designers may choose to implement protection against longer duration surge transients. 图 28 suggests two
circuit designs providing protection against short and long duration surge transients. 表 3 lists the bill of materials
for the external protection devices.
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ZHCSK86 –SEPTEMBER 2019
Application Information (接下页)
注
The unit of the pulse-power changes from kW to MW, thus making the power of the 500-V
surge transient almost dropping off the scale.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6kV Surge
22
20
18
16
14
12
10
8
0.5kV Surge
4kV EFT
6
4
2
0.5kV Surge
10kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time - μs
Time - μs
图 26. Power Comparison of ESD, EFT, and Surge Transients
In the case of surge transients, high-energy content is signified by long pulse duration and slow decaying pulse
power.
The electrical energy of a transient that is dumped into the internal protection cells of the transceiver is converted
into thermal energy. This thermal energy heats the protection cells and literally destroys them, thus destroying
the transceiver. 图 27 shows the large differences in transient energies for single ESD, EFT, and surge transients
as well as for an EFT pulse train, commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8
10
15
Peak Pulse Voltage - kV
图 27. Comparison of Transient Energies
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Application Information (接下页)
表 3. List of Components
DEVICE
FUNCTION
ORDER NUMBER(1)
MANUFACTURER
XCVR
5-V, 1-Mbps RS-485 Transceiver
THVD1505DR
TI
R1, R2
10-Ω, Pulse-Proof Thick-Film Resistor
CRCW0603010RJNEAHP
CDSOT23-SM712
Vishay
Bidirectional 400-W Transient Voltage
Suppressor
TVS
Bourns
Bourns
Bourns
TBU1, TBU2
MOV1, MOV2
Bidirectional 200mA Transient Blocking Unit
TBU-CA-065-200-WH
MOV-10D201K
200-mA Transient Blocking Unit 200-V, Metal-
Oxide Varistor
(1) See Third Party Disclaimer
Vcc
Vcc
Vcc
0.1ꢀF
Vcc
10k
10k
0.1ꢀF
TBU1
MOV1
R1
R1
1
8
7
6
5
1
2
3
4
8
7
6
5
RxD
MCU
R
Vcc
B
RxD
MCU
R
Vcc
B
TVS
TVS
2
3
4
RE
DE
D
RE
DE
D
XCVR
XCVR
DIR
TxD
A
DIR
TxD
A
MOV2
TBU2
GND
GND
R2
R2
10k
10k
Copyright © 2016, Texas Instruments Incorporated
图 28. Transient Protections Against Surge Transients
The left circuit shown in 图 28 provides surge protection of 1-kV transients, while the right protection circuits can
withstand surge transients of 5 kV.
20
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9.2 Typical Application
Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their
disruptive impact on signal integrity. An isolated bus node typically includes a micro controller that connects to
the bus transceiver through a multi-channel, digital isolator (图 29).
THVD1505
A. See 表 3.
图 29. Isolated Bus Node With Transient Protection
9.2.1 Design Requirements
Example Application: Isolated Bus Node with Transient Protection
•
•
•
•
RS-485-compliant bus interface.
Galvanic isolation of both signal and power supply lines.
Able to withstand surge transients up to 1 kV (per IEC 61000-4-5).
Full control of data flow on bus in order to prevent contention (for half-duplex communication).
9.2.2 Detailed Design Procedure
Power isolation is accomplished using the push-pull transformer driver SN6501, a low-cost LDO and TLV70733.
Signal isolation uses the quadruple digital isolator ISO7741. Notice that both enable inputs, EN1 and EN2, are
pulled-up via 4.7-kΩ resistors to limit input currents during transient events.
While the transient protection is similar to the one in 图 28 (left circuit), an additional high-voltage capacitor
diverts transient energy from the floating RS-485 common further towards protective earth (PE) ground. This
diversion is necessary as noise transients on the bus are usually referred to Earth potential.
RVH refers to a high-voltage resistor, and in some applications even a varistor. This resistance is applied to
prevent charging of the floating ground to dangerous potentials during normal operation.
Occasionally varistors are used instead of resistors in order to rapidly discharge CHV, if expected that fast
transients might charge CHV to high-potentials.
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Typical Application (接下页)
Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire
connecting this island to PE ground at the entrance of the power supply unit (PSU).
In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically
the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are
connecting to the chassis at the other end.
9.2.3 Application Curve
图 30. Waveforms at 1 Mbps Operation, PRBS7 Data Pattern
图 31. Waveforms at 1 Mbps Operation, Clock Data Pattern
22
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THVD1505
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ZHCSK86 –SEPTEMBER 2019
10 Power Supply Recommendations
To ensure reliable operation at all data rates and supply voltages, each supply should be decoupled with a 100-
nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage ripple
present on the outputs of switched-mode power supplies and also helps to compensate for the resistance and
inductance of the PCB power planes.
版权 © 2019, Texas Instruments Incorporated
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11 Layout
11.1 Layout Guidelines
11.1.1 Design and Layout Considerations For Transient Protection
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use Vcc and ground planes to provide low inductance. Note that high frequency currents follow the path of
least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transients currents to
divert from the signal path to reach the protection device.
4. Apply 100 to 220-nF decoupling capacitors as close as possible to the VCC pins of transceiver and UART or
controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1 to 10-k pull-up or pull-down resistors for enable lines to limit noise currents in theses lines during
transient events.
7. Insert pulse-proof resistors into the A and B bus lines if the TVS clamping voltage is higher than the specified
maximum voltage of the transceiver bus terminals. These resistors limit the residual clamping current into the
transceiver and prevent it from latching up.
–
While pure TVS protection is sufficient for surge transients up to 1 kV, higher transients require metal-
oxide varistors (MOVs) which reduce the transients to a few-hundred volts of clamping voltage, and
transient blocking units (TBUs) that limit transient current to about 200 mA.
11.2 Layout Example
5
Via to ground
Via to VCC
C
4
R
R
R
6
6
1
R
R
7
R
MCU
5
TVS
THVD1505
5
图 32. THVD1505 Layout Example
24
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THVD1505
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12 器件和文档支持
12.1 器件支持
12.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此类
产品或服务单独或与任何 TI 产品或服务一起的表示或认可。
12.2 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2019, Texas Instruments Incorporated
25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
THVD1505DR
ACTIVE
SOIC
D
8
2500 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1505
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD1505DR
SOIC
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
THVD1505DR
D
8
2500
Pack Materials-Page 2
PACKAGE OUTLINE
D0008A
SOIC - 1.75 mm max height
SCALE 2.800
SMALL OUTLINE INTEGRATED CIRCUIT
C
SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A
PIN 1 ID AREA
6X .050
[1.27]
8
1
2X
.189-.197
[4.81-5.00]
NOTE 3
.150
[3.81]
4X (0 -15 )
4
5
8X .012-.020
[0.31-0.51]
B
.150-.157
[3.81-3.98]
NOTE 4
.069 MAX
[1.75]
.010 [0.25]
C A B
.005-.010 TYP
[0.13-0.25]
4X (0 -15 )
SEE DETAIL A
.010
[0.25]
.004-.010
[0.11-0.25]
0 - 8
.016-.050
[0.41-1.27]
DETAIL A
TYPICAL
(.041)
[1.04]
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
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EXAMPLE BOARD LAYOUT
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
SEE
DETAILS
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED
METAL
EXPOSED
METAL
.0028 MAX
[0.07]
.0028 MIN
[0.07]
ALL AROUND
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
D0008A
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
8X (.061 )
[1.55]
SYMM
1
8
8X (.024)
[0.6]
SYMM
(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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