THVD2450VDRCR [TI]
70V 总线故障保护、灵活 IO、3V 至 5.5V、50Mbps 半双工 RS-485 收发器 | DRC | 10 | -40 to 125;
| 型号： | THVD2450VDRCR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 70V 总线故障保护、灵活 IO、3V 至 5.5V、50Mbps 半双工 RS-485 收发器 | DRC | 10 | -40 to 125 |
| 文件： | 总39页 (文件大小：2460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
THVD2410V, THVD2450V
ZHCSOO2A –DECEMBER 2022 –REVISED FEBRUARY 2023
THVD24xxV 具有灵活的I/O 电源和IEC ESD 保护功能的±70V 故障保护、3V 至
5.5V RS-485 收发器
1 特性
3 说明
• 符合或超出TIA/EIA-485A 和TIA/EIA-422B 标准的
要求
• 3V 至5.5V RS-485 电源电压
• 差分输出超过2.1V，在5V 电源下
与PROFIBUS 兼容
• 用于逻辑信号接口的1.65V 至5.5V 电源
• SLR 引脚可选数据速率：
THVD24xxV 是具有 ±70V 故障保护功能的半双工和全
双工 RS-422/RS-485 收发器，对逻辑信号接口使用
1.65V 至5.5V 电源，对总线侧使用 3V 至5.5V 电源。
这些器件具有压摆率选择功能，因此可在两种最大速度
（根据SLR 引脚设置）下使用。
这些器件具有集成式 IEC ESD 保护，无需外部系统级
保护组件。在更长的电缆敷设长度和/或存在大接地环
路电压的情况下，扩展的 ±25V 输入共模范围可实现可
靠的数据通信。增强型 250mV 接收器迟滞可提供高噪
声抑制。此外，当输入同时开路或短路时，接收器失效
防护功能可确保逻辑高电平。
– THVD2410V、THVD2412V：250kbps 和
1Mbps
– THVD2450V、THVD2452V：20Mbps 和
50Mbps
• 总线I/O 保护
封装信息
– ±70V 直流总线故障
– ±16kV HBM ESD
– 半双工器件：±15kV IEC 61000-4-2 接触放电和
空气间隙放电
– 全双工器件：±8kV IEC 61000-4-2 接触放电和
空气间隙放电
封装(1)
VSON (10)
SOIC (14)
封装尺寸（标称值）
器件型号
THVD2450V
3.00mm × 3.00mm
THVD2410V
THVD2412V(2)
THVD2452V(2)
8.65mm × 3.91mm
– ±4kV IEC 61000-4-4 快速瞬变脉冲
• 提供两种速度等级的半双工和全双工器件
• 更宽泛的工作环境温度范围： -40°C 至125°C
• 扩展的运行共模电压范围：±25V
• 增强型接收器迟滞，可获得抗噪能力
• 低功耗
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
(2) 产品预发布
表3-1. 器件信息
器件型号
THVD2410V
双工
最大数据速率
半双工
全双工
半双工
全双工
SLR = 高电平，250kbps
SLR = 低电平，1Mbps
– 低待机电源电流：< 5µA
THVD2412V
THVD2450V
THVD2452V
– 运行期间静态电流：< 5.3mA
• 适用于热插拔功能的无干扰上电/断电
• 开路、短路和空闲总线失效防护
• 热关断
SLR = 高电平，20Mbps
SLR = 低电平，50Mbps
VIO SLR
VCC
• 1/8 单位负载（多达256 个总线节点）（在-7V 至
12V 的共模范围内）
• 小型3mm x 3mm VSON 封装（可节省布板空间）
或14-SOIC 封装（可方便插接）
A
R
B
Internally connected
only for Half duplex
devices
RE
I/O
and
Control
2 应用
DE
D
• 电机驱动器
• 工厂自动化和控制
• HVAC 系统
• 楼宇自动化
• 电网基础设施
• 电表
Z
Y
Only for full
duplex devices
简化版原理图
• 过程分析
• 视频监控
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFO2
THVD2410V, THVD2450V
ZHCSOO2A –DECEMBER 2022 –REVISED FEBRUARY 2023
www.ti.com.cn
Table of Contents
8 Detailed Description......................................................19
8.1 Overview...................................................................19
8.2 Functional Block Diagrams....................................... 19
8.3 Feature Description...................................................19
8.4 Device Functional Modes..........................................20
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 Power Supply Recommendations.............................28
9.4 Layout....................................................................... 28
10 Device and Documentation Support..........................29
10.1 Device Support....................................................... 29
10.2 接收文档更新通知................................................... 29
10.3 支持资源..................................................................29
10.4 商标.........................................................................29
10.5 静电放电警告.......................................................... 29
10.6 术语表..................................................................... 29
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings .............................................................. 5
6.3 ESD Ratings [IEC]...................................................... 5
6.4 Recommended Operating Conditions.........................6
6.5 Thermal Information....................................................6
6.6 Power Dissipation....................................................... 7
6.7 Electrical Characteristics.............................................8
6.8 Switching Characteristics_250 kbps......................... 10
6.9 Switching Characteristics_1 Mbps............................ 11
6.10 Switching Characteristics_20 Mbps........................12
6.11 Switching Characteristics_50 Mbps........................ 13
6.12 Typical Characteristics............................................14
7 Parameter Measurement Information..........................17
Information.................................................................... 29
4 Revision History
Changes from Revision * (December 2022) to Revision A (February 2023)
Page
• 删除了封装信息表中THVD2410V 的“产品预发布”说明................................................................................ 1
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5 Pin Configuration and Functions
V
ꢀ
1
2
3
4
5
10
9
V
B
A
ꢀ
IO
CC
R
Thermal
Pad
DE
RE
D
8
7
SLR
GND
6
Not to scale
图5-1. THVD2410V, THVD2450V
10-Pin DRC Package (VSON)
Top View
表5-1. Pin Functions
NO.
1
NAME
VIO
R
TYPE
DESCRIPTION
Logic Supply Supply for logic I/O signals (R, RE, D, DE, and SLR)
Digital Output Receive data output
2
3
DE
RE
D
Digital Input Driver enable input; integrated pull-down
Digital Input Receiver enable input; integrated pull-up
Digital Input Transmission data input; integrated pull-up
4
5
Reference
6
7
GND
SLR
Local device ground
Potential
Slew rate select. For THVD2410V: Low = 1 Mbps, High = 250 kbps. Defaults to 1 Mbps if
Digital Input SLR is left floating. For THVD2450V: Low = 50 Mbps, High = 20 Mbps. Defaults to 50 Mbps
if left floating.
8
A
Bus I/O
Bus I/O
RS 485 bus I/O, A
RS 485 bus I/O, B
9
B
10
VCC
Bus Supply Bus supply
-- Connect to GND for optimal thermal performance
Thermal Pad
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V
ꢀ
1
2
3
4
5
6
7
14
13
12
11
10
9
V
ꢀ
IO
CC
R
NC
A
RE
DE
B
D
Z
GND
NC
Y
8
SLR
Not to scale
图5-2. THVD2412V, THVD2452V
14-Pin SOIC Package (D)
Top View
表5-2. Pin functions
NO.
1
NAME
VIO
R
TYPE
DESCRIPTION
Logic supply 1.65 V to 5.5 V supply for logic I/O signals (R, RE, D, DE and SLR)
Digital output Receive data output
2
3
RE
Digital input
Digital input
Digital input
Receiver enable input; integrated pull-up
Driver enable input; integrated pull-down
Transmission data input; integrated pull-up
Local device ground
4
DE
5
D
6
GND
Reference
potential
7
8
NC
No connect
Digital input
Not connected internally
SLR
Slew rate select. For THVD2412V: Low = 1 Mbps, High = 250 kbps. Defaults to 1 Mbps if
SLR is left floating. For THVD2452V: Low = 50 Mbps, High = 20 Mbps. Defaults to 50 Mbps
if left floating.
9
Y
Bus output
Bus output
Bus input
RS 485 driver non-inverting output
RS 485 driver inverting output
RS 485 receiver inverting input
RS 485 receiver non-inverting input
Not connected internally
10
11
12
13
14
Z
B
A
Bus input
NC
VCC
No connect
Bus supply
3 V to 5.5 V bus supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)(2)
MIN
–0.5
–0.5
MAX
VCC + 0.2
6.5
UNIT
V
Logic supply voltage
Bus supply voltage
VIO
VCC
V
Range at any bus pin as differential or common-mode
with respect to GND
Bus voltage
70
V
–70
Input voltage
Range at any logic pin (D, DE, SLR or RE)
VIO + 0.2
24
V
–0.3
–24
–65
Receiver output current
Storage temperature
IO
mA
°C
Tstg
170
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.
6.2 ESD Ratings
VALUE
UNIT
Bus terminals and GND
±16,000
V
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
All pins except bus terminals
and GND
V(ESD)
Electrostatic discharge
±4,000
±1,500
V
V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings [IEC]
VALUE
UNIT
Electrostatic discharge, Half
duplex devices THVD2410V/
2450V (1)
Contact discharge, per IEC 61000-4-2
Air-gap discharge, per IEC 61000-4-2
Contact discharge, per IEC 61000-4-2
Air-gap discharge, per IEC 61000-4-2
Per IEC 61000-4-4
Bus terminals and GND
Bus terminals and GND
Bus terminals and GND
Bus terminals and GND
Bus terminals
±15,000
±15,000
±8,000
±8,000
±4,000
V(ESD)
V
Electrostatic discharge, Full
duplex devices THVD2412V/
2452V
V(ESD)
V(EFT)
V
V
Electrical fast transient
(1) For optimised IEC ESD performance, it is recommended to have series resistor (≥50 Ω) on all logic inputs to minimize transient
currents going into or out of the logic pins.
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6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
3
NOM
MAX
UNIT
VCC
VIO
VI
Supply voltage
5.5
VCC
25
V
V
V
I/O supply voltage
1.65
–25
Input voltage at any bus terminal (separately or common mode)(1)
High-level input voltage (driver, driver enable, receiver enable and slew rate select
inputs)
VIH
VIL
0.7*VIO
0
VIO
V
V
Low-level input voltage (driver, driver enable, receiver enable and slew rate select
inputs)
0.3*VIO
VID
IO
Differential input voltage bus pins
Output current, driver
25
60
4
V
–25
–60
–4
–8
54
mA
mA
mA
IOR
IOR
RL
Output current, receiver
Output current, receiver
Differential load resistance
VIO = 1.8 V or 2.5 V
VIO = 3.3 V or 5 V
8
60
Ω
THVD2410V, THVD2412V with SLR = VIO
250
1
kbps
THVD2410V, THVD2412V with SLR = GND
or floating
Mbps
Mbps
Mbps
1/tUI
Signaling rate
THVD2450V, THVD2452V with SLR = VIO
20
50
THVD2450V, THVD2452V with SLR = GND
or floating
TA
TJ
Operating ambient temperature
Junction temperature
-40
-40
125
150
°C
°C
(1) The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet.
6.5 Thermal Information
THVD2410V
THVD2450V
THVD2412V
THVD2452V
THERMAL METRIC(1)
DRC
D
UNIT
(VSON)
(SOIC)
10 PINS
46.7
47.7
19.1
0.7
14 PINS
87.5
41.8
43.7
8.1
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
19.1
4.6
43.3
N/A
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.6 Power Dissipation
PARAMETER
TEST CONDITIONS
THVD2410V,
VALUE
UNIT
250 kbps
1Mbps
160
THVD2412V
THVD2410V,
THVD2412V
250
310
630
170
250
290
570
220
280
325
560
Unterminated
mW
RL = 300 Ω, CL = 50 pF (driver)
THVD2450V,
THVD2452V
20Mbps
50 Mbps
250 kbps
1Mbps
THVD2450V,
THVD2452V
THVD2410V,
THVD2412V
Driver and receiver enabled, loopback for
full duplex devices (A connected to Y, B
connected to Z)
VCC = 5.5 V, TA = 125 °C,
square wave at 50% duty cycle
THVD2410V,
THVD2412V
RS-422 load
PD
mW
RL = 100 Ω, CL = 50 pF (driver)
THVD2450V,
THVD2452V
20Mbps
50 Mbps
250 kbps
1Mbps
THVD2450V,
THVD2452V
THVD2410V,
THVD2412V
THVD2410V,
THVD2412V
RS-485 load
mW
RL = 54 Ω, CL = 50 pF (driver)
THVD2450V,
THVD2452V
20Mbps
50 Mbps
THVD2450V,
THVD2452V
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6.7 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
= 5 V, VIO = 3.3 V , unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
Driver
1.5
2.1
2
3.3
3.3
4
V
V
V
V
RL = 60 Ω, –25 V ≤Vtest ≤25 V (See 图7-1 )
RL = 60 Ω, –25 V ≤Vtest ≤25 V, 4.5 V ≤VCC ≤5.5 V (See 图7-1 )
RL = 100 Ω(See 图7-2 )
Driver differential output
voltage magnitude
|VOD
|
1.5
3.5
RL = 54 Ω(See 图7-2 )
Change in differential
output voltage
50
3
mV
V
Δ|VOD
|
RL = 54 Ωor 100 Ω(See 图7-2 )
RL = 54 Ωor 100 Ω(See 图7-2 )
–50
Common-mode output
voltage
VOC
1
VCC/2
Change in steady-state
common-mode output
voltage
50
mV
mA
ΔVOC(SS)
RL = 54 Ωor 100 Ω(See 图7-2 )
–50
DE = VIO, -70 V ≤(VA or VB) ≤70 V, or A shorted to B (A,B are driver
terminals for half duplex, Y/Z are for full duplex)
IOS
Short-circuit output current
Bus input current
250
–250
Receiver
VI = 12 V
90
200
125
250
μA
μA
μA
μA
VI = 25 V
DE = 0 V, VCC and VIO = 0 V or 5.5 V
VI = –7 V
II
–100
–350
–80
–220
VI = –25 V
Positive-going input
threshold voltage (2)
VTH+
VTH-
40
125
200
-40
mV
mV
Negative-going input
threshold voltage (2)
–200
–125
Over common-mode range of ± 25 V
VHYS
Input hysteresis
250
mV
mV
VTH_FSH
Input fail-safe threshold
40
–40
Input differential
capacitance
CA,B
Measured between A and B, f = 1 MHz
50
pF
VIO –
0.4
VIO –
0.2
VOH
VOL
VOH
VOL
IOZ
Output high voltage
Output low voltage
Output high voltage
Output low voltage
V
V
IOH = –8 mA, VIO = 3 to 3.6 V or 4.5 V to 5.5 V
IOL = 8 mA, VIO = 3 to 3.6 V or 4.5 V to 5.5 V
IOH = –4 mA, VIO = 1.65 to 1.95 V or 2.25 V to 2.75 V
IOL = 4 mA, VIO = 1.65 to 1.95 V or 2.25 V to 2.75 V
VO = 0 V or VIO, RE = VIO
0.2
0.4
VIO –
0.4
VIO –
0.2
V
0.2
0.4
1
V
Output high-impedance
current, R pin
µA
–1
Logic
IIN
Input current (DE , SLR)
Input current (D, RE)
5
µA
µA
1.65 V ≤VIO ≤5.5 V, 0 V ≤VIN ≤VIO
1.65 V ≤VIO ≤5.5 V, 0 V ≤VIN ≤VIO
IIN
–5
Thermal Protection
Thermal shutdown
threshold
TSHDN
Temperature rising
150
180
10
°C
°C
Thermal shutdown
hysteresis
THYS
Supply
UVVCC
Rising under-voltage
threshold on VCC
2.3
2.2
170
1.4
2.6
1.6
V
V
(rising)
UVVCC
Falling under-voltage
threshold on VCC
1.95
(falling)
Hysteresis on under-voltage
of VCC
UVVCC(hys)
mV
V
UVVIO
Rising under-voltage
threshold on VIO
(rising)
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6.7 Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted). All typical values are at 25°C and supply voltage of VCC
= 5 V, VIO = 3.3 V , unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
UVVIO
Falling under-voltage
threshold on VIO
1.2
1.3
V
(falling)
Hysteresis on under-voltage
of VIO
UVVIO(hys)
120
3.5
2.5
1.8
0.1
3
mV
RE = 0 V, DE = VIO
No load
,
Driver and receiver enabled
5.3
4.2
2.4
1.2
4.1
3
mA
mA
mA
µA
RE = VIO, DE = VIO
No load
,
Driver enabled, receiver disabled
Supply current (quiescent),
VCC = 4.5 V to 5.5 V
ICC
RE = 0 V, DE = 0 V,
No load
Driver disabled, receiver enabled
RE = VIO, DE = 0 V,
D = open, No load
Driver and receiver disabled
RE = 0 V, DE = VIO
No load
,
Driver and receiver enabled
mA
mA
mA
µA
RE = VIO, DE = VIO
No load
,
Driver enabled, receiver disabled
2
Supply current (quiescent),
VCC = 3 V to 3.6 V
ICC
RE = 0 V, DE = 0 V,
No load
Driver disabled, receiver enabled
1.6
0.1
4.5
3.3
0.1
1.8
2.2
1
RE = VIO, DE = 0 V,
D = open, No load
Driver and receiver disabled
DE = 0 V, RE = 0 V,
No load
Driver disabled, Receiver enabled, SLR = GND
Driver disabled, Receiver enabled, SLR = VIO
Driver disabled, Receiver disabled, SLR = GND
Driver disabled, Receiver disabled, SLR = VIO
8.4
8.4
1
µA
DE = 0 V, RE = 0 V,
No load
µA
Logic supply current
(quiescent), VIO = 3 to 3.6 V
IIO
DE = 0 V, RE = VIO
No load
,
µA
DE = 0 V, RE = VIO
No load
,
4
µA
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for
Full duplex devices
(2) Under any specific conditions, VTH+ is assured to be at least VHYS higher than VTH–
.
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6.8 Switching Characteristics_250 kbps
250-kbps (THVD2410V, THVD2412V with SLR = VIO) over recommended operating conditions. All typical values are at 25°C
and supply voltage of VCC = 5 V , VIO = 3.3 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3V
450
500
560
625
500
540
10
1200
1200
720
770
70
ns
ns
ns
ns
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3V
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3V
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
10
70
tPHZ, tPLZ
tPZH, tPZL
Disable time
RE = X
40
70
75
280
4.5
ns
ns
µs
ns
RE = 0 V
RE = VIO
RE = VIO
Enable time
See 图7-4 and 图7-5
2.5
tSHDN
Time to shutdown
50
500
Receiver
tr, tf
Output rise/fall time
Propagation delay
Pulse skew, |tPHL –tPLH
Disable time
7
800
5
20
1270
45
ns
ns
ns
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See 图7-6
|
tPHZ, tPLZ
DE = X
30
40
VIO = 3 V to 3.6 V; DE = VIO
VIO = 1.65 V to 1.95 V, DE = VIO
VIO = 3 V to 3.6 V; DE = VIO
VIO = 1.65 V to 1.95 V; DE = VIO
90
120
130
1320
1320
tPZH(1)
100
900
900
Enable time
See 图7-7
See 图7-8
tPZL(1)
tPZH(2)
,
Enable time
DE = 0 V
3.3
5.4
μs
tPZL(2)
tD(OFS)
tD(FSO)
tSHDN
Delay to enter fail-safe operation
Delay to exit fail-safe operation
Time to shutdown
7
540
50
11
18
1260
500
μs
ns
CL = 15 pF
DE = 0 V
See 图7-9
See 图7-8
800
ns
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for
Full duplex device
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6.9 Switching Characteristics_1 Mbps
1Mbps (THVD2410V, THVD2412V with SLR = 0) over recommended operating conditions. All typical values are at 25°C and
supply voltage of VCC = 5 V , VIO = 3.3 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3 V
125
130
150
160
160
185
2
300
300
240
280
20
ns
ns
ns
ns
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3 V
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3 V
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
2
15
tPHZ, tPLZ
tPZH, tPZL
Disable time
RE = X
40
90
3
95
275
4.6
ns
ns
µs
ns
RE = 0 V
RE = VIO
RE = VIO
Enable time
See 图7-4 and 图7-5
tSHDN
Time to shutdown
50
500
Receiver
tr, tf
Output rise/fall time
Propagation delay
Pulse skew, |tPHL –tPLH
Disable time
7
50
4
15
85
ns
ns
ns
ns
ns
ns
tPHL, tPLH
tSK(P)
CL = 15 pF
See 图7-6
12.5
40
|
tPHZ, tPLZ
DE = X
30
90
90
VIO = 3 V to 3.6 V; DE = VIO
VIO = 1.65 V to 1.95 V; DE = VIO
120
130
tPZH(1)
,
Enable time
Enable time
See 图7-7
See 图7-8
tPZL(1)
tPZH(2)
tPZL(2)
,
DE = 0 V
3
4.5
μs
tD(OFS)
tD(FSO)
tSHDN
Delay to enter fail-safe operation
Delay to exit fail-safe operation
Time to shutdown
7
27
50
10
40
18
60
μs
ns
CL = 15 pF
DE = 0 V
See 图7-9
See 图7-8
500
ns
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for
Full duplex device
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6.10 Switching Characteristics_20 Mbps
20-Mbps (THVD2450V, THVD2452V with SLR = VIO) over recommended operating conditions. All typical values are at 25°C
and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3 V
4
4
6
4
8
7
15
15
30
26
3
ns
ns
ns
ns
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3 V
12
9
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VCC = 4.5 to 5.5 V,
Typical at 5 V
VCC = 3 to 3.6 V, Typical
at 3.3 V
1
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
1
3
tPHZ, tPLZ
tPZH, tPZL
Disable time
RE = X
17
14
3
35
39
ns
ns
RE = 0 V
RE = VIO
RE = VIO
Enable time
See 图7-4 and 图7-5
4.5
500
μs
ns
tSHDN
Time to shutdown
50
Receiver
tr, tf
Output rise/fall time
Propagation delay
CL = 15 pF
1.5
33
35
0.5
12
6
58
60
5
ns
ns
ns
ns
ns
VIO = 3 V to 3.6 V
VIO = 1.65 V to 1.95 V
CL = 15 pF
25
25
tPHL, tPLH
See 图7-6
tSK(P)
Pulse skew, |tPHL –tPLH
|
tPHZ, tPLZ
Disable time
DE = X
25
tPZH(1)
tPZL(1)
,
Enable time
Enable time
DE = VIO
DE = 0 V
50
82
5
ns
See 图7-7
See 图7-8
tPZH(2)
tPZL(2)
,
2.8
μs
tD(OFS)
tD(FSO)
tSHDN
Delay to enter fail-safe operation
Delay to exit fail-safe operation
Time to shutdown
7
19
50
10
32
18
50
μs
ns
CL = 15 pF
DE = 0 V
See 图7-9
See 图7-8
500
ns
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for
Full duplex device
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6.11 Switching Characteristics_50 Mbps
50-Mbps (THVD2450V, THVD2452V with SLR = 0) over recommended operating conditions. All typical values are at 25°C
and supply voltage of VCC = 5 V, VIO = 3.3 V, unless otherwise noted. (1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Driver
VCC = 3 to 3.6 V, Typical
at 3.3 V
1
1
5
5
7
6
ns
ns
tr, tf
Differential output rise/fall time
VCC = 4.5 to 5.5 V,
Typical at 5 V
VIO = 3 V to 3.6 V, VCC
=
3 to 3.6 V, Typical at 3.3
V
5
7
4
6
11
12
8
19
22
15
ns
ns
ns
VIO = 1.65 V to 1.95 V,
VCC = 3 to 3.6 V, Typical
at 3.3 V
RL = 54 Ω, CL = 50 pF
See 图7-3
tPHL, tPLH
Propagation delay
VIO = 3 V to 3.6 V, VCC
4.5 to 5.5 V, Typical at 5
V
=
VIO = 1.65 V to 1.95 V,
VCC = 4.5 to 5.5 V,
Typical at 5 V
10
1
19
3
ns
ns
VCC = 3 to 3.6 V, Typical
at 3.3 V
tSK(P)
Pulse skew, |tPHL –tPLH
|
VCC = 4.5 to 5.5 V,
Typical at 5 V
1
14
20
3
30
35
ns
ns
ns
tPHZ, tPLZ
Disable time
RE = X
RE = 0 V ; VIO = 1.65 V to 1.95 V,
2.25 V to 2.75 V
tPZH, tPZL
Enable time
See 图7-4 and 图7-5
RE = 0 V ; VIO = 3 V to VCC
RE = VIO
V
15
32
4.5
ns
μs
ns
2.5
tSHDN
Time to shutdown
RE = VIO
50
500
Receiver
tr, tf
Output rise/fall time
Propagation delay
1.5
33
6
ns
ns
See 图7-6
CL = 15 pF
VIO = 3 V to 3.6 V, See 图
7-6
tPHL, tPLH
25
25
58
VIO = 1.65 V to 1.95 V,
See 图7-6
tPHL, tPLH
Propagation delay
35
60
ns
tSK(P)
CL = 15 pF
DE = X
0.5
12
5
ns
ns
Pulse skew, |tPHL –tPLH
|
See 图7-6
tPHZ, tPLZ
Disable time
25
VIO = 1.65 V to 1.95 V,
See 图7-7
50
50
82
75
5
ns
ns
tPZH(1)
tPZL(1)
,
Enable time
DE = VIO
DE = 0 V
VIO = 3 V to 3.6 V, See 图
7-7
tPZH(2)
tPZL(2)
,
Enable time
2.8
See 图7-8
μs
tD(OFS)
tD(FSO)
tSHDN
Delay to enter fail-safe operation
Delay to exit fail-safe operation
Time to shutdown
7
19
50
10
32
18
50
μs
ns
CL = 15 pF
DE = 0 V
See 图7-9
See 图7-8
500
ns
(1) A, B are driver output and receiver input terminals for Half duplex devices; A/B are Receiver input, Y/Z are driver output terminals for
Full duplex device
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6.12 Typical Characteristics
4.75
4.25
3.75
3.25
2.75
2.25
1.75
1.25
0.75
VOD (VCC = 3.3 V)
VOD (VCC = 5 V)
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80
Driver Output Current (mA)
DE = VIO
D = GND
TA = 27 °C
DE = VIO
D = GND
TA = 27 °C
图6-2. Driver Differential Output voltage vs Driver
图6-1. Driver Output Voltage vs Driver Output
Output Current
Current
75
70
65
60
55
50
45
40
35
3.8
VOD (VCC = 3.3 V)
VOD (VCC = 5 V)
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
2
1.8
-60 -40 -20
0
20
40
60
80 100 120 140
3
3.25 3.5 3.75
DE = D = VIO
4
4.25 4.5 4.75
5
5.25 5.5
Temperature (°C)
Supply Voltage (V)
DE = D = VIO
RL = 54 Ω
TA = 27 °C
RL = 54 Ω
图6-4. Driver differential output voltage vs
图6-3. Supply Current vs Supply Voltage
Temperature
620
550
545
540
600
580
560
540
520
500
480
535
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
530
525
520
515
510
505
500
-40
-20
0
20
40
60
80
100 120 140
CL = 50 pF
-40
-20
0
20
40
60
80
100 120 140
CL = 50 pF
Temperature (°C)
Temperature (°C)
DE = VIO
DE = VIO
RL = 54 Ω
RL = 54 Ω
图6-5. THVD2410V 250kbps Driver rise or fall time
图6-6. THVD2410V 250kbps Driver propagation
vs Temperature
delay vs Temperature
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DE = VIO
CL = 50 pF
DE = VIO
CL = 50 pF
RL = 54 Ω
RL = 54 Ω
图6-7. THVD2410V 1Mbps Driver rise or fall time vs
图6-8. THVD2410V 1Mbps Driver propagation
Temperature
delay vs Temperature
10
9.5
9
16
15.5
15
14.5
14
VCC = 3.3 V
VCC = 5 V
13.5
13
8.5
VCC = 3.3 V
VCC = 5 V
12.5
12
8
7.5
7
11.5
11
10.5
10
9.5
9
6.5
6
-40
-20
0
20
40
60
80
100 120 140
CL = 50 pF
-40
-20
0
20
40
60
80
100 120 140
CL = 50 pF
Temperature (°C)
Temperature (°C)
DE = VIO
RL = 54 Ω
DE = VIO
RL = 54 Ω
图6-10. THVD2450V 20Mbps Driver propagation
图6-9. THVD2450V 20Mbps Driver rise or fall time
delay vs Temperature
vs Temperature
11.5
VCC = 3.3 V
VCC = 5 V
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
-40
-20
0
20
40
60
80
100 120 140
CL = 50 pF
Temperature (°C)
DE = VIO
RL = 54 Ω
DE = VIO
CL = 50 pF
RL = 54 Ω
图6-12. THVD2450V 50Mbps Driver propagation
图6-11. THVD2450V 50Mbps Driver rise or fall time
delay vs Temperature
vs Temperature
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90
85
80
75
70
65
60
55
50
45
40
120
110
100
90
ICC (VCC = 3.3 V)
ICC (VCC = 5 V)
ICC (VCC = 3.3 V)
ICC (VCC = 5 V)
80
70
60
50
40
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Data Rate (MHz)
0
20
40
60
80
100
120
140
Data Rate (kHz)
DE = VIO
TA = 27 °C
RL = 54 Ω
DE = VIO
TA = 27 °C
RL = 54 Ω
图6-13. THVD2450V Supply Current vs Signal Rate
图6-14. THVD2410V Supply Current vs Signal Rate
11.2
37.5
VCC = 3.3 V
VCC = 5 V
VCC = 3.3 V
VCC = 5 V
37
36.5
36
11
35.5
35
34.5
34
33.5
33
32.5
32
31.5
31
30.5
30
10.8
10.6
10.4
10.2
10
29.5
-40
-20
0
20
40
60
80
100 120 140
CL(RXD) = 15 pF
-40
-20
0
20
40
60
80
100 120 140
CL(RXD) = 15 pF
Temperature (C)
Temperature (°C)
SLR = GND
RE = GND
SLR = GND
RE = GND
图6-15. Failsafe entry delay vs Temperature
图6-16. Failsafe exit delay vs Temperature
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7 Parameter Measurement Information
375
VIO
DE
A or Y
B or Z
Vtest
D
VOD
0 V or VIO
RL
375
图7-1. Measurement of Driver Differential Output Voltage With Common-Mode Load
A
V
A
A or Y
B or Z
R /2
L
B
D
V
B
0 V or VIO
V
OD
V
OC(PP)
R /2
L
V
OC(SS)
V
OC
C
L
V
OC
图7-2. Measurement of Driver Differential and Common-Mode Output With RS-485 Load
VIO
VIO
50%
V
I
DE
0 V
A or Y
B or Z
R =
L
54
t
t
PHL
PLH
D
~
~
V
2 V
C = 50 pF
L
OD
90%
50%
Input
V
I
Generator
V
OD
10%
~ –2 V
~
t
r
t
f
图7-3. Measurement of Driver Differential Output Rise and Fall Times and Propagation Delays
A or Y
S1
VIO
VO
D
50%
VI
tPZH
0 V
VOH
B or Z
CL= 50
pF
DE
RL= 110
Input
Generator
90%
50
VI
50%
VO
0 V
tPHZ
图7-4. Measurement of Driver Enable and Disable Times With Active High Output and Pull-Down Load
VCC
VIO
0 V
Vcc
RL= 110
VO
A or Y
B or Z
50%
VI
tPZL
VO
S1
D
tPLZ
DE
50
CL= 50 pF
Input
Generator
50%
VI
10%
VOL
图7-5. Measurement of Driver Enable and Disable Times With Active Low Output and Pull-up Load
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3 V
50%
V
I
A
0 V
R
VO
t
tPHL
Input
PLH
50 Ω
V
1.5V
0 V
VOH
Generator
I
90%
B
CL=15 pF
50%
10%
RE
V
OD
V
tr
OL
t
f
图7-6. Measurement of Receiver Output Rise and Fall Times and Propagation Delays
V
IO
50%
VIO
DE
VIO
V
I
0V
A
B
tPZH(1)
tPHZ
1 k
D
V
O
R
D at VIO
S1 to GND
0 V or VIO
S1
V
OH
90%
V
50%
O
CL=15 pF
≈ 0V
RE
tPZL(1)
tPLZ
Input
D at 0V
S1 to VIO
V
IO
50
Generator
V
I
V
50%
O
10%
V
OL
图7-7. Measurement of Receiver Enable/Disable Times With Driver Enabled
VIO
VIO
VI
50%
50%
tPHZ
0V
A
B
tPZH(2)
1 k
0 V or 1.5 V
1.5 V or 0 V
R
VO
S1
VOH
A at 1.5 V
B at 0 V
S1 to GND
90%
VO
VO
50%
CL= 15 pF
0 V
RE
tPZL(2)
tPLZ
10%
Input
Generator
VIO
A at 0 V
B at 1.5 V
S1 to VIO
50
VI
50%
VOL
图7-8. Measurement of Receiver Enable Times With Driver Disabled
0 V
VA - VB
A
VA = 0 V or -750 mV
VB = 0 V or +750 mV
-1.5 V
R
VO
tD(FSO)
tD(OFS)
B
CL= 15 pF
RE
VIO
0 V
VO
VIO / 2
0 V
图7-9. Measurement of Fail-Safe Delay
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8 Detailed Description
8.1 Overview
THVD24xxV are ±70 V bus fault-protected, ±25V common-mode voltage range capable half and full-duplex
RS-485 transceivers. The devices have active-high driver enable and active-low receiver enable logic. Each
device has SLR pin which allows it to be used for two different maximum speed settings. This is beneficial as
customers can qualify one device and use it in two different end-applications. The devices also have flexible I/O
supply pin VIO which enables digital interface voltage range, from 1.65 V to 5.5 V, different from bus voltage
supply 3 V to 5.5 V.
8.2 Functional Block Diagrams
VIO SLR
VCC
A
B
R
Internally connected
only for Half duplex
devices
RE
I/O
and
Control
DE
D
Z
Y
Only for full
duplex devices
图8-1. THVD2410 and THVD2450 Block Diagram
8.3 Feature Description
8.3.1 ±70 V Fault Protection
THVD24xxV transceivers have extended bus fault protection compared to standard RS-485 devices.
Transceivers that operate in rugged industrial environments are often exposed to voltage transients greater than
the -7 V to +12 V defined by the TIA/EIA-485A standard. To protect against such conditions, the generic RS-485
devices with lower absolute maximum ratings requires expensive external protection components. To simplify
system design and reduce overall system cost, THVD24xxV devices are protected up to ±70 V without the need
for any external components.
8.3.2 Integrated IEC ESD and EFT Protection
Internal ESD protection circuits protect the transceivers against electrostatic discharges (ESD) according to IEC
61000-4-2 of up to ±15 kV contact and air discharge (for half-duplex devices) and up to ±8 kV contact and air
discharge (for full-duplex devices). Bus structures also protect against electrical fast transients (EFT) according
to IEC 61000-4-4 for up to ±4 kV. With careful system design, integrated bus structures can enable EFT Criterion
A at the system level (minimum to no data loss when transient noise is present).
8.3.3 Driver Overvoltage and Overcurrent Protection
The THVD24xxV drivers are protected against any DC supply shorts in the range of -70 V to +70 V. The devices
internally limit the short circuit current to ±250 mA in order to comply with the TIA/EIA-485A standard. In addition,
a fold-back current limiting circuit further reduces the driver short circuit current to less than ±5 mA if the output
fault voltage exceeds |±25 V|.
All devices feature thermal shutdown protection that disables the driver and the receiver if the junction
temperature exceeds the TSHDN threshold due to excessive power dissipation.
8.3.4 Enhanced Receiver Noise Immunity
The differential receivers of THVD24xxV feature fully symmetric thresholds to maintain duty cycle of the signal
even with small input amplitudes. In addition, 250 mV (typical) hysteresis provides noise immunity. When the
device is in slew rate limited mode of 250 kbps, typical 700 ns of glitch filter in receiver signal chain prevents
high frequency noise pulses from the bus to appear on R pin.
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8.3.5 Receiver Fail-Safe Operation
The receivers are fail-safe to invalid bus states caused by the following:
• Open bus conditions, such as a disconnected connector
• Shorted bus conditions, such as cable damage shorting the twisted-pair together
• Idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the receiver outputs a fail-safe logic high state if the input amplitude stays for longer than
tD(OFS) at less than |VTH_FSH|.
8.3.6 Low-Power Shutdown Mode
Driving DE low and RE high for longer than 500 ns puts the devices into the shutdown mode. If either DE goes
high or RE goes low, the counters reset. The devices does not enter the shutdown mode if the enable pins are in
disable state for less than 50 ns. This feature prevents the devices from accidentally going into shutdown mode
due to skew between DE and RE.
8.4 Device Functional Modes
When the driver enable pin, DE, is logic high (H), the differential outputs A and B follow the logic states at data
input D. A logic high at D causes A to turn high and B to turn low. In this case the differential output voltage
defined as VOD = VA –VB is positive. When D is low (L), the output states reverse: B turns high, A becomes low,
and VOD is negative.
When DE is low, both outputs turn high-impedance. In this condition the logic state at D is irrelevant (X). The DE
pin has an internal pull-down resistor to ground, thus when left open the driver is disabled (Z= high-impedance)
by default. The D pin has an internal pull-up resistor to VIO, thus, when left open while the driver is enabled,
output A turns high and B turns low.
表8-1. Driver Function Table
INPUT
ENABLE
OUTPUTS
FUNCTION
D
DE
A
H
L
B
L
H
H
Actively drive bus high
Actively drive bus low
L
X
H
L
H
Z
Z
L
Z
Z
H
Driver disabled
X
OPEN
H
Driver disabled by default
Actively drive bus high by default
OPEN
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When the receiver enable pin, RE, is logic low, the receiver is enabled. When the differential input voltage
defined as VID = VA – VB is higher than the positive input threshold, VTH+, the receiver output, R, turns high.
When VID is lower than the negative input threshold, VTH-, the receiver output, R, turns low. If VID is between
VTH+ and VTH- the output is indeterminate.
When RE is logic high or left open, the receiver output is high-impedance and the magnitude and polarity of VID
are irrelevant. Internal biasing of the receiver inputs causes the output to go failsafe-high when the transceiver is
disconnected from the bus (open-circuit), the bus lines are shorted to one another (short-circuit), or the bus is not
actively driven (idle bus).
表8-2. Receiver Function Table
DIFFERENTIAL INPUT
VID = VA –VB
VTH+ < VID
ENABLE
OUTPUT
FUNCTION
RE
R
H
?
L
Receive valid bus high
Indeterminate bus state
Receive valid bus low
Receiver disabled
VTH- < VID < VTH+
VID < VTH-
L
L
L
X
H
Z
Z
H
H
H
X
OPEN
Receiver disabled by default
Fail-safe high output
Fail-safe high output
Fail-safe high output
Open-circuit bus
Short-circuit bus
Idle (terminated) bus
L
L
L
表 8-3 shows SLR (slew rate select) pin functionality. SLR has intergated pull-down, so the device remains in
higher speed mode until SLR is pulled high which limits the slew rate and puts the device in slower speed mode.
表8-3. SLR pin control
Device
Functionality w.r.t SLR pin
THVD2410V, THVD2412V
SLR = Low or floating: Both transmitter (TX) and receiver (RX)
maximum speed is 1 Mbps
SLR = High: Both TX and RX maximum speed is limited to 250 kbps
THVD2450V, THVD2452V
SLR = Low or floating: Both transmitter (TX) and receiver (RX)
maximum speed is 50 Mbps
SLR = High: Both TX and RX maximum speed is limited to 20 Mbps
Table shows the device behavior in undervoltage scenarios:
表8-4. Supply Function Table
VCC
VIO
Driver Output
Receiver Output
Determined by RE and A-B
High impedance
> UVVCC(rising)
< UVVCC(falling)
> UVVCC(rising)
< UVVCC(falling)
> UVVIO(rising)
> UVVIO(rising)
< UVVIO(falling)
< UVVIO(falling)
Determined by DE and D inputs
High impedance
High impedance
High impedance
High impedance
High impedance
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Application Information
THVD24xxV are fault-protected, half- and full-duplex RS-485 transceivers commonly used for asynchronous
data transmissions. For these devices, the driver and receiver enable pins allow for the configuration of different
operating modes.
9.2 Typical Application
An RS-485 bus consists of multiple transceivers connecting in parallel to a bus cable. To eliminate line
reflections, each cable end is terminated with a termination resistor, RT, whose value matches the characteristic
impedance, Z0, of the cable. This method, known as parallel termination, generally allows for higher data rates
over longer cable length.
R
R
R
R
A
B
A
B
RE
RE
R
R
T
T
DE
D
DE
D
D
D
A
B
A
B
R
R
R
R
D
D
D
D
RE DE
RE DE
图9-1. Typical RS-485 Network With Half-Duplex Transceivers
Commander
Responder
R
D
R
R
DE
RE
RE
D
DE
D
R
D
R
R
D
D
RE DE
Responder
图9-2. Typical RS-485 Network with Full-Duplex transceivers
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9.2.1 Design Requirements
RS-485 is a robust electrical standard suitable for long-distance networking that may be used in a wide range of
applications with varying requirements, such as distance, data rate, and number of nodes.
9.2.1.1 Data Rate and Bus Length
There is an inverse relationship between data rate and cable length, which means the higher the data rate, the
short the cable length; and conversely, the lower the data rate, the longer the cable length. While most RS-485
systems use data rates between 10 kbps and 100 kbps, some applications require data rates up to 250 kbps at
distances of 4000 feet and longer. Longer distances are possible by allowing for small signal jitter of up to 5 or
10%.
10000
5%, 10%, and 20% Jitter
1000
Conservative
Characteristics
100
10
100
1k
10k
100 k
1M
10M
100 M
Data Rate (bps)
图9-3. Cable Length vs Data Rate Characteristic
Even higher data rates are achievable (that is, 50 Mbps for the THVD24xxV) in cases where the interconnect is
short enough (or has suitably low attenuation at signal frequencies) to not degrade the data.
9.2.1.2 Stub Length
When connecting a node to the bus, the distance between the transceiver inputs and the cable trunk, known as
the stub, should be as short as possible. Stubs present a non-terminated piece of bus line which can introduce
reflections of varying phase as the length of the stub increases. As a general guideline, the electrical length, or
round-trip delay, of a stub should be less than one-tenth of the rise time of the driver, thus giving a maximum
physical stub length as shown in 方程式1.
L(STUB) ≤0.1 × tr × v × c
(1)
where
• tr is the 10/90 rise time of the driver
• c is the speed of light (3 × 108 m/s)
• v is the signal velocity of the cable or trace as a factor of c
9.2.1.3 Bus Loading
The RS-485 standard specifies that a compliant driver must be able to drive 32 unit loads (UL), where 1 unit load
represents a load impedance of approximately 12 kΩ. Because the THVD24xxV devices consist of 1/8 UL
transceivers, connecting up to 256 receivers to the bus is possible for a limited common mode range of - 7 V to
12 V.
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9.2.1.4 Transient Protection
The bus pins of the THVD24xxV transceivers include on-chip ESD protection against ±16-kV HBM and ±15-kV
IEC 61000-4-2 contact discharge for half-duplex devices ±8-kV for full-duplex devices. The International
Electrotechnical Commission (IEC) ESD test is far more severe than the HBM ESD test. The 50% higher charge
capacitance, C(S), and 78% lower discharge resistance, R(D), of the IEC model produce significantly higher
discharge currents than the HBM model. As stated in the IEC 61000-4-2 standard, contact discharge is the
preferred transient protection test method.
R(C)
R(D)
40
35
30
25
20
15
10
5
50 M
(1 M)
330 Ω
10-kV IEC
(1.5 kΩ)
Device
Under
Test
High-Voltage
Pulse
Generator
150 pF
(100 pF)
C(S)
10-kV HBM
0
0
50
100
150
200
250
300
Time (ns)
图9-4. HBM and IEC ESD Models and Currents in Comparison (HBM Values in Parenthesis)
The on-chip implementation of IEC ESD protection significantly increases the robustness of equipment.
Common discharge events occur because of human contact with connectors and cables. Designers may choose
to implement protection against longer duration transients, typically referred to as surge transients.
EFTs are generally caused by relay-contact bounce or the interruption of inductive loads. Surge transients often
result from lightning strikes (direct strike or an indirect strike which induce voltages and currents), or the
switching of power systems, including load changes and short circuit switching. These transients are often
encountered in industrial environments, such as factory automation and power-grid systems.
图 9-5 compares the pulse-power of the EFT and surge transients with the power caused by an IEC ESD
transient. The left side of the diagram shows the relative pulse-power for a 0.5-kV surge transient and 4-kV EFT
transient, both of which exceeds the 10-kV ESD transient visible in the lower-left corner. 500-V surge transients
are representative of events that may occur in factory environments in industrial and process automation.
The right side of the diagram shows the pulse power of a 6-kV surge transient, relative to the same 0.5-kV surge
transient. 6-kV surge transients are may occur in power generation and power-grid systems.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6-kV Surge
22
20
18
16
14
12
10
8
0.5-kV Surge
4-kV EFT
6
4
2
0.5-kV Surge
10-kV ESD
0
0
5
10 15 20 25 30 35 40
0
5
10 15 20 25 30 35 40
Time (µs)
Time (µs)
图9-5. Power Comparison of ESD, EFT, and Surge Transients
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For surge transients, high-energy content is characterized by long pulse duration and slow decaying pulse
power. The electrical energy of a transient that is dumped into the internal protection cells of a transceiver is
converted into thermal energy, which heats and destroys the protection cells, thus destroying the transceiver. 图
9-6 shows the large differences in transient energies for single ESD, EFT, surge transients, and an EFT pulse
train that is commonly applied during compliance testing.
1000
100
Surge
10
1
EFT Pulse Train
0.1
0.01
EFT
10-3
10-4
ESD
10-5
10-6
0.5
1
2
4
6
8 10
15
Peak Pulse Voltage (kV)
图9-6. Comparison of Transient Energies
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9.2.2 Detailed Design Procedure
图 9-7 suggests a protection circuit against 1 kV surge (IEC 61000-4-5) transients. 表 9-1 shows the associated
bill of materials. SMAJ30CA TVS diodes are rated to operate up to 30 V. This makes sure the protection diodes
do not conduct if a direct RS-485 bus shorts to 24-V DC industrial power rail.
3.3 V - 5 V
100 nF
VCC
VIO
10 k
R
RxD
MCU/
UART
DIR
RE
A
B
DE
D
TVS
TxD
THVD24xxV
GND
10 k
SLR
TVS
图9-7. Transient Protection Against Surge Transients for Half-Duplex Devices
表9-1. Components List
DEVICE
XCVR
TVS
FUNCTION
ORDER NUMBER
THVD2410V or THVD2450V
SMAJ30CA
MANUFACTURER(1)
RS-485 transceiver
TI
Bidirectional 400-W transient suppressor
Littelfuse
(1) See 节10.1
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9.2.3 Application Curves
50% duty square wave on D pin at 250 kbps
50% duty square wave on D pin at 250 kbps
SLR = VIO
DE = VIO
SLR = VIO
DE = VIO
RL = 54 Ω
RL = 54 Ω
图9-8. THVD2410V Waveforms at VCC = 5 V
图9-9. THVD2410V Waveforms at VCC = 3.3 V
Random (PRBS7) data on D pin at 50 Mbps
Random (PRBS7) data on D pin at 50 Mbps
SLR = GND
DE = VIO
SLR = GND
DE = VIO
RL = 54 Ω
RL = 54 Ω
图9-10. THVD2450V Waveforms at VCC = 5 V
图9-11. THVD2450V Waveforms at VCC = 3.3 V
A pin given ±200mV VID with DC offset of 1.5 V
RE = GND
B pin at 1.5 V
图9-12. THVD2450V Receiver Waveform with ±200 mV VID
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9.3 Power Supply Recommendations
For reliable operation at all data rates and supply voltages, each supply should be decoupled with a minimum of
100 nF ceramic capacitor located as close to the supply pins as possible. This helps to reduce supply voltage
ripple present on the outputs of switched-mode power supplies and also helps to compensate for the resistance
and inductance of the PCB power planes.
9.4 Layout
9.4.1 Layout Guidelines
Robust and reliable bus node design often requires the use of external transient protection devices in order to
protect against surge transients that may occur in industrial environments. Since these transients have a wide
frequency bandwidth (from approximately 3 MHz to 300 MHz), high-frequency layout techniques should be
applied during PCB design.
1. Place the protection circuitry close to the bus connector to prevent noise transients from propagating across
the board.
2. Use VCC and ground planes to provide low inductance. Note that high-frequency currents tend to follow the
path of least impedance and not the path of least resistance.
3. Design the protection components into the direction of the signal path. Do not force the transient currents to
divert from the signal path to reach the protection device.
4. Apply 100-nF to 220-nF decoupling capacitors as close as possible to the VCC and VIO pins of transceiver,
UART and/or controller ICs on the board.
5. Use at least two vias for VCC and ground connections of decoupling capacitors and protection devices to
minimize effective via inductance.
6. Use 1-kΩto 10-kΩpull-up and pull-down resistors for enable/SLR lines to limit noise currents in these lines
during transient events.
7. Insert pulse-proof resistors into the A/Y and B/Z bus lines if the TVS clamping voltage is higher than the
specified maximum voltage of the transceiver bus pins. These resistors limit the residual clamping current
into the transceiver and prevent it from latching up.
9.4.2 Layout Example
Via to ground
Via to VCC
C
C
VCC
1
2
3
4
5
10
9
VIO
R
TVS
TVS
R
R
B
A
R
MCU
8
DE
RE
D
VIO
7
SLR
GND
GND
6
图9-13. Half-Duplex Layout Example
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10 Device and Documentation Support
10.1 Device Support
10.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
10.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 商标
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTHVD2412VDR
PTHVD2452VDR
THVD2410VDRCR
THVD2450VDRCR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
VSON
VSON
D
14
14
10
10
250
250
TBD
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Samples
Samples
Samples
Samples
D
Call TI
NIPDAU
NIPDAU
Call TI
DRC
DRC
5000 RoHS & Green
5000 RoHS & Green
Level-1-260C-UNLIM
Level-1-260C-UNLIM
2410
2450
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2023
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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14-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
THVD2410VDRCR
THVD2450VDRCR
VSON
VSON
DRC
DRC
10
10
5000
5000
330.0
330.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
THVD2410VDRCR
THVD2450VDRCR
VSON
VSON
DRC
DRC
10
10
5000
5000
367.0
367.0
367.0
367.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
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PACKAGE OUTLINE
DRC0010J
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.65 0.1
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4 0.1
10
1
8X 0.5
0.30
0.18
10X
SYMM
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
10X
4218878/B 07/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
11
(2.4)
(3.4)
SYMM
(0.95)
8X (0.5)
6
5
(R0.05) TYP
(
0.2) VIA
TYP
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218878/B 07/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DRC0010J
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.5)
(0.5)
SYMM
EXPOSED METAL
TYP
11
10X (0.6)
1
10
(1.53)
10X (0.24)
2X
(1.06)
SYMM
(0.63)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4218878/B 07/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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