TI380C25 [TI]
TOKEN-RING COMMPROCESSOR; 令牌环COMMPROCESSOR型号: | TI380C25 |
厂家: | TEXAS INSTRUMENTS |
描述: | TOKEN-RING COMMPROCESSOR |
文件: | 总71页 (文件大小:997K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
• IEEE 802.5 and IBM Token-Ring Network
• Dual-Port DMA and Direct I/O Transfers to
Compatible
Host Bus
• Compatible With TI380FPA FNL
• Supports 8- or 16-Bit Pseudo-DMA
PacketBlaster
Operation
• Token-Ring Features
• Enhanced-Address-Copy-Option (EACO)
Interface Supports External
– 16- or 4-Megabit-per-Second Data Rates
– Supports up to 18K-Byte Frame Size
(16-Mbps Operation Only)
Address-Checking Logic for Bridging or
External Custom Applications
– Supports Universal-and Local-Network
Addressing
– Early Token-Release Option
(16-Mbps Operation Only)
• Support for Module High-Impedance
In-Circuit Testing
• Built-In Real-Time Error Detection
• Bring-Up and Self-Test Diagnostics With
– Compatible With the TMS38054
Loopback
• Expandable Local LAN-Subsystem Memory
• Automatic Frame-Buffer Management
• 2- to 33-MHz System-Bus Clock
• Slow-Clock Low-Power Mode
• Single 5-V Supply
• 0.8-µm CMOS Technology
• 250-mA Typical Latch-Up Immunity at 25°C
• ESD Protection Exceeds 2000 V
Space up to 2 Megabytes
• Glueless Interface to DRAMs
• High-Performance 16-Bit CPU for
Communications-Protocol Processing
• 1- to 16.5-Megabyte-per-Second
High-Speed Bus Master DMA Interface
• Low-Cost Host-Slave I/O Interface Option
• Up to 32-Bit Host Address Bus
• Selectable Host System-Bus Options
• 144-Pin Plastic Thin Quad Flat Package
(PGE Suffix)
• Adapter Local-Bus Speed Is Switchable
• Operating Temperature Range
0°C to 70°C
Between 4 MHz and 6 MHz
• 80x8x or 68xxx-Type Bus and Memory
Organization
– 8- or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking
LAN Subsystem
Attached
System
Bus
(2 MHz
to
Transmit
Token-Ring
To
Physical-Layer
Network
TI380C25
Circuitry
Receive
33 MHz)
16
Memory
Figure 1. Network-Commprocessor Applications Diagram
IBM and Token-Ring Network are trademarks of International Business Machines Corp.
PacketBlaster is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
pin assignments
PGE PACKAGE
(TOP VIEW)
NC
1
V
108
107
106
105
104
103
102
101
100
99
SSL
NC
V
2
SSL
MOE
MBEN
MADH7
MADH6
MADH5
MADH4
3
V
DD
4
XMATCH
XFAIL
5
6
TEST0
TEST1 (NC)
TEST2
TEST3
TEST4
TEST5
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
7
8
9
V
DD
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
98
V
SS
97
MADH3
MADH2
MADH1
MADH0
MAXPH
MBRQ
96
95
94
93
92
91
MBGR
V
SS
NC
90
V
SS
89
MAXPL
MADL7
MADL6
MADL5
MADL4
MADL3
MADL2
MADL1
MADL0
EXTINT3
EXTINT2
EXTINT1
EXTINT0
NMI
V
DD
NC
88
87
V
SSC
86
SADH6
85
SADH7
SPH
SRD/SUDS
SRDY/SDTACK
SOWN
84
83
82
81
80
SDBEN
79
SBHE/SRNW
SHRQ/SBRQ
SPL
SADL0
SADL1
SADL2
V
SSL
78
77
76
75
V
DD
NC
74
73
V
SSL
NC – No internal connection
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
description
The TI380C25 is a single-chip network-communications processor (commprocessor) that supports token-ring
local area networks (LANs) at data rates of 16 Mbps or 4 Mbps. The TI380C25 conforms to ISO 8802–5/IEEE
802.5–1992 standards and has been verified to be completely IBM Token-Ring Network compatible. By
integrating the essential control building blocks needed on a LAN-subsystem card into one device, the
TI380C25 ensures that this IBM compatibility is maintained in silicon.
The high degree of integration of the TI380C25 makes it a virtual LAN subsystem on a single chip. Protocol
handling, host-system interfacing, memory interfacing, and communications processing are all provided
through the TI380C25. To complete LAN-subsystem design, only the network-interface hardware, local
memory, and minimal additional components such as PAL devices and crystal oscillators need to be added.
The TI380C25 provides a 32-bit system-memory address reach with a high-speed bus-master DMA interface
that supports rapid communications with the host system. In addition, the TI380C25 supports direct I/O and a
low-cost 8- or 16-bit pseudo-DMA interface that requires only a chip select to work directly on an 80x8x 8-bit
slave I/O interface. Finally, selectable 80x8x or 68xxx-type host-system bus and memory organization add to
design flexibility.
The TI380C25 supports addressing for up to 2M bytes of local memory. This expanded memory capacity can
improve LAN-subsystem performance by allowing larger blocks of information to be transferred at one time and
minimizing the frequency of host LAN-subsystem communications. The support of large local memory is
importantinapplicationsthatrequirelargedatatransfers(suchasgraphicsordatabasetransfers)andinheavily
loaded networks where the extra memory can provide data buffers to store data until it can be processed by
the host.
The proprietary CPU used in the TI380C25 allows protocol software to be downloaded into RAM or stored in
ROM in the local-memory space. By moving protocols (such as LLC) to the LAN-subsystem, overall system
performance is increased. This is accomplished by offloading the processing from the host system to the
TI380C25, which can also reduce LAN-subsystem-to-host communications. As other protocol software is
developed, greater differentiation of end products with enhanced system performance is possible.
In addition, the TI380C25 includes hardware counters that provide real-time error detection and automatic
frame-buffer management. These counters control system-bus retries and burst size, and track host and
LAN-subsystembuffer status. Previously, these counters needed to be maintained in software. Integrating them
into hardware removes software overhead and improves LAN-subsystem performance.
The TI380C25 implements a TI-patented enhanced-address-copy-option (EACO) interface. This interface
supports external address-checking devices, such as the TMS380SRA source-routing accelerator. The
TI380C25 has a 128-word external I/O space in its memory to support external address-checker devices and
other hardware extensions to the TMS380 architecture.
The major blocks of the TI380C25 include the communications processor (CP), the system interface (SIF), the
memory interface (MIF), the protocol handler (PH), the clock generator (CG), and the adapter-support function
(ASF), as shown in the functional block diagram.
The TI380C25 is available in a 144-pin plastic thin quad flat package (PGE suffix) and is characterized for
operation from 0°C to 70°C.
The TI380C25 has a bus interface to the host system, a bus interface to local memory, and an interface to the
physical-layercircuitry. PinnamesstartingwiththeletterSattachtothehost-systembus, andpinnamesstarting
with the letter M attach to the local-memory bus.
PAL is a registered trademark of Advanced Micro Devices, Inc. Other companies also manufacture programmable array logic devices.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
functional block diagram
System
Interface
(SIF)
Memory
Interface
(MIF)
SADH0
MADH0
SADH7
SADL0
MADH7
MADL0
• DIO Control
• Bus Control
• DMA Control
• DRAM Refresh
• Local-Bus
Arbitrator
• Local-Bus
Control
• Local
Parity-Check/
Generator
SADL7
MADL7
SPH
SPL
SBRLS
MRAS
MCAS
MAXPH
MAXPL
MW
SINTR/SIRQ
SDDIR
SDBEN
MOE
SALE
SXAL
MDDIR
MAL
SOWN
MAX0
SIACK
MAX2
SBCLK
MRESET
MROMEN
MBEN
MBRQ
MBGR
MACS
MBIAEN
MREF
SRD/SUDS
SWR/SLDS
SRDY/SDTACK
SI/M
SHLDA/SBGR
SBHE/SRNW
SRAS/SAS
S8/SHALT
SRESET
SRS0
OSCIN
OSCOUT
MBCLK1
MBCLK2
SYNCIN
CLKDIV
Clock
Generator
(CG)
SRS1
SRS2/SBERR
SCS
SRSX
SHRQ/SBRQ
SBBSY
BTSTRP
PRTYEN
NSELOUT0
NSELOUT1
NMI
EXTINT0
Adapter-
Support
Function
(ASF)
EXTINT3
TEST0
• Interrupts
Communications
Processor
• Test Function
TEST5
XMATCH
XFAIL
RCLK
REDY
WFLT
FRAQ
NSRT
WRAP
DRVR
DRVR
Token-Ring
Protocol Handler (PH)
RCVR
PXTALIN
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions
PIN
NAME
†
DESCRIPTION
I/O
NO.
Bootstrap. The value on BTSTRP is loaded into the BOOT bit of the SIFACL register at reset (i.e., when
SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value. BTSTRP
indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM,
the TI380C25 is denied access to the local-memory bus until the CPHALT bit in the SIFACL register
is cleared.
BTSTRP
42
I
H = Chapters 0 and 31 of local memory are RAM based (see Note 1).
L
= Chapters 0 and 31 of local memory are ROM based.
Clock divider select (see Note 2)
CLKDIV
38
I
H = 64-MHz OSCIN for 4-MHz local bus
L
= 32-MHz OSCIN for 4-MHz local bus or 48-MHz OSCIN for 6-MHz local bus
EXTINT0
EXTINT1
EXTINT2
EXTINT3
32
31
30
29
I/O
I
Reserved; must be pulled high (see Note 3)
MACS
132
Reserved; must be tied low (see Note 4)
MADH0
MADH1
MADH2
MADH3
MADH4
MADH5
MADH6
MADH7
15
14
13
12
8
7
6
5
Local-memory address, data, and status bus — high byte. For the first quarter of the local-memory
cycle, these bus lines carry address bits AX4 and A0 to A6; for the second quarter, they carry status
bits; and for the third and fourth quarters, they carry data bits 0 to 7. The most significant bit is MADH0
and the least significant bit is MADH7.
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX4, A0–A6
Status
D0–D7
D0–D7
MADL0
MADL1
MADL2
MADL3
MADL4
MADL5
MADL6
MADL7
28
27
26
25
24
23
22
21
Local-memory address, data, and status bus — low byte. For the first quarter of the local-memory
cycle, these bus lines carry address bits A7 to A14; for the second quarter, they carry address bits AX4
and A0 to A6; and for the third and fourth quarters, they carry data bits 8 to 15. The most significant
bit is MADL0 and the least significant bit is MADL7.
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
A7–A14
AX4, A0–A6 D8–D15
D8–D15
Memory-address latch. MAL is a strobe signal for sampling the address at the start of the memory
cycle; it is used by SRAMs and EPROMs. The full 20-bit word address is valid on MAX0, MAXPH,
MAX2, MAXPL, MADH0–MADH7, and MADL0–MADL7. Three 8-bit transparent latches can be used
to retain a 20-bit static address throughout the cycle.
MAL
131
139
O
Rising edge
Falling edge
=
=
No signal latching
Allows the above address signals to be latched
Local-memory-extended address bit. MAX0 drives AX0 at row-address time and drives A12 at
column-address and data-valid times for all cycles. This signal can be latched by MRAS. Driving A12
eases interfacing to a BIA ROM.
MAX0
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX0
A12
A12
A12
†
I = input, O = output
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
2. TheTI380FPA and TMS380SRA are currently supported only with the 4-MHz local bus in either CLKDIV state. Expansion to support
the 6-MHz local bus is under development.
3. Each pin must be individually tied to V
4. Pin should be connected to ground.
with a 1-kΩ pullup resistor.
CC
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
†
DESCRIPTION
I/O
NAME
NO.
Local-memory-extended address bit. MAX2 drives AX2 at row-address time, which can be latched by
MRAS and A14 at column-address and data-valid times for all cycles. Driving A14 eases interfacing
to a BIA ROM.
Memory Cycle
MAX2
140
I/O
1Q
2Q
3Q
4Q
Signal
AX2
A14
A14
A14
Local-memory-extended address and parity — high byte. For the first quarter of a memory cycle,
MAXPH carries the extended-address bit AX1; for the second quarter of a memory cycle, it carries the
extended-address bit AX0; and for the last half of the memory cycle, it carries the parity bit for the high
data byte.
MAXPH
MAXPL
16
20
I/O
Memory Cycle
1Q
AX1
2Q
3Q
4Q
Parity
Signal
AX0
Parity
Local-memory-extended address and parity — low byte. For the first quarter of a memory cycle,
MAXPL carries the extended-address bit AX3; for the second quarter of a memory cycle, it carries
extended-address bit AX2; and for the last half of the memory cycle, it carries the parity bit for the low
data byte.
I/O
Memory Cycle
1Q
2Q
3Q
4Q
Signal
AX3
AX2
Parity
Parity
Local-bus clock 1 and local-bus clock 2. MBCLK1 and MBCLK2 are referenced for all local-bus
transfers. MBCLK2 lags MBCLK1 by a quarter of a cycle. These clocks operate according to:
MBCLK1
MBCLK2
123
124
MBCLK[1:2]
8 MHz
8 MHz
12 MHz
OSCIN
64 MHz
32 MHz
48 MHz
CLKDIV
O
H
L
L
Buffer enable. MBEN enables the bidirectional buffer outputs on the MADH, MAXPH, MAXPL, and
MADLbuses during the data phase. MBEN is used in conjunction with MDDIR, which selects the buffer
output direction.
MBEN
4
O
I/O
O
H = Buffer output disabled
L
= Buffer output enabled
MBGR
MBIAEN
MBRQ
18
Reserved; must be left unconnected.
Burned-in address enable. MBIAEN is an output signal used to provide an output enable for the ROM
containing the adapter’s burned-in address (BIA).
127
H = MBIAEN is driven high for any write accesses to the addresses between >00.0000 and
>00.000F, or any accesses (read/write) to any other address.
L
=
MBIAEN is driven low for any read from addresses between >00.0000 and >00.000F.
17
I/O
Reserved; must be pulled high (see Note 3).
†
I = input, O = output
NOTE 3: Each pin must be individually tied to V
with a 1-kΩ pullup resistor.
CC
6
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
I/O
NO.
Column-address strobe for DRAMs. The column address is valid for the 3/16 of the memory cycle
following the row-address portion of the cycle. MCAS is driven low every memory cycle while the
column address is valid on MADL0–MADL7, MAXPH, and MAXPL, except when one of the following
conditions occurs:
1) When the address accessed is in the BIA ROM (>00.0000 – >00.000F)
2) When the address accessed is in the EPROM memory map (i.e., when the BOOT bit in
the SIFACL register is zero and an access is made between >00.0010 – >00.FFFF
or >1F.0000 – >1F.FFFF)
MCAS
141
O
3) When the cycle is a refresh cycle, in which case MCAS is driven at the start of the cycle before
MRAS (for DRAMs that have CAS-before-RAS refresh). For DRAMs that do not support CAS-
before-RAS refresh, it may be necessary to disable MCAS with MREF during the refresh
cycle.
Datadirection. MDDIRisusedasadirectioncontrolforbidirectionalbusdrivers. MDDIRbecomesvalid
before MBEN becomes active.
MDDIR
138
I/O
H = TI380C25 memory-bus write
L
= TI380C25 memory-bus read
Memory output enable. MOE is used to enable the outputs of the DRAM memory during a read cycle.
MOE is high for EPROM or BIA ROM read cycles.
MOE
3
O
O
O
H = Disable DRAM outputs
L
= Enable DRAM outputs
Row-address strobe for DRAMs. The row address lasts for the first 5/16 of the memory cycle. MRAS
is driven low every memory cycle while the row address is valid on MADL0–MADL7, MAXPH, and
MAXPL for both RAM and ROM cycles. It is also driven low during refresh cycles when the refresh
address is valid on MADL0–MADL7.
MRAS
MREF
143
130
DRAM refresh cycle in progress. MREF is used to indicate that a DRAM refresh cycle is occurring. It
is also used for disabling MCAS to all DRAMs that do not use a CAS-before-RAS refresh.
H = DRAM refresh cycle in process
L
= Not a DRAM refresh cycle
Memory-bus reset. MRESET is a reset signal generated when either the ARESET bit in the SIFACL
register is set or SRESET is asserted. This signal is used for resetting external local-bus glue logic.
MRESET
125
O
H = External logic not reset
L
= External logic reset
ROM enable. During the first 5/16 of the memory cycle, MROMEN is used to provide a chip select for
ROMs when the BOOT bit of the SIFACL register is zero (i.e., when code is resident in ROM, not RAM).
It can be latched by MAL. MROMEN goes low for any read from addresses >00.0010 – >00.FFFF or
>1F.0000 – >1F.FFFF when the BOOT bit in the SIFACL register is zero. MROMEN stays high for
writes to these addresses, accesses of other addresses, or accesses of any address when the BOOT
bit is 1. During the final three quarters of the memory cycle, MROMEN outputs the A13 address signal
for interfacing to a BIA ROM. This means MBIAEN, MAX0, ROMEN, and MAX2 together form a
glueless interface for the BIA ROM.
MROMEN
133
O
H = ROM disabled
L
=
ROM enabled
†
I = input, O = output
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
†
DESCRIPTION
I/O
NAME
NO.
142
33
Local-memory write. MW is used to specify a write cycle on the local-memory bus. The data on the
MADH0–MADH7 and MADL0–MADL7 buses is valid while MW is low. DRAMs latch data on the
falling edge of MW, while SRAMs latch data on the rising edge of MW.
MW
NMI
O
I
H = Not a local-memory write cycle
L
= Local-memory write cycle
Nonmaskable interrupt request. NMI must be left unconnected.
External oscillator input. OSCIN provides the clock frequency to the TI380C25 for a 4-MHz or 6-MHz
internal bus (see Notes 5 and 6).
OSCIN
135
I
CLKDIV
OSCIN
H
L
64 MHz for a 4-MHz local bus
32 MHz for a 4-MHz local bus or 48 MHz for a 6-MHz local bus
Oscillator output
CLKDIV
L
OSCOUT
OSCOUT
PRTYEN
122
41
O
OSCIN / 4 (if OSCIN = 32 MHz, OSCOUT = 8 MHz;
if OSCIN = 48 MHz, OSCOUT = 12 MHz)
OSCIN/8 (if OSCIN = 64 MHz, OSCOUT = 8 MHz)
H
Parity enable. The value on PRTYEN is loaded into the PEN bit of the SIFACL register at reset (i.e.,
when SRESET is asserted or the ARESET bit in the SIFACL register is set) to form a default value.
PRTYEN enables parity checking for the local memory.
I
H = Local-memory data bus checked for parity (see Note 1).
L
= Local-memory data bus not checked for parity.
Network selection outputs. NSELOUT0 and NSELOUT1 are controlled by the host through the
correspondingbits of the SIFACL register. The value of these bits/signals can be changed only while
the TI380C25 is reset.
NSELOUT0
NSELOUT1
40
119
O
O
NSELOUT0
NSELOUT1
DESCRIPTION
16-Mbps token ring
4-Mbps token ring
L
H
H
H
SADH0
SADH1
SADH2
SADH3
SADH4
SADH5
SADH6
SADH7
97
96
95
94
93
92
86
85
System address/data bus—high byte (see Note 1).These lines make up the most significant byte
of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit
is SADH0, and the least significant bit is SADH7.
I/O
Address multiplexing: Bits 31 – 24 and bits 15 – 8
Data multiplexing: Bits 15 – 8
SADL0
SADL1
SADL2
SADL3
SADL4
SADL5
SADL6
SADL7
76
75
74
70
69
68
67
66
System address/data bus—low byte (see Note 1). These lines make up the least significant byte
of each address word (32-bit address bus) and data word (16-bit data bus). The most significant bit
is SADL0 and the least significant bit is SADL7.
I/O
Address multiplexing: Bits 23 – 16 and bits 7 – 0
Data multiplexing: Bits 7 – 0
†
I = input, O = output
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
5. Pin has an expanded input voltage specification.
6. A maximum of two TI380C25 devices can be connected to any one oscillator.
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
I/O
NO.
System address-latch enable. SALE is the enable pulse used to externally latch the 16 LSBs of the
addressfromtheSADH0 – SADH7andSADL0 – SADL7busesatthestartoftheDMAcycle. Systems
that implement address parity can also externally latch the parity bits (SPH and SPL) for the latched
address.
SALE
64
O
System bus busy. The TI380C25 samples the value on SBBSY during arbitration (see Note 1). The
sample has one of two values:
SBBSY
SBCLK
50
65
I
I
H = Not busy. The TI380C25 can become bus master if the grant condition is met.
L
= Busy. The TI380C25 cannot become bus master.
System bus clock. The TI380C25 requires SBCLK to synchronize its bus timings for all DMA transfers.
Valid frequencies are 2 MHz–33 MHz.
SBHE is used for system byte high enable. SBHE is a 3-state output driven during DMA;
it is an input at all other times.
Intel Mode
H = System byte high not enabled (see Note 1)
L
= System byte high enabled
SBHE/SRNW
79
I/O
SRNW is used for system read not write. SRNW serves as a control signal to indicate
a read or write cycle.
Motorola
Mode
H = Read cycle (see Note 1)
L
= Write cycle
System bus release. SBRLS indicates to the TI380C25 that a higher-priority device requires the
system bus. The value on SBRLS is ignored when the TI380C25 is not perfoming DMA. SBRLS is
internally synchronized to SBCLK.
SBRLS
49
I
H = The TI380C25 can hold onto the system bus (see Note 1).
L
=
The TI380C25 should release the system bus upon completion of current DMA cycle. If the
DMA transfer is not yet complete, the SIF rearbitrates for the system bus.
System chip select. SCS activates the system interface of the TI380C25 for a DIO read or write.
SCS
48
80
I
H = Not selected (see Note 1)
L
= Selected
System data-bus enable. SDBEN signals to the external data buffers to begin driving data. SDBEN
is activated during both DIO and DMA.
SDBEN
O
H = Keep external data buffers in the high-impedance state
L
= Cause external data buffers to begin driving data
System data direction. SDDIR provides the external data buffers with a signal indicating the direction
the data is moving. During DIO writes and DMA reads, SDDIR is low (data direction is into the
TI380C25).DuringDIOreadsandDMAwrites,SDDIRishigh(datadirectionisoutfromtheTI380C25).
When the system interface is not involved in a DIO or DMA operation, SDDIR is high by default.
SDDIR
59
O
DATA
SDDIR
H
L
DIRECTION
output
DIO
read
write
DMA
write
read
input
†
I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
†
DESCRIPTION
I/O
NAME
NO.
SHLDA is used for system-hold acknowledge. SHLDA indicates that the system DMA
hold request has been acknowledged. It is internally synchronized to SBCLK
(see Note 1).
Intel Mode
H = Hold request acknowledged
L
= Hold request not acknowledged
58
I
SHLDA/SBGR
SBGR is used for system bus grant. SBGR is an active-low bus grant, as defined in the
standard 68xxx interface, and is internally synchronized to SBCLK (see Note 1).
Motorola
Mode
H = System bus not granted
L
= System bus granted
SHRQ is used for system-hold request. SHRQ is used to request control of the system
bus in preparation for a DMA transfer. SHRQ is internally synchronized to SBCLK.
Intel Mode
H = System bus requested
L
= System bus not requested
78
O
SHRQ/SBRQ
SBRQ is used for system-bus request. SBRQ is used to request control of the system
bus in preparation for a DMA transfer. SBRQ is internally synchronized to SBCLK.
Motorola
Mode
H = System bus not requested
L
= System bus requested
System-interruptacknowledge.SIACKisfromthehostprocessortoacknowledgetheinterruptrequest
from the TI380C25.
SIACK
SI/M
43
56
I
I
H = System interrupt not acknowledged (see Note 1)
L
=
System interrupt acknowledged: The TI380C25 places its interrupt vector onto the system
bus.
System Intel/Motorola mode select. The value on SI/M specifies the system-interface mode.
H = Intel-compatible interface mode selected. Intel interface can be 8-bit or 16-bit mode
(see S8/SHALT description and Note 1).
L
=
Motorola-compatible interface mode selected. Motorola interface mode is always 16 bits.
SINTR is used for system-interrupt request. TI380C25 activates SINTR to signal an
interrupt request to the host processor.
Intel Mode
H = Interrupt request by TI380C25
No interrupt request
L
=
57
O
SINTR/SIRQ
SIRQ is used for system-interrupt request. TI380C25 activates SIRQ to signal an
interrupt request to the host processor.
Motorola
Mode
H = No interrupt request
L
= Interrupt request by TI380C25
System bus owned. SOWN indicates to external devices that TI380C25 has control of the system bus.
SOWN drives the enable signal of the bus-transceiver chips that drive the address and bus-control
signals.
SOWN
81
O
H = TI380C25 does not have control of the system bus.
L
= TI380C25 has control of the system bus.
†
I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
I/O
NO.
System parity high. The optional odd-parity bit for each address or data byte transmitted over
SADH0–SADH7 (see Note 1).
SPH
SPL
84
I/O
I/O
System parity low. The optional odd-parity bit for each address or data byte transmitted over
SADL0–SADL7 (see Note 1).
77
SRAS is used for system memory-address strobe (see Note 7). SRAS is used to latch
the SCS and SRSX – SRS2 register input signals. In a minimum-chip system, SRAS is
tied to the SALE output of the system bus. The latching capability can be defeated
because the internal latch for these inputs remains transparent as long as SRAS
remains high. This permits SRAS to be pulled high and the signals at SCS,
Intel Mode SRSX – SRS2, and SBHE to be applied independently of the SALE strobe from the
system bus. During DMA, SRAS remains an input.
H
L
= Transparent mode
= Holds latched values of SCS, SRSX–SRS2, and SBHE
60
I/O
SRAS/SAS
Falling edge = Latches SCS, SRSX – SRS2, and SBHE
SAS is used for sytem-memory address strobe (see Note 7). SAS is an active-low
address strobe that is an input during DIO (although ignored as an address strobe) and
an output during DMA.
Motorola
Mode
H = Address is not valid.
L
= Address is valid and a transfer operation is in progress.
SRDisusedforsystem-readstrobe(seeNote7). SRDistheactive-lowstrobeindicating
that a read cycle is performed on the system bus. SRD is an input during DIO and an
output during DMA.
Intel Mode
H = Read cycle is not occurring.
L
=
If DMA, host provides data to system bus.
If DIO, SIF provides data to system bus.
83
I/O
SRD/SUDS
SUDS is used for upper-data strobe (see Note 7). SUDS is the active-low upper-data
strobe. SUDS is an input during DIO and an output during DMA.
Motorola
Mode
H = Not valid data on SADH0–SADH7 lines
L
= Valid data on SADH0–SADH7 lines
SRDY is used for system bus ready (see Note 7). SRDY indicates to the bus master that
a data transfer is complete. SRDY is asynchronous but during DMA and pseudo-DMA
cycles, it is internally synchronized to SBCLK. During DMA cycles, SRDY must be
asserted before the falling edge of SBCLK in state T2 to prevent a wait state. SRDY is
an output when the TI380C25 is selected for DIO; otherwise; it is an input.
Intel Mode
H = System bus is not ready.
L
= Data transfer is complete; system bus is ready.
82
I/O
SRDY/SDTACK
SDTACK is used for system data-transfer acknowledge (see Note 7). The purpose of
SDTACK is to indicate to the bus master that a data transfer is complete. SDTACK is
internally synchronized to SBCLK. During DMA cycles, SDTACK must be asserted
before the falling edge of SBCLK in state T2 in order to prevent a wait state. SDTACK
is an output when the TI380C25 is selected for DIO; otherwise, it is an input.
Motorola
Mode
H = System bus is not ready.
L
= Data transfer is complete; system bus is ready.
†
I = input, O = output
NOTES: 1. Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to V
CC
with a 4.7-kΩ pullup resistor.
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
†
DESCRIPTION
I/O
NAME
NO.
System reset. SRESET is activated to place the TI380C25 into a known initial state. Hardware reset
puts most of the TI380C25 outputs into the high-impedance state and places all blocks into the reset
state. The Intel mode DMA bus-width selection (S8) is latched on the rising edge of SRESET.
SRESET
44
I
H
L
=
=
No system reset
System reset
Rising edge = Latch bus width for DMA operations (for Intel-mode applications)
SRSX and SRS0–SRS2 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS2 (see Note 1).
Intel Mode
MSb
LSb
Register selected = SRSX
SRS0
SRS1
SRS2/SBERR
SRSX, SRS0 and SRS1 are used for system-register select. These inputs select the
word or byte to be transferred during a system DIO access. The most significant bit is
SRSX and the least significant bit is SRS1 (see Note 1).
47
46
45
54
SRSX
SRS0
SRS1
SRS2/SBERR
I
MSb
LSb
Motorola
Mode
Register selected
=
SRSX
SRS0
SRS1
SBERRisusedforbuserror. Thissignalcorrespondstothebus-errorsignalofthe68xxx
microprocessor. SBERR is internally synchronized to SBCLK. This input is driven low
during a DMA cycle to indicate to the TI380C25 that the cycle must be terminated (see
Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s Guide
(SPWU005) for more information).
SWR is used for system-write strobe (see Note 7). SWR is an active-low write strobe
that is an input during DIO and an output during DMA.
Intel Mode
H = Write cycle is not occurring.
L
=
If DMA, data to be driven from SIF to host bus.
If DIO, on the rising edge, the data is latched and written to the selected register.
61
I/O
SWR/SLDS
SLDS is used for lower-data strobe (see Note 7). SLDS is an input during DIO and an
output during DMA.
Motorola
Mode
H = Not valid data on SADL0–SADL7 lines
L
= Valid data on SADL0–SADL7 lines
System-extended-address latch. SXAL provides the enable pulse used to externally latch the most
significant 16 bits of the 32-bit system address during DMA. SXAL is activated prior to the first cycle
of each block DMA transfer, and thereafter as necessary (whenever an increment of the DMA address
counter causes a carry out of the lower 16 bits). Systems that implement parity on addresses can use
SXAL to externally latch the parity bits (available on SPL and SPH) for the DMA address extension.
SXAL
63
O
I
SYNCIN
136
Reserved. SYNCIN must be left unconnected (see Note 1).
†
I = input, O = output
NOTES: 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
7. Pin should be tied to V
with a 4.7-kΩ pullup resistor.
CC
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
PIN
NAME
†
DESCRIPTION
I/O
NO.
S8 is used for system 8/16-bit bus select. S8 selects the bus width used for
communications through the system interface. On the rising edge of SRESET, the
TI380C25 latches the DMA bus width; otherwise, the value on S8 dynamically selects
the DIO bus width.
Intel Mode
H = Selects 8-bit mode (see Note 1)
51
I
S8/SHALT
L
= Selects 16-bit mode
SHALT is used for system halt/bus error retry. If SHALT is asserted along with SBERR,
the adapter retries the last DMA cycle. This is the rerun operation as defined in the 68xxx
specification. The BERETRY counter is not decremented by SBERR when SHALT is
asserted (see Section 3.4.5.3 of the TMS380 Second-Generation Token Ring User’s
Guide (SPWU005) for more information).
Motorola
Mode
37
55
126
Positive-supply voltage for digital logic. All V
power-supply plane.
pins must be attached to the common-system
DDL
V
V
I
I
DDL
9
34
72
Positive-supply voltage for output buffers. All V
power-supply plane.
pins must be attached to the common-system
DD
DD
89
106
137
39
87
117
144
Ground reference for output buffers (clean ground). All V
common-system ground plane.
pins must be attached to the
SSC
V
I
I
SSC
SSL
2
52
53
73
36
V
Groundreferencefordigitallogic.AllV
SSL
pinsmustbeattachedtothecommon-systemgroundplane.
108
128
129
11
19
62
91
V
SS
I
Ground connections for output buffers. All V pins must be attached to system ground plane.
SS
134
1
10
35
71
88
NC
These pins should be left unconnected.
90
107
109
†
I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
13
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
Token-Ring Media Interface
PIN
†
DESCRIPTION
I/O
NAME
NO.
DRVR
115
114
Differential-driver data output. DRVR and DRVR are the differential outputs that send the TI380C25
transmit data to the TMS38054 for driving onto the ring-transmit-signal pair.
O
O
DRVR
FRAQ
Frequency-acquisition control. FRAQ determines the use of frequency- or phase-acquisition mode in
the TMS38054.
111
H = Wide range. Frequency centering to PXTALIN by TMS38054.
L
= Narrow range. Phase lock onto the incoming data (RCVINA and RCVINB) by the TMS38054.
Insert-control signal to the TMS38054. NSRT enables the phantom-driver outputs (PHOUTA and
PHOUTB) of the TMS38054, through the watchdog timer, for insertion onto the token ring.
NSRT
112
118
O
I
Static high
Static low
NSRT low and pulsed high
=
=
=
Inactive, phantom current removed (due to watchdog timer)
Inactive, phantom current removed (due to watchdog timer)
Active, current output on PHOUTA and PHOUTB
Ring-interface clock-frequency control (see Note 5). At 16-Mbps ring speed, PXTALIN must be
supplied a 32-MHz signal. At 4-Mbps ring speed, PXTALIN must be 8 MHz and can be the output from
OSCOUT.
PXTALIN
Ring-interface recovered clock (see Note 5). RCLK is the clock recovered by the TMS38054 from the
token-ring received data. For 16-Mbps operation, RCLK is a 32-MHz clock; for 4-Mbps operation,
RCLK is an 8-MHz clock.
RCLK
RCVR
120
121
I
I
Ring-interface received data (see Note 5). RCVR contains the data received by the TMS38054 from
the token ring.
Ring-interface ready. REDY indicates the presence of received data as monitored by the TMS38054
energy-detect capacitor.
REDY
WFLT
110
113
I
I
H = Not ready. Ignore received data.
L
= Ready. Received data.
Wire-faultdetect. WFLTis an input to the TI380C25 driven by the TMS38054. WFLTindicates a current
imbalance of the TMS38054 PHOUTA and PHOUTB pins.
H = No wire fault detected
L
= Wire fault detected
Internal wrap select. WRAP is an output from the TI380C25 to the ring interface to activate an internal
attenuated feedback path from the transmitted data (DRVR) to receive data (RCVR) signals for
bring-up diagnostic testing. When active, the TMS38054 also cuts off the current drive to the
transmission pair.
WRAP
116
O
H = Normal ring operation
L
= Transmit data drives receive data (loopback).
†
I = input, O = output
NOTE 5: Pin has an expanded input-voltage specification.
14
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Pin Functions (Continued)
Token-Ring Media Interface
PIN
NAME
†
DESCRIPTION
I/O
NO.
Network select inputs. TEST0–TEST2 are used to select the network speed and type to be used by
the TI380C25. These inputs should be changed only during adapter reset. Connect TEST2 to V
TEST0 TEST1 TEST2 DESCRIPTION
.
DDL
TEST0
TEST1
TEST2
103
102
101
I
L
H
X
NC
NC
X
H
H
L
16-Mbps token ring
4-Mbps token ring
Reserved
TEST3
TEST4
TEST5
100
99
98
Test inputs. TEST3–TEST5 should be left unconnected (see Note 1). Module-in-place test mode is
achieved by tying TEST3 and TEST4 to ground. In this mode, all TI380C25 outputs are in the
high-impedance state. Internal pullups on all TI380C25 inputs are disabled (except TEST3–TEST5).
I
I
External fail-to-match signal. An enhanced-address-copy-option (EACO) device uses XFAIL to
indicateto the TI380C25 that it should not copy the frame nor set the ARI/FCI bits in a token-ringframe
due to an external address match.The ARI/FCI bits in a token-ring frame can be set due to an internal
address-matched frame. If an EACO device is not used, XFAIL must be left unconnected. XFAIL is
ignored when CAF mode is enabled [see table in XMATCH description (see Note 1)].
XFAIL
104
H = No address match by external address checker
L
= External address-checker-armed state
External match signal. An enhanced-address-copy-option (EACO) device uses XMATCH to indicate
to the TI380C25 to copy the frame and set the ARI/FCI bits in a token-ring frame. If an EACO device
is not used, XMATCH must be left unconnected. XMATCH is ignored when CAF mode is enabled
(see Note 1).
H = Address match recognized by external address checker
L
= External address-checker-armed state
XMATCH
105
I
XMATCH
XFAIL
FUNCTION
0
0
1
0
1
0
Armed (processing frame data)
Do not externally match the frame (XFAIL takes precedence).
Copy the frame
1
Hi-Z
1
Hi-Z
Do not externally match the frame (XFAIL takes precedence).
Reset state (adapter not initialized)
†
I = input, O = output
NOTE 1: Pin has an internal pullup device to maintain a high-voltage level when left unconnected (no etch).
15
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
architecture
The major blocks of the TI380C25 include the communications processor (CP), system interface (SIF), memory
interface (MIF), protocol handler (PH), clock generator (CG), and adapter-support function (ASF). The
functionality of each block is described in the following sections.
communications processor (CP)
The CP performs the control and monitoring of the other functional blocks in the TI380C25. The control and
monitoring protocols are specified by the software (downloaded or ROM based) in local memory. Available
protocols include:
•
•
•
Media access control (MAC) software
Logical link control (LLC) software
Copy all frames (CAF) software
The CP is a proprietary 16-bit central processing unit (CPU) with data cache and a single prefetch pipe for
pipelining of instructions. These features enhance the TI380C25 maximum performance capability to about 8
million instructions per second (MIPS) with an average of about 5 MIPS.
system interface (SIF)
The SIF performs the interfacing of the LAN subsystem to the host system. This interface may require additional
logic depending on the application. The system interface can transfer information/data using any of these three
methods:
•
•
•
Direct memory access (DMA)
Direct input/output (DIO)
Pseudo-direct memory access (PDMA)
DMA (or PDMA) is used to transfer all data to/from host memory from / to local memory. The main uses of DIO
are for loading the software to local memory and for initializing the TI380C25. DIO also allows command/status
interrupts to occur to and from the TI380C25.
The system interface can be hardware selected for either of two modes by use of SI / M. The mode selected
determines the memory organizations and control signals used. These modes are as follows:
•
The Intel 80x8x families: 8-, 16-, and 32-bit bus devices
The Motorola 68xxx microprocessor family: 16- and 32-bit bus devices
•
The system interface supports host-system memory addressing up to 32 bits (32-bit reach into the host-system
memory). This allows greater flexibility in using/accessing host-system memory. System designers can
customize the system interface to their particular bus by using one of the following:
•
Programmable burst transfers or cycle-steal DMA operations
Optional parity protection
•
These features are implemented in hardware to reduce system overhead, facilitate automatic rearbitration of
the bus after a burst, or repeat a cycle when errors occur (parity or bus). Bus retries are also supported.
The system-interface hardware also includes features to enhance the integrity of the TI380C25 and the data.
These features include the following:
•
•
•
Always internally maintain odd-byte parity regardless of parity being disabled
Monitor for the presence of a clock failure
Can switch SIF speeds from 2 MHz to 33 MHz
On every cycle, the system interface compares all the system clocks to a reference clock. If any of the clocks
become invalid, the TI380C25 enters the slow-clock mode, which prevents latch-up of the TI380C25. If the
SBCLK is invalid, any DMA cycle is terminated immediately; otherwise, the DMA cycle is completed and the
TI380C25 is placed in slow-clock mode.
16
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
system interface (SIF) (continued)
When the TI380C25 enters the slow-clock mode, the clock that failed is replaced by a slow free-running clock
and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the
TI380C25 must be reinitialized.
For DMA with a 16-MHz clock, a continuous transfer rate of 64 megabits per second (8 Mbps) can be obtained.
For DMA with a 25-MHz clock, a continuous transfer rate of 96 megabits per second (12 Mbps) can be obtained.
For DMA with a 33-MHz clock, a continuous transfer rate of 128 megabits per second (16 Mbps) can be
obtained. For 8-bit and 16-bit pseudo-DMA, the following data rates can be obtained:
LOCAL BUS SPEED
4 MHz
8-BIT PDMA
48 Mbps
16-BIT PDMA
64 Mbps
6 MHz
72 Mbps
96 Mbps
Since the main purpose of DIO is for downloading and initialization, the DIO transfer rate is not a significant
issue.
memory interface (MIF)
The MIF performs the memory management to allow the TI380C25 to address 2M bytes in local memory.
Hardware in the MIF allows the TI380C25 to be directly connected to DRAMs without additional circuitry. This
glueless-DRAM connection includes the DRAM refresh controller. The MIF also handles all internal bus
arbitration between these blocks. When required, the MIF then arbitrates for the external bus.
The MIF is responsible for the memory mapping of the CPU of a task. The memory maps of DRAMs, EPROMs,
burned-in addresses (BIA), and external devices are appropriately addressed when required by the system
interface, protocol handler, or for a DMA transfer.
The memory interface is capable of a 64-Mbps continuous transfer rate when using a 4-MHz local bus (64-MHz
device crystal) and a 96-Mbps continuous transfer rate when using a 6-MHz local bus.
protocol handler (PH)
The PH performs the hardware-based real-time protocol functions for a token-ring LAN. Network type is
determined by TEST0–TEST2. Token-ring network is determined by software and can be either 16 Mbps or
4 Mbps. These speeds are not fixed by the hardware but by the software.
The PH converts the parallel-transmit data to serial-network data of the appropriate coding and converts the
received serial data to parallel data. The PH data-management state machines direct the
transmission / reception of data to / from local memory through the MIF. The PH buffer-management state
machines automatically oversee this process, directly sending / receiving linked lists of frames without CPU
intervention.
The protocol handler contains many state machines that provide the following features:
•
•
•
•
•
•
•
Transmit and receive frames
Capture tokens
Provide token-priority controls
Manage the TI380C25 buffer memory
Provide frame-address recognition (group, specific, functional, and multicast)
Provide internal parity protection
Control and verify the PHY-layer circuitry-interface signals
Integrity of the transmitted and received data is assured by cyclic redundancy checks (CRC), detection of
network data violations, and parity on internal data paths. All data paths and registers are optionally parity
protected to assure functional integrity.
17
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
adapter-support function (ASF)
The ASF performs support functions not contained in the other blocks. The support functions are:
•
•
•
•
The TI380C25 base timer
Identification, management, and service of internal and external interrupts
Test-pin mode control, including the unit-in-place mode for board testing
Illegal state check (checks for illegal states such as parity and illegal opcodes)
clock generator (CG)
The CG performs the generation of all the internal clocks required by the other functional blocks, including the
local memory-bus clocks (MBCLK1, MBCLK2). The CG also generates the reference timer used to sample all
inputclocks(SBCLK, OSCIN, RCLK, andPXTALIN). Ifnotransitionisdetectedwithintheperiodofthereference
timer on any input clock signal, the CG places the TI380C25 into slow-clock mode. The frequency of the
reference timer is in the range of 10 kHz–100 kHz.
user-accessible hardware registers and TI380C25 internal pointers
The following tables show how to access internal data via pointers and how to address the registers in the host
interface. The SIFACL register, which directly controls device operation, is described in detail. The
adapter-internal pointers table on the following page is defined only after TI380C25 initialization and until the
OPEN command is issued. These pointers are defined by the TI380C25 software (microcode), and this table
describes the release 2.x of the TI380C25 software.
18
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
†
Adapter-Internal Pointers for Token Ring
ADDRESS
DESCRIPTION
Pointer to software raw microcode level in chapter 0
‡
>00.FFF8
‡
>00.FFFA
Pointer to starting location of copyright notices. Copyright notices are separated by a >0A character and
terminated by a >00 character in chapter 0.
>01.0A00
>01.0A02
>01.0A04
Pointer to burned-in address in chapter 1
Pointer to software level in chapter 1
Pointer to TI380C25 addresses in chapter 1:
Pointer + 0 node address
Pointer + 6 group address
Pointer + 10 functional address
>01.0A06
Pointer to TI380C25 parameters in chapter 1:
Pointer + 0 physical-drop number
Pointer + 4 upstream neighbor address
Pointer + 10 upstream physical-drop number
Pointer + 14 last ring-poll address
Pointer + 20 reserved
Pointer + 22 transmit access priority
Pointer + 24 source class authorization
Pointer + 26 last attention code
Pointer + 28 source address of the last received frame
Pointer + 34 last beacon type
Pointer + 36 last major vector
Pointer + 38 ring status
Pointer + 40 soft-error timer value
Pointer + 42 ring-interface error counter
Pointer + 44 local ring number
Pointer + 46 monitor error code
Pointer + 48 last beacon-transmit type
Pointer + 50 last beacon-receive type
Pointer + 52 last MAC-frame correlator
Pointer + 54 last beaconing-station UNA
Pointer + 60 reserved
Pointer + 64 last beaconing-station physical-drop number
>01.0A08
>01.0A0A
Pointer to MAC buffer (a special buffer used by the software to transmit adapter-generated MAC frames) in chapter 1
Pointer to LLC counters in chapter 1:
Pointer + 0 MAX_SAPs
Pointer + 1 open SAPs
Pointer + 2 MAX_STATIONs
Pointer + 3 open stations
Pointer + 4 available stations
Pointer + 5 reserved
>01.0A0C
>01.0A0E
Pointer to 4-/16-Mbps word flag. If zero, the adapter is set to run at 4 Mbps. If nonzero, the adapter is set to run at 16 Mbps.
Pointer to total TI380C25 RAM found in 1K bytes in RAM allocation test in chapter 1.
†
‡
This table describes the pointers for release 2.x of the TI380C25 software.
This address valid only for microcode release 2.x
19
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
User-Access Hardware Registers
†
80x8x 16-BIT MODE: (SI / M = 1, S8 / SHALT = 0)
NORMAL MODE
SBHE = 0
PSEUDO-DMA MODE ACTIVE
SBHE = 0
WORD TRANSFERS
SRS2 = 0
SRS2 = 0
SBHE = 0
BYTE TRANSFERS
SBHE = 1
SRS2 = 0
SBHE = 0
SRS2 = 1
SBHE = 1
SRS2 = 0
SRS2 = 1
SRSX
SRS0
SRS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SIFDAT MSB
SIFDAT LSB
SIFDAT / INC LSB
SIFADR LSB
SIFSTS
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SDMADAT MSB
DMALEN MSB
SDMAADR MSB
SDMAADX MSB
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SDMADAT LSB
DMALEN LSB
SDMAADR LSB
SDMAADX LSB
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SIFDAT / INC MSB
SIFADR MSB
SIFCMD
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
†
SBHE = 1 and SRS2 = 1 are not defined
80x8x 8-BIT MODE: (SI / M = 1, S8/SHALT = 1)
NORMAL MODE
SBHE = X
PSEUDO-DMA MODE ACTIVE
SBHE = X
SRSX
SRS0
SRS1
SRS2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SIFDAT LSB
SIFDAT MSB
SIFDAT/INC LSB
SIFDAT/INC MSB
SIFADR LSB
SIFADR MSB
SIFSTS
SDMADAT LSB
SDMADAT MSB
DMALEN LSB
DMALEN MSB
SDMAADR LSB
SDMAADR MSB
SDMAADX LSB
SDMAADX MSB
SIFACL LSB
SIFCMD
SIFACL LSB
SIFACL MSB
SIFADR LSB
SIFADR MSB
SIFADX LSB
SIFADX MSB
DMALEN LSB
DMALEN MSB
SIFACL MSB
SIFADR LSB
SIFADR MSB
SIFADX LSB
SIFADX MSB
DMALEN LSB
DMALEN MSB
‡
68xxx MODE: (SI/M = 0)
NORMAL MODE
PSEUDO-DMA MODE ACTIVE
SUDS = 0
WORD TRANSFERS
SUDS = 0
SLDS = 0
SLDS = 0
SUDS = 0
SLDS = 1
SUDS = 1
SLDS = 0
SUDS = 0
SLDS = 1
SUDS = 1
SLDS = 0
BYTE TRANSFERS
SRSX
SRS0
SRS1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
SIFDAT MSB
SIFDAT/INC MSB
SIFADR MSB
SIFCMD
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SIFDAT LSB
SIFDAT/INC LSB
SIFADR LSB
SIFSTS
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
SDMADAT MSB
DMALEN MSB
SDMAADR MSB
SDMAADX MSB
SIFACL MSB
SIFADR MSB
SIFADX MSB
DMALEN MSB
SDMADAT LSB
DMALEN LSB
SDMAADR LSB
SDMAADX LSB
SIFACL LSB
SIFADR LSB
SIFADX LSB
DMALEN LSB
‡
68xxx mode is always 16 bit.
20
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SIF adapter-control register (SIFACL)
The SIFACL register allows the host processor to control and to some extent reconfigure the TI380C25 under
software control.
SIFACL Register
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
E
S
T
0
T
E
S
T
1
T
E
S
T
2
NSEL
OUT0
NSEL
OUT1
—
SWHLDA SWDDIR SWHRQ PSDMAEN ARESET CPHALT BOOT
LBP
SINTEN
PEN
RW
–0
R
R
R
RP –0
R –u
R –0
RS –0
RW –0
RP –b
RP –b
RW –1
RP–p
RP– 0
RP–1
Legend:
R
W
P
S
–n
b
=
=
=
=
=
=
=
=
Read
Write
Write during ARESET = 1 only
Set only
Value after reset
Value on BTSTRP
Value on PRTYEN
Indeterminate
p
u
Bits 0–2:
Value on TEST0 and TEST2 pins
These bits are read only and always reflect the value on the corresponding device pins. This
allows the host S/W to determine speed configuration. If the network speed and type are
software configurable, these bits can be used to determine which configurations are supported
by the network hardware.
TEST0 TEST1 TEST2 Description
L
H
X
NC
NC
X
H
H
L
16-Mbps token ring
4-Mbps token ring
Reserved
Bit 3:
Bit 4:
Reserved. Read data is indeterminate.
SWHLDA — Software Hold Acknowledge
This bit allows the function of SHLDA / SBGR to be emulated from software control for
pseudo-DMA mode.
PSDMAEN
SWHLDA
SWHRQ
RESULT
†
0
X
0
0
1
X
0
1
X
SWHLDA value in the SIFACL register cannot be set to a one.
No pseudo-DMA request pending
†
1
†
1
Indicates a pseudo-DMA request interrupt
Pseudo-DMA process in progress
†
1
†
The value on SHLDA / SBGR is ignored.
21
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Bit 5:
SWDDIR — Current SDDIR Signal Value
This bit contains the current value of the pseudo-DMA direction. This enables the host to easily
determine the direction of DMA transfers, which allows system DMA to be controlled by system
software.
0
1
=
=
Pseudo DMA from host system to TI380C25
Pseudo DMA from TI380C25 to host system
Bit 6:
SWHRQ — Current SHRQ Signal Value
This bit contains the current value on SHRQ/SBRQ when in Intel mode, and the inverse of the
value on SHRQ/SBRQ when in Motorola mode. This enables the host to easily determine if a
pseudo-DMA transfer is requested.
INTEL MODE (SI/M = H)
= System bus not requested
= System bus requested
MOTOROLA MODE (SI/M = L)
System bus not requested
System bus requested
0
1
Bit 7:
Bit 8:
PSDMAEN — Pseudo-System-DMA Enable
This bit enables pseudo-DMA operation.
0
1
=
=
Normal bus-master DMA operation is possible.
Pseudo-DMA operation selected. Operation dependent on the values of the SWHLDA
and SWHRQ bits in the SIFACL register.
ARESET — Adapter Reset
This bit is a hardware reset of the TI380C25. This bit has the same effect as SRESET except
that the DIO interface to the SIFACL register is maintained. This bit is set to 1 if a clock failure
is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).
0
1
=
=
The TI380C25 operates normally.
The TI380C25 is held in the reset condition.
Bit 9:
CPHALT — Communications-Processor Halt
This bit controls the TI380C25 processor access to the internal TI380C25 buses. This prevents
the TI380C25 from executing instructions before the microcode has been downloaded.
0
1
=
=
The TI380C25 processor can access the internal TI380C25 buses.
The TI380C25 processor is prevented from accessing the internal adapter buses.
Bit 10:
BOOT — Bootstrap CP Code
This bit indicates whether the memory in chapters 0 and 31 of the local-memory space is RAM
or ROM/PROM/EPROM. This bit controls the operation of MCAS and MROMEN.
0
1
=
=
ROM/PROM/EPROM memory in chapters 0 and 31
RAM memory in chapters 0 and 31
22
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
Bit 11:
LBP — Local-Bus Priority
This bit controls the priority levels of devices on the local bus.
0
1
=
=
No external devices (such as TI380FPA) are used with the TI380C25.
An external device (such as TI380FPA) is used with the TI380C25. This allows the
external bus master to operate at the necessary priorities on the local bus.
If the system uses the TMS380SRA only, the bit must be set to 0. If the system uses both the
TMS380SRA and the TI380FPA, the bit must be set to 1.
Bit 12:
SINTEN — System-Interrupt Enable
This bit allows the host processor to enable or disable system-interrupt requests from the
TI380C25. The system-interrupt request from the TI380C25 is on SINTR/SIRQ. The following
equation shows how SINTR/SIRQ is driven. The table also explains the results of the states.
SINTR/SIRQ = (PSDMAEN * SWHRQ * !SWHLDA) + (SINTEN * SYSTEM_INTERRUPT)
SYSTEM
INTERRUPT
(SIFSTS
PSDMAEN
SWHRQ SWHLDA
SINTEN
RESULT
REGISTER)
†
†
†
1
1
1
1
1
1
0
X
X
X
1
1
0
X
X
X
1
Pseudo DMA is active.
The TI380C25 generated a system interrupt for a pseudo DMA.
Not a pseudo-DMA interrupt
0
0
X
X
X
X
X
X
X
The TI380C25 generates a system interrupt.
The TI380C25 does not generate a system interrupt.
The TI380C25 cannot generate a system interrupt.
0
0
0
X
†
The value on SHLDA / SBGR is ignored.
Bit 13:
PEN — Parity Enable
This bit determines whether data transfers within the TI380C25 are checked for parity.
0
1
=
=
Data transfers are not checked for parity.
Data transfers are checked for correct odd parity.
Bit 14 – 15: NSELOUT0, NSELOUT0 1 — Network-Selection Outputs
The values in these bits control NSELOUT0 and NSELOUT1. These bits can be modified only
while the ARESET bit is set.
These bits can be used to software configure a TI380C25 as follows: NSELOUT0 should be
connected to TEST0 (TEST1 should be left unconnected and TEST2 should be tied high).
NSELOUT0 and NSELOUT1 are used to select network speed as shown below:
NSELOUT0
NSELOUT1
SELECTION
Reserved
0
0
1
1
0
1
0
1
16-Mbps token ring
Reserved
4-Mbps token ring
At power up, these bits are set corresponding to 16-Mbps token ring (NSELOUT1 = 1,
NSELOUT0 = 0).
23
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SIFACL control for pseudo-DMA operation
Pseudo DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACL
register control of pseudo-DMA operation is shown in Figure 2.
Internal
Signals
Motorola Mode
Host
Interface
M
U
X
SINTR/SIRQ
SYSTEM_INTERRUPT
(SIFSTS register)
M
U
X
SHRQ/SBRQ
SHLDA/SBGR
DMA
Request
M
U
X
DMA
Grant
SDDIR
DMADIR
. . .
. . .
. . .
SWHLDA
SWDDIR
SWHRQ
PSDMAEN SINTEN
SIFACL Register
Figure 2. Pseudo-DMA Logic Related to SIFACL Bits
24
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Input voltage range, V (see Note 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 20 V
I
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 2 V to 7 V
Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.9 W
Operating free-air temperature range, T
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 8: Voltage values are with respect to V
.
SS
recommended operating conditions
MIN
4.75
0
NOM
MAX
5.25
0
UNIT
V
V
V
Supply voltage
5
0
DD
Supply voltage (see Note 9)
V
SS
TTL-level signal
OSCIN
2
V
V
V
+0.3
DD
DD
DD
V
High-level input voltage
2.4
2.6
–0.3
+0.3
+0.3
V
IH
RCLK, PXTALIN, RCVR
V
IL
Low-level input voltage, TTL-level signal (see Note 10)
High-level output current
0.8
–400
2
V
I
I
µA
mA
°C
°C
OH
High-level output current (see Note 11)
Operating free-air temperature
OL
T
A
0
70
T
C
Operating case temperature
100
NOTES: 9. All V
pins should be routed to minimize inductance to system ground.
SS
10. The algebraic convention, where the more negative (less positive) limit is designated as a minimum, is used for logic-voltage levels
only.
11. Output current of 2 mA is sufficient to drive five low-power Schottky TTL loads or ten advanced low-power Schottky TTL loads (worst
case).
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
‡
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage, TTL-level signal (see Note 12)
Low-level output voltage, TTL-level signal
V
V
V
V
= MIN,
= MIN,
= MAX,
= MAX,
I
I
= MAX
= MAX
= 2.4 V
= 0.4 V
2.4
OH
DD
DD
DD
DD
OH
0.6
20
V
OL
OL
V
V
O
I
O
High-impedance output current
µA
– 20
± 20
160
O
I
I
I
Input current, any input or input / output
Supply current
V = V
to V
DD
µA
mA
mA
pF
I
I
SS
V
= MAX
= 5 V
DD
SCM
DD
DD
Supply current, slow-clock mode
Input capacitance, any input
V
3
C
C
f = 1 MHz,
f = 1 MHz,
Others at 0 V
Others at 0 V
15
15
i
Output capacitance, any output or input/output
pF
o
‡
For conditions shown as MIN/MAX, use the appropriate value specified under the recommended operating conditions.
NOTE 12: The following signals require an external pullup resistor: SRAS/SAS, SRDY/SDTACK, SRD/SUDS, SWR/SLDS,
EXTINT0–EXTINT3, and MBRQ.
25
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
timing parameters
The timing parameters for all the signals of the TI380C25 are shown in the following tables and are illustrated
in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships
among the various signals. The parameters are numbered for convenience.
static signals
The following table lists signals that are not allowed to change dynamically and therefore have no timing
associated with them. They should be strapped high, low, or left unconnected as required.
SIGNAL
SI/M
FUNCTION
Host-processor select (Intel/Motorola)
Reserved
CLKDIV
BTSTRP
PRTYEN
TEST0
TEST1
TEST2
TEST3
TEST4
TEST5
Default-bootstrap mode (RAM/ROM)
Default-parity select (enabled/disabled)
Test terminal indicates network type
NC
Test terminal indicates network type
†
†
†
Test terminal for TI manufacturing test
Test terminal for TI manufacturing test
Test terminal for TI manufacturing test
†
For unit-in-place test
timing parameter symbology
Some timing parameter symbols have been created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the signal names and other related terminology have been abbreviated as shown
below:
DR
DRVR
DRVR
OSCIN
SBCLK
RS
SRESET
, V
DRN
OSC
SCK
VDD
V
DDL DD
Lower case subscripts are defined as follows:
c
d
h
w
cycle time
r
sk
su
t
rise time
delay time
skew
hold time
setup time
transition time
pulse duration (width)
The following additional letters and phrases are defined as follows:
H
L
High
Low
Valid
Z
High impedance
No longer high
No longer low
Falling edge
Rising edge
V
26
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
PARAMETER MEASUREMENT INFORMATION
Outputs are driven to a minimum high-logic level of 2.4 V and to a maximum low-logic level of 0.6 V. These levels
are compatible with TTL devices.
Output transition times are specified as follows: For a high-to-low transition on either an input or output signal,
the level at which the signal is said to be no longer high is 2 V and the level at which the signal is said to be low
is 0.8 V. For a low-to-high transition, the level at which the signal is said to be no longer low is 0.8 V and the level
at which the signal is said to be high is 2 V, as shown below.
TheriseandfalltimesarenotspecifiedbutareassumedtobethoseofstandardTTLdevices, whicharetypically
1.5 ns.
2 V (high)
0.8 V (low)
test measurement
The test-load circuit shown in Figure 3 represents the programmable load of the tester pin electronics that are
used to verify timing parameters of TI380C25 output signals.
Tester Pin
Electronics
I
OL
Output
Under
Test
V
LOAD
C
T
I
OH
Where: I
I
=
=
=
2 mA, dc-level verification (all outputs)
400 µA (all outputs)
1.5 V, typical dc-level verification or
0.7 V, typical timing verification
65 pF, typical load-circuit capacitance
OL
OH
LOAD
V
C
=
T
Figure 3. Test-Load Circuit
27
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing
NO.
MIN
NOM
MAX
1
UNIT
ms
ms
ms
ns
†
100
101
102
103
104
105
106
107
t
t
t
t
t
t
t
t
)
Rise time, 1.2 V to minimum V -high level
DD
r(VDD
†‡
†‡
Delay time, minimum V -highlevel to first valid SBCLK no longer high
DD
1
d(VDDH-SCKV)
d(VDDH-OSCV)
c(SCK)
Delay time, minimum V -high level to first valid OSCIN high
DD
1
Cycle time, SBCLK (see Note 13)
Pulse duration, SBCLK high
Pulse duration, SBCLK low
Transition time, SBCLK
30.3
13
500
500
500
2
ns
w(SCKH)
w(SCKL)
13
ns
†
ns
t(SCK)
Cycle time, OSCIN (see Note 14)
1/OSCIN
ns
c(OSC)
OSCIN = 64 MHz
5.5
8
108
109
t
Pulse duration, OSCIN high (see Note 15)
OSCIN = 48 MHz
OSCIN = 32 MHz
OSCIN = 64 MHz
OSCIN = 48 MHz
OSCIN = 32 MHz
ns
ns
w(OSCH)
w(OSCL)
8
5.5
8
t
Pulse duration, OSCIN low (see Note 15)
Transition time, OSCIN
8
†
110
t
t
t
t
t
t
t
3
1
ns
ms
ms
µs
µs
ns
ns
t(OSC)
†
111
117
118
119
288
289
Delay time, OSCIN valid to MBCLK1 and MBCLK2 valid
d(OSCV-CKV)
h(VDDH-RSL)
w(RSH)
†
†
†
Hold time, SRESET low after V
Pulse duration, SRESET high
Pulse duration, SRESET low
reaches minimum high level
5
14
14
10
10
DD
w(RSL)
†
†
Setup time, DMA size to SRESET high (Intel mode only)
Hold time, DMA size from SRESET high (Intel mode only)
su(RST)
h(RST)
CLKDIV = H
CLKDIV = L
2t
2t
c(OSC)
t
M
One-eighth of a local memory cycle
ns
c(OSC)
†
‡
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
If parameter 101 or 102 cannot be met, parameter 117 must be extended by the larger difference: real value of parameter 101 or 102 minus the
max value listed.
NOTES: 13. SBCLK can be any value between 2 MHz to 33 MHz. This data sheet describes the system interface (SIF) timing parameters for
the case of SBCLK at 25 MHz and at 33 MHz.
14. The value of OSCIN can be 64 MHz ±1%, 32 MHz ± 1%, or 48 MHz ± 1%. If OSCIN is used to generate PXTALIN, the OSCIN
tolerance must be ±0.01%.
15. This is to assure a ± 5% duty-cycle crystal, provided that OSCIN meets the recommended operating conditions for V and V
.
IL
IH
28
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
100
Minimum V -High Level
DD
V
DD
103
106
106
104
101
105
SBCLK
OSCIN
107
110
102
108
110
109
MBCLK1
MBCLK2
111
118
117
119
SRESET
288
289
S8/SHALT
NOTE A: In order to represent the information in one illustration, nonactual phase and timebase characteristics
are shown. Refer to specified parameters for precise information.
Figure 4. Timing for Power Up, System Clocks, SYNCIN, and SRESET
29
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: local-memory clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
1
MIN
4t
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Period of MBCLK1 and MBCLK2
M
2
Pulse duration, clock high
2t –9
M
3
Pulse duration, clock low
2t –9
M
4
Hold time, MBCLK2 low after MBCLK1 high
t
M
t
M
t
M
t
M
t
M
–9
–9
–9
–9
–9
5
Hold time, MBCLK1 high after MBCLK2 high
6
Hold time, MBCLK2 high after MBCLK1 low
7
Hold time, MBCLK1 low after MBCLK2 low
8
Setup time, address/enable on MAX0, MAX2, and MROMEN before MBCLK1 no longer high
Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no longer high
Setup time, address on MADH0–MADH7 before MBCLK1 no longer high
Setup time, MAL high before MBCLK1 no longer high
Setup time, address on MAX0, MAX2, and MROMEN before MBCLK1 no longer low
9
t
t
–14
–14
M
10
11
12
M
13
0.5t –9
M
Setup time, column address on MADL0–MADL7, MAXPH, and MAXPL before MBCLK1 no
longer low
13
0.5t –9
ns
M
14
Setup time, status on MADH0–MADH7 before MBCLK1 no longer low
Setup time, NMI valid before MBCLK1 low
0.5t –9
M
ns
ns
ns
ns
ns
120
121
126
129
30
0
Hold time, NMI valid after MBCLK1 low
Delay time, MBCLK1 no longer low to MRESET valid
Hold time, column address/status after MBCLK1 no longer low
0
20
t
M
–7
Reference
4 Periods
8 Periods
12 Periods
16 Periods
20 Periods
OSCIN
(when CLKDIV = 1)
OSCIN
(when CLKDIV = 0)
OSCOUT
†
†
MBCLK1
MBCLK2
†
MBCLK1 and MBCLK2 have no timing relationship to OSCOUT. MBCLK1 and MBCLK2 can start on any OSCIN rising edge, depending on when
the memory cycle starts execution.
Figure 5. Clock Waveforms After Clock Stabilization
30
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
M8
4
M1
M2
M3
M4
M5
M6
M7
M8
M1
1
t
M
3
MBCLK1
MBCLK2
6
2
1
5
8
7
3
2
12
MAX0,
MAX2,
MROMEN
ADD/EN
Address
9
13
Col
14
Status
MAXPH,
MAXPL,
MADL0–MADL7
Row
10
11
Address
MADH0–MADH7
MAL
129
120
121
NMI
Valid
126
Valid
MRESET
Figure 6. Memory-Bus Timing: Local-Memory Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and AD
DRESS
31
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: clocks, MRAS, MCAS, and MAL to ADDRESS
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
1.5t – 11.5
MAX
UNIT
Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer
high
15
ns
M
16
17
18
19
Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high
Delay time, MRAS no longer high to MRAS no longer high in the next memory cycle
Pulse duration, MRAS low
t
–6.5
ns
ns
ns
ns
M
8t
M
4.5t –5
M
Pulse duration, MRAS high
3.5t –5
M
Setup time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) before MCAS no longer high
20
21
22
0.5t –9
ns
ns
ns
M
Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) after MCAS low
t
M
–5
Hold time, column address (MADL0–MADL7, MAXPH, and MAXPL) and status
(MADH0–MADH7) after MRAS no longer high
2.5t –6.5
M
23
24
25
26
27
28
29
30
31
Pulse duration, MCAS low
3t –9
ns
ns
ns
ns
ns
ns
ns
ns
ns
M
Pulse duration, MCAS high, refresh cycle follows read or write cycle
Hold time, row address on MAXL0–MAXL7, MAXPH, and MAXPL after MAL low
Setup time, row address on MAXL0–MAXL7, MAXPH, and MAXPL before MAL no longer high
Pulse duration, MAL high
2t –9
M
1.5t –9
M
t
M
t
M
t
M
–9
–9
–9
Setup time, address/enable on MAX0, MAX2, and MROMEN before MAL no longer high
Hold time, address/enable of MAX0, MAX2, and MROMEN after MAL low
Setup time, address on MADH0–MADH7 before MAL no longer high
Hold time, address on MADH0–MADH7 after MAL low
1.5t –9
M
t
M
–9
1.5t –9
M
32
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
MAXPH,
MAXPL,
MADL0–MADL7
Column
Row
16
Column
Row
26
17
22
15
19
18
MRAS
21
23
24
20
MCAS
MAL
25
27
28
29
MAX0,
MAX2,
MROMEN
ADD/EN
Address
Address
21
30
31
20
Status
22
MADH0–MADH7
Address
Status
Figure 7. Memory-Bus Timing: Clocks, MRAS, MCAS, and MAL to ADDRESS
33
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: read cycle
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
MAX
6t – 23
UNIT
32
Access time, address/enable valid on MAX0, MAX2, and MROMEN to valid data/parity
ns
M
Access time, address valid on MAXPH, MAXPL, MADH0–MADH7, and MADL0–MADL7 to
valid data/parity
33
ns
6t –23
M
35
36
Access time, MRAS low to valid data/parity
4.5t –21.5
ns
ns
M
Hold time, valid data/parity after MRAS no longer low
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7 and
MADL0–MADL7 after MRAS high (see Note 16)
†
37
2t –10.5
M
ns
38
39
Access time, MCAS low to valid data/parity
3t –23
M
ns
ns
Hold time, valid data/parity after MCAS no longer low
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and
MADL0–MADL7 after MCAS high (see Note 16)
†
40
2t –13
M
ns
ns
ns
41
Delay time, MCAS no longer high to MOE low
t +13
M
Setup time, address/status in the high-impedance state on MAXPH, MAXPL,
MADL0–MADL7, and MADH0–MADH7 before MOE no longer high
†
42
0
43
44
45
46
Access time, MOE low to valid data/parity
Pulse duration, MOE low
2t –20
M
ns
ns
ns
ns
2t –9
M
Delay time, MCAS low to MOE no longer low
Hold time, valid data/parity in after MOE no longer low
3t –9
M
0
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and
MADL0–MADL7 after MOE high (see Note 16)
†
47
2t –15
M
ns
ns
ns
Setup time, address/status in the high-impedance state on MAXPH, MAXPL,
MADL0–MADL7, and MADH0–MADH7, before MBEN no longer high
†
48
0
0
Setup time, address/status in the high-impedance state on MAXPH, MAXPL,
MADL0–MADL7, and MADH0–MADH7 and before MBIAEN no longer high
†
48a
49
Access time, MBEN low to valid data/parity
Access time, MBIAEN low to valid data/parity
Pulse duration, MBEN low
2t –25
ns
ns
ns
ns
ns
ns
M
49a
50
2t –25
M
2t –9
M
50a
51
Pulse duration, MBIAEN low
2t –9
M
Hold time, valid data/parity after MBEN no longer low
Hold time, valid data/parity after MBIAEN no longer low
0
0
51a
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and
MADL0–MADL7 after MBEN high (see Note 16)
†
52
2t –15
ns
ns
M
Hold time, address in the high-impedance state on MAXPH, MAXPL, MADH0–MADH7, and
MADL0–MADL7 after MBIAEN high
†
52a
2t –15
M
53
54
55
Hold time, MDDIR high after MBEN high, read follows write cycle
Setup time, MDDIR low before MBEN no longer high
1.5t –12
ns
ns
ns
M
3t –5
M
Hold time, MDDIR low after MBEN high, write follows read cycle
3t –12
M
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 16: The data/parity that exists on the address lines will most likely reach the high-impedance state sometime later than the rising edge
of MRAS, MCAS, MOE, or MBEN (between MIN and MAX of timing parameter 36) and will be a function of the memory being read.
The MIN time given represents the time from the rising edge of MRAS, MCAS, MOE, or MBEN to the beginning of the next address,
and does not represent the actual high-impedance period on the address bus.
34
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
MAX0,
MAX2,
MROMEN
Address/
Enable
Address
Data/Parity
32
MAXPH, MAXPL,
MADH0–MADH7,
MADL0–MADL7
Address/
Status
Address
Address
33
36
37
35
MRAS
MCAS
38
39
40
43
45
41
42
46
47
44
MOE
49a
48a
51a
52a
50a
MBIAEN
49
51
52
48
50
MBEN
53
54
55
MDDIR
Figure 8. Memory-Bus Timing: Read Cycle
35
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: write cycle
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
58
60
63
64
65
66
67
69
70
71
72
73
Setup time, MW low before MRAS no longer low
Setup time, MW low before MCAS no longer low
Setup time, valid data/parity before MW no longer high
Pulse duration, MW low
t
M
1.5t –6.5
M
5.1
2.5t –9
M
Hold time, data/parity out valid after MW high
Setup time, address valid on MAX0, MAX2, and MROMEN before MW no longer low
Hold time, MRAS low to MW no longer low
0.5t –10.5
M
7t –11.5
M
5.5t –9
M
Hold time, MCAS low to MW no longer low
4t –11.5
M
Setup time, MBEN low before MW no longer high
Hold time, MBEN low after MW high
1.5t –13.5
M
0.5t –6.5
M
Setup time, MDDIR high before MBEN no longer high
Hold time, MDDIR high after MBEN high
2t –9
M
1.5t –12
M
MAX0,
MAX2,
MROMEN
Address/
Enable
Address
MAXPH, MAXPL,
MADH0–MADH7,
MADL0–MADL7
Address
ADD/STS
Data/Parity Out
MRAS
MCAS
58
60
65
63
64
MW
69
67
66
71
70
MBEN
72
73
MDDIR
Figure 9. Memory-Bus Timing: Write Cycle
36
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
memory-bus timing: DRAM-refresh timing
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
15
MIN
1.5t –11.5
MAX
UNIT
ns
Setup time, row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer high
Hold time, row address on MADL0–MADL7, MAXPH, and MAXPL after MRAS no longer high
Pulse duration, MRAS low
M
16
t
M
–6.5
ns
18
4.5t –5
ns
M
19
Pulse duration, MRAS high
3.5t –5
ns
M
73a Setup time, MCAS low before MRAS no longer high
73b Hold time, MCAS low after MRAS low
1.5t –11.5
ns
M
4.5t – 6.5
M
ns
73c Setup time, MREF high before MCAS no longer high
73d Hold time, MREF high after MCAS high
14
ns
t
M
–9
ns
Refresh
Address
MADL0–MADL7
Address
16
15
19
18
MRAS
73a
73b
MCAS
73c
73d
MREF
Figure 10. Memory-Bus Timing: DRAM-Refresh Cycle
XMATCH and XFAIL timing
t
is the cycle time of one-eighth of a local-memory cycle (31.25 ns minimum for a 4-MHz local bus or
M
20.83 ns minimum for a 6-MHz local bus).
NO.
MIN
7t
MAX
UNIT
ns
127 Delay time, status bit 7 high to XMATCH and XFAIL recognized
128 Pulse duration, XMATCH or XFAIL high
M
50
ns
Status
Bit 7
MADH7
127
128
XMATCH,
XFAIL
Figure 11. XMATCH and XFAIL Timing
37
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
token ring: ring-interface timing
NO.
MIN
TYP
125
MAX UNIT
4Mbps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
153
Period of RCLK (see Note 17)
16 Mbps
31.25
4 Mbps nominal: 62.5 ns
16 Mbps nominal: 15.625 ns
4 Mbps nominal: 62.5 ns
16 Mbps nominal: 15.625 ns
46
15
35
8
154L Pulse duration, RCLK low
154H Pulse duration, RCLK high
155
156
Setup time, RCVR valid before rising edge (1.8 V) of RCLK at 16 Mbps
Hold time, RCVR valid after rising edge (1.8 V) of RCLK at 16 Mbps
10
4
4 Mbps
40
8
158L Pulse duration, ring baud clock low
158H Pulse duration, ring baud clock high
16 Mbps
4 Mbps
40
8
16 Mbps
4 Mbps
125
165
Period of OSCOUT and PXTALIN (see Note 17)
Tolerance of PXTALIN input frequency (see Note 17)
16 Mbps (for PXTALIN only)
31.25
± 0.01
%
NOTE 17: This parameter is not tested but is required by the IEEE 802.5 specification.
153
154H
RCLK
RCVR
154L
156
155
Valid
158H
158L
OSCOUT,
PXTALIN
1.5 V
165
Figure 12. Ring-Interface Timing
38
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
token ring: transmitter timing
NO.
MIN MAX
UNIT
ns
DelayfromDRVRrisingedge(1.8V)toDRVR falling edge (1 V)orDRVRfalling
edge (1 V) to DRVR rising edge (1.8 V)
159
160
161
t
t
t
±2
sk(DR)
†
Delay from RCLK (or PXTALIN) falling edge (1 V) to DRVR rising edge (1.8 V) See Note 18
ns
d(DR)H
Delay from RCLK (or PXTALIN) falling edge (1 V) to DRVR falling edge
(1 V)
†
See Note 18
See Note 18
ns
d(DR)L
Delay from RCLK (or PXTALIN) falling edge (1 V) to DRVR falling edge
(1 V)
†
162
163
t
t
ns
ns
d(DRN)H
†
Delay from RCLK (or PXTALIN) falling edge (1 V) to DRVR rising edge (1.8 V) See Note 18
(DRN)L
td(DR)L td(DRN)H
td(DR)H td(DRN)L
DRVR / DRVR
asymmetry
164
±1.5
ns
–
2
2
†
When in active-monitor mode, the clock source is PXTALIN; otherwise, the clock source is either RCLK or PXTALIN.
NOTE 18: This parameter is not tested to a minimum or a maximum but is measured and used as a component required for parameter 164.
2.6 V
RCLK or PXTALIN
DRVR
1.5 V
0.6 V
2.4 V
1.5 V
0.6 V
160
161
159
159
2.4 V
1.5 V
0.6 V
DRVR
162
163
Figure 13. Skew and Asymmetry From RCLK or PXTALIN to DRVR and DRVR
39
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
15
MAX
MIN
15
MAX
255
256
Delay time, SRDY low to either SCS or SRD high
Pulse duration, SRAS high
ns
ns
30
30
Hold time, SAD in the high-impedance state after SRD low
(see Note 19)
†
259
260
261
0
0
0
0
ns
ns
ns
ns
ns
Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid before SRDY low
Delay time, SRD or SCS high to SAD in the high-impedance
state (see Note 19)
†
35
35
Hold time, output data valid after SRD or SCS high
(see Note 19)
261a
264
0
0
Setup time, SRSX, SRS0–SRS2, SCS, and SBHE valid to
SRAS no longer high (see Note 20)
30
30
Hold time, SRSX, SRS0–SRS2, SCS, and SBHE valid after
SRAS low
265
10
15
15
10
15
15
ns
ns
ns
266a
Setup time, SRAS high to SRD no longer high (see Note 20)
Setup time, SRSX, SRS0–SRS2 valid before SRD no longer
high (see Note 19)
‡
267
Hold time, SRSX, SRS0–SRS2 valid after SRD no longer low
(see Note 20)
268
0
0
ns
Setup time, SRD, SWR, and SIACK high from previous cycle
to SRD no longer high
272a
273a
275
t
t
t
t
ns
ns
ns
c(SCK)
c(SCK)
Hold time, SRD, SWR, and SIACK high after SRD high
c(SCK)
0
c(SCK)
0
Delay time, SRD and SWR, or SCS high to SRDY high
(see Note 19)
25
25
Delay time, SRD and SWR, high to SRDY in the
high-impedance state
†
279
0
0
t
0
0
t
ns
ns
c(SCK)
c(SCK)
282a
282R
Delay time, SDBEN low to SRDY low in a read cycle
t
t
/ 2 + 4
t
t
/ 2 + 4
c(SCK)
c(SCK)
Delay time, SRD low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1), provided previous cycle completed
0
t
+ 3
0
t
+ 3
ns
c(SCK)
c(SCK)
283R
286
Delay time, SRD high to SDBEN high (see Note 19)
0
/ 2 + 4
0
/ 2 + 4
ns
ns
c(SCK)
c(SCK)
Pulse duration, SRD high between DIO accesses
(see Note 19)
t
t
c(SCK)
c(SCK)
†
‡
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
NOTES: 19. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
20. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0 – SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
40
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS, SRSX,
SRS0–SRS2,
SBHE
†
Valid
Valid
264
268
265
SRAS
256
266a
267
SIACK
272a
273a
273a
SWR
SRD
272a
272a
273a
286
High
SDDIR
279
282R
283R
SDBEN
275
255
282a
‡
Hi-Z
Hi-Z
Hi-Z
SRDY
261
260
261a
259
SADH0–SADH7,
SADL0–SADL7,
Hi-Z
Output Data Valid
§
SPH, SPL
†
In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet
parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a and 264 are
irrelevant and parameter 268 must be met.
‡
§
When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input
of the data buffers.
In 8-bit 80x8x mode DIO reads, the SADH0–SADH7 contain don’t care data.
Figure 14. 80x8x DIO Read-Cycle Timing
41
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x DIO write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
15
MAX
MIN
15
MAX
255
256
Delay time, SRDY low to either SCS or SWR high
Pulse duration, SRAS high
ns
ns
30
30
Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL
valid before SCS or SWR no longer low
262
263
264
15
15
30
15
15
30
ns
ns
ns
Hold time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL
valid after SCS or SWR high
Setup time, SRSX, SRS0–SRS2, SCS, and SBHE to SRAS no
longer high (see Note 20)
Hold time, SRSX, SRS0–SRS2, SCS, and SBHE after SRAS
low
265
10
15
15
10
15
15
ns
ns
ns
266a
Setup time, SRAS high to SWR no longer high (see Note 19)
Setup time, SRSX, SRS0–SRS2 before SWR no longer high
(see Note 19)
†
267
Hold time, SRSX, SRS0–SRS2 valid after SWR no longer low
(see Note 20)
268
0
0
ns
Setup time, SRD, SWR, and SIACK high from previous cycle to
SWR no longer high
272a
273a
t
t
t
t
ns
ns
c(SCK)
c(SCK)
Hold time, SRD, SWR, and SIACK high after SWR high
c(SCK)
c(SCK)
Delay time, SRDY low in the first DIO access to the SIF register
to SRDY low in the immediately following access to the SIF (see
TMS380 Second-Generation Token Ring User’s Guide,
SPWU005, subsection 3.4.1.1.1)
‡
276
4000
25
4000
25
ns
275
Delay time, SWR or SCS high to SRDY high (see Note 19)
Delay time, SWR high to SRDY in the high-impedance state
Delay time, SWR low to SDDIR low (see Note 19)
If SIF register is
0
0
0
0
0
0
ns
ns
ns
§
279
t
t
c(SCK)
c(SCK)
280
t
t
/ 2 + 4
t
t
/ 2 + 4
c(SCK)
c(SCK)
ready (no waiting
required)
0
0
/ 2 + 4
0
0
/ 2 + 4
c(SCK)
c(SCK)
Delay time, SDBEN low to SRDY low (see
TMS380 Second Generation Token-Ring
282b
ns
User’s Guide, SPWU005, subsection
3.4.1.1.1)
If SIF register is
not ready (waiting
required)
4000
4000
282W Delay time, SDDIR low to SDBEN low
283W Delay time, SCS or SWR high to SDBEN no longer low
286 Pulse duration, SWR high between DIO accesses (see Note 19)
0
0
t
t
/ 2 + 4
/ 2 + 4
0
0
t
t
/ 2 + 4
/ 2 + 4
ns
ns
ns
c(SCK)
c(SCK)
c(SCK)
c(SCK)
t
t
c(SCK)
c(SCK)
†
‡
§
It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
NOTES: 19. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
20. In 80x8x mode, SRAS can be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
42
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS, SRSX,
SRS0–SRS2,
SBHE
Valid
264
268
265
SRAS
SIACK
SWR
256
266a
267
273a
272a
273a
286
272a
SRD
273a
272a
280
SDDIR
282W
283W
†
SDBEN
279
276
275
255
SRDY
282b
Hi-Z
Hi-Z
263
262
SADH0–SADH7,
SADL0–SADL7,
Hi-Z
Data
Hi-Z
‡
SPH, SPL
†
‡
When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input
of the data buffers.
In 8-bit 80x8x-mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.
Figure 15. 80x8x DIO Write-Cycle Timing
43
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x interrupt-acknowledge-cycle timing: first SIACK pulse
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
286
287
Pulse duration, SIACK high between DIO accesses (see Note 19)
Pulse duration, SIACK low on first pulse of two pulses
t
t
t
t
ns
ns
c(SCK)
c(SCK)
c(SCK)
c(SCK)
NOTE 19: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt acknowledge cycles.
SRD, SWR,
SCS
286
287
First
Second
SIACK
Figure 16. 80x8x Interrupt-Acknowledge-Cycle Timing: First SIACK Pulse
80x8x interrupt-acknowledge-cycle timing: second SIACK pulse
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255
Delay time, SRDY low to SCS high
15
15
ns
ns
ns
ns
Hold time, SAD in the high-impedance state after SIACK low
(see Note 19)
†
259
260
261
0
0
0
0
Setup time, output data valid before SRDY low
Delay time, SIACK high to SAD in the high-impedance state
(see Note 19)
†
35
35
261a
272a
273a
275
Hold time, output data valid after SIACK high (see Note 19)
Setup time, inactive data strobe high to SIACK no longer high
Hold time, inactive data strobe high after SIACK high
Delay time, SIACK high to SRDY high (see Note 19)
0
0
ns
ns
ns
ns
t
t
t
t
c(SCK)
c(SCK)
c(SCK)
0
c(SCK)
0
25
25
Delay time, SRDY low in the first DIO access to the SIF register
to SRDY low in the immediately following access to the SIF
‡
276
4000
4000
ns
†
279
Delay time, SIACK high to SRDY in the high-impedance state
Delay time, SDBEN low to SRDY low in a read cycle
0
0
t
0
0
t
ns
ns
c(SCK)
c(SCK)
282a
282R
283R
t
t
/ 2 + 4
t
/ 2 + 4
c(SCK)
c(SCK)
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1), provided previous cycle completed
0
t
+ 3
0
0
t
+ 3
ns
ns
c(SCK)
c(SCK)
Delay time, SIACK high to SDBEN high (see Note 19)
0
/ 2 + 4
t
/ 2 + 4
c(SCK)
c(SCK)
†
‡
This specification is provided as an aid to board design. It is not assured during manufacturing.
This specification has been characterized to meet stated value. It is not assured during manufacturing.
NOTE 19: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
44
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS, SRSX,
SRS0–SRS2,
SBHE
Only SCS needs to be inactive.
All others are don’t care.
SIACK
SWR
273a
273a
272a
272a
272a
SRD
273a
High
SDDIR
279
282R
283R
275
SDBEN
276
282a
255
†
SRDY
Hi-Z
259
Hi-Z
261
260
261a
SADH0–SADH7,
SADL0–SADL7,
Hi-Z
Output Data Valid
Hi-Z
‡
SPH, SPL
†
‡
SRDY is an active-low bus ready signal. It must be asserted before data output.
In 8-bit 80x8x mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.
Figure 17. 80x8x Interrupt-Acknowledge-Cycle Timing: Second SIACK Pulse
45
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode bus-arbitration timing, SIF takes control
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, asynchronous signal SBBSY and SHLDA before SBCLK no
longer high to assure recognition on that cycle
208a
10
10
ns
ns
ns
Hold time, asynchronous signal SBBSY and SHLDA after SBCLK low to
assure recognition on that cycle
208b
10
0
10
0
Delay time, SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and
SPL valid
212
20
20
224a
224c
230
Delay time, SBCLK low in cycle I2 to SOWN low
20
28
20
25
15
23
15
25
ns
ns
ns
ns
Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
Delay time, SBCLK high to SHRQ high
241
Delaytime, SBCLKhighinTXcycletoSRDand SWRhigh, busacquisition
Hold time, SRD and SWR in the high-impedance state after SOWN low,
bus acquisition
†
241a
t
t
ns
c(SCK)–15
c(SCK)–15
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
46
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
User Master
Bus Exchange
SIF Master
(T4)
I1
I2
TX
SIF Inputs:
SBCLK
208a
SBBSY,
SHLDA
208b
230
SIF Outputs:
SHRQ
241
SRD, SWR
SBHE
241a
212
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
Address
224c
Write
SDDIR
Read
224a
†
SOWN
†
While the system interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
Figure 18. 80x8x-Mode Bus-Arbitration Timing, SIF Takes Control
47
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode DMA read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, SADL0–SADL7, SADH0–SADH7,
205
206
SPH, and SPL valid before SBCLK in T3 cycle no
longer high
10
10
ns
Hold time, SADL0–SADL7, SADH0–SADH7, SPH,
and SPL valid after SBCLK low in T4 cycle if
parameters 207a and 207b not met
10
10
ns
Hold time, SADL0–SADL7, SADH0–SADH7, SPH,
and SPL valid after SRD high
207a
207b
0
0
0
0
ns
ns
Hold time, SADL0–SADL7, SADH0–SADH7, SPH,
and SPL valid after SDBEN no longer low
Setup time, asynchronous signal SRDY before
SBCLK no longer high to assure recognition on this
cycle
208a
10
10
10
10
ns
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on this cycle
208b
212
ns
ns
Delay time, SBCLK low to address valid
20
20
20
20
15
20
Delay time, SBCLK low in T1 cycle to
SADH0–SADH7, SADL0–SADL7, SPH, and SPL in
the high-impedance state
†
214
ns
216
Delay time, SBCLK high to SALE or SXAL high
Hold time, SALE or SXAL low after SRD high
ns
ns
216a
217
0
0
0
0
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
25
25
ns
ns
Hold time, SADH0–SADH7, SADL0–SADL7, SPH,
and SPL valid after SALE or SXAL low
218
t
–15
t
/2 – 4
t
–15
t
/2 – 4
w(SCKH)
c(SCK)
w(SCKH)
c(SCK)
Delay time, SBCLK low in T4 cycle to SRD high
(see Note 21)
223R
225R
0
16
0
11
ns
ns
Delay time, SBCLK low in T4 cycle to SDBEN high
16
15
11
15
Delay time, SADH0–SADH7, SADL0–SADL7,
SPH, and SPL in the high-impedance state to SRD
low
†
226
227R
0
0
0
0
0
0
ns
ns
ns
ns
ns
Delay time, SBCLK low in T2 cycle to SRD low
Hold time, SADH0–SADH7, SADL0–SADL7, SPH,
and SPL in the high-impedance state after SBCLK
low in T1 cycle
†
229
231
233
Pulse duration, SRD low
2t
–25
2t
–25
c(SCK)
c(SCK)
Setup time, SADH0–SADH7, SADL0–SADL7,
SPH, and SPL valid before SALE, SXAL no longer
high
10
10
237R
247
Delay time, SBCLK high in the T2 cyle to SDBEN low
16
11
ns
ns
Setup time, data valid before SRDY low if parameter
208a not met
0
0
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 21: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
48
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TWAIT
V
T4
TX
T1
T2
T3
T4
T1
SBCLK
SRAS
Hi-Z
212
†
SBHE
Valid
High
SWR
227R
223R
‡
SRD
218
216
217
216
217
SXAL
SALE
226
216a
212
233
207a
206
214
205
229
Address
233
218
212
SADH0–SADH7,
SADL0–SADL7,
Address
218
Data
§
SPH, SPL
247
Extended
Address
¶
207b
225R
208a
SRDY
208b
237R
‡
SDBEN
SDDIR
Low
†
‡
§
¶
In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held after T4 high.
If parameter 208A is not met, valid data must be present before SRDY goes low.
Figure 19. 80x8x-Mode DMA Read-Cycle Timing
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, asynchronous signal SRDY before
208a
SBCLK no longer high to assure recognition on that
cycle
10
10
ns
Hold time, asynchronous signal SRDY after SBCLK
low to assure recognition on that cycle
208b
212
10
10
ns
ns
Delay time, SBCLK low to SADH0–SADH7,
SADL0–SADL7, SPH, and SPL valid
20
20
20
20
216
Delay time, SBCLK high to SALE or SXAL high
Hold time, SALE or SXAL low after SWR high
ns
ns
216a
0
0
0
0
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
217
218
219
25
25
ns
ns
ns
Hold time, address valid after SALE, SXAL low
t
–15
–12
t
/2 – 4
t
–15
–12
t
/2 – 4
w(SCKH)
c(SCK)
w(SCKH)
c(SCK)
Delay time, SBCLK low in T2 cycle to output data and
parity valid
29
29
Hold time, SADH0–SADH7, SADL0–SADL7, SPH,
and SPL valid after SWR high
221
t
t
ns
c(SCK)
c(SCK)
223W
225W
Delay time, SBCLK low to SWR high
0
16
16
0
11
11
ns
ns
Delay time, SBCLK high in T4 cycle to SDBEN high
Hold time, SDBEN low after SWR, SUDS, and SLDS
high
225WH
227W
t
/2 – 7
t
/2 – 7
ns
ns
c(SCK)
c(SCK)
Delay time, SBCLK low in T2 cycle to SWR low
0
20
16
0
15
11
Setup time, SADH0–SADH7, SADL0–SADL7,
SPH, and SPL valid before SALE, SXAL no longer
high
233
10
10
ns
ns
237W
Delay time, SBCLK high in T1 cycle to SDBEN low
50
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TWAIT
V
T4
TX
T1
T2
T3
T4
T1
SBCLK
212
†
SBHE
Valid
High
SRD
223W
227W
SWR
216
217
217
SXAL
216
216a
SALE
212
233
218
233
SADL0–
SADH7,
SADH0–
SADL7,
221
218
212
219
Address
Output Data
‡
SPH, SPL
Extended Address
208a
SRDY
225W
237W
208b
225WH
SDBEN
SDDIR
High
†
‡
In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA.
In 8-bit 80x8x mode, the most significant byte of the address is maintained on SADH for T2, T3, and T4. The address is maintained according to parameter 21; i.e., held after T4 high.
Figure 20. 80x8x-Mode DMA Write-Cycle Timing
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode bus-arbitration timing, SIF returns control
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Delay time, SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH,
SRD, and SWR in the high-impedance state
†
220
35
35
ns
†
223b
224b
224d
230
Delay time, SBCLK low in I1 cycle to SBHE in the high-impedance state
Delay time, SBCLK low in cycle I2 to SOWN high
Delay time, SBCLK low in cycle I2 to SDDIR high
Delay time, SBCLK high in cycle I1 to SHRQ low
45
20
27
20
45
15
22
15
ns
ns
ns
ns
0
0
0
0
Setup time, SRD, SWR, and SBHE in the high-impedance state before SOWN no longer
low
†
240
ns
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
SIF Master
Bus Exchange
User Master
T3
T4
I1
I2
(T1)
(T2)
SBCLK
SHLDA
SIF Outputs:
230
†
SHRQ
220
240
SRD, SWR
Hi-Z
223b
SBHE
SIF
SIF
Hi-Z
Hi-Z
240
220
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
224d
224b
Write
Read
SDDIR
‡
SOWN
†
‡
In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it
controls. In68xxxmode, thesysteminterfacedeassertsSBRQontherisingedgeofSBCLKinstateT2ofthefirstsystembustransferitcontrols.
While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
Figure 21. 80x8x-Mode Bus-Arbitration Timing, SIF Returns Control
52
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
80x8x-mode bus-release timing
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, asynchronous input SBRLS low before SBCLK no longer high to assure
recognition
208a
10
10
ns
208b Hold time, asynchronous input SBRLS low after SBCLK low to assure recognition
208c Hold time, SBRLS low after SOWN high
10
0
10
0
ns
ns
T(W or 2)
T3
T4
T1
T2
SBCLK
208a
208b
SBRLS
(see Note A)
SOWN
208c
NOTES: A. The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the
assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has
internally started, the system interface releases the bus before starting another.
B. If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed regardless of the
value of SRDY. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface
releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA bus cycle
onthesystembus. WhenSBERRisproperlyassertedandBERETRYiszero, thesysteminterfacereleasesthebusuponcompletion
of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus and DMA stops
on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not defined after
a system-bus error.
C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer
and whenever the increment of the DMA address register carries beyond the least significant 16 bits.
D. SDTACK is not sampled to verify that it is deasserted.
E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,
the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
Figure 22. 80x8x-Mode Bus-Release Timing
53
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx DIO read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255
259
Delay time, SDTACK low to either SCS, SUDS, or SLDS high
15
15
ns
ns
Hold time, SAD in the high-impedance state after SUDS or SLDS
low (see Note 19)
†
†
0
0
0
0
Setup time, SADH0–SADH7, SADL0–SADL7, SPH, and SPL
valid before SDTACK low
260
261
ns
ns
Delay time, SCS, SUDS, or SLDS high to SADH0–SADH7,
SADL0–SADL7, SPH, and SPL in the high-impedance state
(see Note 19)
35
35
Hold time, output data valid after SUDS or SLDS no longer low
(see Note 19)
261a
267
268
272
0
15
0
0
15
0
ns
ns
ns
ns
Setup time, register address before SUDS or SLDS no longer
high (see Note 19)
Hold time, register address valid after SUDS or SLDS no longer
low (see Note 20)
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 19)
12
12
273
Hold time, SRNW after SUDS or SLDS high
0
0
ns
ns
273a
Hold time, SIACK high after SUDS or SLDS high
t
t
c(SCK)
c(SCK)
Delay time, SCS, SUDS, or SLDS high to SDTACK high
(see Note 19)
275
0
25
0
25
ns
ns
Delaytime, SDTACKlow inthe first DIO access to the SIF register
to SDTACK low in the immediately following access to the SIF
‡
276
279
4000
4000
Delay time, SUDS or SLDS high to SDTACK in the
high-impedance state
†
0
0
t
0
0
t
ns
ns
c(SCK)
c(SCK)
282a
282R
Delay time, SDBEN low to SDTACK low
t
t
/2 + 4
t
/2 + 4
c(SCK)
c(SCK)
Delay time, SUDS or SLDS low to SDBEN low (see TMS380
Second Generation Token-Ring User’s Guide, SPWU005,
subsection 3.4.1.1.1) provided the previous cycle completed
0
t
+ 3
0
t
+ 3
ns
c(SCK)
c(SCK)
283R
286
Delay time, SUDS or SLDS high to SDBEN high (see Note 19)
0
/2 + 4
0
t
/2 + 4
ns
ns
c(SCK)
c(SCK)
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 19)
t
t
c(SCK)
c(SCK)
†
‡
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTES: 19. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt acknowledge
cycles.
20. In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
54
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS, SRSX,
SRS0, SRS1
Valid
267
268
SIACK
SRNW
273a
272
273
SUDS,
SLDS
286
SDDIR
High
279
282R
283R
SDBEN
276
282a
275
255
†
SDTACK
Hi-Z
Hi-Z
Hi-Z
261
259
260
261a
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
Hi-Z
Output Data Valid
†
SDTACK is an active-low bus ready signal. It must be asserted before data output.
Figure 23. 68xxx DIO Read-Cycle Timing
55
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx DIO write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
15
MAX
MIN
15
MAX
255
262
263
Delay time, SDTACK low to either SCS, SUDS or SLDS high
Setup time, write data valid before SUDS or SLDS no longer low
Hold time, write data valid after SUDS or SLDS high
ns
ns
ns
15
15
15
15
Setup time, register address before SUDS or SLDS no longer
high (see Note 19)
†
267
268
272
15
0
15
0
ns
ns
ns
Hold time, register address valid after SUDS or SLDS no longer
low (see Note 20)
Setup time, SRNW before SUDS or SLDS no longer high
(see Note 19)
12
12
Setup time, inactive SUDS or SLDS high to active data strobe no
longer high
272a
273
t
t
t
t
ns
ns
ns
c(SCK)
c(SCK)
Hold time, SRNW after SUDS or SLDS high
0
0
Hold time, inactive SUDS or SLDS high after active data strobe
high
273a
c(SCK)
0
c(SCK)
0
Delay time, SCS, SUDS or SLDS high to SDTACK high
(see Note 19)
275
25
25
ns
ns
Delaytime, SDTACKlowinthefirstDIOaccesstotheSIFregister
to SDTACK low in the immediately following access to the SIF
‡
276
4000
4000
Delay time, SUDS or SLDS high to SDTACK in the
high-impedance state
§
279
280
0
0
t
0
0
t
ns
ns
c(SCK)
c(SCK)
Delay time, SUDS or SLDS low to SDDIR low (see Note 19)
If SIF register is
t
t
/2 + 4
/2 + 4
t
t
/2 + 4
/2 + 4
c(SCK)
c(SCK)
ready (no waiting
required)
0
0
0
0
c(SCK)
c(SCK)
Delay time, SDBEN low to SDTACK low
(see TMS380 Second Generation Token-
282b
ns
Ring User’s Guide, SPWU005, subsection
3.4.1.1.1)
If SIF register is
not ready (waiting
required)
4000
4000
282W
283W
Delay time, SDDIR low to SDBEN low
0
0
t
t
/2 + 4
0
0
t
t
/2 + 4
ns
ns
c(SCK)
c(SCK)
/2 + 4
c(SCK)
Delay time, SUDS or SLDS high to SDBEN no longer low
/2 + 4
c(SCK)
Pulse duration, SUDS or SLDS high between DIO accesses
(see Note 19)
286
t
t
ns
c(SCK)
c(SCK)
†
‡
§
It is the later of SRD and SWR or SCS low that indicates the start of the cycle.
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
NOTES: 19. The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge
cycles.
20. In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must
meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264. If SRAS is strapped high, parameters 266a
and 264 are irrelevant and parameter 268 must be met.
56
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS SRSX,
SRS0, SRS1
Valid
267
272
268
SIACK
273a
273
SRNW
SUDS,
†
286
272a
†
SLDS
273a
280
SDDIR
High
282W
283W
‡
SDBEN
279
276
275
255
§
Hi-Z
Hi-Z
SDTACK
263
282b
262
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
Hi-Z
Data
Hi-Z
†
For 68xxx mode, skew between SLDS and SUDS must not exceed 10 ns. Provided this limitation is observed, all events referenced to a data
strobe edge use the later occurring edge. Events defined by two data strobes edges, such as parameter 286, are measured between latest and
earlier edges.
‡
§
When the TMS380C25 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input
of the data buffers.
SDTACK is an active-low bus ready signal. It must be asserted before data output.
Figure 24. 68xxx DIO Write-Cycle Timing
57
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx interrupt-acknowledge-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
255
259
260
261
Delay time, SDTACK low to either SCS or SUDS, or SIACK high
15
15
ns
ns
ns
ns
Hold time, SAD in the high-impedance state after SIACK no
longer high (see Note 19)
†
†
0
0
0
0
Setup time, output data valid before SDTACK no longer high
Delay time, SIACK high to SAD in the high-impedance state
(see Note 19)
35
35
Hold time, output data valid after SCS or SIACK no longer low
(see Note 19)
261a
0
0
ns
ns
ns
Setup time, register address before SIACK no longer high
(see Note 19)
§
267
15
15
Setup time, inactive high SIACK to active data strobe no longer
high
272a
t
t
t
t
c(SCK)
c(SCK)
273a
275
Hold time, inactive SRNW high after active data strobe high
Delay time, SCS or SRNW high to SDTACK high (see Note 19)
ns
ns
c(SCK)
0
c(SCK)
0
25
25
Delaytime,SDTACKlowinthefirstDIOaccessto theSIFregister
to SDTACK low in the immediately following access to the SIF
‡
276
0
4000
0
4000
ns
†
279
Delay time, SIACK high to SDTACK in the high-impedance state
Delay time, SDBEN low to SDTACK low in a read cycle
0
0
t
0
0
t
ns
ns
c(SCK)
c(SCK)
282a
282R
t
t
/2 + 4
t
/2 + 4
c(SCK)
c(SCK)
Delay time, SIACK low to SDBEN low (see TMS380 Second
Generation Token-Ring User’s Guide, SPWU005, subsection
3.4.1.1.1) provided the previous cycle completed
0
t
+ 3
0
t
+ 3
ns
c(SCK)
c(SCK)
283R
286
Delay time, SIACK high to SDBEN high (see Note 19)
0
/2 + 4
0
t
/2 + 4
ns
ns
c(SCK)
c(SCK)
Pulseduration, SIACKhighbetweenDIOaccesses(seeNote19)
t
t
c(SCK)
c(SCK)
†
‡
§
This specification is provided as an aid to board design. It is not assured during manufacturing testing.
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
It is the later of SRD and SRD or SCS low that indicates the start of the cycle.
NOTE 19: The inactive chip select is SIACK in DIO read and DIO write cycles, and SCS is the inactive chip select in interrupt-acknowledge cycles.
58
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
SCS, SRSX,
SRS0, SRS1,
SBHE
Only SCS needs to be Inactive.
All others are don’t care.
267
SIACK
SRNW
286
272a
273a
SLDS
286
High
SDDIR
279
282R
283R
SDBEN
275
255
276
Hi-Z
282a
260
Hi-Z
†
SDTACK
261
259
261a
SADH0–SADH7,
SADL0–SADL7,
Hi-Z
Output Data Valid
Hi-Z
‡
SPH, SPL
†
‡
SDTACK is an active-low bus ready signal. It must be asserted before data output.
Internal logic drives SDTACK high and verifies that it has reached a valid high level before making it a 3-state signal.
Figure 25. 68xxx Interrupt-Acknowledge-Cycle Timing
59
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx-mode bus-arbitration timing, SIF takes control
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, asynchronous input SBGR before SBCLK no longer high to
assure recognition on this cycle
208a
10
10
ns
ns
Hold time, asynchronous input SBGR after SBCLK low to assure
recognition on this cycle
208b
10
10
212
Delay time, SBCLK low to address valid
0
0
20
20
28
20
25
0
0
20
15
23
15
25
ns
ns
ns
ns
ns
224a
224c
230
Delay time, SBCLK low in cycle I2 to SOWN low (see Note 22)
Delay time, SBCLK low in cycle I2 to SDDIR low in DMA read
Delay time, SBCLK high to either SHRQ low or SBRQ high
Delay time, SBCLK high in TX cycle to SUDS and SLDS high
241
Hold time, SUDS, SLDS, SRNW, and SAS in the high-impedance state
after SOWN low, bus acquisition
†
241a
t
t
ns
c(SCK)–15
c(SCK)–15
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 22: Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
60
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
User Master
Bus Exchange
SIF Master
T1
(T4)
I1
I2
TX
T2
SIF Inputs:
SBCLK
208b
208a
SBGR
SBERR,
SDTACK,
SBBSY
SIF Outputs:
230
230
†
SBRQ
208a
208b
241
241
SAS, SLDS,
SUDS
Output
Input
Read
Write
SRNW
212
SADH0–
SADH7,
SADL0–
SADL7,
Hi-Z
SIF
SPH, SPL
224c
224a
Write
Read
SDDIR
‡
241a
SOWN
†
‡
In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface
deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
Figure 26. 68xxx-Mode Bus-Arbitration Timing, SIF Takes Control
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx-mode DMA read-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, input data valid before SBCLK in T3
cycle no longer high
205
10
10
ns
ns
ns
ns
Hold time, input data valid after SBCLK low in T4
cycle if parameters 207a and 207b not met
206
10
0
10
0
Holdtime, inputdatavalidafterdatastrobenolonger
207a
low
Hold time, input data valid after SDBEN no longer
207b
low
0
0
Setup time, asynchronous input SDTACK before
208a
SBCLK no longer high to assure recognition on this
cycle
10
10
10
ns
Hold time, asynchronous input SDTACK after
SBCLK low to assure recognition on this cycle
208b
209
10
ns
ns
t
+
–18
t
+
–18
c(SCK)
w(SCKL)
c(SCK)
w(SCKL)
Pulse duration, SAS, SUDS, and SLDS high
t
t
Delay time, SBCLK high in T2 cycle to SUDS and
SLDS active
210
212
16
20
20
20
11
20
15
20
ns
ns
ns
ns
ns
Delay time, SBCLK low to address valid
Delay time, SBCLK low in T2 cycle to SAD in the
high-impedance state
†
214
216
Delay time, SBCLK high to SALE or SXAL high
Hold time, SALE or SXAL low after SUDS and SAS
high
216a
217
0
0
0
0
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
25
25
ns
218
222
Hold time, address valid after SALE, SXAL low
Delay time, SBCLK high to SAS low
t
–15
t
/2 – 4
c(SCK)
20
t
–15
t
/2 – 4
c(SCK)
15
ns
ns
w(SCKH)
w(SCKH)
Delay time, SBCLK low in T4 cycle to SUDS, SLDS,
and SAS high (see Note 23)
223R
225R
0
16
16
0
11
11
ns
ns
ns
Delay time, SBCLK low in T4 cycle to SDBEN high
Hold time, SAD in the high-impedance state after
SBCLK low in T4 cycle
†
229
0
0
Setup time, address valid before SALE or SXAL no
longer high
233
10
10
ns
ns
ns
233a
237R
t
–15
t
–15
Setup time, address valid before SAS no longer high
w(SCKL)
w(SCKL)
Delay time, SBCLK high in the T2 cycle to SDBEN
low
16
11
Setup time, data valid before SDTACK low if
parameter 208a not met
247
0
0
ns
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
NOTE 23: While the system-interface DMA controls are active (i.e., SOWN is asserted), SCS is disabled.
62
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TWAIT
V
T4
TX
T1
T2
T3
T4
T1
S1
222
210
S2
S3
S4
S5
S6
S7
SBCLK
†
SAS
209
209
223R
SUDS,
SLDS
218
217
High
217
216
SRNW
SXAL
216
218
216a
SALE
229
212
233a
212
206
205
233
233
214
207a
SADL0–SADH7,
SADH0–SADL7,
SPH, SPL
Address
Data In
Hi-Z
Extended Address
‡
247
207b
208a
§¶
SDTACK
208b
SDDIR
237R
225R
†
SDBEN
†
On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data may be removed when either the read strobe or SDBEN becomes
no longer active.
‡
§
¶
If parameter 208a is not met, valid data must be present before SDTACK goes low.
Motorola-style bus slaves hold SDTACK active until the bus master deasserts SAS.
All V
SS
pins should be routed to minimize inductance to system ground.
Figure 27. 68xxx-Mode DMA Read-Cycle Timing
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx-mode DMA write-cycle timing
25-MHz OPERATION
33-MHz OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Setup time, asynchronous input SDTACK before
208a
SBCLK no longer high to assure recognition on this
cycle
10
10
ns
Holdtime, asynchronousinputSDTACKafterSBCLK
low to assure recognition on this cycle
208b
209
10
10
ns
ns
ns
ns
t
+
–18
t
+
c(SCK)
w(SCKL)
c(SCK)
w(SCKL)
Pulse duration, SAS, SUDS, and SLDS high
t
t
t
t
–18
–15
Delay time, SBCLK high in T2 cycle to SUDS and
SLDS active
211
25
25
Delay time, output data valid to SUDS and SLDS no
longer high
211a
–15
w(SCKL)
w(SCKL)
212
216
Delay time, SBCLK low to address valid
20
20
20
20
ns
ns
Delay time, SBCLK high to SALE or SXAL high
Hold time, SALE or SXAL low after SUDS and SAS
high
216a
0
0
0
0
ns
Delay time, SBCLK high to SXAL low in the TX cycle
or SALE low in the T1 cycle
217
218
219
25
25
ns
ns
ns
Hold time, address valid after SALE, SXAL low
t
–15
–12
t
/2 – 4
t
–15
–12
t
/2 – 4
w(SCKH)
c(SCK)
w(SCKH)
c(SCK)
Delay time, SBCLK low in T2 cycle to output data and
parity valid
29
29
Hold time, output data, parity valid after SUDS and
SLDS high
221
t
t
ns
ns
ns
c(SCK)
c(SCK)
222
Delay time, SBCLK high to SAS low
20
16
16
15
11
11
Delay time, SBCLK low to SUDS, SLDS, and SAS
high
223W
225W
0
0
Delay time, SBCLK high in T4 cycle to SDBEN high
ns
ns
225WH Hold time, SDBEN low after SUDS and SLDS high
t
/2 – 7
t
/2 – 7
c(SCK)
c(SCK)
Setup time, address valid before SALE or SXAL no
longer high
233
10
10
ns
233a
t
–15
t
–15
ns
ns
Setup time, address valid before SAS no longer high
Delay time, SBCLK high in T1 cycle to SDBEN low
w(SCKL)
w(SCKL)
237W
16
11
64
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TWAIT
V
T4
TX
T1
T2
T3
T4
T1
SBCLK
SAS
222
211
223W
209
233a
SUDS,
SLDS
218
216
211a
217
SRNW
Low
217
218
SXAL
SALE
216
216a
212
212
233
221
233
219
SADL0–SADH7,
SADH0–SADL7,
SPL, SPH
Address
Output Data
208a
Extended Address
†‡
SDTACK
208b
225W
225WH
SDDIR
237W
SDBEN
†
‡
All V
SS
pins should be routed to minimize inductance to system ground.
On a read cycle, the read strobe remains active until the internal sample of incoming data is completed. Input data can be removed when either the read strobe or SDBEN becomes
no longer active.
Figure 28. 68xxx-Mode DMA Write-Cycle Timing
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx-mode bus-arbitration timing, SIF returns control
25-MHz
25-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
Delay time, SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS in the
high-impedance state, bus release
†
220
35
35
ns
†
223b
224b
224d
230
Delay time, SBCLK low in I1 cycle to SBHE/SRNW in the high-impedance state
Delay time, SBCLK low in cycle I2 to SOWN high
45
20
27
20
45
15
22
15
ns
ns
ns
ns
0
0
0
0
Delay time, SBCLK low in cycle I2 to SDDIR high
Delay time, SBCLK high to either SHRQ low or SBRQ high
Setup from, SUDS, SLDS, SRNW, and SAS control signals in the high-impedance state
before SOWN no longer low
†
240
ns
†
This specification has been characterized to meet stated value. It is not assured during manufacturing testing.
66
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
SIF Master
Bus Exchange
I1
User
T1
T2
T3
T4
I2
SIF Inputs:
SBCLK
SBGR
SDTACK
SIF Outputs:
230
†
SBRQ
220
240
SAS, SUDS,
SLDS
240
223b
Read
Hi-Z
SRNW
Write
SIF
220
SADH0–SADH7,
SADL0–SADL7,
SPH, SPL
Hi-Z
224d
224b
Write
Read
SDDIR
SOWN
†
In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface
deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
Figure 29. 68xxx-Mode Bus-Arbitration Timing, SIF Returns Control
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
68xxx-mode bus-release and error timing
25-MHz
33-MHz
OPERATION
OPERATION
NO.
UNIT
MIN
MAX
MIN
MAX
208a Setup time, asynchronous input before SBCLK no longer high to assure recognition
10
10
ns
ns
Hold time, asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to assure
208b
10
10
recognition
208c Hold time, SBRLS low after SOWN high
0
0
ns
ns
236
Setup time, SBERR low before SDTACK no longer high if parameter 208a not met
30
30
T(W or 2)
208a
T3
T4
T1
T2
SBCLK
SBRLS
208b
(see Note A)
208b
SOWN
208c
208a
SBERR
(see Note B)
236
SDTACK
NOTES: A. The system interface ignores the assertion of SBRLS if it does not own the system bus. If it does own the bus, when it detects the
assertion of SBRLS, it completes any internally started DMA cycle and relinquishes control of the bus. If no DMA transfer has
internally started, the system interface releases the bus before starting another.
B. If SBERR is asserted when the system interface controls the system bus, the current bus transfer is completed regardless of the
value of SDTACK. If the BERETRY register is nonzero, the cycle is retried. If the BERETRY register is zero, the system interface
releases control of the system bus. The system interface ignores the assertion of SBERR if it is not performing a DMA bus cycle
onthesystembus. WhenSBERRisproperlyassertedandBERETRYiszero, thesysteminterfacereleasesthebusuponcompletion
of the current bus transfer and halts all further DMA on the system side. The error is synchronized to the local bus, and DMA stops
on the local sides. The value of the SDMAADR, SDMADDRX, and SDMALEN registers in the system interface are not defined after
a system-bus error.
C. In cycle-steal mode, state TX is present on every system bus transfer. In burst mode, state TX is present on the first bus transfer
and whenever the increment of the DMA address register carries beyond the least significant 16 bits.
D. SDTACK is not sampled to verify that it is deasserted.
E. Unless otherwise specified, for all signals specified as a maximum delay from the end of an SBCLK transition to the signal valid,
the signal is also specified to hold its previous value (including high impedance) until the start of that SBCLK transition.
Figure 30. 68xxx-Mode Bus-Release and Error Timing
68
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
TH
T1
T1
T(W or 2)
T3
T4
SBCLK
SDTACK
SBERR
SHALT
†
Figure 31. 68xxx-Mode Bus Halt and Retry, Normal Completion With Delayed Start
†
Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown.
T1
T2
T3
T4
TH
TH
T1
B
E
SBCLK
SDTACK
SBERR
SHALT
SOWN
†
Figure 32. 68xxx-Mode Bus Halt and Retry, Rerun Cycle With Delayed Start
†
Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement can vary from waveforms shown.
69
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443
TI380C25
TOKEN-RING COMMPROCESSOR
SPWS012 – JANUARY 1995
MECHANICAL DATA
PGE (S-PQFP-G144)
PLASTIC QUAD FLATPACK
108
73
109
72
0,27
0,17
M
0,08
0,50
0,13 NOM
144
37
1
36
Gage Plane
17,50 TYP
20,20
SQ
19,80
0,25
0,05 MIN
22,20
SQ
0°– 7°
21,80
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040147/B 10/94
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
70
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IMPORTANT NOTICE
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相关型号:
TI380C27PGE
1 CHANNEL(S), 20Mbps, LOCAL AREA NETWORK CONTROLLER, PQFP144, PLASTIC, QFP-144
ROCHESTER
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