TIBPAL16L8-15MJB [TI]
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| 型号： | TIBPAL16L8-15MJB |
| 厂家： | 
TEXAS INSTRUMENTS |
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TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C
TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
TIBPAL16L8’
High-Performance Operation:
Propagation Delay
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
C Suffix . . . 15 ns Max
M Suffix . . . 20 ns Max
Functionally Equivalent, but Faster Than
PAL16L8A, PAL16R4A, PAL16R6A, and
PAL16R8A
I
V
CC
O
1
2
3
4
5
6
7
8
9
10
20
19
18
17
I
I
I/O
I/O
I
Power-Up Clear on Registered Devices (All
Register Outputs Are Set High, but Voltage
Levels at the Output Pins Go Low)
I
16 I/O
15
14
13
12
11
I
I/O
I/O
I/O
O
I
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to
Plastic and Ceramic DIPs
I
I
GND
I
Dependable Texas Instruments Quality and
Reliability
TIBPAL16L8’
3-STATE
O
OUTPUTS
REGISTERED
Q
OUTPUTS
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
I
I/O
PORTS
DEVICE
INPUTS
PAL16L8
PAL16R4
10
8
2
0
6
4
4 (3-state
buffers)
0
3
2
1 20 19
18
6 (3-state
buffers)
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
4
5
6
7
8
PAL16R6
PAL16R8
8
8
0
0
2
0
17
16
15
14
8 (3-state
buffers)
9 10 11 12 13
description
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT circuits combine the latest Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses to provide reliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows for
quick design of custom functions and typically
results in a more compact circuit board. In
addition, chip carriers are available for further
reduction in board space.
The TIBPAL16’ C series is characterized from 0°C
to 75°C. The TIBPAL16’ M series is characterized
for operation over the full military temperature
range of –55°C to 125°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
These devices are covered by U.S. Patent 4,410,987.
IMPACT is a trademark of Texas Instruments.
PAL is a registered trademark of Advanced Micro Devices Inc.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C
TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
TIBPAL16R4’
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
CC
I/O
I
I
I
I
I
I
I
I
3
2
1 20 19
18
18 I/O
I/O
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Q
Q
Q
Q
17
16
15
14
Q
Q
Q
9 10 11 12 13
13 I/O
12 I/O
GND
11
OE
TIBPAL16R6’
TIBPAL16R6’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
CLK
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
I
I
I
I
I
I
I
I
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
3
2
1 20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND 10
TIBPAL16R8’
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J OR W PACKAGE
(TOP VIEW)
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
CLK
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
OE
3
2
1 20 19
18
I
I
I
I
I
Q
Q
Q
Q
Q
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-15C, TIBPAL 16R4-15C
TIBPAL 16L8-20M, TIBPAL 16R4-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
functional block diagrams (positive logic)
TIBPAL16L8’
≥ 1
&
EN
O
7
32 × 64
O
7
7
7
7
7
7
16 ×
I/O
I/O
I/O
I/O
I/O
I/O
10
16
16
I
6
7
6
TIBPAL16R4’
OE
CLK
EN 2
C1
I = 1
≥ 1
Q
Q
Q
Q
2
&
8
32 × 64
1D
8
8
8
16 ×
8
16
16
I
4
≥ 1
EN
7
I/O
I/O
I/O
I/O
4
7
7
7
4
4
denotes fused inputs
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16R6-15C, TIBPAL 16R8-15C
TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
I = 1
&
8
32 × 64
≥ 1
Q
Q
Q
Q
Q
Q
2
1D
8
8
16 ×
8
16
16
I
8
8
8
6
2
≥ 1
EN
7
I/O
I/O
7
2
6
TIBPAL16R8’
OE
CLK
EN 2
C1
I = 1
≥ 1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
32 × 64
1D
8
8
8
8
8
8
8
16 ×
8
16
16
I
8
8
denotes fused inputs
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-15C
TIBPAL 16L8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
logic diagram (positive logic)
1
I
Increment
16
First
Fuse
0
4
8
12
20
24
28
31
Numbers
0
32
64
96
19
18
17
16
15
14
13
O
128
160
192
224
2
3
4
5
6
7
8
9
I
256
288
320
352
384
416
448
480
I/O
I/O
I/O
I/O
I/O
I/O
I
I
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
I
I
I
I
I
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I
Fuse number = First fuse number + Increment
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16R4-15C
TIBPAL 16R4-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
logic diagram (positive logic)
1
CLK
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
I/O
Q
128
160
192
224
2
I
256
288
320
352
384
416
448
480
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 1
1D
C1
768
800
832
864
896
928
960
992
I = 1
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I/O
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16R6-15C
TIBPAL 16R6-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
logic diagram (positive logic)
1
CLK
Increment
16
First
Fuse
Numbers
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
128
160
192
224
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
256
288
320
352
384
416
448
480
I = 1
1D
Q
C1
512
544
576
608
640
672
704
736
I = 1
1D
Q
C1
768
800
832
864
896
928
960
992
I = 1
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 1
1D
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16R8-15C
TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
logic diagram (positive logic)
1
CLK
Increment
First
Fuse
Numbers
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
224
I = 1
1D
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
C1
2
3
4
5
6
7
8
9
I
I
I
I
I
I
I
I
256
288
320
352
384
416
448
480
I = 1
1D
C1
512
544
576
608
640
672
704
736
I = 1
1D
C1
768
800
832
864
896
928
960
992
I = 1
1D
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 1
1D
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 1
1D
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 1
1D
C1
1792
1824
1856
1888
1920
1952
1984
2016
I = 1
1D
12
11
Q
C1
OE
Fuse number = First fuse number + Increment
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
IH
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
8
50
High
Low
t
w
Pulse duration, clock (see Note 2)
ns
9
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
15
0
ns
ns
°C
su
h
T
0
25
75
A
NOTE 2: Thetotalclockperiodofclockhighandclocklowmustnotexceedclockfrequency, f
clock high or low only, but not for both simultaneously.
. Theminimumpulsedurationsspecifiedarefor
clock
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-15C, TIBPAL 16R4-15C, TIBPAL 16R6-15C, TIBPAL 16R8-15C
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
2.4
3.3
OH
OL
OH
OL
I
0.35
0.5
20
Outputs
I/O ports
Outputs
I/O ports
I
V
= 5.25 V,
= 5.25 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
OZL
CC
CC
O
O
100
–20
–250
0.1
I
V
V
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
V = 5.5 V
I
mA
µA
I
V = 2.7 V
I
20
IH
IL
V = 0.4 V
I
–0.2
–125
180
mA
mA
mA
‡
V
O
= 2.25 V
–30
O
V = 0,
I
Outputs open
140
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
The output conditions have been chosen to produce a current that closely approximates one-half of the short-circuit output current, I
.
OS
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
f
t
t
t
t
t
t
50
10
8
MHz
ns
max
I, I/O
CLK↑
OE↓
O, I/O
Q
15
12
12
10
15
15
pd
ns
pd
R1 = 500 Ω,
R2 = 500 Ω,
See Figure 3
Q
8
ns
en
OE↑
Q
7
ns
dis
en
I, I/O
I, I/O
O, I/O
O, I/O
10
10
ns
ns
dis
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
NOTE 1: These ratings apply, except for programming pins, during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
IH
V
IL
I
I
f
mA
mA
MHz
OH
OL
clock
12
0
10
11
41.6
High
Low
t
w
Pulse duration, clock (see Note 2)
ns
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
20
0
ns
ns
°C
su
h
T
–55
25
125
A
NOTE 2: Thetotalclockperiodofclockhighandclocklowmustnotexceedclockfrequency, f
clock high or low only, but not for both simultaneously.
. Theminimumpulsedurationsspecifiedarefor
clock
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
3.2
OH
OL
OH
OL
I
0.25
0.4
20
Outputs
I
I
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
OZL
I
O
O
I/O ports
Outputs
100
–20
–250
0.2
V
I/O ports
Pin 1, 11
All others
Pin 1, 11
I/O ports
All others
I/O ports
All others
V = 5.5 V
I
mA
0.1
50
I
IH
V
CC
= 5.5 V,
V = 2.7 V
I
100
20
µA
–0.25
–0.2
–250
190
I
IL
V
CC
= 5.5 V,
V = 0.4 V
I
mA
‡
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 0.5 V
O
–30
mA
mA
OS
CC
V = 0,
I
Outputs open
140
CC
CC
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set V at 0.5 V to avoid
test-equipment degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITIONS
MIN TYP
MAX
UNIT
f
t
t
t
t
t
t
41.6
MHz
ns
max
I, I/O
CLK↑
OE↓
O, I/O
Q
10
8
20
15
15
15
20
20
pd
ns
pd
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 4
Q
8
ns
en
OE↑
Q
7
ns
dis
en
I, I/O
I, I/O
O, I/O
O, I/O
10
10
ns
ns
dis
†
All typical values are at V
= 5 V, T = 25°C.
A
CC
12
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TIBPAL 16L8-20M, TIBPAL 16R4-20M, TIBPAL 16R6-20M, TIBPAL 16R8-20M
HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic also is available, upon request, from the nearest TI field sales office or local authorized TI
distributor, by calling Texas Instruments at +1 (972) 644–5580, or by visiting the TI Semiconductor Home Page
at www.ti.com/sc.
preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 V and Pin 1 at V , raise Pin 11 to V
.
IHH
CC
IL
Apply either V or V to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 11 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
V
IHH
Pin 11
Pin 1
IL
t
t
d
su
t
t
w
d
V
V
IH
IL
V
V
V
V
IH
OH
Input
Output
Registered I/O
IL
OL
NOTE 3:
t
d
= t = t = 100 ns to 1000 ns V = 10.25 V to 10.75 V
su IHH
h
Figure 1. Preload Waveforms
13
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HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
power-up reset (see Figure 2)
Following power up, all registers are set high. This feature provides extra flexibility to the system designer and
is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is important
that the rise of V
all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not occur until
CC
5 V
4 V
V
CC
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active-Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
14
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HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
7 V
S1
R1
From Output
Under Test
Test
Point
C
L
(see Note A)
R2
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3.5 V
3.5 V
0.3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0.3 V
t
w
t
h
t
su
3.5 V
3.5 V
0.3 V
Low-Level
Data
Input
1.3 V
1.3 V
Pulse
0.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
Output
Control
(low-level
enabling)
1.3 V
1.3 V
0.3 V
3.5 V
0.3 V
t
Input
en
1.3 V
1.3 V
t
dis
t
t
t
pd
≈3.5 V
pd
pd
Waveform 1
S1 Closed
(see Note B)
V
OL
+ 0.3 V
1.3 V
V
V
OH
In-Phase
Output
1.3 V
1.3 V
1.3 V
V
OL
OL
t
dis
t
t
pd
en
V
V
OH
Waveform 2
S1 Open
(see Note B)
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
– 0.3 V
1.3 V
OH
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t .
pd en dis
L
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol.Waveform
2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2 ns, duty cycle = 50%
r
f
D. When measuring propagation delay times of 3-state outputs from low to high, switch S1 is closed.
When measuring propagation delay times of 3-state outputs from high to low, switch S1 is open.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
15
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SRPS019A – FEBRUARY 1984 – REVISED APRIL 2000
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
L
(see Note A)
R2
LOAD CIRCUIT FOR 3-STATE OUTPUTS
3 V
0
3 V
High-Level
Pulse
Timing
Input
1.5 V
1.5 V
1.5 V
1.5 V
1.5 V
0
t
w
t
h
t
su
3 V
0
3 V
0
Low-Level
Pulse
Data
Input
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Control
(low-level
enabling)
1.5 V
1.5 V
0
3 V
0
t
Input
en
1.5 V
1.5 V
t
dis
t
t
t
≈3.3 V
pd
pd
pd
Waveform 1
S1 Closed
(see Note B)
V
OL
+ 0.5 V
1.5 V
V
V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
V
OL
OL
t
dis
t
t
pd
en
V
V
OH
Waveform 2
S1 Open
(see Note B)
Out-of-Phase
Output
(see Note D)
V
V
OH
1.5 V
– 0.5 V
1.5 V
OH
≈0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t .
pd en dis
L
B. Waveform1isforanoutputwithinternalconditionssuchthattheoutputislowexceptwhendisabledbytheoutputcontrol.Waveform
2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, t = t ≤ 2 ns, duty cycle = 50%
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 4. Load Circuit and Voltage Waveforms
16
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Copyright 2000, Texas Instruments Incorporated
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