TIBPAL16L8-7MFK [TI]
HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS; 高性能Impact -X é PAL电路
| 型号： | TIBPAL16L8-7MFK |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-PERFORMANCE IMPACT-X E PAL CIRCUITS |
| 文件： | 总30页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL16L8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
•
High-Performance Operation:
f
f
f
(no feedback)
TIBPAL16R’ -5C Series . . . 125 MHz Min
TIBPAL16R’ -7M Series . . . 100 MHz Min
(internal feedback)
TIBPAL16R’ -5C Series . . . 125 MHz Min
TIBPAL16R’ -7M Series . . . 100 MHz Min
max
(TOP VIEW)
max
I
I
I
I
I
I
I
I
I
V
1
2
3
4
5
6
7
8
9
10
20
19
18
CC
O
I/O
(external feedback)
max
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
TIBPAL16R’ -5C Series . . . 117 MHz Min
TIBPAL16R’ -7M Series . . . 74 MHz Min
Propagation Delay
TIBPAL16L8-5C Series . . . 5 ns Max
TIBPAL16L8-7M Series . . . 7 ns Max
TIBPAL16R’ -5C Series
12
11
O
I
GND
(CLK-to-Q) . . . 4 ns Max
TIBPAL16R ’ -7M Series
(CLK-to-Q) . . . 6.5 ns Max
•
•
•
Functionally Equivalent, but Faster than,
Existing 20-Pin PLDs
TIBPAL16L8’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
Preload Capability on Output Registers
Simplifies Testing
(TOP VIEW)
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
•
•
Package Options Include Both Plastic and
Ceramic Chip Carriers in Addition to Plastic
and Ceramic DIPs
3
2
1
20 19
18
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Security Fuse Prevents Duplication
I/O
PORT
S
9 10 11 12 13
I
3-STATE
REGISTERED
Q OUTPUTS
DEVICE
INPUTS O OUTPUTS
’PAL16L8
’PAL16R4
’PAL16R6
’PAL16R8
10
8
2
0
0
0
0
6
4
2
0
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
8
8
Pin assignments in operating mode
description
These programmable array logic devices feature high speed and functional equivalency when compared with
currently available devices. These IMPACT-X circuits combine the latest Advanced Low-Power Schottky
technology with proven titanium-tungsten fuses to provide reliable, high-performance substitutes for
conventional TTL logic. Their easy programmability allows for quick design of custom functions and typically
results in a more compact circuit board.
The TIBPAL16’ C series is characterized from 0°C to 75°C. The TIBPAL16’ M series is characterized for
operation over the full military temperature range of –55°C to 125°C.
These devices are covered by U.S. Patent 4,410,987.
IMPACT-X is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
This documentcontains informationonproducts inmore thanone phase
of development. The status of each device is indicated on the page(s)
specifying its electrical characteristics.
Copyright 1992, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
TIBPAL16R4’
TIBPAL16R4’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
CC
I
I
I
I
I
I
I
I
I/O
I/O
Q
Q
Q
3
2
1
20 19
18
I/O
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
Q
Q
Q
Q
9 10 11 12 13
13 I/O
12 I/O
11 OE
GND
TIBPAL16R6’
TIBPAL16R6’
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
CC
I
I
I
I
I
I
I
I
19 I/O
3
2
1
20 19
18
18
17
16
15
14
13
12
11
Q
Q
Q
Q
Q
Q
I/O
OE
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
TIBPAL16R8’
TIBPAL16R8’
C SUFFIX . . . J OR N PACKAGE
M SUFFIX . . . J PACKAGE
C SUFFIX . . . FN PACKAGE
M SUFFIX . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
CLK
V
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
CC
I
I
I
I
I
I
I
I
Q
Q
Q
Q
Q
Q
Q
Q
3
2
1
20 19
18
Q
Q
Q
Q
Q
I
I
I
I
I
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
11 OE
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL16L8-5C, TIBPAL16R4-5C
TIBPAL16L8-7M, TIBPAL16R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL16L8’
≥1
&
EN
O
7
32 X 64
O
7
7
7
7
7
7
7
16 x
I/O
I/O
I/O
I/O
I/O
I/O
10
16
16
I
6
6
TIBPAL16R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
32 X 64
1D
8
8
8
16 x
8
16
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
16
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
functional block diagrams (positive logic)
TIBPAL16R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
32 X 64
1D
16 x
8
16
16
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL16R8’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
32 X 64
1D
8
8
8
8
8
8
8
16 x
8
16
16
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL16L8-5C
TIBPAL16L8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
I
INCREMENT
16
FIRST
FUSE
NUMBERS
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I/O
I/O
I/O
I/O
I/O
I/O
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
12
11
O
I
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL16R4-5C
TIBPAL16R4-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
INCREMENT
FIRST
FUSE
NUMBERS
0
4
8
12
16
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
I/O
Q
128
160
192
224
2
I
256
288
320
352
384
416
448
480
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I/O
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL16R6-5C
TIBPAL16R6-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
INCREMENT
16
FIRST
FUSE
NUMBERS
0
4
8
12
20
24
28
31
0
32
64
96
19
18
17
16
15
14
13
I/O
128
160
192
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
Q
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
Q
C1
768
800
832
864
896
928
960
992
I = 0
1D
Q
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
Q
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
Q
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
Q
C1
1792
1824
1856
1888
1920
1952
1984
2016
12
11
I/O
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL16R8-5C
TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
logic diagram (positive logic)
1
CLK
INCREMENT
FIRST
FUSE
NUMBERS
0
4
8
12
16
20
24
28
31
0
32
64
96
128
160
192
I = 0
1D
19
18
17
16
15
14
13
Q
Q
Q
Q
Q
Q
Q
C1
224
2
I
256
288
320
352
384
416
448
480
I = 0
1D
C1
3
4
5
6
7
8
9
I
I
I
I
I
I
I
512
544
576
608
640
672
704
736
I = 0
1D
C1
768
800
832
864
896
928
960
992
I = 0
1D
C1
1024
1056
1088
1120
1152
1184
1216
1248
I = 0
1D
C1
1280
1312
1344
1376
1408
1440
1472
1504
I = 0
1D
C1
1536
1568
1600
1632
1664
1696
1728
1760
I = 0
1D
C1
1792
1824
1856
1888
1920
1952
1984
2016
I = 0
1D
12
11
Q
C1
OE
Fuse number = First fuse number + Increment
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL16L8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
V
0.8
V
IL
I
I
–3.2
24
mA
mA
°C
OH
OL
Low-level output current
T
A
Operating free-air temperature
0
25
75
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
V
OH
OL
OH
OL
I
0.3
0.5
100
V
‡
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
pF
pF
OZH
O
‡
= 0.4 V
–100
100
OZL
O
V = 5.5 V
I
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–250
–130
180
IL
§
V
O
= 0.5 V
–30
–70
OS
V = 0,
I
Outputs open
CC
C
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
8.5
10
i
V
O
= 2 V
o
†
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
I/O leakage is the worst case of I
and I or I
and I , respectively.
OZH IH
OZL
IL
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16L8-5CJ
TIBPAL16L8-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL16L8-5CN
PARAMETER
UNIT
MIN
MAX
MIN
MAX
with up to 4 outputs
switching
I, I/O
I, I/O
O, I/O
O, I/O
1.5
5
1.5
5
t
ns
pd
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
with more than 4
outputs switching
1.5
5
1.5
5.5
t
t
I, I/O
I, I/O
O, I/O
O, I/O
2
2
7
7
2
2
7
7
ns
ns
en
dis
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL16R4-5C, TIBPAL16R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
4
125
High
Low
ns
t
w
Pulse duration, clock
4
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
4.5
0
ns
ns
°C
su
h
T
0
25
75
A
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL16R4-5C, TIBPAL16R6-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
IK
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
V
OH
OL
OH
I
0.3
0.5
100
V
OL
‡
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
OZH
O
‡
= 0.4 V
–100
100
OZL
O
V = 5.5 V
I
I
‡
V = 2.7 V
I
25
IH
‡
V = 0.4 V
I
–250
–130
200
IL
§
V
O
= 0.5 V
–30
–70
OS
V = 0,
I
Outputs open
CC
I
7
5
pF
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
C
C
i
CLK/OE
I/O
10
7
V
O
= 2 V
pF
o
Q
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16R4-5CJ
TIBPAL16R6-5CJ
TIBPAL16R4-5CN
TIBPAL16R6-5CN
TIBPAL16R4-5CFN
TIBPAL16R6-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
without feedback
125
125
¶
f
with internal feedback (counter configuration)
with external feedback
125
125
MHz
max
117
111
t
t
t
t
t
t
t
t
t
t
CLK↑
CLK↑
I, I/O
OE↓
Q
1.5
4
3.5
5
1.5
4.5
3.5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
pd
pd
pd
en
dis
en
dis
r
Internal feedback
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
I/O
Q
1.5
1.5
1
1.5
1.5
1
6
6
OE↑
Q
6.5
7
7
I, I/O
I, I/O
I/O
I/O
2
2
7
2
7
2
7
1.5
1.5
0.5
1.5
1.5
0.5
f
#
Skew between registered outputs
= 5 V, T = 25°C.
sk(o)
†
‡
§
All typical values are at V
CC
I/O leakage is the worst case of I
A
OZL
and I or I
and I , respectively.
IL
OZH IH
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
¶
#
See ’f
Specification’ near the end of this data sheet.
max
is the skew time between registered outputs.
t
sk(o)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
0
4
125
High
Low
ns
t
w
Pulse duration, clock
4
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
4.5
0
ns
ns
°C
su
h
T
0
25
75
A
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
TIBPAL16R8-5CJ
TIBPAL16R8-5CN
TIBPAL16R8-5CFN
PARAMETER
TEST CONDITIONS
I = –18 mA
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–0.8
2.7
–1.5
–0.8
2.7
–1.5
V
V
IK
I
I
= –3.2 mA
= 24 mA
= 2.7 V
2.4
2.4
OH
OL
OZH
OZL
I
OH
I
0.3
0.5
100
0.3
0.5
100
V
OL
I
I
I
I
I
I
I
V
V
µA
µA
µA
µA
µA
mA
mA
O
= 0.4 V
–100
100
–100
100
O
V = 5.5 V
I
V = 2.7 V
I
25
25
IH
V = 0.4 V
I
–250
–130
180
–250
–130
180
IL
‡
V
O
= 0.5 V
–30
–70
–30
–70
OS
V = 0, Outputs open
I
CC
I
8.5
7.5
10
6.5
5.5
8
pF
pF
C
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
i
CLK/OE
V
O
= 2 V
o
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
TIBPAL16R8-5CJ
TIBPAL16R8-5CFN
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
TIBPAL16R8-5CN
PARAMETER
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
without feedback
125
125
§
f
with internal feedback (counter configuration)
with external feedback
125
125
MHz
max
117
111
with up to 4 outputs
switching
CLK↑
CLK↑
Q
Q
1.5
1.5
4
4
1.5
1.5
4
R1 = 200 Ω,
R2 = 200 Ω,
See Figure 8
t
pd
ns
with more than 4
outputs switching
4.5
¶
t
t
t
t
t
t
CLK↑
OE↓
OE↑
Internal feedback
3.5
6
3.5
6
ns
ns
ns
ns
ns
ns
pd
en
dis
r
Q
Q
1.5
1
1.5
1
6.5
7
1.5
1.5
0.5
1.5
1.5
0.5
f
#
Skew between outputs
= 5 V, T = 25°C.
sk(o)
†
‡
All typical values are at V
CC
A
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
§
¶
#
See ’f
Specification’ near the end of this data sheet.
max
This parameter is calculated from the measured f
with internal feedback in a counter configuration (see Figure 2 for illustration).
max
is the skew time between registered outputs.
t
sk(o)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily
include testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle or during a preload cycle.
recommended operating conditions
MIN NOM
MAX
5.5
5.5
0.8
–2
UNIT
V
V
V
V
Supply voltage
4.5
2
5
CC
IH
High-level input voltage (see Note 2)
Low-level input voltage (see Note 2)
High-level output current
V
V
IL
I
I
mA
mA
OH
OL
Low-level output current
12
†
f
Clock frequency
0
5
5
100
MHz
clock
High
Low
†
ns
t
w
Pulse duration, clock
†
t
t
Setup time, input or feedback before clock↑
Hold time, input or feedback after clock↑
Operating free-air temperature
7
0
ns
ns
°C
su
†
h
T
–55
25
125
A
†
f
, t , t , and t do not apply to TIBPAL16L8’
clock w su
h
NOTE 2: These are absolute voltage levels with respect to the ground pin of the device and include all overshoots due to system and/or tester
noise. Testing these parameters should not be attempted without suitable equipment.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 4.5 V,
–0.8
2.7
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –2 mA
= 12 mA
2.4
OH
OL
OH
OL
I
0.25
0.5
20
0, Q outputs
I
V
CC
V
CC
= 5.5 V,
= 5.5 V,
V
= 2.7 V
= 0.4 V
µA
OZH
O
O
I/O ports
100
–20
–250
1
0, Q outputs
I/O ports
I
V
µA
mA
µA
OZL
I
I
V
V
= 5.5 V,
= 5.5 V,
V = 5.5 V
I
I
CC
I/O ports
All others
100
25
V = 2.7 V
I
CC
IH
I
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
V = 0.4 V
–250
µA
mA
mA
IL
I
‡
I
V
O
= 0.5 V
–30
–70 –130
OS
CC
I
V = GND, OE = V
I
,
IH
Outputs open
210
I
8.5
7.5
10
pF
pF
C
f = 1 MHz,
f = 1 MHz,
V = 2 V
I
i
CLK/OE
C
V
O
= 2 V
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. V is set at 0.5 V to
avoid test problems caused by test equipment ground degradation.
O
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
TEST CONDITION
MIN
100
100
MAX
UNIT
without feedback
with internal feedback
(counter configuration)
§
f
MHz
max
with external feedback
R1 = 390 Ω,
R2 = 750 Ω,
See Figure 8
74
1
t
t
t
t
t
t
I, I/O
O, I/O
Q
7
7
ns
ns
ns
ns
ns
ns
pd
pd
en
dis
en
dis
CLK
OE↓
OE↑
I, I/O
I, I/O
1
Q
1
8
Q
1
10
9
O, I/O
O, I/O
1
1
10
§
See’f
Specification’neartheendofthisdatasheet.f
doesnotapplyforTIBPAL16L8’.f withexternalfeedbackisnotproductiontested
max max
specifications section.
max
and is calculated from the equation located in the f
max
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other specifications
are design goals. Texas Instruments reserves the right to change or
discontinue these products without notice.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
†
asynchronous preload procedure for registered outputs (see Figure 1 and Note 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 11 to V
.
IHH
CC
IL
Apply either V or V to the output corresponding to the register to be preloaded.
Lower Pin 11 to 5 V.
Remove output voltage, then lower Pin 11 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
IHH
Pin 11
5 V
V
IL
t
t
+ t
t
d
d
su
h
V
V
V
OH
IH
Registered Output
Input
Output
V
OL
IL
†
Figure 1. Asynchronous Preload Waveforms
†
Not applicable for TIBPAL16L8-5C and TIBPAL16L8-7M.
NOTE 3: t = t = t = 100 ns to 1000 ns
d
IHH
su
h
V
= 10.25 V to 10.75 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
f
SPECIFICATIONS
max
f
without feedback (see Figure 3)
max
In this mode, data is presented at the input to the flip-flop and clocked through to the Q output with no feedback.
Under this condition, the clock period is limited by the sum of the data setup time and the data hold time (t + t ).
su
h
However, the minimum fmax is determined by the minimum clock period (t high + t low).
w
w
1
1
f
without feedback
Thus,
or
.
max
(t
t )
(t high
w
t low)
w
su
h
CLK
Logic
Array
C1
1D
t
+ t
h
su
or
high + t low
t
w
w
Figure 3. f
Without Feedback
max
f
with internal feedback (see Figure 4)
max
This configuration is most popular in counters and on-chip state-machine designs. The flip-flop inputs are
defined by the device inputs and flip-flop outputs. Under this condition, the period is limited by the internal delay
from the flip-flop outputs through the internal feedback and logic array to the inputs of the next flip-flop.
1
f
with internal feedback
Thus,
.
max
(t
t
CLK to FB)
su
pd
Where tpd CLK-to-FB is the deduced value of the delay from CLK to the input of the logic array.
CLK
Logic
Array
C1
1D
t
t
CLK-to-FB
pd
su
Figure 4. f
With Internal Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
18
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
f
SPECIFICATIONS
max
f
with external feedback (see Figure 5)
max
This configuration is a typical state-machine design with feedback signals sent off-chip. This external feedback
could go back to the device inputs or to a second device in a multi-chip state machine. The slowest path defining
the period is the sum of the clock-to-output time and the input setup time for the external signals
(t + t CLK-to-Q).
su
pd
1
f
with external feedback
Thus,
.
max
(t
t
CLK to Q)
su
pd
CLK
Next Device
Logic
Array
C1
1D
t
t
CLK-to-Q
t
su
su
pd
Figure 5. f
With External Feedback
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
19
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
thermal management of the TIBPAL16R8-5C
ThermalmanagementoftheTIBPAL16R8-5CNandTIBPAL16R8-5CFNisnecessarywhenoperatingatcertain
conditions of frequency, output loading, and outputs switching simultaneously. The device and system
application will determine the appropriate level of management.
Determining the level of thermal management is based on factors such as power dissipation (P ), ambient
D
temperature (T ), and transverse airflow (FPM). Figures 6 (a) and 6 (b) show the relationship between ambient
A
temperature and transverse airflow at given power dissipation levels. The required transverse airflow can be
determined at a particular ambient temperature and device power dissipation level in order to ensure the device
specifications.
Figure 7 illustrates how power dissipation varies as a function of frequency and the number of outputs switching
simultaneously. It should be noted that all outputs are fully loaded (C = 50 pF). Since the condition of eight fully
L
loaded outputs represents the worst-case condition, each application must be evaluated accordingly.
MINIMUM TRANSVERSE AIR FLOW
MINIMUM TRANSVERSE AIR FLOW
vs
vs
AMBIENT TEMPERATURE
AMBIENT TEMPERATURE
1000
800
1000
800
P
P
P
= 1.6 W
= 1.4 W
= 1.2 W
P
= 1.6 W
= 1.4 W
= 1.2 W
D
D
D
D
600
600
P
P
D
D
P
= 1 W
= 0.8 W
= 0.6 W
P
= 1 W
D
D
P
D
P
D
P
D
P
D
= 0.8 W
= 0.6 W
400
200
0
400
200
0
0
10
20
30
40
50
60
70
80
0
10
20
T – Ambient Temperature – °C
A
30
40
50
60
70
80
T
– Ambient Temperature – °C
A
(a) TIBPAL16R8-5CN
(b) TIBPAL16R8-5CFN
Figure 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
20
TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
THERMAL INFORMATION
POWER DISSIPATION
vs
FREQUENCY
1800
1600
1400
1200
1000
800
V
= 5 V
= 25 °C
= 50 pF
CC
T
A
C
L
8 Outputs Switching
7 Outputs Switching
6 Outputs Switching
5 Outputs Switching
4 Outputs Switching
3 Outputs Switching
2 Outputs Switching
1 Output Switching
600
1
2
4
10
20
40
100 200
f – Frequency – MHz
Figure 7
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21
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
3 V
0
Timing
Input
High-Level
1.5 V
1.5 V 1.5 V
Pulse
t
t
w
h
t
su
3 V
0
Data
Input
3 V
1.5 V
1.5 V
Low-Level
Pulse
1.5 V 1.5 V
0
(see Note B)
(see Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
3 V
0
Output
Control
(low-level
enabling)
1.5 V
1.5 V
Input
1.5 V
1.5 V
t
0
pd
t
pd
(see Note B)
t
en
V
OH
t
80 %
20 %
dis
In-Phase
Output
1.5 V
1.5 V
≈ 2.7 V
V
OL
t
t
f
r
Waveform 1
1.5 V
t
S1 Closed
(see Note C)
t
pd
pd
V
V
OL
OL
V
OH
20 %
80 %
t
+ 0.5 V
Out-of-Phase
Output
(see Note D)
dis
1.5 V
1.5 V
t
en
V
OL
V
V
OH
t
f
t
r
Waveform 2
S1 Open
(see Note C)
1.5 V
– 0.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
OH
≈ 0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. All input pulses have the following characteristics: For C suffix, PRR ≤ 1 MHz, t = t = 2 ns, duty cycle = 50%; For M suffix,
r
f
PRR ≤ 10 MHz, t = t ≤ 2 ns, duty cycle = 50%
r
f
C. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 8. Load Circuit and Voltage Waveforms
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22
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
metastable characteristics of TIBPAL16R4-5C, TIBPAL16R6-5C, and TIBPAL16R8-5C
At some point a system designer is faced with the problem of synchronizing two digital signals operating at two
different frequencies. This problem is typically overcome by synchronizing one of the signals to the local clock
through use of a flip-flop. However, this solution presents an awkward dilemma since the setup and hold time
specifications associated with the flip-flop are sure to be violated. The metastable characteristics of the flip-flop
can influence overall system reliability.
Whenever the setup and hold times of a flip-flop are violated, its output response becomes uncertain and is said
to be in the metastable state if the output hangs up in the region between V and V . This metastable condition
IL
IH
lasts until the flip-flop falls into one of its two stable states, which takes longer than the specified maximum
propagation delay time (CLK to Q max).
From a system engineering standpoint, a designer cannot use the specified data sheet maximum for
propagation delay time when using the flip-flop as a data synchronizer – how long to wait after the specified data
sheet maximum must be known before using the data in order to guarantee reliable system operation.
The circuit shown in Figure 9 can be used to evaluate MTBF (Mean Time Between Failure) and ∆t for a selected
flip-flop. Whenever the Q output of the DUT is between 0.8 V and 2 V, the comparators are in opposite states.
When the Q output of the DUT is higher than 2 V or lower than 0.8 V, the comparators are at the same logic level.
The outputs of the two comparators are sampled a selected time (∆t) after system clock (SCLK). The exclusive
OR gate detects the occurrence of a failure and increments the failure counter.
DUT
Noise
Generator
V
IH
Comparator
MTBF
Counter
Data in
1D
1D
C1
1D
C1
+
V
IL
Comparator
SCLK
C1
1D
C1
SCLK + ∆t
Figure 9. Metastable Evaluation Test Circuit
In order to maximize the possibility of forcing the DUT into a metastable state, the input data signal is applied
so that it always violates the setup and hold time. This condition is illustrated in the timing diagram in Figure 10.
Any other relationship of SCLK to data will provide less chance for the device to enter into the metastable state.
Data in
SCLK
SCLK + ∆t
∆t
∆t
Time (sec)
# Failures
MTBF
t
= ∆t – CLK to Q (max)
rec
Figure 10. Timing Diagram
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23
TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
By using the described test circuit, MTBF can be determined for several different values of ∆t (see Figure 9).
Plotting this information on semilog scale demonstrates the metastable characteristics of the selected flip-flop.
Figure 11 shows the results for the TIBPAL16’-5C operating at 1 MHz.
9
8
7
6
5
4
3
2
1
10
10
10
10
10
10
10
10
10
10 yr
1 yr
1 mo
1 wk
1 day
1 hr
1 min
10 s
f
f
= 1 MHz
clk
= 500 kHz
data
0
10
20
30
40
50
60
70
∆t – Time Difference – ns
Figure 11. Metastable Characteristics
From the data taken in the above experiment, an equation can be derived for the metastable characteristics at
other clock frequencies.
1
(
C2 x t)
The metastable equation:
f
x f
x C1 e
SCLK
data
MTBF
The constants C1 and C2 describe the metastable characteristics of the device. From the experimental data,
–3
these constants can be solved for: C1 = 4.37 X 10 and C2 = 2.01
Therefore
1
3
( 2.01 x t)
f
x f
x 4.37 x 10
e
SCLK
data
MTBF
definition of variables
DUT (Device Under Test): The DUT is a 5-ns registered PLD programmed with the equation Q : = D.
MTBF (Mean Time Between Failures): The average time (s) between metastable occurrences that cause a
violation of the device specifications.
f
f
(system clock frequency): Actual clock frequency for the DUT.
SCLK
(data frequency): Actual data frequency for a specified input to the DUT.
data
C1: Calculated constant that defines the magnitude of the curve.
C2: Calculated constant that defines the slope of the curve.
t
(metastability recovery time): Minimum time required to guarantee recovery from metastability, at a given
rec
MTBF failure rate. t
= ∆t – t (CLK to Q, max)
rec
pd
∆t: The time difference (ns) from when the synchronizing flip-flop is clocked to when its output is sampled.
The test described above has shown the metastable characteristics of the TIBPAL16R4/R6/R8-5C series. For
additional information on metastable characteristics of Texas Instruments logic circuits, please refer to TI
Applications publication SDAA004, ”Metastable Characteristics, Design Considerations for ALS, AS, and LS
Circuits.’’
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24
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT CURRENT
vs
vs
LOW-LEVEL OUTPUT VOLTAGE
HIGH-LEVEL OUTPUT VOLTAGE
20
15
10
5
0
–10
–20
–30
V
T
A
= 5 V,
= 25 °C
V
T
A
= 5 V,
= 25 °C
CC
CC
–40
–50
0
–60
–70
–80
–90
–5
–10
–15
–100
–20
–0.8 –0.6 –0.4 –0.2
0
0.2
0.4 0.6
0.8
0
0.5
1
1.5
2
2.5
3
V
OL
– Low-Level Output Voltage – V
V
OH
– High-Level Output Voltage – V
Figure 12
Figure 13
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
220
200
180
160
140
120
V
V
= 5.5 V
= 5.25 V
CC
CC
V
V
V
= 4.5 V
= 4.75 V
= 5 V
CC
CC
CC
100
–75 –50 –25
0
25
50
75
100 125
T
A
– Free-Air Temperature – °C
Figure 14
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25
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
POWER DISSIPATION
vs
PROPAGATION DELAY TIME
FREQUENCY
vs
8-BIT COUNTER MODE
SUPPLY VOLTAGE
6
5
1100
1000
900
T
C
= 25 °C
= 50 pF
A
L
V
= 5 V
CC
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
T
A
= 80 °C
4
3
t
(I, I/O to O, I/O)
PHL
T
A
= 25 °C
t
(I, I/O to O, I/O)
PLH
T
= 0 °C
A
t
(CLK to Q)
2
1
PLH
T
A
= 0 °C
T
A
= 80 °C
t
(CLK to Q)
PHL
800
700
0
1
2
4
10
20
40
100 200
4.5
4.75
V
5
5.25
5.5
– Supply Voltage – V
f – Frequency – MHz
CC
Figure 15
Figure 16
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
LOAD CAPACITANCE
16
14
12
10
6
5
V
C
= 5 V
= 50 pF
V
T
= 5 V
= 25 °C
CC
L
CC
A
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
R1 = 200 Ω
R2 = 200 Ω
1 Output Switching
t
(I, I/O to O, I/O)
4
3
PHL
t
t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
PHL
PLH
8
6
t
(CLK to Q)
PHL
2
1
t
(CLK to Q)
PLH
t
(CLK to Q)
PHL
50
4
2
t
(I, I/O to O, I/O)
PLH
t
(CLK to Q)
PLH
0
0
–75 –50 –25
0
25
75 100 125
0
100
200
300
400
500
600
T
A
– Free-Air Temperature – °C
C
– Load Capacitance – pF
L
Figure 17
Figure 18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
26
TIBPAL16L8-5C, TIBPAL16R4-5C, TIBPAL16R6-5C, TIBPAL16R8-5C
TIBPAL16L8-7M, TIBPAL16R4-7M, TIBPAL16R6-7M, TIBPAL16R8-7M
HIGH-PERFORMANCE IMPACT-X PAL CIRCUITS
SRPS011D – D3359, OCTOBER 1989 – REVISED SEPTEMBER 1992
TYPICAL CHARACTERISTICS
SKEW BETWEEN OUTPUTS
PROPAGATION DELAY TIME
vs
vs
NUMBER OF OUTPUTS SWITCHING
NUMBER OF OUTPUTS SWITCHING
0.8
0.7
0.6
0.5
6
5
V
T
= 5 V
= 25 °C
V
T
C
= 5 V
= 25 °C
= 50 pF
CC
A
CC
A
L
R1 = 200 Ω
R2 = 200 Ω
C
R1 = 200 Ω
R2 = 200 Ω
= 50 pF
L
8-Bit Counter
4
3
2
0.4
0.3
Outputs Switching in the Opposite Direction
= t
= t
= t
= t
(I, I/O to O, I/O)
(I, I/O to O, I/O)
(CLK to Q)
PHL
PLH
PHL
PLH
0.2
0.1
1
0
Outputs Switching in the Same Direction
(CLK to Q)
0
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
Number of Outputs Switching
Number of Outputs Switching
Figure 19
Figure 20
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27
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D0892
1992 Texas Instruments Incorporated
SRPS011D
PACKAGE OPTION ADDENDUM
www.ti.com
4-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
LCCC
CDIP
CFP
Drawing
FK
J
5962-85155212A
5962-8515521RA
5962-8515521SA
5962-85155222A
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
OBSOLETE
ACTIVE
NRND
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
1
1
1
1
1
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Call TI
W
LCCC
CDIP
CFP
FK
J
5962-8515522RA
5962-8515522SA
TIBPAL16L8-5CFN
TIBPAL16L8-5CN
TIBPAL16R4-5CFN
TIBPAL16R4-5CN
TIBPAL16R4-7MFKB
TIBPAL16R4-7MJB
TIBPAL16R4-7MWB
TIBPAL16R6-5CFN
TIBPAL16R6-5CN
TIBPAL16R8-5CFN
TIBPAL16R8-5CN
TIBPAL16R8-7MFKB
TIBPAL16R8-7MJB
TIBPAL16R8-7MWB
W
PLCC
PDIP
PLCC
PDIP
LCCC
CDIP
CFP
FN
N
Call TI
FN
N
46
20
1
Level-1-220-UNLIM
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
Level-1-220-UNLIM
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
Level-NC-NC-NC
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
FK
J
1
W
1
PLCC
PDIP
PLCC
PDIP
LCCC
CDIP
CFP
FN
N
46
20
46
20
1
FN
N
FK
J
1
W
1
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:
Products
Applications
Audio
Amplifiers
amplifier.ti.com
www.ti.com/audio
Data Converters
dataconverter.ti.com
Automotive
www.ti.com/automotive
DSP
dsp.ti.com
Broadband
Digital Control
Military
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/military
Interface
Logic
interface.ti.com
logic.ti.com
Power Mgmt
Microcontrollers
power.ti.com
Optical Networking
Security
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
microcontroller.ti.com
Telephony
Video & Imaging
Wireless
www.ti.com/wireless
Mailing Address:
Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2005, Texas Instruments Incorporated
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