TIBPAL20R4-25CJT [TI]
LOW-POWER HIGH-PERFORMANCE IMPACT E PAL CIRCUITS; 低功耗高性能影响é PAL电路
| 型号： | TIBPAL20R4-25CJT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LOW-POWER HIGH-PERFORMANCE IMPACT E PAL CIRCUITS |
| 文件： | 总17页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
TIBPAL20L8’
JT OR NT PACKAGE
•
•
Low-Power, High-Performance
Reduced I of 105 mA Max
CC
(TOP VIEW)
f
:
max
Without Feedback . . . 33 MHz Min
With Feedback . . . 25 MHz Min
I
I
I
I
I
I
I
I
V
I
O
I/O
I/O
I/O
I/O
I/O
I/O
O
1
24
23
22
21
20
19
18
17
16
15
14
13
CC
2
t
. . . 25 ns Max
pd
3
Direct Replacement for PAL20L8A,
PAL20R4A, PAL20R6A, PAL20L8A, with at
Least 50% Reduction in Power
4
5
6
7
•
•
Preload Capability on Output Registers
Simplifies Testing
8
I
I
I
9
10
11
12
Power-Up Clear on Registered Devices (All
Register Outputs are Set Low, but Voltage
Levels at the Output Pins Go High)
I
I
GND
•
•
Package Options Include Plastic Chip
Carriers in Addition to Plastic and Ceramic
DIPs
TIBPAL20L8’
FN PACKAGE
(TOP VIEW)
Dependable Texas Instruments Quality and
Reliability
I/O
PORT
S
I
3-STATE
REGISTERED
Q OUTPUTS
4
5
3
2
1
28 27 26
25
DEVICE
INPUTS O OUTPUTS
I
I
I
I/O
I/O
I/O
PAL20L8
PAL20R4
PAL20R6
PAL20R8
14
12
12
12
2
0
0
0
0
6
4
2
0
6
24
23
4 (3-state buffers)
6 (3-state buffers)
8 (3-state buffers)
7
8
NC
22 NC
21 I/O
20 I/O
19 I/O
9
I
I
I
10
11
description
12 13 14 15 16 17 18
These programmable array logic devices feature
high speed and functional equivalency when
compared with currently available devices. These
IMPACT
circuits
combine
the
latest
NC – No internal connection
Pin assignments in operating mode
AdvancedLow-Power Schottky technology with
proventitanium-tungstenfusestoprovidereliable,
high-performance substitutes for conventional
TTL logic. Their easy programmability allows forquick design of custom functions and typically results in a more
compact circuit board. In addition, chip carriers are available for futher reduction in board space.
Alloftheregisteroutputsaresettoalowlevelduringpower-up. Extracircuitryhasbeenprovidedtoallowloading
of each register asynchronously to either a high or low state. This feature simplifies testing because the registers
can be set to an initial state prior to executing the test sequence.
The TIBPAL20’ C series is characterized from 0°C to 75°C.
These devices are covered by U.S. Patent 4,410,987
IMPACT is a trademark of Texas Instruments Incorporated.
PAL is a registered trademark of Advanced Micro Devices Inc.
PRODUCTION DATA information is current as of publication date. Products
Copyright 1992, Texas Instruments Incorporated
conform to specifications per the terms of Texas Instruments standard
warranty. Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
TIBPAL20R4’
TIBPAL20R4’
JT OR NT PACKAGE
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
I/O
Q
Q
Q
Q
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25 I/O
I
5
6
7
8
9
I
24
23
Q
Q
I
NC
22 NC
I
I
I
21
20
Q
Q
9
I/O
I/O
I
10
11
10
11
12
I
I
19 I/O
12 13 14 15 16 17 18
GND
OE
TIBPAL20R6’
JT OR NT PACKAGE
TIBPAL20R6’
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
I/O
Q
Q
Q
Q
Q
Q
I/O
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
TIBPAL20R8’
JT OR NT PACKAGE
TIBPAL20R8’
FN PACKAGE
(TOP VIEW)
(TOP VIEW)
V
I
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
CLK
CC
I
I
I
I
I
I
I
I
4
3
2
1 28 27 26
25
Q
Q
Q
Q
Q
Q
Q
Q
I
I
5
6
7
8
9
Q
Q
Q
I
24
23
I
NC
22 NC
I
I
I
21
20
19
Q
Q
Q
9
10
11
10
11
12
I
I
12 13 14 15 16 17 18
GND
OE
NC – No internal connection
Pin assignments in operating mode
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPAL20L8-25C, TIBPAL20R4-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL20L8’
&
≥1
EN
O
7
40 X 64
O
7
7
7
7
7
7
7
20 x
I/O
I/O
I/O
I/O
I/O
I/O
14
20
20
I
6
6
TIBPAL20R4’
OE
CLK
EN 2
C1
I = 0
≥1
&
8
Q
Q
Q
Q
2
40 X 64
1D
8
8
8
20 x
12
20
I
4
≥1
EN
7
I/O
I/O
I/O
I/O
4
20
7
7
7
4
4
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
functional block diagrams (positive logic)
TIBPAL20R6’
OE
CLK
EN 2
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
2
8
8
8
8
8
8
40 X 64
1D
20 x
12
20
20
I
6
2
≥1
EN
7
7
2
I/O
I/O
6
TIBPAL20R8’
OE
EN 2
CLK
C1
I = 0
≥1
&
Q
Q
Q
Q
Q
Q
Q
Q
2
8
40 X 64
1D
8
8
8
8
8
8
8
20 x
12
20
20
I
8
8
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
TIBPAL20L8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
logic diagram (positive logic)
1
I
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
I/O
I/O
I/O
I/O
I/O
O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
960
1000
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520
1560
1600
1640
1680
1720
1760
1800
1840
1880
1920
1960
2000
2040
2080
2120
2160
2200
2240
2280
2320
2360
2400
2440
2480
10 2520
14
13
I
I
I
I
11
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TIBPAL20R4-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
21
20
19
18
17
16
15
I/O
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I/O
I/O
2240
2280
2320
2360
2400
2440
2480
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPAL20R6-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
120
160
200
240
I/O
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
Q
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
Q
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
Q
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
Q
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
Q
C1
2240
2280
2320
2360
2400
2440
2480
I/O
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
logic diagram (positive logic)
1
CLK
Increment
0
4
8
12
16
20
24
28
32
36 39
2
23
22
I
I
First Fuse
Numbers
0
40
80
I = 0
1D
120
160
200
240
Q
C1
280
3
I
320
360
400
440
480
520
560
600
I = 0
1D
21
20
19
18
17
16
15
Q
Q
Q
Q
Q
Q
Q
C1
4
5
6
7
8
9
I
I
I
I
I
I
640
680
720
760
800
840
880
920
I = 0
1D
C1
960
1000
1040
1080
1120
1160
1200
1240
I = 0
1D
C1
1280
1320
1360
1400
1440
1480
1520
1560
I = 0
1D
C1
1600
1640
1680
1720
1760
1800
1840
1880
I = 0
1D
C1
1920
1960
2000
2040
2080
2120
2160
2200
I = 0
1D
C1
2240
2280
2320
2360
2400
2440
2480
I = 0
1D
C1
10 2520
I
I
11
14
13
I
Fuse number = First fuse number + Increment
Pin numbers shown are for JT and NT packages.
OE
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Clock frequency
V
0.8
V
IL
I
I
f
–3.2
24
mA
mA
MHz
OH
OL
clock
†
0
15
15
25
33
High
Low
†
ns
t
w
Pulse duration, clock
†
t
t
Setup time, input or feedback before clock↑
ns
su
†
Hold time, input or feedback after clock↑
0
0
ns
h
T
A
Operating free-air temperature
25
75
°C
†
f
, t , t , and t do not apply for TIBPAL20L8’.
clock w su
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
electrical characteristics over recommended operating free-air temperature range
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
–0.8
3.3
–1.5
V
V
V
IK
CC
CC
CC
I
I
= –3.2 mA
= 24 mA
2.4
OH
OL
OH
OL
I
0.3
0.5
20
O, Q outputs
I
V
= 5.25 V,
= 5.25 V,
V
= 2.7 V
= 0.4 V
µA
µA
OZH
CC
CC
O
I/O ports
100
–20
–250
0.1
O, Q outputs
I/O ports
I
V
V
O
OZL
I
I
I
I
V
CC
V
CC
V
CC
= 5.25 V,
= 5.25 V,
= 5.25 V,
V = 5.5 V
I
mA
µA
I
‡
V = 2.7 V
I
20
IH
‡
V = 0.4 V
I
–0.25
mA
mA
IL
§
V
V
= 5.25 V,
= 5.25 V,
V = 0
O
–30
–70 –130
75 105
OS
CC
V = 0,
CC
I
I
mA
CC
Outputs open,
OE at V
IH
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
With feedback
Without feedback
O, I/O
25
33
3
40
50
14
10
8
¶
f
MHz
max
t
pd
t
pd
t
en
t
t
t
I, I/O
CLK↑
OE
R1 = 200 Ω,
R2 = 390 Ω,
See Figure 3
25
15
15
15
25
25
ns
ns
ns
ns
ns
ns
Q
Q
2
2
OE↑
I, I/O
I, I/O
Q
2
8
dis
en
dis
O, I/O
O, I/O
3
15
15
3
†
‡
§
All typical values are at V
For I/O ports, the parameters I and I include the off-state output current.
Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.
= 5 V, T = 25°C.
A
IH IL
CC
¶
1
,
,
f
(with feedback)
max
1
f
(without feedback)
max
t
t
(CLK to Q)
su
does not apply for TIBPAL20L8,.
t
high
t
low
w
pd
w
f
max
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
preload procedure for registered outputs (see Figure 1 and Notes 2 and 3)
The output registers can be preloaded to any desired state during device testing. This permits any state to be
tested without having to step through the entire state-machine sequence. Each register is preloaded individually
by following the steps given below.
Step 1.
Step 2.
Step 3.
Step 4.
With V
at 5 volts and Pin 1 at V , raise Pin 13 to V
.
CC
IL
IHH
Apply either V or V to the output corresponding to the register to be preloaded.
Pulse Pin 1, clocking in preload data.
Remove output voltage, then lower Pin 13 to V . Preload can be verified by observing the
voltage level at the output pin.
IL
IH
IL
V
V
IHH
Pin 13
IL
t
t
d
su
t
t
w
d
V
V
V
V
IH
Pin 1
IL
V
V
IH
OH
OL
Registered I/O
Input
Output
IL
Figure 1. Preload Waveforms
NOTES: 2. Pin numbers shown are for JT and NT packages only. If chip carrier socket adapter is not used, pin numbers must be changed
accordingly.
3. t = t = t = 100 ns to 1000 ns V
su IHH
= 10.25 V to 10.75 v
d
h
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
power-up reset (see Figure 2)
Following power up, all registers are reset to zero. This feature provides extra flexibility to the system designer
and is especially valuable in simplifying state-machine initialization. To ensure a valid power-up reset, it is
important that the rise of V
occur until all applicable input and feedback setup times are met.
be monotonic. Following power-up reset, a low-to-high clock transition must not
CC
V
CC
5 V
4 V
†
t
pd
(600 ns TYP, 1000 ns MAX)
V
V
OH
Active Low
Registered Output
1.5 V
OL
‡
t
su
V
V
IH
CLK
1.5 V
1.5 V
IL
t
w
†
‡
This is the power-up reset time and applies to registered outputs only. The values shown are from characterization data.
This is the setup time for input or feedback.
Figure 2. Power-Up Reset Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPAL20L8-25C, TIBPAL20R4-25C, TIBPAL20R6-25C, TIBPAL20R8-25C
LOW-POWER HIGH-PERFORMANCE IMPACT PAL CIRCUITS
SRPS022 – D2920, MAY 1987 – REVISED MARCH 1992
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
High-Level
Pulse
3.5 V
0.3 V
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Low-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low-level
enabling)
3.5 V
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, t and t ≤ 2 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 3. Load Circuit and Voltage Waveforms
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B0892
1992 Texas Instruments Incorporated
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D0892
1992 Texas Instruments Incorporated
SRPS022
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