TIBPSG507ACNT [TI]
13 Ã 80 Ã 8 PROGRAMMABLE SEQUENCE GENERATOR;
| 型号： | TIBPSG507ACNT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 13 Ã 80 Ã 8 PROGRAMMABLE SEQUENCE GENERATOR 时钟 输入元件 光电二极管 可编程逻辑 |
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TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
JT OR NT PACKAGE
(TOP VIEW)
•
•
58-MHz Max Clock Rate
Ideal for Waveform Generation and
High-Performance State Machine
Applications
CLK
I0
V
CC
I6
I7
I8
1
24
23
22
21
20
19
18
17
16
15
14
13
2
I1
I2
I3
I4
3
•
•
•
•
6-Bit Internal Binary Counter
8-Bit Internal State Register
Programmable Clock Polarity
4
I9
5
I10
I11
I12/OE
Q7
Q6
Q5
Q4
6
I5
7
Q0
Q1
Q2
Q3
GND
8
Outputs Programmable for Registered or
Combinational Operation
9
10
11
12
•
•
6-Bit Counter Simplifies Logic Equation
Development in State Machine Designs
Programmable Output Enable
FK OR FN PACKAGE
(TOP VIEW)
description
The TIBPSG507AC is
a 13 × 80 × 8
Programmable Sequence Generator (PSG) that
offers the system designer unprecedented
4
3
2
1
28 27 26
25
5
I2
I3
I4
NC
I5
Q0
Q1
I8
I9
I10
flexibility
in
a
high-performance
6
24
23
field-programmable logic device. Applications
such as waveform generators, state machines,
dividers, timers, and simple logic reduction are all
possible with the PSG. By utilizing the built
binary counter, the PSG is capable of generating
complex timing controllers. The binary counter
also simplifies logic equation development in state
machine and waveform generator applicas.
7
8
22 NC
21 I11
20 I12/OE
19 Q7
9
10
11
12 13 14 15 16 17 18
The TIBPSG507AC contains 80 product (AND)
terms, a 6-bit binary counter with control logic,
eight S/R state holding registers, and eight
outputs. The eight outputs can be individually
NC – No internal connection
programmed
for
either
registered
or
combinational operation. The clock input is fuse
programmable for either positive- or negative-
edge operation.
The 6-bit binary counter is trolled by a synchronous-clear and a count/hold function. Each control function
has a nonregistered and registered option. When either SCLR0 or SCLR1 is taken high, the counter resets to
zero on the next active clock edge. When either CNT/HLD0 or CNT/HLD1 is taken high, the counter is held at
the present count and is not allowed to advance on the active clock edge. The SCLR function overrides the
CNT/HLD feature when both lines are simultaneously high.
Clock polarity is programmable through the clock polarity fuse. Leaving this fuse intact selects positive-edge
triggering. Negative-edge triggering is selected by blowing this fuse. Pin 17 functions as an input and/or an
output enable. When the output enable fuse is intact, all outputs are always enabled allowing pin 17 to be used
strictly as aput. Blowing the output enable fuse lets pin 17 function as an output enable and an input. In this
mode, the uts are enabled when pin 17 is low and are in a high-impedance state when pin 17 is high.
PRODUCTION DATA information is current as of publication date.
Copyright 1995, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
description (continued)
The eight outputs can be individually programmed for combinational operation by blowing the output multiplexer
fuse. After power up, the device must be initialized to the desired state. When the output multiplexer fuse is left
intact, registered operation is selected.
The TIBPSG507AC is characterized for operation from 0°C to 75°C.
6-BIT COUNTER CONTROL FUNCTION TABLE (see Note 1)
CNT/HLD1
CNT/HLD0
SCLR1
SCLR0
OPERATION
counter active
L
X
X
X
H
L
X
X
H
X
L
X
H
L
L
H
X
L
hronous clear
synchronous clear
hold counter
L
L
hold counter
NOTE 1: When all fuses are blown on a product line (AND), its output will be high. When all fuses
are blown on a sum line (OR), its output will be low. All product and sum terms are low
on devices with fuses intact.
S/R FUNCTION TABLE (see Note 2)
CLK POLARITY FUSE
INTACT
CLK
S
R
L
STATE REGISTER
↑
↑
↑
↑
↓
↓
↓
Q
L
0
INTACT
L
H
L
INTACT
H
H
L
H
†
INTACT
H
L
INDET
BLOWN
Q
L
0
BLOWN
L
H
L
BLOWN
H
H
H
†
BLOWN
H
INDET
†
Output state is indeterminate
NOTE 2: After power up, the device must be initialized to its desired state. Q is the state of the
0
S/R register before the active clock edge.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
functional block diagram (positive logic)
CLK
8
6
State Registers
C1
≥1
80 x 38
Binary Counter
CTR 6
G2
1S
1R
1S
1R
1CT = 0
&
6
54 x 80
6
6
8
8
6 x
8 x
C0 – C5
C1/2,3+
G3
6
8
1CT = 0
C1
80
8 x
1S
8
8
8
8
12
1
13
13
13 x
I0 – I11
I12/OE
1R
Output Cell
1
C1
8
8
8 x
1S
1
Q0 – Q7
8
8
1R
G1
EN
denotes fused inputs
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
logic diagram (positive logic)
1
CLK
7360
Binary Counter
Functional
Logic Symbol
2
0
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
3
4
5
CTR 6
G2
5
C0
C1
C2
C3
C4
C5
CNT/HLD1
SCLR1
7
10
15
20
25
1CT = 0
23
22
CLK
C1/2,3+
G3
21
20
CNT/HLD0
SCLR0
19
1CT = 0
18
17
PRE/OE
P0
P1
P2
P3
P4
P5
P6
P7
26
7361
41
CTR
C0
C1
C2
C3
C4
C5
53
54
SCLR0
1S
C1
1R
SCLR1
CNT/HLD0
1S
C1
1R
58
62
66
CNT/HLD1
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
1S
C1
1R
70
74
1S
C1
1R
1S
C1
1R
MUX
1
8
9
1S
C1
1R
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
G1
7362
7363
7364
7365
7366
7367
7368
69
MUX
1
1S
C1
1R
78
82
86
G1
MUX
1
10
11
13
14
15
16
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
C1
1R
G1
MUX
1
1S
1
1R
90
91
G1
All inputs to AND gates, exclusive-OR gates, and multiplexers with a blown link assume the logic-1 state.
All OR gate inputs with a blown link assume the logic-0 state.
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Voltage applied to disabled output (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 75°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
NOTE 3: These ratings apply except for programming pins during a programming cycle or during the diagnostic mode.
recommended operating conditions
MIN NOM
MAX
5.25
5.5
UNIT
V
V
V
V
Supply voltage
4.75
2
5
CC
IH
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
V
0.8
V
IL
I
I
–3.2
16
mA
mA
OH
OL
Clock high
6
6
t
w
ns
Pulse duration
Clock low
Input or feedback to S/R↑ inputs
12
‡
Input or feedto S/R↓ inputs
Input or feedback to SCLR0
Input or fek to CNT/HLD0
Input or feedback at S/R inputs
Input or feedback at SCLR0
Input or feedback at CNT/HLD0
19
20
25
0
†
t
Setup time before CLK active transition
ns
su
†
t
Hold time after CLK active transition
0
ns
h
0
T
A
Operating free-air temperature
0
25
75
°C
†
Internal setup and hold times, t feedback to SCLR1, feedback to CNT/HLD1; t feedback at SCLR1 and feedback at CNT/HLD1, are
su
max
See the OR term loading section and Figure 3.
h
guaranteed by f
specifications. The active transition of CLK is determined by the programmed state of the CLK polarity fuse.
‡
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
I = –18 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
= 4.75 V,
= 4.75 V,
= 4.75 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
= 5.25 V,
–1.2
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
I
I
= –3.2 mA
= 16 mA
= 2.7 V
2.4
3.2
V
OH
OL
OZH
OZL
I
OH
I
0.25
0.5
20
V
OL
I
I
I
I
I
I
I
V
V
µA
µA
mA
µA
mA
mA
mA
pF
pF
pF
O
= 0.4 V
–20
0.1
O
V = 5.5 V
I
V = 2.7 V
I
20
IH
V = 0.4 V
I
–0.25
–130
210
IL
‡
V
O
= 0.5 V
–30
O
See Note 4,
V = 2 V
Outputs open
156
7
CC
C
C
C
f = 1 MHz,
f = 1 MHz,
f = 1 MHz,
i
I
V = 2 V
O
11
14
o
V = 2 V
CLK
clk
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
TEST CONDITION
MIN TYP
MAX
UNIT
6-Bit counter with SCLR1 or CNT/HLD1
6-Bit counter with SCLR0
58
40
33
45
65
55
50
60
§
f
MHz
max
6-Bit counter with CNT/HLD0
With external feedback (see Figure 1)
R1 = 300 Ω,
R2 = 390 Ω,
See Figure 6
#
Q (nonregistered)
6
3
6
1
1
25
10
20
10
10
ns
CLK
¶
t
pd
Q (registered)
I or Feedback
OE↓
Q egistered)
ns
ns
ns
t
t
Q
Q
6
6
en
OE↑
dis
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
OS
CC
This parameter approximates I . The condition V = 0.5 V takes tester noise into account. Not more than one output should be shorted at a
time and duration of the short circuit should not exceed one second.
O
§
¶
#
See the f
calculations section.
max
The active edge of CLK is determined by the programmed state of the CLK polarity fuse.
CLK to Q (nonregistered) is the same for data clocked from the counter or state registered.
t
pd
NOTE 4: When the clock is programmefor negitive edge, then V = 4.5 V. When the clock is programmed for positive edge, then V = 0.
I
I
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7
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
f
calculations
max
The following are the different speeds that can be achieved when using the TIBPSG507AC as a state machine.
The way the 6-bit counter is controlled will largely determine the operating frequency of the state machine.
1
f
for a 6-bit counter using SCLR1 or CNT/HLD1 =
where setup time t for input
su
max
t
t
CLK to Q
su
or feedback to the S/R inputs = 12 ns and propagation delay time t CLK to Q for the internal S/R
pd
pd
registers = 5 ns (difference in t from CLK and feedback, 25 to 20).
pd
1
1
Thus: f
for this condition
58 MHz.
max
(12 + 5) ns
17 ns
1
f
for a 6-bit counter using SCLR0 for reset =
where setup time t for input or
su
max
t
t
CLK to Q
su
pd
feedback to the SCLR0 inputs = 20 ns and propagation delay time t CLK to Q for the internal S/R
pd
registers = 5 ns (difference in t from CLK and feedback, 25 to 20)
pd
1
1
Thus: f
for this condition
40 MHz.
max
(20 + 5) ns
25 ns
1
f
for a 6-bit counter using CNT/HLD0 for reset =
where setup time t for input or
su
max
t
t
CLK to Q
su
feedback to CNT/HLD0 = 25 ns and propagation delay me t CLK to Q for the internal S/R registers = 5 ns
pd
pd
(difference in t from CLK and feedback, 25 to 20).
pd
1
Thus: f
for this condition
33 MHz.
max
(25 + 5) ns
30 ns
programming information
Texas Instruments programmable logic devices an be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, ithms, and the latest information on hardware, software, and
firmware are available upon request. Inforation on programmers that are capable of programming Texas
Instruments programmable logic is also available, upon request, from the nearest TI sales office, local
authorized TI distributor, or by calling Texas Instruments at (214) 997-5666.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
t
Min Clock Period Using This Path
min(1)
t
Min Clock Period using This Path
min(2)
t
Min Clock Period Using This Path
min(3)
Dedicated Inputs
Counter or Internal SRs
SCLR0
or
CNT/HLD0
t
su(3)
Feedback Lines
t
min(2)
SR
t
CLK
su(2)
I to Internal S or R
SR
SR
CLK Internal
Out SRs
CLK
SR
t
min(1)
t
CLK Internal to Output Response
pd(3)
t
I to Output S or R
su(1)
t
t
CLK to Q Pin
SR
pd(2)
pd(1)
I to Output Pin
Dedicated Inputs
Output Pin
Figure 1. Timing Model
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
glossary — timing model
tpd
—
—
—
Maximum time interval from the time a signal edge is received at any input pin to the time any logically
affected combinational output pin delivers a response.
(1)
pd(2)
pd(3)
t
t
Maximum time interval from a positive edge on the clock input pin to data delivery on the output pin
corresponding to any output SR register.
Maximum time interval from the positive edge on the clock input pin to the response on any logically
affected combinational configured output (at the pin), where data orign is any internal SR register
or counter bit.
t
t
t
t
t
t
t
—
—
—
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects thor R line of any output SR register.
su(1)
su(2)
su(3)
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin when data affects the S or R line of any internal SR register.
Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin only when entering data on the CNT/HLD0 line.
) — Minimum time interval that must be allowed between the data edge on any dedicated input and the
active clock edge on the clock input pin only when entering data on the SCLR0 line.
su(4
— Minimum clock period (or 1/[maximum frequcy]) that the device will accommodate when using
feedback from any internal SR register or counter bit to feed the S or R line of any output SR register.
min(1)
min(2)
min(3)
— Minimum clock period (or 1/[maximum freqncy]) that the device will accommodate when using
feedback from any internal SR register to feed the S or R line of any internal SR register.
— Minimum clock period (or 1/[maximum frequency]) that the device will accommodate when using
feedback from any internal SR regir counter bit to feed SCLR0 or CNT/HLD0.
PARAMETER VALUES FOR TIMING MODEL
†
†
t
t
t
= 20 ns
= 10 ns
= 25 ns
t
t
t
t
2 ns
= 12 ns
= 25 ns
= 20 ns
t
t
t
= 17 ns
= 17 ns
= 25 ns
pd(1)
pd(2)
pd(3)
su
su(2)
su(3)
su(4)
min(1)
min(2)
min(3)
INTERNAL NODE NUMBERS
SCLR0
SCLR1
25
CNTHLD0 28
CNTHLD1 SET 29
RESET 30
P0-P7
Q0-Q7
SET 31-38
SET 26
RESET 27
RESET 39-46
RESET 47-54
C0-C5
55-60
†
Use t = 19 ns for applications where the setup time for S/R↓ inputs are required.
su
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10
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
diagnostics
A diagnostic mode is provided that allows the user to inspect the contents of the state registers. The following
are step-by-step procedures required for the diagnostics.
Step 1.
Step 2.
Step 3.
Disable all outputs by taking pin 17 (OE) high (see Note 5).
Take pin 8 (Q0) to V to enable the diagnostics test sequence.
Apply appropriate levels of voltage to pins 11 (Q3), 13 (Q4), and 14 (Q5) to select the desired
state register (see Table 1).
IHH
The voltage level monitored on pin 9 will indicate the state of the selected state register.
NOTE 5: If pin 17 is being used as an input to the array, then pin 7 (I5) must be taken to V
before pin 17 is taken high.
IHH
†
V
V
IHH
I5
Pin 7
IH
OE
Pin 17
100 ns
V
V
OHH
OH
Q0
Pin 8
V
V
OL
100 ns
OHH
V
OH
V
OL
V
OH
V
OL
Q3, Q4, Q5
Pins 11, 13, 14
100 ns
Q1
Pin 9
†
V
IHH
= 10.25 V min, 10.5 V nom, 10.75 V max
Figure 2. Diagnostics Waveforms
Table 1. ressing State Registers
Ding Diagnostics
REGISTER BINARY ADDRESS
BURIED REGISTER
PIN 11
PIN13
L
PIN 14
L
SELECTED
L
L
SCLR0
L
H
SCLR1
L
L
HH
L
CNT/HLD0
L
H
CNT/HLD1
P0
L
H
H
L
H
HH
L
P1
L
HH
HH
HH
L
P2
L
H
P3
L
HH
L
P4
H
H
H
H
H
H
H
H
H
P5
L
H
P6
L
HH
L
P7
H
C0
H
H
C1
H
HH
L
C2
HH
HH
HH
C3
H
C4
HH
C5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
PRINCIPLES OF OPERATION
PSG design theory
Most state machine and waveform generator designs can be simplified with the PSG by referencing all or part
of each sequence to a binary count. The internal state registers can then be used to keep track of which binary
count sequence is in operation, to store input data and keep track of internally generated status bits, or as output
registers when connected to a nonregistered output cell. State registers can also be used to expand the binary
counter when a larger counter is needed.
Through the use of the binary counter, the number of product lines and state registers required for a design is
usually reduced. In addition, the designer does not have to be concerned about generating wait states where
the outputs are unaffected because these can be timed from the binarnter. For detailed information and
examples using this design concept, see A Designer’s Guide to the TIBPSG507 applications report.
OR term loading
As shown in Figure 3 and by the f
calculation, f
is affected by the number of terms connected to each OR
max
max
array line. Theoretically, f
is calculated as:
max
1
f
=
max
t
t
CLK to Q
su
Since the setup time (input or feedback to S/R↓) varies h the number of terms connected to each OR array
line, (due to capacitance loading) f will also vary. Figure 3 illustrates the relationship between the number
pd
max
of terms connected per OR line and the setup time.
Use Figure 3 to determine the worst-case setup time for a particular application. Identify the OR array line with
the maximum number of terms connected. Count the number of terms and use the graph to determine the setup
time.
WORST-ASE SETUP TIME
(input or feedback to SR↓)
vs
”OR” TERM LOAD
20
V
T
= 4.75 V
CC
= 75°C
A
19
18
17
16
15
14
13
12
11
10
0
20
40
60
80
Maximum Number of OR Terms Connected
Figure 3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
f
with external feedback
max
The configuration shown is a typical state-machine design with feedback signals sent off-chip. This external
feedback could go back to the device inputs or to a second device in a multi-chip state machine. The slowest
path defining the clock period is the sum of the clock-to-output delay time and the setup time for the input or
feedback signals (t + t CLK to Q).
su
pd
1
Thus: f
with external feedback =
max
t
t
CLK to Q
su
pd
Internal
SR
Registers
CLK
Logic
Array
Input
Output
SR
Registers
Next Device
t
pd
t
su
CLK to Q
Figure 4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
13
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
APPLICATION INFORMATION
The TIBPSG507AC is used in this application to generate the required memory timing control signals (RAS, CAS,
etc.) for the memory timing controller.
RFC
Dynamic RAM
Bank0
1 Meg x 32 Bit
TMS4C1027
Refresh
Timer
Dynamic
Memory
Controller
SN74ALS6301
A0-A8
RAS0
CAS0
W
REFREQ
REFEQ
Memory
Timing
Controller
TIBPSG507A
Bank1
1 Meg x 32 Bit
TMS4C1027
OSC
CLK
RFC
Clock
Generator
A0-A8
Q0-Q8
V
CC
RAS1
CAS1
W
LE
RESET
RAASI
I
M
MC1
WAIT
R/W
A22
Bank2
1 Meg x 32 Bit
TMS4C1027
A0-A8
AS
ALE
OE
RAS2
CAS2
W
CS
Microprocessor
SN74ALS6301
Bank3
1 Meg x 32 Bit
TMS4C1027
A0-A8
Address
RAS3
CAS3
W
2
SEL0,1
Memory Bank Signals
Data
For detailed information, please see the Systems Solution for Static Column Decode Application Report.
Figure 5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
14
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5 V
S1
R1
From Output
Under Test
Test
Point
C
R2
L
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3.5 V
0.3 V
High-Level
Pulse
3.5 V
0.3 V
1.5 V 1.5 V
Timing
Input
1.5 V
t
w
t
h
t
su
3.5 V
0.3 V
3.5 V
0.3 V
Data
Input
Lw-Level
Pulse
1.5 V
1.5 V 1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3.5 V
0.3 V
Output
Control
(low–level
3.5 V
0.3 V
1.5 V
1.5 V
1.5 V
1.5 V
Input
enabling)
t
en
t
pd
t
t
t
dis
pd
V
OH
In-Phase
Output
≈ 3.3 V
1.5 V
1.5 V
1.5 V
Waveform 1
S1 Closed
(see Note B)
1.5 V
V
+0.5 V
OL
V
OL
V
OL
t
pd
pd
t
dis
V
OH
t
en
Out-of-Phase
Output
(see Note D)
1.5 V
V
OH
Waveform 2
S1 Open
(see Note B)
V
OL
1.5 V
V
–0.5 V
OH
≈ 0 V
VOLTAGE WAVEFORMS
PROPAGATION DELMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. C includes probe and jig capacitance and is 50 pF for t and t , 5 pF for t
pd en dis
.
L
B. Waveform1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output wh internal conditions such that the output is high except when disabled by the output control.
C. All input pulses ve the following characteristics: PRR ≤ 1 MHz, t = t ≤ 2 ns, duty cycle = 50%.
r
f
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 6. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
15
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
FREE-AIR TEMPERATURE
200
175
150
125
V
CC
= 5.25 V
V
CC
= 5 V
100
75
V
CC
= 4.75 V
50
25
0
0
25
50
75
T
A
– Free-Air Temperature – °C
Figure 7
POWER DISSIPATION
vs
REQUENCY
1000
950
900
800
750
700
T
= 0°C
A
T
= 25°C
A
T
= 50°C
A
1
2
4
7
10
20
40
70 100
f – Frequency – MHz
Figure 8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16
TIBPSG507AC
13 × 80 × 8 PROGRAMMABLE SEQUENCE GENERATOR
SRPS002D – D3029, MAY 1987 – REVISED NOVEMBER 1995
TYPICAL CHARACTERISTICS
PROPAGATION DELAY TIME
PROPAGATION DELAY TIME
vs
vs
SUPPLY VOLTAGE
LOAD CAPACITANCE
30
25
20
15
10
5
20
18
16
14
12
10
8
V
= 5 V
CC
R1 = 300 Ω
R2 = 390 Ω
T
A
t
(I or Feedback to Q)
PHL
= 25°C
t
(I or Feedback to Q)
PLH
t
t
t
t
(I or Feedback to Q)
(I or Feedback to Q)
(CLK to Q)
t
t
(CLK to Q)
PHL
PLH
PLH
PHL
PLH
PHL
6
(CLK to Q)
(CLK to Q)
4
2
0
R1 = 300 Ω
R2 = 390 Ω
C
= 50 pF
= 25°C
L
T
A
0
0
100
200
300
400
500
600
4.75
5
5.25
C
– Load Capacitance – pF
V
CC
– Supply Voltage – V
L
Figure 10
Figure 9
PROPAGATION DELAY TIME
vs
PROPAGATION DELAY TIME
vs
FREE-AIR TEMPERATURE
NUMBER OF OUTPUTS SWITCHING
20
18
16
14
12
10
8
20
18
16
14
12
10
8
t
(I or Feedback to Q)
PHL
t
(I or Feedback o Q)
PHL
t
(I or Feedback to Q)
t
(I or Feedback to Q)
PLH
PLH
t
t
(CLK to Q)
(CLK to Q)
PLH
PHL
t
t
(CLK to Q)
(CLK to Q)
PLH
PHL
6
6
V
= 5 V
CC
4
2
0
4
2
0
V
= 5 V
R1 = 300 Ω
R2 = 390 Ω
CC
R1 = 300 Ω
R2 = 390 Ω
C
C
T
= 50 pF
L
= 50 pF
= 25°C
L
A
0
25
0
50
75
0
1
2
3
4
5
6
7
8
– Free-Air Temperature – °C
Number of Outputs Switching
Figure 11
Figure 12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
17
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