TIC10024-Q1 [TI]
具有 SPI 的汽车类 35V 多开关检测接口 (MSDI);
| 型号： | TIC10024-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SPI 的汽车类 35V 多开关检测接口 (MSDI) 开关 |
| 文件： | 总82页 (文件大小：2790K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
适用于汽车系统并具有可调湿性电流的TIC10024-Q1 24 路输入
多开关检测接口(MSDI) 器件
1 特性
3 说明
• 符合汽车应用要求
• 具有符合AEC-Q100 标准的下列特性：
TIC10024-Q1 是一款先进的多开关检测接口 (MSDI)
器件，用于检测 12V 汽车系统中的外部开关状态。
TIC10024-Q1 配有可调阈值的比较器，可以独立于
MCU 的方式监控数字开关。该器件监控多达 24 路直
接开关输入，并可配置其中 10 路输入以监控接地或连
接到电池的开关。可为每路输入设定 6 种独特的湿性
电流设置，从而支持不同的应用场景。该器件支持所有
开关输入的唤醒操作，因此无需持续使 MCU 保持活动
状态，进而可降低系统功耗。TIC10024-Q1 还提供集
成故障检测和 ESD 保护功能，从而提高系统稳健性。
TIC10024-Q1 支持 2 种工作模式：连续模式和轮询模
式。连续模式下将连续提供湿性电流。轮询模式下将根
据可编程计时器来定期接通湿性电流以对输入状态进行
采样，从而显著降低系统功耗。
– 器件温度等级1：–40°C 至125°C 的工作环境
温度范围
– 器件HBM ESD 分类等级H2
– 器件CDM ESD 分类等级C4B
• 提供功能安全
– 有助于进行功能安全系统设计的文档
• 旨在支持12V 汽车系统，并提供过压和欠压警告
• 监控多达24 路直接开关输入，并可配置其中10 路
输入以监控接地或连接到电池的开关
• 开关输入可承受高达40V 的电压（负载突降条件）
和低至-24V 的电压（反极性条件）
• 6 种可配置的湿性电流设置：
（0mA、1mA、2mA、5mA、10mA 和15mA）
• 适用于数字开关监控并具有4 个可编程阈值的集成
比较器
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TIC10024-Q1
TSSOP (38)
9.70 mm x 4.40 mm
• 轮询模式下的超低工作电流：
68μA 典型值（tPOLL = 64ms，tPOLL_ACT
128μs，
=
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
全部24 路输入均有效，比较器模式，所有开关均
打开）
VBAT
Voltage
Regulator
GND
• 使用3.3V/5V 串行外设接口(SPI) 协议直接与MCU
对接
• 可产生中断来支持所有输入的唤醒操作
• 采用适当的外部组件根据ISO-10605 在输入引脚上
实现±8kV 接触放电ESD 保护
37
38
VS
VS
VDD 19
VDD
/INT
IN0
IN1
IN2
13
14
25
/INT
/CS
24
15
/CS
IN9
33
MCU
SCLK 16
SCLK
MOSI
MISO
GPIO
SI
• 38 引脚TSSOP 封装
17
SO 18
IN10
IN11
IN12
34
35
36
TIC10024-Q1
RESET 21
2 应用
20
CAP_A
• 车身控制模块和网关
• 汽车照明
CAP_D 23
22
IN23
12
CAP_PRE
• 制热和制冷
• 电动座椅
• 后视镜
9
AGND
DGND 28
Copyright © 2016, Texas Instruments Incorporated
EP
简化版原理图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCPS268
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
9.1 SPI Communication Interface Buses........................ 33
9.2 SPI Sequence...........................................................34
9.3 Programming Guidelines.......................................... 35
9.4 Register Maps...........................................................36
10 Application and Implementation................................65
10.1 Application Information........................................... 65
10.2 Digital Switch Detection in Automotive Body
Control Module............................................................65
10.3 Systems Examples................................................. 68
11 Power Supply Recommendations..............................71
12 Layout...........................................................................72
12.1 Layout Guidelines................................................... 72
12.2 Layout Example...................................................... 73
13 Device and Documentation Support..........................74
13.1 Receiving Notification of Documentation Updates..74
13.2 Community Resources............................................74
13.3 Trademarks.............................................................74
14 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements..................................................9
6.7 Typical Characteristics..............................................10
7 Parameter Measurement Information.......................... 11
8 Detailed Description......................................................12
8.1 Overview...................................................................12
8.2 Functional Block Diagram.........................................13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................26
9 Programming................................................................. 33
Information.................................................................... 74
4 Revision History
Changes from Revision * (September 2017) to Revision A (February 2022)
Page
• 添加了特性“提供功能安全”.............................................................................................................................1
• 将提到的旧术语实例全部更改为控制器和响应器................................................................................................ 1
• Changed the paragraph following 表8-3 for CRC calculations........................................................................ 25
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
5 Pin Configuration and Functions
IN13
1
2
3
38
VS
37
36
IN14
IN15
VS
IN12
35
34
IN16
IN17
4
5
IN11
IN10
6
7
33
32
IN18
IN19
IN9
IN8
IN20
AGND
IN21
8
9
31
30
IN7
IN6
IN5
Exposed
Pad
10
11
29
28
IN22
IN23
DGND
IN4
12
13
27
26
IN0
IN1
IN3
IN2
14
15
25
24
/CS
/INT
16
17
18
19
23
22
21
20
SCLK
CAP_D
SI
CAP_PRE
RESET
SO
VDD
CAP_A
Not to Scale
图5-1. DCP (TSSOP) Package, 38-Pin, Top View
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NO.
1
NAME
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
AGND
IN21
IN22
IN23
IN0
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground for analog circuitry
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
I/O
I/O
I/O
I/O
I/O
I
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Active-low input. Chip select from the commander for the SPI Interface.
Serial clock output from the commander for the SPI Interface
Serial data input for the SPI Interface.
IN1
CS
SCLK
SI
I
I
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NO.
NAME
18
SO
O
Serial data output for the SPI Interface
3.3 V to 5 V logic supply for the SPI communication. The SPI I/Os are not fail-safe protected:
VDD needs to be present during any SPI traffic to avoid excessive leakage currents and
corrupted SPI I/O logic levels.
19
20
VDD
P
CAP_A
I/O
External capacitor connection for the analog LDO. Use capacitance value of 100nF.
Keep RESET low for normal operation and drive RESET high and release it to perform a
hardware reset of the device. The RESET pin is connected to ground via a 1MΩ pull-down
resistor. If not used, the RESET pin shall be grounded to avoid any accidental device reset
due to coupled noise onto this pin.
21
RESET
I
22
23
CAP_Pre
CAP_D
I/O
I/O
External capacitor connection for the pre-regulator. Use capacitance value of 1 μF.
External capacitor connection for the digital LDO. Use capacitance value of 100 nF.
Open drain output. Pulled low (internally) upon change of state on the input or occurrence of
a special event.
24
INT
O
25
26
27
28
29
30
31
32
33
34
35
36
37
38
IN2
IN3
I/O
I/O
I/O
P
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground for digital circuitry
IN4
DGND
IN5
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground/VBAT switch monitoring input with configurable current sink or source.
Ground switch monitoring input with current source
IN6
IN7
IN8
IN9
IN10
IN11
IN12
VS
Ground switch monitoring input with current source
Ground switch monitoring input with current source
Power supply input pin.
VS
P
Power supply input pin.
Exposed Pad. The exposed pad is not electrically connected to AGND or DGND. Connect
EP to the board ground to achieve rated thermal and ESD performance.
---
EP
P
(1) I = input, O = output, I/O = input and output, P = power.
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
-0.3
-0.3
-24
MAX
40(2)
6
UNIT
V
VS, INT
VDD, SCLK, SI, SO, CS, RESET
V
IN0- IN23
Input voltage
40(2)
5.5
5.5
2
V
CAP_Pre
-0.3
-0.3
-0.3
-40
V
CAP_A
CAP_D
V
V
Operating junction temperature, TJ
Storage temperature, Tstg
150
155
°C
°C
-55
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16 V for the life of a 12-V automotive
system. Refer to Using TIC10024-Q1 in a 12 V Automotive System for more details.
6.2 ESD Ratings
VALUE
±2000
±4000
±500
UNIT
All pins
Pins IN0-IN23(2)
All pins
Human-body model (HBM), per AEC Q100-002(1)
Charged-device model (CDM), per AEC Q100-011
Electrostatic
discharge
V(ESD)
V
Corner pins (pin 1, 19, 20
and 38)
±750
Contact discharge, un-powered, per ISO- 10605(3) (5)
Contact discharge, powered-up, per ISO- 10605 (4) (6)
Pins IN0-IN23
Pins IN0-IN23
±8000
±8000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) ±4kV rating on pins IN0-IN23 are stressed with respect to GND (with AGND, DGND, and EP tied together).
(3) External components: capacitor = 15 nF; resistor = 10 Ω
(4) External components: capacitor = 15 nF; resistor = 33 Ω
(5) ESD generator parameters: storage capacitance = 150 pF; discharge resistance = 330 Ωor 2000 Ω
(6) ESD generator parameters: storage capacitance = 150 pF or 330pF; discharge resistance = 330 Ωor 2000 Ω
6.3 Recommended Operating Conditions
over operating free-air temperature range and VS = 12 V (unless otherwise noted)
MIN
4.5
3.0
0
NOM
MAX
35 (2)
5.5
UNIT
V
VS
Power supply voltage
Logic supply voltage
VDD
V
V/INT
VINX
VRESET
VSPI_IO
fSPI
INT pin voltage
35(2)
35(2)
5.5
V
IN0 to IN23 input voltage
RESET pin voltage
0
V
0
V
SPI input/output logic level
SPI communication frequency
Operating free-air temperature
0
VDD
4M
V
20(1)
Hz
°C
TA
-40
125
(1) Lowest frequency characterized.
(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16 V for the life of a 12-V automotive
system. Refer to Using TIC10024-Q1 in a 12 V Automotive System for more details.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6.4 Thermal Information
TIC10024-Q1
DCP (TSSOP)
38 PINS
33.6
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
18.4
15.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
0.5
ψJT
15.0
ψJB
RθJC(bot)
1.2
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range, VS = 4.5 V to 35 V, and VDD = 3 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
Continuous mode VS Continuous mode, IWETT= 10 mA, all switches open, no active
power supply current comparator operation, no unserviced interrupt
IS_CONT
5.6
7
mA
IS_POLL_COMP_25
IS_POLL_COMP_85
IS_POLL_COMP
TA= 25°
68
68
68
100
110
170
µA
µA
µA
Polling mode VS
Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128
µs, all switches open, IWETT= 10 mA, no
unserviced interrupt
power supply average TA= -40° to 85°C
current
TA= -40° to 125°C
Reset mode VS power
supply current
IS_RESET
IS_IDLE_25
IS_IDLE_85
IS_IDLE
Reset mode, VRESET= VDD. VS= 12 V, all switches open, TA=25°C
12
50
50
50
1.5
17
75
µA
µA
µA
µA
µA
V
TRIGGER bit in CONFIG register = logic 0, TA= 25°C, no
unserviced interrupt
VS power supply
average current in
idle state
TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 85°C, no
unserviced interrupt
95
TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 125°C, no
unserviced interrupt
145
10
Logic supply current
from VDD
IDD
SCLK = SI = 0 V, CS = INT = VDD, no SPI communication
Threshold for rising VS from device OFF condition resulting in INT
pin assertion and a flagged POR bit in the INT_STAT register
VPOR_R
VPOR_F
VOV_R
3.85
1.95
35
4.5
2.8
40
Power on reset (POR)
voltage for VS
Threshold for falling VS from device normal operation to reset mode
and loss of SPI communication
V
Over-voltage (OV)
condition for VS
Threshold for rising VS from device normal operation resulting in
INT pin assertion and a flagged OV bit in the INT_STAT register
V
Over-voltage (OV)
condition hysteresis
for VS
VOV_HYST
1
3.5
V
Threshold for rising VS from under-voltage condition resulting in INT
pin assertion and a flagged UV bit in the INT_STAT register
VUV_R
VUV_F
3.85
3.7
4.5
4.4
V
V
Under-voltage (UV)
condition for VS
Threshold for falling VS from under-voltage condition resulting in
INT pin assertion and a flagged UV bit in the INT_STAT register
Under-voltage (UV)
condition hysteresis
for VS
VUV_HYST
75
275
mV
(1)
VDD_F
Threshold for falling VDD resulting in loss of SPI communication
2.5
50
2.9
V
Valid VDD voltage
hysteresis
VDD_HYST
150
mV
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating free-air temperature range, VS = 4.5 V to 35 V, and VDD = 3 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤100Ω , MINIMUM RESISTANCE
VALUE WITH SWITCH OPEN ≥5000 Ω)
1 mA setting
2 mA setting
0.84
1.71
2.39
4.3
1
2
1.14
2.32
5.5
4.5 V ≤VS ≤35 V
4.5 V ≤VS < 5 V
5 V ≤VS ≤35 V
4.5 V ≤VS < 6 V
6 V ≤VS ≤35 V
4.5 V ≤VS < 6.5 V
6.5 V ≤VS ≤35 V
5 mA setting
10 mA setting
15 mA setting
Wetting current
accuracy for CSO
(switch closed)
5
5.6
IWETT (CSO)
mA
2.4
11
8.4
10
11.4
16.5
17
2.4
12.5
0.75
1.6
15
1.1
1 mA setting
2 mA setting
5 mA setting
10 mA setting
2.05
3.3
2.2
4.5 V ≤VS ≤35 V
Wetting current
accuracy for CSI
(switch closed)
4.3
5.6
7.1
IWETT (CSI)
mA
9.2
11.5
16.5
16.5
13.4
19.2
19.2
11
4.5 V ≤VS < 6 V
6 V ≤VS ≤35V
15 mA setting
10 mA setting,
13.7
1.7
1.7
Voltage drop from INx
pin to AGND across
CSI (switch open)
R
SW= 5kΩ
15 mA setting,
SW= 5kΩ
2mA setting, IIN
VCSI_DROP_OPEN
V
V
4.5 V ≤VS ≤35V
R
=
1mA (4.5V ≤VS
≤35V)
1.2
5mA setting, IIN
1mA or 2mA
=
1.3
1.5
V
V
Voltage drop from INx
pin to ground across
CSI (switch closed)
VCSI_DROP_CLOSED
4.5 V ≤VS ≤35V
10mA setting, IIN
1mA, 2mA, or 5mA
=
15mA setting, IIN
=
1mA, 2mA, 5mA,
or 10mA
2.1
V
LEAKAGE CURRENTS
IIN_LEAK_OFF
-4
5.3
0.5
0 V ≤VINx ≤VS , channel disabled (EN_INx register bit= logic 0)
Leakage current at
input INx when
channel is disabled
µA
0 V ≤VINx ≤VS , channel disabled (EN_INx register bit= logic 0),
TA = 25°C
IIN_LEAK_OFF_25
-0.5
Leakage current at
input INx when
wetting current setting
is 0mA
µA
µA
IIN_LEAK_0mA
-110
-5
110
0 V ≤VINx ≤6 V, 6 V ≤VS ≤35 V , IWETT setting = 0 mA
Leakage current at
input INx under loss
of GND condition
VS = 24 V, 0 V ≤VINx ≤24 V, all grounds (AGND, DGND, and EP)
IIN_LEAK_LOSS_OF_GND
µA
µA
= 24 V, VDD shorted to the grounds(1)
Leakage current at
input INx under loss
of VS condition
IIN_LEAK_LOSS_OF_VS
5
0 V ≤VINx ≤24 V, VS shorted to the grounds = 0 V, VDD = 0 V
LOGIC LEVELS
I/INT = 2 mA
I/INT = 4 mA
0.35
0.6
INT output low
voltage
V/INT_L
V
VSO_L
VSO_H
VIN_L
VIN_H
SO output low voltage ISO = 2 mA
0.2VDD
V
V
SO output high
ISO = -2 mA
voltage
0.8VDD
0.7VDD
SI, SCLK, and CS
input low voltage
0.3VDD
V
V
SI, SCLK, and CS
input high voltage
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6.5 Electrical Characteristics (continued)
over operating free-air temperature range, VS = 4.5 V to 35 V, and VDD = 3 V to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RESET input low
voltage
VRESET_L
VRESET_H
0.8
V
RESET input high
voltage
1.6
V
RRESET_25
RRESET
VRESET= 0 to 5.5V, TA = 25°C
0.85
0.2
1.25
1.7
2.1
RESET pin internal
pull-down resistor
MΩ
VRESET= 0 to 5.5V, TA = –40° to 125°C
COMPARATOR PARAMETERS
Comparator threshold
for 2 V
VTH_ COMP_2V
VTH_ COMP_2p7V
VTH_ COMP_3V
VTH_ COMP_4V
THRES_COMP = 2 V
THRES_COMP = 2.7 V
THRES_COMP = 3 V
THRES_COMP = 4 V
1.85
2.4
2.25
2.9
V
V
V
V
Comparator threshold
for 2.7 V
Comparator threshold
for 3 V
2.85
3.7
3.3
Comparator threshold
for 4 V
4.35
THRES_COMP = 2 V
THRES_COMP = 2.7 V
THRES_COMP = 3 V
THRES_COMP = 4 V
THRES_COMP = 2 V
THRES_COMP = 2.7 V
THRES_COMP = 3 V
THRES_COMP = 4 V
4.5
5
Minimum VS
requirement for
proper detection
VS_COMP
V
5.5
6.5
30
35
35
43
130
130
105
95
Comparator
equivalent input
resistance
RIN, COMP
kΩ
(1) Specified by design.
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6.6 Timing Requirements
VS= 4.5 V to 35 V, VDD= 3 V to 5.5 V, and 10 pF capacitive load on SO unless otherwise noted; verified by design and
characterization
MIN
NOM
MAX UNIT
SWITCH MONITORING, INTERRUPT, STARTUP AND RESET
tPOLL_ACT Polling active time accuracy
Polling mode
Polling mode
-12%
-12%
12%
12%
µs
tPOLL
Polling time accuracy
tCOMP
Comparator detection time
18
20
tCCP_TRA
Transition time between last input sampling and start of clean current
µs
N
tCCP_ACT Clean current active time
tSTARTUP Polling startup time
-12%
200
12%
300
2
400
2.5
µs
tINT_ACTIV
Active INT assertion duration
1.5
ms
E
tINT_INACT
INT de-assertion duration during a pending interrupt
3
80
2
4
5
ms
µs
µs
IVE
tINT_IDLE Interrupt idle time
100
120
Time required to keep the RESET pin high to successfully reset the device (no pending
tRESET
tREACT
interrupt)(1)
Delay between a fault event (OV, UV, TW, or TSD) to a
high to low transition on the INT pin
20
µs
See 图7-2 for OV example.
SPI INTERFACE
tLEAD Falling edge of CS to rising edge of SCLK setup time
tLAG
100
100
30
ns
ns
ns
ns
ns
ns
Falling edge of SCLK to rising edge of CS setup time
SI to SCLK falling edge setup time
tSU
tHOLD
tVALID
tSO(EN)
SI hold time after falling edge of SCLK
20
Time from rising edge of SCLK to valid SO data
Time from falling edge of CS to SO low-impedance
70
60
Loading of 1 kΩ to GND.
See 图7-3.
tSO(DIS)
Time from rising edge of CS to SO high-impedance
60
ns
tR
tF
SI, CS, and SCLK signals rise time
SI, CS, and SCLK signals fall time
5
5
30
30
ns
ns
tINTER_FR
Delay between two SPI communication ( CS low) sequences
1.5
µs
AME
tCKH
tCKL
SCLK High time
SCLK Low time
120
120
45
ns
ns
µs
tINITIATION Delay between valid VDD voltage and initial SPI communication
(1) If there is a pending interrupt (/INT pin asserted low), it can take up to 1ms for the device to complete the reset.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
6.7 Typical Characteristics
18
16
14
12
10
8
IWETT=1mA
IWETT=1mA
16
14
12
10
8
IWETT=2mA
IWETT=5mA
IWETT=10mA
IWETT=15mA
IWETT=2mA
IWETT=5mA
IWETT=10mA
IWETT=15mA
6
6
4
4
2
2
0
0
0
5
10
15
20
VS voltage (V)
25
30
35
40
-40 -20
0
20
40
60
Temperature (C)
80 100 120 140 160
D001
D001
TA = 25°C
VS = 12 V
图6-1. Wetting Current Output - CSO vs. VS Voltage
图6-2. Wetting Current Output - CSO vs. Temperature
4
3.75
3.5
THRES_COMP=2V
THRES_COMP=2.7V
THRES_COMP=3V
THRES_COMP=4V
3.25
3
2.75
2.5
2.25
2
1.75
0
5
10
15
20
VS voltage (V)
25
30
35
40
D001
TA = 25°C
图6-3. Comparator Threshold vs. VS Voltage
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
7 Parameter Measurement Information
VDD
tINITIATION
tINTERFRAME
/CS
ttLAG
t
ttCKH
t
ttCKLt
ttLEAD
t
SCLK
tHOLD
ttSU
t
SI
tSO(EN)
tVALID
tSO(DIS)
SO
图7-1. SPI Timing Parameters
VOV_R
VS
tREACT
/INT
V/INT_L
图7-2. tREACT Timing Parameters
VIN_H
/CS
SO
tSO(DIS)
SO
VSO_H
GND
图7-3. tSO(DIS) Timing Parameters
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8 Detailed Description
8.1 Overview
The TIC10024-Q1 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect
external mechanical switch status in a 12-V automotive system by acting as an interface between the switches
and the low-voltage microcontroller. The TIC10024-Q1 is an integrated solution that replaces many discrete
components and provides integrated protection, input serialization, and system wake-up capability.
The device monitors 14 switches to GND and 10 additional switches that can be programmed to be connected to
either GND or VBAT. It features SPI interface to report individual switch status and provides programmability to
control the device operation. The TIC10024-Q1 features an integrated comparator that can be used to monitor
external digital switch input status. The device has 2 modes of operation: continuous mode and polling mode.
The polling mode is a low-power mode that can be activated to reduce current drawn in the system by only
turning on the wetting current for a small duty cycle to detect switch status changes. An interrupt is generated
upon detection of switch status change and it can be used to wake up the microcontroller to bring the entire
system back to operation.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.2 Functional Block Diagram
VS
37
VS
38
VS
Over-voltage
protection
1mA to 15mA
or
Over-temperature
protection
OFF
SW
Under-voltage
protection
IN0
IN1
IN2
IN3
13
14
AGND
ESD
Protection
1mA to 15mA
22
Pre-regulator
CAP_PRE
or
OFF
25
26
AGND
20
23
Analog LDO
Digital LDO
CAP_A
CAP_D
VS
Power management
AGND
1mA to 15mA
or
OFF
SW
IN9
33
ESD
Protection
1mA to 15mA
VDIG
or
OFF
Oscillator
24
/INT
AGND
State
machine
AGND
R1
SW
+
19
15
16
17
18
21
VDD
/CS
VS
œ
Control
logic
+
œ
SCLK
SI
Input/
output
buffer
AGND
AGND
1mA to 15mA
or
OFF
SO
Registers
SW
RESET
IN10 34
ESD
Protection
Digital Block
35
IN11
1MΩ
VS
DGND
AGND
IN12 36
1
IN13
1mA to 15mA
or
OFF
SW
IN23 12
ESD
Protection
AGND
DGND
9
28
DGND
AGND
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.3 Feature Description
8.3.1 VS Pin
The VS supply provides power to the entire chip and it is designed to be connected directly to a 12-V automotive
battery through a reverse-polarity blocking diode.
8.3.2 VDD Pin
The VDD supply is used to determine the logic level on the SPI communication interface, source the current for
the SO driver, and sets the pull-up voltage for the CS pin. It can also be used as a possible external pull-up
supply for the INT pin in addition to the VS and it shall be connected to a 3 V to 5.5-V logic supply. Removing
VDD from the device disables SPI communications but does not reset the register configurations.
8.3.3 Device Initialization
When the device is powered up for the first time, the condition is called Power-On Reset (POR), which sets the
registers to their default values and initializes the device state machine. The internal POR controller holds the
device in a reset condition until VS has reached VPOR_R, at which the reset condition is released with the device
registers and state machine initialized to their default values. After the initialization process is completed, the INT
pin is asserted low to notify the microcontroller, and the register bit POR in the INT_STAT register is asserted to
logic 1. The SPI flag bit POR is also asserted at the SPI output (SO).
During device initialization, factory settings are programmed into the device to allow accurate device operation.
The device performs a self-check after the device is programmed to ensure correct settings are loaded. If the
self-check returns an error, the CHK_FAIL bit in the INT_STAT register will be flagged to logic 1 along with the
POR bit. If this event occurs the microcontroller is recommended to initiate software reset (see section Software
Reset) to re-initialize the device to allow the correct settings to be re-programmed.
8.3.4 Device Trigger
After device initialization, the TIC10024-Q1 is ready to be configured. The microcontroller can use SPI
commands to program desired settings to the configuration registers. Once the device configuration is
completed, the microcontroller is required to set the bit TRIGGER in the CONFIG register to logic 1 in order to
activate wetting current and start external switch monitoring.
After switch monitoring initiates, the configuration registers turn into read-only registers (with the exception of the
TRIGGER, CRC_T, and RESET bits in the CONFIG register and all bits in the CCP_CFG1 register). If at any
time the device setting needs to be re-configured, the microcontroller is required to first set the bit TRIGGER in
the CONFIG register to logic 0 to stop wetting current and switch monitoring. The microcontroller can then
program configuration registers to the desired settings. Once the re-configuration is completed the
microcontroller can set the TRIGGER bit back to logic 1 to re-start switch monitoring.
Note the cyclic redundancy check (CRC) feature stays accessible when TRIGGER bit is in logic 1, allowing the
microcontroller to verify device settings at all time. Refer to section Cyclic Redundancy Check (CRC) for more
details of the CRC feature.
8.3.5 Device Reset
There are 3 ways to reset the TIC10024-Q1 and re-initialize all registers to their default values:
8.3.5.1 VS Supply POR
The device is turned off and all register contents are lost if the VS voltage drops below VPOR_F. To turn the device
back on, the VS voltage must be raised back above VPOR_R, as illustrated in 图 8-1. The device then starts the
initialization process as described in section Device Initialization.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
VS
Device
OFF
Normal
Operation
Device
OFF
Normal
Operation
VPOR_R
VPOR_F
Time
图8-1. VS is Lowered Below The POR threshold, Then Ramped Back Up To Complete A POR Cycle
8.3.5.2 Hardware Reset
Microcontroller can toggle the RESET pin to perform a hardware reset to the device. The RESET pin is internally
pulled-down by a resistor (1.25MΩ typical) and must be kept low for normal operation. When the RESET pin is
toggled high, the device enters the reset state with most of the internal blocks turned off and consumes very little
current of IS_RESET. Switch monitoring and SPI communications are stopped in the reset state, and all register
contents are cleared. When RESET pin is toggled back low, all the registers are set to their default values and
the device state machine is re-initialized, similar to a POR event. When the re-initialization process is completed
the INT pin is asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to
notify the microcontroller that the device has completed the reset process.
Note in order to successfully reset the device, the RESET pin needs to be kept high for a minimum duration of
tRESET. The pin is required to be driven with a stable input (below VRESET_L for logic low or above VRESET_H for
logic H) to prevent the device from accidental reset.
8.3.5.3 Software Reset
In addition to hardware reset the microcontroller can also issue a SPI command to initiate software reset.
Software reset is triggered by setting the RESET bit in the register CONFIG to logic 1, which re-initializes the
device with all registers set to their default values. Once the re-initialization process is completed, the INT pin is
asserted low, and the interrupt register bit POR and the SPI status flag POR are both asserted to notify the
microcontroller that the device has completed the reset process.
8.3.6 VS Under-Voltage (UV) Condition
During normal operation of a typical 12 V automotive system, the VS voltage is usually quite stable and stays
well above 11 V. However, the VS voltage may drop temporarily during certain vehicle operations, such as cold
cranking. If the VS voltage drops below VUV_F, the TIC10024-Q1 enters the under-voltage (UV) condition since
there is not enough voltage headroom for the device to accurately generate wetting currents. The following
describes the behavior of the TIC10024-Q1 under UV condition:
1. All current sources and sinks de-activate and switch monitoring stops.
2. Interrupt is generated by asserting the INT pin low and the bit UV in the interrupt register (INT_STAT) is
flagged to logic 1. The bit UV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is
asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is
cleared on the rising edge of CS provided that the interrupt register has been read during the SPI
transaction.
3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status,
if needed, can be retrieved without interruption.
4. The device continues to monitor the VS voltage, and the UV condition sustains if the VS voltage continues to
stay below VUV_R. No further interrupt is generated once cleared.
Note the device resets as described in section VS Supply POR if the VS voltage drops below VPOR_F
.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
When the VS voltage rises above VUV_R, the INT pin is asserted low to notify the microcontroller that the UV
condition no longer exists. The UV bit in the register INT_STAT is flagged to logic 1 and the bit UV_STAT bit is
de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the UV condition. The device
resumes operation using current register settings (regardless of the INT pin and SPI communication status) with
polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is generated at the
end of the first polling cycle and the detected switch status becomes the baseline switch status for subsequent
polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared, and the INT
pin is released afterwards.
The following diagram describes the TIC10024-Q1 operation at various different VS voltages. If the VS voltage
stays above VUV_F (Case 1), the device stays in normal operation. If the VS voltage drops below VUV_F but stays
above VPOR_F (Case 2), the device enters the UV condition. If VS voltage drops below VPOR_F (Case 3), the
device resets and all register settings are cleared. The microcontroller is then required to re-program all the
configuration registers in order to resume normal operation after the VS voltage recovers.
VS
tCrankingt
Device
OFF
VPOR_R
Case 1
VUV_F
Case 2
VPOR_F
Case 3
Time
图8-2. TIC10024-Q1 Operation At Various VS Voltage Levels
8.3.7 VS Over-Voltage (OV) Condition
If VS voltage rises above VOV_R, the TIC10024-Q1 enters the over-voltage (OV) condition to prevent damage to
internal structures of the device on the VS and INx (for battery-connected switches) pins. The following describes
the behavior of the TIC10024-Q1 under OV condition:
1. All current sources and sinks de-activate and switch monitoring stops.
2. Interrupt is generated by asserting the INT pin low and the bit OV in the interrupt register (INT_STAT) is
flagged to logic 1. The bit OV_STAT is asserted to logic 1 in the register IN_STAT_MISC. The OI SPI flag is
asserted during any SPI transactions. The INT pin is released and the interrupt register (INT_STAT) is
cleared on the rising edge of CS provided that the interrupt register has been read during the SPI
transaction.
3. SPI communication stays active, and all register settings stay intact without resetting. Previous switch status,
if needed, can be retrieved without any interruption.
4. The device continues to monitor the VS voltage, and the OV condition sustains if the VS voltage continues to
stay above VOV_R- VOV_HYST. No further interrupt is generated once cleared.
When the VS voltage drops below VOV_R - VOV_HYST, the INT pin is asserted low to notify the microcontroller that
the over-voltage condition no longer exists. The OV bit in the register INT_STAT is flagged to logic 1 and the bit
OV_STAT bit is de-asserted to logic 0 in the register IN_STAT_MISC to reflect the clearance of the OV condition.
The device resumes operation using current register settings (regardless of the INT pin and SPI communication
status) with polling restarted from the first enabled channel. The Switch State Change (SSC) interrupt is
generated at the end of the first polling cycle and the detected switch status becomes the baseline status for
subsequent polling cycles. The content of the INT_STAT register, once read by the microcontroller, is cleared
and the INT pin is released afterwards.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.3.8 Switch Inputs Settings
IN0 to IN23 are inputs connected to external mechanical switches. The switch status of each input, whether
open or closed, is indicated by the status registers. 表 8-1 below describes various settings that can be
configured for each input. Note some settings are shared between multiple inputs. It is required to first stop
device operation by setting the TRIGGER bit low in the register CONFIG before making any configuration
changes, as described in Device Trigger.
表8-1. TIC10024-Q1 Wetting Current and Threshold Setting Details
Current Source (CSO) / Current
Input
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
IN8
IN9
Threshold
Wetting Current
Supported Switch Type
Sink (CSI)
CSO
CSI
Switch to GND
Switch to VBAT
WC_IN0_IN1
CSO
CSI
Switch to GND
Switch to VBAT
THRES_COMP_IN0_IN3
CSO
CSI
Switch to GND
Switch to VBAT
WC_IN2_IN3
CSO
CSI
Switch to GND
Switch to VBAT
CSO
CSI
Switch to GND
Switch to VBAT
WC_IN4
WC_IN5
CSO
CSI
Switch to GND
Switch to VBAT
THRES_COMP_IN4_IN7
CSO
CSI
Switch to GND
Switch to VBAT
WC_IN6_IN7
WC_IN8_IN9
CSO
CSI
Switch to GND
Switch to VBAT
CSO
CSI
Switch to GND
Switch to VBAT
CSO
CSI
Switch to GND
Switch to VBAT
THRES_COMP_IN8_IN11
IN10
IN11
IN12
IN13
IN14
IN15
IN16
IN17
IN18
IN19
IN20
IN21
IN22
IN23
WC_IN10
WC_IN11
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
CSO
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
Switch to GND
WC_IN12_13
WC_IN14_15
WC_IN16_17
WC_IN18_19
WC_IN20_21
THRES_COMP_IN12_IN15
THRES_COMP_IN16_IN19
THRES_COMP_IN20_IN23
WC_IN22
WC_IN23
8.3.8.1 Input Current Source and Sink Selection
Among the 24 inputs, IN10 to IN23 are intended for monitoring only ground-connected switches and are
connected to current sources. IN0 to IN9 can be programmed to monitor either ground-connected switches or
battery-connected switches by configuring the CS_SELECT register. The default configuration of the IN0-IN9
inputs after POR is to monitor ground-connected switches (current sources are selected). To set an input to
monitor battery-connected switches, set the corresponding bit to logic 1.
8.3.8.2 Input Enable Selection
The TIC10024-Q1 provides switch status monitoring for up to 24 inputs, but there might be circumstances in
which not all inputs need to be constantly monitored. The microcontroller may choose to enable or disable
monitoring of certain inputs by configuring the IN_EN register. Setting the corresponding bit to logic 0 de-
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
17
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
activates the wetting current source and sink and stops switch status monitoring for the input. Disabling
monitoring of unused inputs reduces overall power consumption of the device.
All inputs are disabled by default upon device reset.
8.3.8.3 Thresholds Adjustment
The threshold level for interrupt generation can be programmed by setting the THRES_COMP register. The
threshold level settings can be set for each individual input groups and each group consists of 4 inputs. Four
threshold levels are available: 2 V, 2.7 V, 3 V, and 4 V.
Remember to use caution when setting up the threshold for switches that are connected externally to the battery
as there is a finite voltage drop (as high as VCSI_DROP_OPEN for 10mA and 15mA settings) across the current
sinks. Therefore, even for an open switch, then voltage on the INx pin can be as high as VCSI_DROP_OPEN and the
detection threshold shall be configured above it. It shall also be noted that a lower wetting current sink setting
may not be strong enough to pull the INx pin close to ground in the presence of a leaky open external switch, as
illustrated in the diagram below (see 图8-3). In this example, the external switch, although in the open state, has
large leakage current and can be modelled as an equivalent resistor (RDIRT) of 5kΩ. The 2mA current sink is only
able to pull the INx pin voltage down to 4 V, even if the switch is in the open state.
Battery- connected switch
+
14V
RDIRT
RSW
œ
VBAT
5kΩ
GND
Open
TIC10024-Q1
INx
2mA
GND
Copyright © 2016, Texas Instruments Incorporated
图8-3. Example Showing The Calculation of The INx Pin Voltage For A Leaky Battery-Connected Switch
8.3.8.4 Wetting Current Configuration
There are 6 different wetting current settings (0 mA, 1 mA, 2 mA, 5 mA, 10 mA, and 15mA) that can be
programmed by configuring the WC_CFG0 and WC_CFG1 registers. 0 mA is selected by default upon device
reset.
The accuracy of the wetting current has stronger dependency on the VS voltage when VS voltage is low. The
lower the VS voltage falls, the more deviation on the wetting currents from their nominal values. Refer to
IWETT (CSO) and IWETT (CSI) specifications for more details.
8.3.9 Interrupt Generation and INT Assertion
The INT pin is an active-low, open-drain output that asserts low when an event (switch input state change,
temperature warning, over-voltage shut down etc.) is detected by the TIC10024-Q1. An external pull-up resistor
to VDD is needed on the INT pin (see 图 8-4). The INT pin can also be connected directly to a 12-V automotive
battery to support the microcontroller wake-up feature, as describe in 节8.3.9.3.
Copyright © 2022 Texas Instruments Incorporated
18
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
TIC10024-Q1
Microcontroller
VDD
VDD
/INT
GPI
AGND
GND
AGND
GND
Copyright © 2016, Texas Instruments Incorporated
图8-4. INT Connection Example #1
8.3.9.1 INT Pin Assertion Scheme
TIC10024-Q1 supports two configurable schemes for INT assertion: static and dynamic. The scheme can be
adjusted by configuring the INT_CONFIG bit in the CONFIG register.
If the static INT assertion scheme is used (INT_CONFIG = 0 in the CONFIG register), the INT pin is asserted low
upon occurrence of an event. The INT pin is released on the rising edge of CS only if a READ command has
been issued to read the INT_STAT register while CS is low, otherwise the INT will be kept low indefinitely. The
content of the INT_STAT interrupt register is latched on the first rising edge of SCLK after CS goes low for every
SPI transaction, and the content is cleared upon a READ command issued to the INT_STAT register, as
illustrated in 图8-5.
ꢀꢁINT_STAT register
content cleared
ꢀꢁ/INT pin released
Event
occurrence
/INT
/CS
Register READ
(non- INT_STAT register)
Register READ
(INT_STAT register)
图8-5. Static INT Assertion Scheme
In some system implementations an edge-triggered based microcontroller might potentially miss the INT
assertion if it is configured to the static scheme, especially when the microcontroller is in the process of waking
up. To prevent missed INT assertion and improve robustness of the interrupt behavior, the TIC10024-Q1
provides the option to use the dynamic assertion scheme for the INT pin. When the dynamic scheme is used
(INT_CONFIG= 1 in the CONFIG register), the INT pin is asserted low for a duration of tINT_ACTIVE and is de-
asserted back to high if the INT_STAT register has not been read after tINT_ACTIVE has elapsed. The INT is kept
high for a duration of tINT_INACTIVE, and is re-asserted low after tINT_INACTIVE has elapsed. The INT pin continues
to toggle until the INT_STAT register is read.
If the INT_STAT register is read when INT pin is asserted low, the INT pin is released on the READ command’s
CS rising edge and the content of the INT_STAT register is also cleared, as shown in 图 8-6. If the INT_STAT
register is read when INT pin is de-asserted, the content of the INT_STAT register is cleared on the READ
command’s CS rising edge, and the INT pin is not re-asserted back low, as shown in 图8-7.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
19
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
ꢀꢁINT_STAT register
content cleared
ꢀꢁ/INT pin released
Event
occurrence
ttINT_INACTIVE
t
/INT
/CS
tINT_ACTIVE
Register READ
(INT_STAT register)
图8-6. Dynamic INT Assertion Scheme With INT_STAT Register Read During tINT_ACTIVE
ꢀꢁINT_STAT register
content cleared
ꢀꢁ/INT pin will not be re-
asserted tINT_INACTIVE
after /INT returns high
Event
occurrence
ttINT_INACTIVE
t
/INT
/CS
tINT_ACTIVE
Register READ
(INT_STAT register)
图8-7. Dynamic INT Assertion Scheme With INT_STAT Register Read During tINT_INACTIVE
The static INT assertion scheme is selected by default upon device reset. The INT pin assertion scheme can
only be changed when bit TRIGGER is logic 0 in the CONFIG register.
8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
Interrupt idle time (tINT_IDLE) is implemented in TIC10024-Q1 to:
• Allow the INT pin enough time to be pulled back high by the external pull-up resistor and allow the next
assertion to be detectable by an edge-triggered microcontroller.
• Minimize the chance of glitching on the INT pin if back-to-back events occur.
When there is a pending interrupt event and the interrupt event is not masked, tINT_IDLE is applied after the
READ command is issued to the INT_STAT register. If another event occurs during the interrupt idle time the
INT_STAT register content is updated instantly but the INT pin is not asserted low until tINT_IDLE has elapsed. If
another READ command is issued to the INT_STAT register during tINT_IDLE, the INT_STAT register content is
cleared immediately, but the INT pin is not re-asserted back low after tINT_IDLE has elapsed. An example of the
interrupt idle time is given below to illustrate the INT pin behavior under the static INT assertion schemes:
Copyright © 2022 Texas Instruments Incorporated
20
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
/INT pin is not
asserted until
tINT_IDLE has expired
1st Event
2nd Event
occurrence
occurrence
/INT
/CS
ttINT_IDLE
Register READ
(INT_STAT register)
Register READ
(INT_STAT register)
图8-8. INT Assertion Scheme With tINT_IDLE
8.3.9.3 Microcontroller Wake-Up
Using a few external components, the INT pin can be used for wake-up purpose to activate a voltage regulator
through its inhibit inputs. An implementation example is shown in 图8-9. This implementation is especially useful
for waking up a microcontroller in sleep mode to allow significant system-level power savings.
Before the wake-up event, the INT pin is in high impedance state on the TIC10024-Q1. The microcontroller can
be kept in sleep state with all its GPIOs in logic low. Hence, Q2 remains off with its based in logic low state and
the base of Q1 is weakly pulled-high to the VS level. This causes Q1 to remain off, and the LDO_EN signal is
pulled-down to logic low to disable the regulator's output. VDD is therefore unavailable to both the TIC10024-Q1
device and the microcontroller and SPI communication is not supported. Switch status monitoring, however, is
still active in the TIC10024-Q1.
When an event, such as switch status change, temperature warning, or overvoltage, occurs, the INT pin is
asserted low by TIC10024-Q1, causing Q1 to turn on to activate the voltage regulator. The microcontroller is
then reactivated, and the communication between the microcontroller and the TIC10024-Q1 is reestablished.
The microcontroller can then access stored event information using SPI communication. Note since the INT pin
is de-asserted after the INT_STAT register is read, the microcontroller is required to keep the regulator on by
driving the μC_LDO_EN signal high. This allows VDD to stay high to provide power to the microcontroller and
support SPI communications.
The wake-up implementation is applicable only when the device is configured to use the static INT assertion
scheme.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
21
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
Regulator
VIN
+
VBAT
10kΩ
œ
VOUT
Q1
GND
Microcontroller
LDO_EN
10kΩ
TIC10024-Q1
10kΩ
GND
V3p3
VDD
VDD
10kΩ
/INT
ꢀC_INT
GPIO 1
GPIO 2
Q2
ꢀC_LDO_EN
AGND
GND
GND
10kΩ
GND
GND
图8-9. INT Connection to Support Microcontroller Wake-Up
8.3.9.4 Interrupt Enable / Disable And Interrupt Generation Conditions
Each switch input can be programmed to enable or disable interrupt generation upon status change by
configuring registers INT_EN_COMP1 to INT_EN_COMP2 .
The abovementioned registers can also be used to control interrupt generation condition based on the following
settings:
1. Rising edge: an interrupt is generated if the current input measurement is above the corresponding
threshold and the previous measurement was below.
2. Falling edge: an interrupt is generated if the current input measurement is below the corresponding
threshold and the previous measurement was above.
3. Both edges: changes of the input voltage in either direction results in an interrupt generation.
Note interrupt generation from switch status change is disabled for all inputs by default upon device reset.
Copyright © 2022 Texas Instruments Incorporated
22
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.3.9.5 Detection Filter
When monitoring the switch input status, a detection filter can be configured by setting the DET_FILTER bits in
the CONFIG register to generate Switch Status Change (SSC) interrupt only if the same input status (w.r.t the
threshold) is sampled consecutively. This detection filter can be useful to debounce inputs during a switch toggle
event. Four different filtering schemes are available:
1. Generate an SSC interrupt if the voltage level at an input crossed its threshold
2. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 2 consecutive polling cycles
3. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 3 consecutive polling cycles
4. Generate an SSC interrupt if the voltage level at an input crossed its threshold and the status is stable (w.r.t.
the threshold) for at least 4 consecutive polling cycles
The default value of switch status is stored internally after the 1st detection cycle, even if detection filter (by
configure the DET_FILTER in the CONFIG register) is used. An example is illustrated below with the assumption
that DET_FILTER in register CONFIG is set to 11 (SSC interrupt is generated if the input crosses the threshold
and the status is stable w.r.t. the threshold for at least 4 consecutive detection cycles). Assume switch status
change is detected in the 3rd detection cycle and stays the same for the next 3 cycles.
DETECTION CYCLE
1
2
3
4
5
6
•
•
•
Default Switch status stored
INT asserted
•
•
INT asserted
SSC flagged
Switch status change
detected
Event
—
—
—
SSC flagged
The detection filter counter is reset to 0 when the TRIGGER bit in the CONFIG register is de-asserted to logic 0.
Upon device reset, the default setting for the detection filter is set to generating an SSC interrupt at every
threshold crossing.
8.3.10 Temperature Monitor
With multiple switch inputs are closed and high wetting current setting is enabled, considerable power can be
dissipated by the device and raise the device temperature. TIC10024-Q1 has integrated temperature monitoring
and protection circuitry to put the device in low power mode to prevent damage due to overheating. Two types of
temperature protection mechanisms are integrated in the device: Temperature Warning (TW) and Temperature
Shutdown (TSD). The triggering temperatures and hysteresis are specified in 表8-2 below:
表8-2. Temperature Monitoring Characteristics of TIC10024-Q1
PARAMETER
MIN
130
150
TYP
140
160
15
MAX
155
UNIT
°C
Temperature warning trigger temperature (TTW
)
Temperature shutdown trigger temperature (TTSD
)
175
°C
Temperature hysteresis (THYS) for TTW and TTSD
°C
8.3.10.1 Temperature Warning (TW)
When the device temperature goes above the temperature warning trigger temperature (TTW), the TIC10024-Q1
performs the following operations:
1. Generate an interrupt by asserting the INT pin low and flag the TW bit in INT_STAT register to logic 1. The
TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.
2. The TW_STAT bit of the IN_STAT_MISC register is flagged to logic 1.
3. If the TW_CUR_DIS_CSO or TW_CUR_DIS_CSO bit in CONFIG register is set to logic 0 (default), the
wetting current is adjusted down to 2 mA for 10 mA or 15 mA settings. The wetting current stays at its pre-
configured value if 0 mA, 1 mA, 2 mA, or 5 mA setting is used.
4. Maintain the low wetting current as long as the device junction temperature stays above TTW - THYS
.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
23
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the
INT_STAT register has been read during CS low. The TIC10024-Q1 continues to monitor the temperature, but
does not issue further interrupts if the temperature continues to stay above TTW- THYS. The status bit TW_STAT
in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature warning condition exists.
If desired, the reduction of wetting current down to 2mA setting (from 10 mA or 15 mA) can be disabled by
setting the TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1. The interrupt is still
generated ( INT asserted low and INT_STAT interrupt register is updated) when the temperature warning event
occurs but the wetting current is not reduced. This setting applies to both the polling and continuous mode
operation. Note if the feature is enabled, switch detection result might be impacted upon TTW event if the wetting
current is reduced to 2mA from 10mA or 15mA.
When the temperature drops below TTW- THYS, the INT pin is asserted low (if released previously) to notify the
microcontroller that the temperature warning condition no longer exists. The TW bit of the interrupt register
INT_STAT is flagged logic 1. The TW_STAT bit in the IN_STAT_MISC register is de-asserted back to logic 0. The
device resumes operation using the current programmed settings (regardless of the INT and CS status).
8.3.10.2 Temperature Shutdown (TSD)
After the device enters TW condition, if the junction temperature continues to rise and goes above the
temperature shutdown threshold (TTSD), the TIC10024-Q1 enters the Temperature Shutdown (TSD) condition
and performs the following operations:
1. Opens all the switches connected to the current sources or sinks to prevent any further heating due to
excessive current flow.
2. Generate an interrupt by asserting the INT pin (if not already asserted) low and flag the TSD bit in the
INT_STAT register to logic 1. The TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions.
3. The TSD_STAT bit of the IN_STAT_MISC register is flagged to logic 1. The TW_STAT bit also stays at logic
1.
4. SPI communication stays on and all register settings stay intact without resetting. Previous switch status, if
needed, can be retrieved without any interruption.
5. Maintain the setting as long as the junction temperature stays above TTSD- THYS
.
The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the
INT_STAT register has been read during CS low. The TIC10024-Q1 continues to monitor the temperature, but
does not issue further interrupts if the temperature continues to stay above TTSD - THYS. The status bit
TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown
condition exists.
When the temperature drops below TTSD - THYS, the INT pin is asserted low (if released previously) to notify the
microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register
INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0,
while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting
described in section Temperature Warning if the temperature stays above TTW - THYS. Note the polling restarts
from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The
detected switch status from the first polling cycle becomes the default switch status for subsequent polling.
8.3.11 Parity Check And Parity Generation
The TIC10024-Q1 uses parity bit check to ensure error-free data transmission from/to the SPI commander.
The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data
on SO (including the parity bit) is an odd number (i.e. Bit0 ⊕Bit1 ⊕…⊕Bit30 ⊕Bit31⊕Parity = 1).
The device also uses odd parity check after receiving data on SI from the SPI commander. If the total number of
ones in the received data (including the parity bit) is an even number the received data is discarded. The INT will
be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host
that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications.
Copyright © 2022 Texas Instruments Incorporated
24
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.3.12 Cyclic Redundancy Check (CRC)
The TIC10024-Q1 includes a CRC module to support redundancy checks on the configuration registers to
ensure the integrity of data. The CRC calculation is based on the ITU-T X.25 implementation, and the CRC
polynomial (0x1021) used is popularly known as CRC-CCITT-16 since it was initially proposed by the ITU-T
(formerly CCITT) committee. The CRC calculation rule is defined in 表8-3:
表8-3. CRC Calculation Rule
CRC RULE
CRC result width
Polynomial
VALUE
16 bits
x16 + x12 + x5 +1 (1021h)
Initial (seed) value
Input data reflected
Result data reflected
XOR value
FFFFh
No
No
0000h
The CRC calculation is done on all the configuration registers starting from register CONFIG and ending at
register INT_EN_CFG0 (address 1Ah through 24h). The device substitutes a “zero” for each reserved
configuration register bit during the CRC calculation. The CRC calculation can be triggered by asserting the
CRC_T bit in the CONFIG register. Once completed, the CRC_CALC interrupt bit in the INT_STAT register is
asserted and an interrupt is issued. The 16-bit CRC calculation result is stored in the register CRC. This interrupt
can be disabled by de-asserting the CRC_CALC_EN bit in the INT_EN_CFG0 register. It is important to avoid
writing data to the configuration registers when the device is undergoing CRC calculations to prevent false
calculation results.
图 8-10 shows the block diagram of the CRC module. The module consists of 16 shift-registers and 3 exclusive-
OR gates. The registers start with 1111-1111-1111-1111 (or FFFFh) and the module performs an XOR function
and shifts its content until the last bit of the register string is used. The final register’s content after the last data
bit is the calculated CRC value of the data set and the content is stored in the CRC register.
Note the CRC_T bit self-clears after the CRC calculation is completed. Logic 1 is used for CRC_T bit during
CRC calculation.
X15 X14 X13 X12
X11 X10
X9
X8
X7
X6
X5
X4
X3
X2
X1
X0
+
+
+
XOR
XOR
XOR
Data
MSB
LSB
图8-10. CCITT-16 CRC Module Block Diagram
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
25
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
8.4 Device Functional Modes
The TIC10024-Q1 has 2 modes of operation: continuous mode and polling mode. The following sections
describe the two operation modes in details as well as some of the advanced features that could be activated
during normal operations.
8.4.1 Continuous Mode
In continuous mode, wetting current is continuously applied to each enabled input channel, and the status of
each channel is sampled sequentially (starting from the IN0 to IN23). The TIC10024-Q1 monitors enabled inputs
and issues an interrupt (if enabled) if a switch status change event is detected. The wetting current setting for
each input can be individually adjusted by configuring the WC_CFG0 and WC_CFG1 to the 0mA, 1mA, 2mA,
5mA, 10mA, or 15mA setting.
图 8-11 below illustrates an example of the timing diagram of the detection sequence in continuous mode. After
the TRIGGER bit in register CONFIG is set to logic 1, it takes tSTARTUP to activate the wetting current for all
enabled inputs. The wetting currents stay on continuously, while each input is routed to the comparator for
sampling in a sequential fashion. After detection is done for an input, the switch status (below or above detection
threshold) is stored in the register (IN_STAT_COMP) to be used as the default state for subsequent detection
cycles. After the end of the first polling cycle, the INT pin is asserted low to notify the microcontroller that the
default switch status is ready to be read. The SSC bit in INT_STAT register and the SPI status flag SSC are also
asserted to logic 1. The polling cycle time (tPOLL) determines how frequently each input is sampled and can be
configured in the register CONFIG.
Input sampling restarts
from first enabled input
after tPOLL_TIME
Wetting
current
TRIGGER bit set
to logic 1 in
CONFIG register
ttPOLL_TIME
t
ttSTARTUP
t
IN0
IN1
IN3
tCOMP
t
tCOMP
t
IN23
/INT
ñ Default input status is stored
ñ /INT pin is asserted after the
1st detection cycle
Time
图8-11. An Example Of The Detection Sequence In Continuous Mode
Copyright © 2022 Texas Instruments Incorporated
26
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
The INT_STAT register is cleared and INT pin de-asserted if a SPI READ command is issued to the register.
Note the interrupt is always generated after the 1st detection cycle (after the TRIGGER bit in register CONFIG is
set to logic 1). In subsequent detection cycles, the interrupt is generated only if switch status change is detected.
No wetting currents are applied to 0mA- configured inputs, although some biasing current (as specified by
IIN_LEAK_0mA) may still flow in and out of the input. Threshold crossing monitoring is still performed for the input
using the defined threshold(s). The 0mA setting is useful to utilize the integrated comparator to measure applied
voltage on a specific input without being affected by the device wetting current.
8.4.2 Polling Mode
The polling mode can be activated to reduce current drawn in ignition-off condition to conserve battery charge.
Unlike the continuous mode, the current sources/sinks do not stay on continuously in the polling mode. Instead,
they are turned on/off sequentially from IN0 to IN23 and cycled through each individual input channel. The
microcontroller can be put to sleep to reduce overall system power. If a switch status change (SSC) is detected
by the TIC10024-Q1, the INT pin (if enabled for the input channel) is asserted low (and the SSC bit in INT_STAT
register and the SPI status flag SSC are also asserted to logic 1). The INT pin assertion can be used to wake up
the system regulator which, in turn, wakes up the microcontroller as described in section Microcontroller Wake-
Up. The microcontroller can then use SPI communication to read the switch status information.
The polling is activated when the TRIGGER bit in the CONFIG register is set to logic 1.
In polling mode, wetting current is applied to each input for a pre-programmed polling active time between 64 μs
and 2048 μs, set by the POLL_ACT_TIME bits in the CONFIG register . At the end of the wetting current
application, the input voltage is sampled by the comparator. Each input is cycled through in sequential order
from IN0 to IN23. Sampling is repeated at a frequency from 2 ms to 4096 ms, set by the POLL_TIME bits in the
CONFIG register . Wetting currents are applied to closed switches only during the polling active time; hence the
overall system current consumption can be greatly reduced.
Similar to continuous mode, after the first polling cycle, the switch status of each input (below or above detection
threshold) is stored in the register (IN_STAT_COMP) to be used as the default state for subsequent polling
cycles. The INT pin is asserted low to notify the microcontroller that the default switch status is ready to be read.
The SSC bit in INT_STAT register and the SPI status flag SSC are also asserted to logic 1. The INT_STAT
register is cleared and INT pin de-asserted if a SPI READ command is issued to the register. Note the interrupt
is always generated after the 1st polling cycle (after the TRIGGER bit in register CONFIG is set to logic 1). In
subsequent polling cycles the interrupt is generated only if switch status change is detected.
An example of the timing diagram of the polling mode operation is shown in 图8-12.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
27
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
Wetting current is
activated for
tPOLL_ACT_TIME
Wetting
current
Input sampling restarts
from first enabled input
after tPOLL_TIME
TRIGGER bit set
to logic 1 in
CONFIG register
ttPOLL_ACT_TIME
t
ttPOLL_TIME
t
ttSTARTUP
t
ttPOLL_ACT_TIMEt
ttSTARTUP
t
IN0
IN1
IN3
tCOMP
t
tCOMP
t
IN23
/INT
ñ Default input status is stored
ñ /INT pin is asserted after the
1st detection cycle
tCOMP
t
Time
图8-12. An Example Of The Polling Sequence In Standard Polling Mode
Copyright © 2022 Texas Instruments Incorporated
28
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
If the switch position changes between two active polling times, no interrupt will be generated and the status
register (IN_STAT_COMP) will not reflect such a change. An example is shown in 图8-13.
Wetting
current
Switch
state
Ignored
Initial switch
switch state
state change
change
/INT
/INT asserted
due to initial
state change
/CS
Time
图8-13. Example For Ignored Switch Position Change Between 2 Wetting Current Cycles
8.4.3 Additional Features
There are additional features that can be enabled during continuous and polling mode to increase robustness of
device operation or provide more system information. These features are described in detail in the following
sections.
8.4.3.1 Clean Current Polling (CCP)
In real automotive system, lower wetting current is generally desired to reduce the system's overall power
consumption. However, certain system design requires 10 mA or higher cleaning current to clear oxide build-up
on the mechanical switch contact surface when the current is applied to closed switches. A special type of
polling, called the Clean Current Polling (CCP), can be used for this application.
If CCP is enabled each polling cycle consists of two wetting current activation steps. The first step uses the
wetting current setting configured in the WC_CFG0 and WC_CFG1 registers as in the continuous mode or
polling mode. The second step (cleaning cycle) is activated simultaneously for all CCP enabled inputs at a time
tCCP_TRAN after the normal polling step of the last enabled input. Interrupt generation and INT pin assertion is not
impacted by the clean current pulses.
The wetting current and its active time for the cleaning cycle can be configured in the CCP_CFG0 register. The
cleaning cycle can be disabled, if desired, for each individual input by programming the CCP_CFG1 register.
CCP is available for both continuous mode and polling mode. To use the CCP feature, at least one input has to
be enabled.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
29
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
图8-14 illustrates the operation of the CCP when the device is configured to the polling mode.
Wetting
current
TRIGGER bit set
to logic 1 in
CONFIG register
ttPOLL_TIME
t
tSTARTUP
IN0
tSTARTUP
IN1
IN2
tCOMP
t
ttCCP_TIME
t
IN22
IN23
ttCCP_TRAN
t
/INT
/CS
ñ Default input status is stored
ñ /INT pin is asserted after the
1st detection cycle
Read on INT_STAT register
release the /INT pin
Time
图8-14. Polling With CCP Enabled
Copyright © 2022 Texas Instruments Incorporated
30
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
图8-15 illustrates the operation of the CCP when the device is configured to the continuous mode:
Wetting
current
TRIGGER bit set
to logic 1 in
CONFIG register
ttPOLL_TIME
t
tSTARTUP
IN0
tSTARTUP
IN1
IN2
tCOMP
t
ttCCP_TIME
t
IN22
IN23
/INT
/CS
ñ Default input status is stored
ñ /INT pin is asserted after the
1st detection cycle
Read on INT_STAT register
release the /INT pin
Time
图8-15. Continue Mode With CCP Enabled
8.4.3.2 Wetting Current Auto-Scaling
The 10 mA and 15 mA wetting current settings are useful to clean oxide build-up on the mechanical switch
contact surface when the switch changes state from open to close. After the switch is closed, it is undesirable to
keep the wetting current level at high level if only digital switches are monitored since it results in high current
consumption and could potentially heat up the device quickly if multiple inputs are monitored. The wetting current
auto-scaling feature helps mitigate this issue.
When enabled (AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0 in the WC_CFG1 register),
wetting current is reduced to 2 mA from 10 mA or 15 mA setting after switch closure is detected. The threshold
used to determine a switch closure is the threshold configured in the THRES_COMP register.
The current reduction takes place N cycles after switch closure is detected on an input, where N depends on the
setting of the DET_FILTER bits in the CONFIG register:
• DET_FILTER= 00: wetting current is reduced immediately in the next detection cycle after a closed switch is
detected.
• DET_FILTER= 01: wetting current is reduced when a closed switch is detected and the switch status is stable
for at least 2 consecutive detection cycles.
• DET_FILTER= 10: wetting current is reduced when a closed switch is detected and the switch status is stable
for at least 3 consecutive detection cycles.
• DET_FILTER= 11: wetting current is reduced when a closed switch is detected and the switch status is stable
for at least 4 consecutive detection cycles.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
31
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
The wetting current is adjusted back to the original setting of 10 mA or 15 mA at a time of N cycles after an open
switch is detected, where N again depends on the DET_FILTER bit setting in the CONFIG register. 图 8-16
depicts the behavior of the wetting current auto-scaling feature.
Switch open
Switch closed
Auto-scaling
disabled
15mA
15mA
0mA
0mA
Auto-scaling
enabled
2mA
图8-16. Wetting Current Auto-scaling Behavior
The wetting current auto-scaling only applies to 10 mA and 15 mA settings and is only available in continuous
mode. If AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit is set to logic 1 in the WC_CFG1 registers,
the wetting current stays at its original setting when a closed switch is detected. Power dissipation needs to be
closely monitored when wetting current auto-scaling is disabled for multiple inputs as the device could heat up
quickly when high wetting current settings are used. If the auto-scaling feature is disabled in continuous mode,
the total power dissipation can be approximated using 方程式1.
P
=VS ì
IS _CONT + IWETT (TOTAL)
TOTAL
(1)
where IWETT (TOTAL) is the sum of all wetting currents from all input channels. Increase in device junction
temperature can be calculated based on P × RθJA. The junction temperature must be below TTSD for proper
device operation. An interrupt will be issued when the junction temperature exceeds TTW or TTSD. For detailed
description of the temperature monitoring, please refer to sections Temperature Warning (TW) and Temperature
Shutdown (TSD).
Copyright © 2022 Texas Instruments Incorporated
32
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9 Programming
The SPI interface communication consists of the 4 pins: CS, SCLK, SI, and SO. The interface can work with
SCLK frequency up to 4 MHz.
9.1 SPI Communication Interface Buses
9.1.1 Chip Select ( CS)
The system microcontroller selects the TIC10024-Q1 to receive communication using the CS pin. With the CS
pin in a logic LOW state, command words may be sent to the TIC10024-Q1 through the serial input (SI) pin, and
the device information can be retrieved by the microcontroller through the serial output (SO) pin. The falling edge
of the CS enables the SO output and latches the content of the interrupt register INT_STAT. The microcontroller
may issue a READ command to retrieve information stored in the registers. Rising edge on the CS pin initiates
the following operations:
1. Disable the output driver and makes SO high-impedance.
2. INT pin is reset to logic HIGH if a READ command to the INT_STAT register was issued during CS = LOW.
To avoid corrupted data, it is essential the HIGH-to-LOW and LOW-to-HIGH transitions of the CS signal occur
only when SCLK is in a logic LOW state. A clean CS signal is needed to ensure that no incomplete SPI words
are sent to the device. The CS pin should be externally pulled up to VDD by a 10 kΩresistor.
9.1.2 System Clock (SCLK)
The system clock (SCLK) input is used to clock the internal shift register of the TIC10024-Q1. The SI data is
latched into the input shift register on the falling edge of the SCLK signal. The SO pin shifts the device stored
information out on the rising edge of SCLK. The SO data is available for the microcontroller to read on the falling
edge of SCLK.
False clocking of the shift register must be avoided to ensure validity of data and it is essential the SCLK pin be
in a logic LOW state whenever CS makes any transition. Therefore, it is recommended that the SCLK pin gets
pulled to a logic LOW state as long as the device is not accessed and CS is in a logic HIGH state. When the CS
is in a logic HIGH state, any signal on the SCLK and SI pins will be ignored and the SO pin remains as a high
impedance output. Refer to 图9-1 and 图9-2 for examples of typical SPI read and write sequence.
9.1.3 Slave In (SI)
The SI pin is used for serial instruction data input. SI information is latched into the input register on the falling
edge of the SCLK. To program a complete word, 32 bits of information must be entered into the device. The SPI
logic counts the number of bits clocked into the IC and enables data latching only if exactly 32 bits have been
clocked in. In case the word length exceeds or does not meet the required length, the SPI_FAIL bit of the
INT_STAT register is asserted to logic 1 and the INT pin will be asserted low. The data received is considered
invalid. Note the SPI_FAIL bit is not flagged if SCLK is not present.
9.1.4 Slave Out (SO)
The SO pin is the output from the internal shift register. The SO pin remains high-impedance until the CS pin
transitions to a logic LOW state. The negative transition of CS enables the SO output driver and drives the SO
output to the HIGH state (by default). The first positive transition of SCLK makes the status data bit 31 available
on the SO pin. Each successive positive clock makes the next status data bit available for the microcontroller to
read on the falling edge of SCLK. The SI/SO shifting of the data follows a first-in, first-out scheme, with both
input and output words transferring the most significant bit (MSB) first.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
33
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.2 SPI Sequence
图 9-1 and 图 9-2 depict the SPI communication sequence during read and write operations for the TIC10024-
Q1.
Bit 31
(MSB)
Bit 0
(LSB)
...
Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 1
Read/
Write
SI
Register address
Data in
PAR
0
Bit 31
(MSB)
Bit 0
(LSB)
...
Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 1
SO
Status flag
Data out
PAR
SPI_ PRTY_
POR
SSC
RES TEMP
OI
FAIL
FAIL
图9-1. TIC10024-Q1 Read SPI Sequence
Bit 31
(MSB)
Bit 0
(LSB)
...
...
Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 1
Read/
Write
SI
Register address
Data in
PAR
1
Bit 31
(MSB)
Bit 0
(LSB)
Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Bit 23 Bit 22
Bit 1
SO
Status flag
Previous content of the
register addressed
PAR
SPI_ PRTY_
FAIL FAIL
POR
SSC
RES TEMP
OI
图9-2. TIC10024-Q1 Write SPI Sequence
9.2.1 Read Operation
The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of
the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent a valid
command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication
errors.
On the SO bus, the status flags will be outputted from the TIC10024-Q1, followed by the data content in the
register that was requested. The LSB is the parity bit used to detect communication errors.
Note there are several test mode registers used in the TIC10024-Q1 in addition to the normal functional
registers, and a READ command to these test registers returns the register content. If a READ command is
issued to an invalid register address, the TIC10024-Q1 returns all 0’s.
9.2.2 Write Operation
The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of the
register to be accessed follows next on the SI bus. Note the register needs to be a writable configuration register,
or otherwise the command will be ignored. The content from bit 24 to bit 1 represents the data to be written to
the register. The LSB (bit 0) is the parity bit used to detect communication errors.
Copyright © 2022 Texas Instruments Incorporated
34
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
On the SO bus, the status flags will be output from the TIC10024-Q1, followed by the previous data content of
the written register. The previous content of the register is latched after the full register address is decoded in the
SI command (after bit 25 is transmitted). The new data will replace the previous data content at the end of the
SPI transaction if the SI write is a valid command (valid register address and no SPI/parity error). If the write
command is invalid, the new data will be ignored and the register content will remain unchanged. The LSB is the
parity bit used to detect communication errors.
Note there are several test mode registers used in the TIC10024-Q1 in addition to the normal functional
registers. A WRITE command to these test registers has no effect on the register content, even though the
register content is returned on the SO output. If a WRITE command is issued to an invalid register address, the
SO output returns all 0’s.
9.2.3 Status Flag
The status flags are output from SO during every READ or WRITE SPI transaction to indicate system conditions.
These bits do not belong to an actual register, but their content is mirrored from the interrupt register INT_STAT.
A READ command executed on the INT_STAT would clear both the bits inside the register and the status flag.
The following table describes the information that can be obtained from each SPI status flag:
表9-1. TIC10024-Q1 SPI Status Flag Description
SYMBOL
NAME
DESCRIPTION
This flag mirrors the POR bit in the interrupt register INT_STAT, and it indicates, if set to 1, that a reset event has
occurred. This bit is asserted after a successful power-on-reset, hardware reset, or software reset. Refer to 节
8.3.5 for more details.
POR
Power-on Reset
This flag mirrors the SPI_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI
responder in (SI) transaction is invalid. To program a complete word, 32 bits of information must be entered into
the device. The SPI logic counts the number of bits clocked into the IC and enables data latching only if exactly
32 bits have been clocked in. In case the word length exceeds or does not meet the required size, the SPI_FAIL
bit, which mirrors its value to this SPI_FAIL status flag, of the interrupt register INT_STAT will be set to 1 and the
INT pin will be asserted low. The data received will be considered invalid. Once the INT_STAT register is read, its
content will be cleared on the rising edge of CS. The SPI_FAIL status flag, which mirrors the SPI_FAIL bit in the
INT_STAT register, will also be de-asserted. Note the SPI_FAIL bit is not flagged if SCLK is not present.
SPI_FAIL
SPI Error
This flag mirrors the PRTY_FAIL bit in the interrupt register INT_STAT and it indicates, if set to 1, that the last SPI
responder in (SI) transaction has a parity error. The device uses odd parity. If the total number of ones in the
received data (including the parity bit) is an even number, the received data is discarded. The INT will be
asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1, and the
PRTY_FAIL status flag, which mirrors the PRTY_FAIL bit in the INT_STAT register, is also set to 1. Once the
INT_STAT register is read, its content will be cleared on the rising edge of CS. The PRTY_FAIL status flag, which
mirrors the PRTY_FAIL bit in the INT_STAT register, will also be de-asserted.
PRTY_FAIL
Parity Fail
This flag mirrors the SSC bit in the interrupt register INT_STAT and it indicates, if set to 1, that one or more switch
inputs crossed a threshold. To determine the origin of the state change, the microcontroller can read the content
of the register IN_STAT_COMP. Once the interrupt register (INT_STAT) is read, its content will be cleared on the
rising edge of CS. The SSC status flag, which mirrors the SSC bit in the INT_STAT register, will also be de-
asserted.
SSC
RES
Switch State Change
Reserved
This flag is reserved and is always at logic 0.
This flag is set to 1 if either Temperature Warning (TW) or Temperature Shutdown (TSD) bit in the interrupt
register INT_STAT is flagged to 1. It indicates a TW event or a TSD event has occurred. It is also flagged to 1 if a
TW event or a TSD event is cleared. The interrupt register INT_STAT should be read to determine which event
occurred. The SPI commander can also read the IN_STAT_MISC register to get information on the temperature
status of the device. Once the interrupt register (INT_STAT) is read, its content will be cleared on the rising edge
of CS, and the TEMP status flag will also be de-asserted.
TEMP
Temperature Event
Other Interrupt
Other interrupt include interrupts such as OV, UV, CRC_CALC and CHK_FAIL. This flag will be asserted 1 when
any of the above mentioned bits is flagged in the interrupt register INT_STAT. The interrupt register INT_STAT
should be read to determine which event(s) occurred. The SPI commander can also read the IN_STAT_MISC
register to get information on the latest status of the device. Once the INT_STAT register is read, its content will
be cleared on the rising edge of CS, and the OI status flag will also be de-asserted.
OI
9.3 Programming Guidelines
When configuring the TIC10024-Q1, it is critical to follow the programming guideline summarized below (see 表
9-2) to ensure proper behavior of the device:
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
35
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-2. TIC10024-Q1 Programming Guidelines
Category
Programming Requirement
Clean Current Polling (if CCP_INx = 1 in the
CCP_CFG1 register)
At least one input has to be enabled: IN_EN_x = 1 in the IN_EN register
•
•
The wetting current auto-scaling feature is only activated in the continuous mode:
POLL_EN = 0 (1)
Wetting current auto-scaling (if WC_CFG1
[22:21] != 2b’11)
The wetting current auto-scaling only applies to 10mA or 15mA wetting currents:
WC_INx bits = 3’b100, 3’b101, 3’b110, or 3’b111 in the WC_CFG0 and
WC_CFG1 registers.(1)
tPOLL_TIME and tPOLL_ACT_TIME settings have to meet the below requirement: tPOLL_TIM E
1.3 × [ tPOLL_ACT_TIME + n × 24 μs + 10 μs](2)
≥
Continuous mode
Polling mode
•
•
•
n: the number of enabled channels configured in register IN_EN
tPOLL_TIME: timing setting configured in CONFIG[4:1]
tPOLL_ACT_TIME: timing setting configured in CONFIG[8:5]
(1) These are soft requirements to take advantage of the wetting current auto-scaling feature. The feature takes no effect otherwise.
(2) If CCP is enabled, add tCCP_TRAN +tCCP_TIME, where tCCP_TIME is the timing setting configured in CCP_CFG0[6:4]
9.4 Register Maps
表 9-3 lists the memory-mapped registers for the TIC10024-Q1. All register offset addresses not listed in 表 9-3
should be considered as reserved locations and the register contents should not be modified.
表9-3. TIC10024-Q1 Registers
OFFSET
1h
TYPE
R
RESET
120h
1h
ACRONYM
REGISTER NAME
SECTION
Go
DEVICE_ID
INT_STAT
Device ID Register
2h
RC
R
Interrupt Status Register
Go
3h
FFFFh CRC
CRC Result Register
Go
4h
R
0h
0h
IN_STAT_MISC
IN_STAT_COMP
Miscellaneous Status Register
Comparator Status Register
RESERVED
Go
5h
R
Go
6h-19h
1Ah
RESERVED
—
—
0h
0h
0h
0h
0h
0h
0h
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CONFIG
Device Global Configuration Register
Input Enable Register
Go
Go
Go
Go
Go
Go
Go
1Bh
IN_EN
1Ch
CS_SELECT
Current Source/Sink Selection Register
Wetting Current Configuration Register
Clean Current Polling Register
Comparator Threshold Control Register
1Dh-1Eh
1Fh-20h
21h
WC_CFG0, WC_CFG1
CCP_CFG0, CCP_CFG1
THRES_COMP
22h-23h
INT_EN_COMP1,
INT_EN_COMP2
Comparator Input Interrupt Generation Control
Register
24h
R/W
0h
INT_EN_CFG0
RESERVED
Global Interrupt Generation Control Register
RESERVED
Go
25h-32h
—
—
—
Copyright © 2022 Texas Instruments Incorporated
36
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.1 DEVICE_ID register (Offset = 1h) [reset = 20h]
DEVICE_ID is shown in 图9-3 and described in 表9-4.
Return to Summary Table.
This register represents the device ID of the TIC10024-Q1.
图9-3. DEVICE_ID Register
23
22
10
21
9
20
8
19
18
RESERVED
R-0h
17
16
15
3
14
2
13
1
12
0
11
7
6
5
4
RESERV
ED
MAJOR
MINOR
R-0h
R-0h
R-12h
LEGEND: R = Read only
表9-4. DEVICE_ID Register Field Descriptions
Bit
Field
Type
Reset
Description
23-11
RESERVED
R
0h
RESERVED
10-4
MAJOR
R
12h
These 7 bits represents major revision ID. For TIC10024-Q1 the
major revision ID is 12h.
3-0
MINOR
R
0h
These 4 bits represents minor revision ID. For TIC10024-Q1 the
minor revision ID is 0h.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
37
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.2 INT_STAT Register (Offset = 2h) [reset = 1h]
INT_STAT is shown in 图9-4 and described in 表9-5.
Return to Summary Table.
This register records the information of the event as it occurs in the device. A READ command executed on this
register clears its content and resets the register to its default value. The INT pin is released at the rising edge of
the CS pin from the READ command.
图9-4. INT_STAT Register
23
22
21
20
19
18
10
2
17
16
RESERVED
R-0h
15
14
13
12
11
9
8
RESERVED
R-0h
CHK_FAIL
RC-0h
RESERVED
R-0h
CRC_CALC
RC-0h
7
6
5
4
3
1
0
UV
OV
TW
TSD
SSC
RC-0h
PRTY_FAIL
RC-0h
SPI_FAIL
RC-0h
POR
RC-1h
RC-0h
RC-0h
RC-0h
RC-0h
LEGEND: R = Read only; RC = Read to clear
表9-5. INT_STAT Register Field Descriptions
Bit
Field
Type
Reset
Description
23-14
RESERVED
R
0h
RESERVED
13
CHK_FAIL
RC
0h
0h = Default factory setting is successfully loaded upon device
initialization or the event status got cleared after a READ command
was executed on the INT_STAT register.
1h = An error is detected when loading factory settings into the
device upon device initialization.
During device initialization, factory settings are programmed into the
device to allow proper device operation. The device performs a self-
check after the device is programmed to diagnose whether correct
settings are loaded. If the self-check returns an error, the CHK_FAIL
bit is flagged to logic 1 along with the POR bit. The host controller is
then recommended to initiate a software reset (see section Software
Reset) to re-initialize the device and allow correct settings to be re-
programmed.
12-9
8
RESERVED
CRC_CALC
R
0h
0h
RESERVED
RC
0h = CRC calculation is running, not started, or was acknowledged
after a READ command was executed on the INT_STAT register.
1h = CRC calculation is finished.
CRC calculation (see section Cyclic Redundancy Check (CRC)) can
be triggered to make sure correct register values are programmed
into the device. Once the calculation is completed, the CRC_CALC
bit is flagged to logic 1 to indicate completion of the calculation, and
the result can then be accessed from the CRC (offset = 3h) register.
Copyright © 2022 Texas Instruments Incorporated
38
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-5. INT_STAT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
7
UV
RC
0h
0h = No under-voltage condition occurred or cleared on the VS pin,
or the event status got cleared after a READ command was
executed on the INT_STAT register.
1h = Under-voltage condition occurred or cleared on the VS pin.
When the UV bit is flagged to logic 1, it indicates the Under-Voltage
(UV) event has occurred. The bit is also flagged to logic 1 when the
event clears. For more details about the UV operation, please refer
to section VS under-voltage (UV) condition.
6
5
4
OV
RC
RC
RC
0h
0h
0h
0h = No over-voltage condition occurred or cleared on the VS pin, or
the event status got cleared after a READ command was executed
on the INT_STAT register.
1h = Over-voltage condition occurred or cleared on the VS pin.
When the OV bit is flagged to logic 1, it indicates the Over-Voltage
(OV) event has occurred. The bit is also flagged to logic 1 when the
event clears. For more details about the OV operation, please refer
to section VS over-voltage (OV) condition.
TW
0h = No temperature warning event occurred or the event status got
cleared after a READ command was executed on the INT_STAT
register.
1h = Temperature warning event occurred or cleared.
When the TW bit is flagged to logic 1, it indicates the temperature
warning event has occurred. The bit is also flagged to logic 1 when
the event clears. For more details about the temperature warning
operation, please refer to section Temperature Warning (TW)
TSD
0h = No temperature Shutdown event occurred or the event status
got cleared after a READ command was executed on the INT_STAT
register.
1h = Temperature Shutdown event occurred or cleared.
When the TSD bit is flagged to logic 1, it indicates the temperature
shutdown event has occurred. The bit is also flagged to logic 1 when
the event clears. For more details about the temperature shutdown
operation, please refer to section Temperature shutdown (TSD)
3
SSC
RC
0h
0h = No switch state change occurred or the status got cleared after
a READ command was executed on the INT_STAT register.
1h = Switch state change occurred.
The Switch State Change (SSC) bit indicates whether input threshold
crossing has occurred from switch inputs IN0 to IN23. This bit is also
flagged to logic 1 after the first polling cycle is completed after device
polling is triggered.
2
PRTY_FAIL
RC
0h
0h = No parity error occurred in the last received SI stream or the
error status got cleared after a READ command was executed on the
INT_STAT register.
1h = Parity error occurred.
When the PRTY_FAIL bit is flagged to logic 1, it indicates the last
SPI responder in (SI) transaction has a parity error. The device uses
odd parity. If the total number of ones in the received data (including
the parity bit) is an even number, the received data is discarded. The
value of this register bit is mirrored to the PRTY_FLAG SPI status
flag.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
39
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-5. INT_STAT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1
SPI_FAIL
RC
0h
0h = 32 clock pulse during a CS = low sequence was detected or the
error status got cleared after a READ command was executed on the
INT_STAT register.
1h = SPI error occurred
When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI
responder in (SI) transaction is invalid. To program a complete word,
32 bits of information must be entered into the device. The SPI logic
counts the number of bits clocked into the IC and enables data
latching only if exactly 32 bits have been clocked in. In case the word
length exceeds or does not meet the required length, the SPI_FAIL
bit is flagged to logic 1, and the data received is considered invalid.
The value of this register bit is mirrored to the SPI_FLAG SPI status
flag. Note the SPI_FAIL bit is not flagged if SCLK is not present.
0
POR
RC
1h
0h = no Power-On-Reset (POR) event occurred or the status got
cleared after a READ command was executed on the INT_STAT
register.
1h = Power-On-Reset (POR) event occurred.
The Power-On-Reset (POR) interrupt bit indicates whether a reset
event has occurred. A reset event sets the registers to their default
values and re-initializes the device state machine. This bit is
asserted after a successful power-on-reset, hardware reset, or
software reset. The value of this register bit is mirrored to the POR
SPI status flag.
Copyright © 2022 Texas Instruments Incorporated
40
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.3 CRC Register (Offset = 3h) [reset = FFFFh]
CRC is shown in 图9-5 and described in 表9-6.
Return to Summary Table.
This register returns the CRC-16-CCCIT calculation result. The microcontroller can compare this value with its
own calculated value to ensure correct register settings are programmed to the device.
图9-5. CRC Register
23 22 21 20 19 18 17 16 15 14 13 12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
R-0h
CRC
R-FFFFh
LEGEND: R = Read only
表9-6. CRC Register Field Descriptions
Bit
Field
Type
Reset
Description
23-16
RESERVED
R
0h
Reserved
15-0
CRC
R
FFFFh
CRC-16-CCITT calculation result: Bit1: LSB of CRC Bit16: MSB or
CRC
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
41
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.4 IN_STAT_MISC Register (Offset = 4h) [reset = 0h]
IN_STAT_MISC is shown in 图9-6 and described in 表9-7.
Return to Summary Table.
This register indicates current device status unrelated to switch input monitoring.
图9-6. IN_STAT_MISC Register
23
15
7
22
14
6
21
13
5
20
12
4
19
11
3
18
10
17
9
16
8
RESERVED
R-0h
RESERVED
R-0h
2
1
0
RESERVED
R-0h
UV_STAT
R-0h
OV_STAT
R-0h
TW_STAT
R-0h
TSD_STAT
R-0h
表9-7. IN_STAT_MISC Register Field Descriptions
Bit
Field
Type
Reset
Description
23-4
3
RESERVED
UV_STAT
R
0h
Reserved
R
R
R
0h
0h
0h
0h = VS voltage is above the under-voltage condition threshold.
1h = VS voltage is below the under-voltage condition threshold.
2
1
OV_STAT
TW_STAT
0h = VS voltage is below the over-voltage condition threshold.
1h = VS voltage is above the over-voltage condition threshold.
0h = Device junction temperature is below the temperature warning
threshold TTW
1h = Device junction temperature is above the temperature warning
threshold TTW
.
.
0
TSD_STAT
R
0h
0h = Device junction temperature is below the temperature shutdown
threshold TTSD
1h = Device junction temperature is above the temperature shutdown
threshold TTSD
.
.
Copyright © 2022 Texas Instruments Incorporated
42
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.5 IN_STAT_COMP Register (Offset = 5h) [reset = 0h]
IN_STAT_COMP is shown in 图9-7 and described in 表9-8.
Return to Summary Table.
This register indicates whether an input is below or above the comparator threshold.
图9-7. IN_STAT_COMP Register
23
22
21
20
19
18
17
16
INC_23
R-0h
INC_22
R-0h
INC_21
R-0h
INC_20
R-0h
INC_19
R-0h
INC_18
R-0h
INC_17
R-0h
INC_16
R-0h
15
14
13
12
11
10
9
8
INC_15
R-0h
INC_14
R-0h
INC_13
R-0h
INC_12
R-0h
INC_11
R-0h
INC_10
R-0h
INC_9
R-0h
INC_8
R-0h
7
6
5
4
3
2
1
0
INC_7
R-0h
INC_6
R-0h
INC_5
R-0h
INC_4
R-0h
INC_3
R-0h
INC_2
R-0h
INC_1
R-0h
INC_0
R-0h
LEGEND: R = Read only
表9-8. IN_STAT_COMP Register Field Descriptions
Bit
Field
Type
Reset
Description
23
INC_23
R
0h
0h = Input IN23 is below the comparator threshold.
1h = Input IN23 is above the comparator threshold.
22
21
20
19
18
17
16
15
14
13
12
11
INC_22
INC_21
INC_20
INC_19
INC_18
INC_17
INC_16
INC_15
INC_14
INC_13
INC_12
INC_11
R
R
R
R
R
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = Input IN22 is below the comparator threshold.
1h = Input IN22 is above the comparator threshold.
0h = Input IN21 is below the comparator threshold.
1h = Input IN21 is above the comparator threshold.
0h = Input IN20 is below the comparator threshold.
1h = Input IN20 is above the comparator threshold.
0h = Input IN19 is below the comparator threshold.
1h = Input IN19 is above the comparator threshold.
0h = Input IN18 is below the comparator threshold.
1h = Input IN18 is above the comparator threshold.
0h = Input IN17 is below the comparator threshold.
1h = Input IN17 is above the comparator threshold.
0h = Input IN16 is below the comparator threshold.
1h = Input IN16 is above the comparator threshold.
0h = Input IN15 is below the comparator threshold.
1h = Input IN15 is above the comparator threshold.
0h = Input IN14 is below the comparator threshold.
1h = Input IN14 is above the comparator threshold.
0h = Input IN13 is below the comparator threshold.
1h = Input IN13 is above the comparator threshold.
0h = Input IN12 is below the comparator threshold.
1h = Input IN12 is above the comparator threshold.
0h = Input IN11 is below the comparator threshold.
1h = Input IN11 is above the comparator threshold.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
43
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-8. IN_STAT_COMP Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
10
INC_10
R
0h
0h = Input IN10 is below the comparator threshold.
1h = Input IN10 is above the comparator threshold.
9
8
7
6
5
4
3
2
1
0
INC_9
INC_8
INC_7
INC_6
INC_5
INC_4
INC_3
INC_2
INC_1
INC_0
R
R
R
R
R
R
R
R
R
R
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = Input IN9 is below the comparator threshold.
1h = Input IN9 is above the comparator threshold.
0h = Input IN8 is below the comparator threshold.
1h = Input IN8 is above the comparator threshold.
0h = Input IN7 is below the comparator threshold.
1h = Input IN7 is above the comparator threshold.
0h = Input IN6 is below the comparator threshold.
1h = Input IN6 is above the comparator threshold.
0h = Input IN5 is below the comparator threshold.
1h = Input IN5 is above the comparator threshold.
0h = Input IN4 is below the comparator threshold.
1h = Input IN4 is above the comparator threshold.
0h = Input IN3 is below the comparator threshold.
1h = Input IN3 is above the comparator threshold.
0h = Input IN2 is below the comparator threshold.
1h = Input IN2 is above the comparator threshold.
0h = Input IN1 is below the comparator threshold.
1h = Input IN1 is above the comparator threshold.
0h = Input IN0 is below the comparator threshold.
1h = Input IN0 is above the comparator threshold.
Copyright © 2022 Texas Instruments Incorporated
44
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.6 CONFIG Register (Offset = 1Ah) [reset = 0h]
CONFIG is shown in 图9-8 and described in 表9-9.
Return to Summary Table.
图9-8. CONFIG Register
23
15
7
22
14
6
21
20
19
18
17
16
RESERVED
TW_CUR_DIS_
CSI
R-0h
12
R/W-0h
8
13
11
10
9
DET_FILTER
R/W-0h
TW_CUR_DIS_ INT_CONFIG
CSO
TRIGGER
POLL_EN
CRC_T
POLL_ACT_TI
ME
R/W-0h
5
R/W-0h
4
R/W-0h
3
R/W-0h
2
R/W-0h
1
R/W-0h
0
POLL_ACT_TIME
R/W-0h
POLL_TIME
R/W-0h
RESET
R/W-0h
LEGEND: R/W = Read/Write
表9-9. CONFIG Register Field Descriptions
Bit
Field
Type
Reset
Description
23-17
RESERVED
R
0h
Reserved
16
TW_CUR_DIS_CSI
R/W
0h
0h = Enable wetting current reduction (to 2 mA) for 10mA and 15mA
settings upon TW event for all inputs enabled with CSI.
1h = Disable wetting current reduction (to 2 mA) for 10mA and 15mA
settings upon TW event for all inputs enabled with CSI.
15-14
DET_FILTER
R/W
0h
For detailed descriptions for the detection filter, refer to section
Detection Filter.
0h = every sample is valid and taken for threshold evaluation
1h = 2 consecutive and equal samples required to be valid data
2h = 3 consecutive and equal samples required to be valid data
3h = 4 consecutive and equal samples required to be valid data
13
12
TW_CUR_DIS_CSO
INT_CONFIG
R/W
R/W
0h
0h
0h = Enable wetting current reduction (to 2mA) for 10mA and 15mA
settings upon TW event for all inputs enabled with CSO.
1h = Disable wetting current reduction (to 2mA) for 10mA and 15mA
settings upon TW event for all inputs enabled with CSO.
For detailed descriptions for the INT pin assertion scheme, refer to
section Interrupt Generation and /INT Assertion.
0h = INT pin assertion scheme set to static
1h = INT pin assertion scheme set to dynamic
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
45
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-9. CONFIG Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
11
TRIGGER
R/W
0h
When the TRIGGER bit is set to logic 1, normal device operation
(wetting current activation and polling) starts. To stop device
operation and keep the device in an idle state, de-assert this bit to 0.
After device normal operation is triggered, if at any time the device
setting needs to be re-configured, the microcontroller is required to
first set the bit TRIGGER to logic 0 to stop device operation. Once
the re-configuration is completed, the microcontroller can set the
TRIGGER bit back to logic 1 to re-start device operation. If re-
configuration is done on the fly without first stopping the device
operation, false switch status could be reported and accidental
interrupt might be issued. The following register bits are the
exception and can be configured when TRIGGER bit is set to logic 1:
–TRIGGER (bit 11 of the CONFIG register)
–CRC_T (bit 9 of the CONFIG register)
–RESET (bit 0 of the CONFIG register)
–The CCP_CFG1 register
0h = Stop TIC10024-Q1 from normal operation.
1h = Trigger TIC10024-Q1 normal operation
10
9
POLL_EN
CRC_T
R/W
R/W
0h
0h
0h = Polling disabled. Device operates in continuous mode.
1h = Polling enabled and the device operates in one of the polling
modes.
Set this bit to 1 to trigger a CRC calculation on all the configuration
register bits. Once triggered, it is strongly recommended the SPI
commander does not change the content of the configuration
registers until the CRC calculation is completed to avoid erroneous
CRC calculation result. The TIC10024-Q1 sets the CRC_CALC
interrupt bit and asserts the INT pin low when the CRC calculation is
completed. The calculated result will be available in the CRC
register. This bit self-clears back to 0 after CRC calculation is
executed.
0h = no CRC calculation triggered
1h = trigger CRC calculation
8-5
POLL_ACT_TIME
R/W
0h
0h = 64μs
1h = 128μs
2h = 192μs
3h = 256μs
4h = 320μs
5h = 384μs
6h = 448μs
7h = 512μs
8h = 640μs
9h = 768μs
Ah = 896μs
Bh = 1024μs
Ch = 2048μs
Dh-15h = 512μs (most frequently-used setting)
Copyright © 2022 Texas Instruments Incorporated
46
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-9. CONFIG Register Field Descriptions (continued)
Bit
Field
POLL_TIME
Type
Reset
Description
4-1
R/W
0h
0h = 2ms
1h = 4ms
2h = 8ms
3h = 16ms
4h = 32ms
5h = 48ms
6h = 64ms
7h = 128ms
8h = 256ms
9h = 512ms
Ah = 1024ms
Bh = 2048ms
Ch = 4096ms
Dh-15h = 8ms (most frequently-used setting)
0
RESET
R/W
0h
0h = No reset
1h = Trigger software reset of the device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
47
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.7 IN_EN Register (Offset = 1Bh) [reset = 0h]
IN_EN is shown in 图9-9 and described in 表9-10.
Return to Summary Table.
图9-9. IN_EN Register
23
22
21
20
19
18
17
16
IN_EN_23
R/W-0h
IN_EN_22
R/W-0h
IN_EN_21
R/W-0h
IN_EN_20
R/W-0h
IN_EN_19
R/W-0h
IN_EN_18
R/W-0h
IN_EN_17
R/W-0h
IN_EN_16
R/W-0h
15
14
13
12
11
10
9
8
IN_EN_15
R/W-0h
IN_EN_14
R/W-0h
IN_EN_13
R/W-0h
IN_EN_12
R/W-0h
IN_EN_11
R/W-0h
IN_EN_10
R/W-0h
IN_EN_9
R/W-0h
IN_EN_8
R/W-0h
7
6
5
4
3
2
1
0
IN_EN_7
R/W-0h
IN_EN_6
R/W-0h
IN_EN_5
R/W-0h
IN_EN_4
R/W-0h
IN_EN_3
R/W-0h
IN_EN_2
R/W-0h
IN_EN_1
R/W-0h
IN_EN_0
R/W-0h
LEGEND: R/W = Read/Write
表9-10. IN_EN Register Field Descriptions
Bit
Field
Type
Reset
Description
23
IN_EN_23
R/W
0h
0h = Input channel IN23 disabled. Polling sequence skips this
channel
1h = Input channel IN23 enabled.
22
21
20
19
18
17
16
15
IN_EN_22
IN_EN_21
IN_EN_20
IN_EN_19
IN_EN_18
IN_EN_17
IN_EN_16
IN_EN_15
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h = Input channel IN22 disabled. Polling sequence skips this
channel
1h = Input channel IN22 enabled.
0h = Input channel IN21 disabled. Polling sequence skips this
channel
1h = Input channel IN21 enabled.
0h = Input channel IN20 disabled. Polling sequence skips this
channel
1h = Input channel IN20 enabled.
0h = Input channel IN19 disabled. Polling sequence skips this
channel
1h = Input channel IN19 enabled.
0h = Input channel IN18 disabled. Polling sequence skips this
channel
1h = Input channel IN18 enabled.
0h = Input channel IN17 disabled. Polling sequence skips this
channel
1h = Input channel IN17 enabled.
0h = Input channel IN16 disabled. Polling sequence skips this
channel
1h = Input channel IN16 enabled.
0h = Input channel IN15 disabled. Polling sequence skips this
channel
1h = Input channel IN15 enabled.
Copyright © 2022 Texas Instruments Incorporated
48
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-10. IN_EN Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
14
IN_EN_14
IN_EN_13
IN_EN_12
IN_EN_11
IN_EN_10
R/W
0h
0h = Input channel IN14 disabled. Polling sequence skips this
channel
1h = Input channel IN14 enabled.
13
12
11
10
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h = Input channel IN13 disabled. Polling sequence skips this
channel
1h = Input channel IN13 enabled.
0h = Input channel IN12 disabled. Polling sequence skips this
channel
1h = Input channel IN12 enabled.
0h = Input channel IN11 disabled. Polling sequence skips this
channel
1h = Input channel IN11 enabled.
0h = Input channel IN10 disabled. Polling sequence skips this
channel
1h = Input channel IN10 enabled.
9
8
7
6
5
4
3
2
1
0
IN_EN_9
IN_EN_8
IN_EN_7
IN_EN_6
IN_EN_5
IN_EN_4
IN_EN_3
IN_EN_2
IN_EN_1
IN_EN_0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = Input channel IN9 disabled. Polling sequence skips this channel
1h = Input channel IN9 enabled.
0h = Input channel IN8 disabled. Polling sequence skips this channel
1h = Input channel IN8 enabled.
0h = Input channel IN7 disabled. Polling sequence skips this channel
1h = Input channel IN7 enabled.
0h = Input channel IN6 disabled. Polling sequence skips this channel
1h = Input channel IN6 enabled.
0h = Input channel IN5 disabled. Polling sequence skips this channel
1h = Input channel IN5 enabled.
0h = Input channel IN4 disabled. Polling sequence skips this channel
1h = Input channel IN4 enabled.
0h = Input channel IN3 disabled. Polling sequence skips this channel
1h = Input channel IN3 enabled.
0h = Input channel IN2 disabled. Polling sequence skips this channel
1h = Input channel IN2 enabled.
0h = Input channel IN1 disabled. Polling sequence skips this channel
1h = Input channel IN1 enabled.
0h = Input channel IN0 disabled. Polling sequence skips this channel
1h = Input channel IN0 enabled.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
49
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.8 CS_SELECT Register (Offset = 1Ch) [reset = 0h]
CS_SELECT is shown in 图9-10 and described in 表9-11.
Return to Summary Table.
图9-10. CS_SELECT Register
23
22
21
20
19
18
RESERVED
R-0h
17
16
15
14
13
1
12
0
11
10
9
8
7
6
5
4
3
2
RESERVED
R-0h
CS_IN9
R/W-0h
CS_IN8
R/W-0h
CS_IN7
R/W-0h
CS_IN6
R/W-0h
CS_IN5
R/W-0h
CS_IN4
R/W-0h
CS_IN3
R/W-0h
CS_IN2
R/W-0h
CS_IN1
R/W-0h
CS_IN0
R/W-0h
LEGEND: R/W = Read/Write; R = Read only
表9-11. CS_SELECT Register Field Descriptions
Bit
Field
Type
Reset
Description
23-10
RESERVED
R
0h
Reserved
9
8
7
6
5
4
3
2
1
0
CS_IN9
CS_IN8
CS_IN7
CS_IN6
CS_IN5
CS_IN4
CS_IN3
CS_IN2
CS_IN1
CS_IN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
0h = Current Source (CSO) selected
1h = Current Sink (CSI) selected
Copyright © 2022 Texas Instruments Incorporated
50
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.9 WC_CFG0 Register (Offset = 1Dh) [reset = 0h]
WC_CFG0 is shown in 图9-11 and described in 表9-12.
Return to Summary Table.
图9-11. WC_CFG0 Register
23
11
22
21
9
20
8
19
18
17
16
WC_IN8_IN9
R/W-0h
15
3
14
2
13
WC_IN6_IN7
R/W-0h
12
0
WC_IN11
R/W-0h
10
WC_IN10
R/W-0h
7
6
5
4
1
WC_IN5
R/W-0h
WC_IN4
R/W-0h
WC_IN2_IN3
R/W-0h
WC_IN0_IN1
R/W-0h
LEGEND: R/W = Read/Write
表9-12. WC_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
23-21
WC_IN11
R/W
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
20-18
17-15
14-12
11-9
WC_IN10
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
WC_IN8_IN9
WC_IN6_IN7
WC_IN5
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
51
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-12. WC_CFG0 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
8-6
WC_IN4
R/W
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
5-3
2-0
WC_IN2_IN3
WC_IN0_IN1
R/W
R/W
0h
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
Copyright © 2022 Texas Instruments Incorporated
52
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.10 WC_CFG1 Register (Offset = 1Eh) [reset = 0h]
WC_CFG1 is shown in 图9-12 and described in 表9-13.
Return to Summary Table.
图9-12. WC_CFG1 Register
23
22
21
20
19
18
17
16
15
14
13
12
RESERV AUTO_S AUTO_S
WC_IN23
WC_IN22
WC_IN20_IN21
ED
CALE_DI CALE_DI
S_CSI
S_CSO
R/W-0h
9
R-0h
11
R/W-0h
R/W-0h
7
R/W-0h
4
R/W-0h
1
10
8
6
5
3
2
0
WC_IN18_IN19
R/W-0h
WC_IN16_IN17
R/W-0h
WC_IN14_IN15
R/W-0h
WC_IN12_IN13
R/W-0h
LEGEND: R/W = Read/Write; R = Read only
表9-13. WC_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
23
RESERVED
R
0h
Reserved
22
AUTO_SCALE_DIS_CSI R/W
0h
0h = Enable wetting current auto-scaling (to 2mA) in continuous
mode for 10mA and 15mA settings upon switch closure for all inputs
enabled with CSI
1h = Disable wetting current auto-scaling (to 2mA) in continuous
mode for 10mA and 15mA settings upon switch closure for all inputs
enabled with CS
For detailed descriptions for the wetting current auto-scaling, refer to
section Wetting Current Auto-Scaling.
21
AUTO_SCALE_DIS_CSO R/W
0h
0h = Enable wetting current auto-scaling (to 2mA) in continuous
mode for 10mA and 15mA settings upon switch closure for all inputs
enabled with CSO
1h = Disable wetting current auto-scaling (to 2mA) in continuous
mode for 10mA and 15mA settings upon switch closure for all inputs
enabled with CSO
For detailed descriptions for the wetting current auto-scaling, refer to
section Wetting Current Auto-Scaling.
20-18
17-15
WC_IN23
WC_IN22
R/W
R/W
0h
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
53
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-13. WC_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
14-12
WC_IN20_IN21
R/W
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
11-9
8-6
5-3
2-0
WC_IN18_IN19
WC_IN16_IN17
WC_IN14_IN15
WC_IN12_IN13
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
0h = no wetting current
1h = 1mA (typ.) wetting current
2h = 2mA (typ.) wetting current
3h = 5mA (typ.) wetting current
4h = 10mA (typ.) wetting current
5h-7h = 15mA (typ.) wetting current
Copyright © 2022 Texas Instruments Incorporated
54
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.11 CCP_CFG0 Register (Offset = 1Fh) [reset = 0h]
CCP_CFG0 is shown in 图9-13 and described in 表9-14.
Return to Summary Table.
图9-13. CCP_CFG0 Register
23
11
22
10
21
20
8
19
18
RESERVED
R-0h
17
16
15
3
14
2
13
1
12
0
9
7
6
5
4
RESERVED
CCP_TIME
WC_CCP WC_CCP WC_CCP WC_CCP
3
2
1
0
R-0h
R-0h
R-0h
R-0h
R-0h
R-0h
LEGEND: R/W = Read/Write; R = Read only
表9-14. CCP_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
23-7
RESERVED
R
0h
Reserved
6-4
CCP_TIME
R/W
0h
Wetting current activation time in CCP mode
0h = 64μs
1h = 128μs
2h = 192μs
3h = 256μs
4h = 320μs
5h = 384μs
6h = 448μs
7h = 512μs
3
2
1
0
WC_CCP3
WC_CCP2
WC_CCP1
WC_CCP0
R/W
R/W
R/W
R/W
0h
0h
0h
0h
Wetting current setting for IN18 to IN23 in CCP mode
0h = 10mA (typ.) wetting current
1h = 15mA (typ.) wetting current
Wetting current setting for IN12 to IN17 in CCP mode
0h = 10mA (typ.) wetting current
1h = 15mA (typ.) wetting current
Wetting current setting for IN6 to IN11 in CCP mode
0h = 10mA (typ.) wetting current
1h = 15mA (typ.) wetting current
Wetting current setting for IN0 to IN5 in CCP mode
0h = 10mA (typ.) wetting current
1h = 15mA (typ.) wetting current
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
55
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.12 CCP_CFG1 Register (Offset = 20h) [reset = 0h]
CCP_CFG1 is shown in 图9-14 and described in 表9-15.
Return to Summary Table.
图9-14. CCP_CFG1 Register
23
22
21
20
19
18
17
16
CCP_IN23
R/W-0h
CCP_IN22
R/W-0h
CCP_IN21
R/W-0h
CCP_IN20
R/W-0h
CCP_IN19
R/W-0h
CCP_IN18
R/W-0h
CCP_IN17
R/W-0h
CCP_IN16
R/W-0h
15
14
13
12
11
10
9
8
CCP_IN15
R/W-0h
CCP_IN14
R/W-0h
CCP_IN13
R/W-0h
CCP_IN12
R/W-0h
CCP_IN11
R/W-0h
CCP_IN10
R/W-0h
CCP_IN9
R/W-0h
CCP_IN8
R/W-0h
7
6
5
4
3
2
1
0
CCP_IN7
R/W-0h
CCP_IN6
R/W-0h
CCP_IN5
R/W-0h
CCP_IN4
R/W-0h
CCP_IN3
R/W-0h
CCP_IN2
R/W-0h
CCP_IN1
R/W-0h
CCP_IN0
R/W-0h
LEGEND: R/W = Read/Write
表9-15. CCP_CFG1 Register Field Descriptions
Bit
Field
Type
Reset
Description
23
CCP_IN23
R/W
0h
0h = no CCP wetting current
1h = CCP wetting current activated
22
21
20
19
18
17
16
15
14
13
12
11
10
CCP_IN22
CCP_IN21
CCP_IN20
CCP_IN19
CCP_IN18
CCP_IN17
CCP_IN16
CCP_IN15
CCP_IN14
CCP_IN13
CCP_IN12
CCP_IN11
CCP_IN10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
Copyright © 2022 Texas Instruments Incorporated
56
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-15. CCP_CFG1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
9
CCP_IN9
CCP_IN8
CCP_IN7
CCP_IN6
CCP_IN5
CCP_IN4
CCP_IN3
CCP_IN2
CCP_IN1
CCP_IN0
R/W
0h
0h = no CCP wetting current
1h = CCP wetting current activated
8
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
0h = no CCP wetting current
1h = CCP wetting current activated
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
57
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.13 THRES_COMP Register (Offset = 21h) [reset = 0h]
THRES_COMP is shown in 图9-15 and described in 表9-16.
Return to Summary Table.
图9-15. THRES_COMP Register
23
15
7
22
14
6
21
13
5
20
12
4
19
18
10
17
9
16
8
RESERVED
R-0h
11
RESERVED
R-0h
THRES_COMP_IN20_IN23
R/W-0h
THRES_COMP_IN16_IN19
R/W-0h
3
2
1
0
THRES_COMP_IN12_IN15
R/W-0h
THRES_COMP_IN8_IN11
R/W-0h
THRES_COMP_IN4_IN7
R/W-0h
THRES_COMP_IN0_IN3
R/W-0h
LEGEND: R/W = Read/Write; R = Read only
表9-16. THRES_COMP Register Field Descriptions
Bit
Field
Type
Reset
Description
23-12
RESERVED
R
0h
Reserved
11-10
THRES_COMP_IN20_IN2 R/W
3
0h
0h
0h
0h
0h
These 2 bits configures the comparator thresholds for input channels
IN20 to IN23
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
9-8
THRES_COMP_IN16_IN1 R/W
9
These 2 bits configures the comparator thresholds for input channels
IN16 to IN19
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
7-6
THRES_COMP_IN12_IN1 R/W
5
These 2 bits configures the comparator thresholds for input channels
IN12 to IN15
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
5-4
THRES_COMP_IN8_IN11 R/W
These 2 bits configures the comparator thresholds for input channels
IN8 to IN11
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
3-2
THRES_COMP_IN4_IN7 R/W
These 2 bits configures the comparator thresholds for input channels
IN4 to IN7
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
Copyright © 2022 Texas Instruments Incorporated
58
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-16. THRES_COMP Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
1-0
THRES_COMP_IN0_IN3 R/W
0h
These 2 bits configures the comparator thresholds for input channels
IN0 to IN3
0h = comparator threshold set to 2V
1h = comparator threshold set to 2.7V
2h = comparator threshold set to 3V
3h = comparator threshold set to 4V
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
59
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.14 INT_EN_COMP1 Register (Offset = 22h) [reset = 0h]
INT_EN_COMP1 is shown in 图9-16 and described in 表9-17.
Return to Summary Table.
图9-16. INT_EN_COMP1 Register
23
INC_EN_11
R/W-0h
22
21
INC_EN_10
R/W-0h
20
19
INC_EN_9
R/W-0h
18
17
INC_EN_8
R/W-0h
16
15
INC_EN_7
R/W-0h
14
13
12
INC_EN_6
R/W-0h
11
10
9
8
7
6
5
4
3
2
1
0
INC_EN_5
R/W-0h
INC_EN_4
R/W-0h
INC_EN_3
R/W-0h
INC_EN_2
R/W-0h
INC_EN_1
R/W-0h
INC_EN_0
R/W-0h
LEGEND: R/W = Read/Write
表9-17. INT_EN_COMP1 Register Field Descriptions
Bit
Field
Type
Reset
Description
23-22
INC_EN_11
R/W
0h
0h = no interrupt generation for IN11
1h = interrupt generation on rising edge above
THRES_COMP_IN8_IN11 for IN11
2h = interrupt generation on falling edge below
THRES_COMP_IN8_IN11 for IN11
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN8_IN11 for IN11
21-20
19-18
17-16
15-14
INC_EN_10
INC_EN_9
INC_EN_8
INC_EN_7
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h = no interrupt generation for IN10
1h = interrupt generation on rising edge above
THRES_COMP_IN8_IN11 for IN10
2h = interrupt generation on falling edge below
THRES_COMP_IN8_IN11 for IN10
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN8_IN11 for IN10
0h = no interrupt generation for IN9
1h = interrupt generation on rising edge above
THRES_COMP_IN8_IN11 for IN9
2h = interrupt generation on falling edge below
THRES_COMP_IN8_IN11 for IN9
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN8_IN11 for IN9
0h = no interrupt generation for IN8
1h = interrupt generation on rising edge above
THRES_COMP_IN8_IN11 for IN8
2h = interrupt generation on falling edge below
THRES_COMP_IN8_IN11 for IN8
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN8_IN11 for IN8
0h = no interrupt generation for IN7
1h = interrupt generation on rising edge above
THRES_COMP_IN4_IN7 for IN7
2h = interrupt generation on falling edge below
THRES_COMP_IN4_IN7 for IN7
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN4_IN7 for IN7
Copyright © 2022 Texas Instruments Incorporated
60
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-17. INT_EN_COMP1 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
13-12
INC_EN_6
INC_EN_5
INC_EN_4
INC_EN_3
INC_EN_2
INC_EN_1
INC_EN_0
R/W
0h
0h = no interrupt generation for IN6
1h = interrupt generation on rising edge above
THRES_COMP_IN4_IN7 for IN6
2h = interrupt generation on falling edge below
THRES_COMP_IN4_IN7 for IN6
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN4_IN7 for IN6
11-10
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h = no interrupt generation for IN5
1h = interrupt generation on rising edge above
THRES_COMP_IN4_IN7 for IN5
2h = interrupt generation on falling edge below
THRES_COMP_IN4_IN7 for IN5
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN4_IN7 for IN5
9-8
0h = no interrupt generation for IN4
1h = interrupt generation on rising edge above
THRES_COMP_IN4_IN7 for IN4
2h = interrupt generation on falling edge below
THRES_COMP_IN4_IN7 for IN4
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN4_IN7 for IN4
7-6
0h = no interrupt generation for IN3
1h = interrupt generation on rising edge above
THRES_COMP_IN0_IN3 for IN3
2h = interrupt generation on falling edge below
THRES_COMP_IN0_IN3 for IN3
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN0_IN3 for IN3
5-4
0h = no interrupt generation for IN2
1h = interrupt generation on rising edge above
THRES_COMP_IN0_IN3 for IN2
2h = interrupt generation on falling edge below
THRES_COMP_IN0_IN3 for IN2
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN0_IN3 for IN2
3-2
0h = no interrupt generation for IN1
1h = interrupt generation on rising edge above
THRES_COMP_IN0_IN3 for IN1
2h = interrupt generation on falling edge below
THRES_COMP_IN0_IN3 for IN1
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN0_IN3 for IN1
1-0
0h = no interrupt generation for IN0
1h = interrupt generation on rising edge above
THRES_COMP_IN0_IN3 for IN0
2h = interrupt generation on falling edge below
THRES_COMP_IN0_IN3 for IN0
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN0_IN3 for IN0
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
61
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.15 INT_EN_COMP2 Register (Offset = 23h) [reset = 0h]
INT_EN_COMP2 is shown in 图9-17 and described in 表9-18.
Return to Summary Table.
图9-17. INT_EN_COMP2 Register
23
INC_EN_23
R/W-0h
22
21
INC_EN_22
R/W-0h
20
19
INC_EN_21
R/W-0h
18
17
INC_EN_20
R/W-0h
16
15
INC_EN_19
R/W-0h
14
13
12
INC_EN_18
R/W-0h
11
10
9
8
7
6
5
4
3
2
1
0
INC_EN_17
R/W-0h
INC_EN_16
R/W-0h
INC_EN_15
R/W-0h
INC_EN_14
R/W-0h
INC_EN_13
R/W-0h
INC_EN_12
R/W-0h
LEGEND: R/W = Read/Write
表9-18. INT_EN_COMP2 Register Field Descriptions
Bit
Field
Type
Reset
Description
23-22
INC_EN_23
R/W
0h
0h = no interrupt generation for IN23
1h = interrupt generation on rising edge above
THRES_COMP_IN20_IN23 for IN23
2h = interrupt generation on falling edge below
THRES_COMP_IN20_IN23 for IN23
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN20_IN23 for IN23
21-20
19-18
17-16
15-14
INC_EN_22
INC_EN_21
INC_EN_20
INC_EN_19
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h = no interrupt generation for IN22
1h = interrupt generation on rising edge above
THRES_COMP_IN20_IN23 for IN22
2h = interrupt generation on falling edge below
THRES_COMP_IN20_IN23 for IN22
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN20_IN23 for IN22
0h = no interrupt generation for IN21
1h = interrupt generation on rising edge above
THRES_COMP_IN20_IN23 for IN21
2h = interrupt generation on falling edge below
THRES_COMP_IN20_IN23 for IN21
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN20_IN23 for IN21
0h = no interrupt generation for IN20
1h = interrupt generation on rising edge above
THRES_COMP_IN20_IN23 for IN20
2h = interrupt generation on falling edge below
THRES_COMP_IN20_IN23 for IN20
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN20_IN23 for IN20
0h = no interrupt generation for IN19
1h = interrupt generation on rising edge above
THRES_COMP_IN16_IN19 for IN19
2h = interrupt generation on falling edge below
THRES_COMP_IN16_IN19 for IN19
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN16_IN19 for IN19
Copyright © 2022 Texas Instruments Incorporated
62
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表9-18. INT_EN_COMP2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
13-12
INC_EN_18
INC_EN_17
INC_EN_16
INC_EN_15
INC_EN_14
INC_EN_13
INC_EN_12
R/W
0h
0h = no interrupt generation for IN18
1h = interrupt generation on rising edge above
THRES_COMP_IN16_IN19 for IN18
2h = interrupt generation on falling edge below
THRES_COMP_IN16_IN19 for IN18
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN16_IN19 for IN18
11-10
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h = no interrupt generation for IN17
1h = interrupt generation on rising edge above
THRES_COMP_IN16_IN19 for IN17
2h = interrupt generation on falling edge below
THRES_COMP_IN16_IN19 for IN17
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN16_IN19 for IN17
9-8
0h = no interrupt generation for IN16
1h = interrupt generation on rising edge above
THRES_COMP_IN16_IN19 for IN16
2h = interrupt generation on falling edge below
THRES_COMP_IN16_IN19 for IN16
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN16_IN19 for IN16
7-6
0h = no interrupt generation for IN15
1h = interrupt generation on rising edge above
THRES_COMP_IN12_IN15 for IN15
2h = interrupt generation on falling edge below
THRES_COMP_IN12_IN15 for IN15
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN12_IN15 for IN15
5-4
0h = no interrupt generation for IN14
1h = interrupt generation on rising edge above
THRES_COMP_IN12_IN15 for IN14
2h = interrupt generation on falling edge below
THRES_COMP_IN12_IN15 for IN14
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN12_IN15 for IN14
3-2
0h = no interrupt generation for IN13
1h = interrupt generation on rising edge above
THRES_COMP_IN12_IN15 for IN13
2h = interrupt generation on falling edge below
THRES_COMP_IN12_IN15 for IN13
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN12_IN15 for IN13
1-0
0h = no interrupt generation for IN12
1h = interrupt generation on rising edge above
THRES_COMP_IN12_IN15 for IN12
2h = interrupt generation on falling edge below
THRES_COMP_IN12_IN15 for IN12
3h = interrupt generation on falling and rising edge of
THRES_COMP_IN12_IN15 for IN12
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
63
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
9.4.16 INT_EN_CFG0 Register (Offset = 24h) [reset = 0h]
INT_EN_CFG0 is shown in 图9-18 and described in 表9-19.
Return to Summary Table.
图9-18. INT_EN_CFG0 Register
23
15
7
22
21
20
12
4
19
18
10
17
9
16
8
RESERVED
R-0h
14
13
11
RESERVED
R-0h
6
5
3
2
1
0
CRC_CALC_E
N
UV_EN
OV_EN
TW_EN
TSD_EN
SSC_EN
PRTY_FAIL_EN SPI_FAIL_EN
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h
R/W-0h R/W-0h
LEGEND: R/W = Read/Write; R = Read only
表9-19. INT_EN_CFG0 Register Field Descriptions
Bit
Field
Type
Reset
Description
23-8
RESERVED
R
0h
Reserved
7
6
5
4
3
2
1
0
CRC_CALC_EN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0h
0h
0h
0h
0h
0h
0h
0h
0h = INT pin assertion due to CRC calculation completion disabled.
1h = INT pin assertion due to CRC calculation completion enabled.
UV_EN
0h = INT pin assertion due to UV event disabled.
1h = INT pin assertion due to UV event enabled.
OV_EN
0h = INT pin assertion due to OV event disabled.
1h = INT pin assertion due to OV event enabled.
TW_EN
0h = INT pin assertion due to TW event disabled.
1h = INT pin assertion due to TW event enabled.
TSD_EN
0h = INT pin assertion due to TSD event disabled.
1h = INT pin assertion due to TSD event enabled.
SSC_EN
0h = INT pin assertion due to SSC event disabled.
1h = INT pin assertion due to SSC event enabled.
PRTY_FAIL_EN
SPI_FAIL_EN
0h = INT pin assertion due to parity fail event disabled.
1h = INT pin assertion due to parity fail event enabled.
0h = INT pin assertion due to SPI fail event disabled.
1h = INT pin assertion due to SPI fail event enabled.
Copyright © 2022 Texas Instruments Incorporated
64
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
10 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
10.1 Application Information
The TIC10024-Q1 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect
external mechanical switch status in a 12-V automotive system by acting as an interface between the switches
and the low- voltage microcontroller. The device offers a number of unique features to replace systems
implemented with discrete components, saving board space and reducing the bill of materials (BOM). The device
can also be configured into low-power polling mode, which provides significant savings on system power
consumption.
10.2 Digital Switch Detection in Automotive Body Control Module
The body control module (BCM) is an electronic control unit responsible for monitoring and controlling various
electronic accessories in a vehicle body. Detection of various mechanical switches status in a vehicle is one
important task handled by the BCM. Most switches inside the BCM are digital in nature, meaning they have
either an ON or an OFF state. The TIC10024-Q1 can detect up to 24 digital switches. The following application
diagram depicts how the TIC10024-Q1 is used in a BCM to detect an external digital switch and a detailed
design example is shown in the following sections.
VBAT
Voltage
Regulator
GND
VS
VS
VDD
VDD
/INT
RESD
/INT
/CS
INx
/CS
CESD
SW
SCLK
SI
SCLK
MOSI
MISO
SO
TIC10024-Q1
MCU
Body Control Module
Copyright © 2016, Texas Instruments Incorporated
图10-1. Using TIC10024-Q1 to Monitor a Digital Switch in Body Control Module Application
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
65
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
10.2.1 Design Requirements
表10-1. Example Digital Switch Specification
PARAMETER
SPECIFICATION
7 V ≤VBAT ≤16 V
0 V ≤VDIODE ≤1 V
50 Ω± 8%
MIN
MAX
16 V
1 V
VBAT
7 V
VDIODE (voltage drop across the reverse-blocking diode)
RESD
0 V
46 Ω
54 Ω
220 ΩMax when
closed ± 8%
RSW
0 Ω
237.6 Ω
RDIRT
5000 ΩMin
5000 Ω
∞
Wetting current requirement
10mA Typical
An example of digital switch connected to ground shown in 图 10-1, with 表 10-1 summarizing its detailed
requirements. The goal of this design is to utilize the TIC10024-Q1’s integrated comparator to detect and
differentiate between the 2 switch states:
1. State 1: SW open
2. State 2: SW closed
To mimic real automotive systems, the battery is assumed to be fluctuating between 7 V and 16 V. Taking into
account the voltage drop across the reverse-blocking diode, the VS supply voltage to the TIC10024-Q1 device
can fluctuate between 6 V and 16 V. RDIRT is introduced to model the small leakage flowing across the switch in
open state. When the switch changes position and the switch state changes from one to another, the TIC10024-
Q1 is required to correctly detect the state transition and issue an interrupt to alert the microcontroller. The
switch information needs to be stored in the status registers for the microcontroller to retrieve.
10.2.2 Detailed Design Procedure
表10-2. Detailed Design Procedure
STEP 1
STEP 2
VINX (V)
Equivalent Resistance Value (Ω)
MIN
5000
0
MAX
MIN
>10
0
MAX
-
State 1: SW open
State 2: SW closed
∞
291.6
3.32
Use the following procedures to calculate thresholds to program to the TIC10024-Q1 for proper switch detection:
1. Calculate the equivalent resistance values at the 2 switch states, taking into account RDIRT and the 8%
resistance variation.
2. Estimate the voltage established when wetting current flows through the switch by utilizing the relationship
VINX = RSW_EQU × IWETT_ACT, where RSW _EQU is the equivalent switch resistance value and IWETT_ACT is the
actual wetting current flowing through the switch. The 10 mA wetting current setting is selected in this design
as required by the specification. The wetting current variation, however, can occur depending on
manufacturing process variation and operating temperature, and needs to be taken into account. Referring
to the electrical table of the TIC10024-Q1 and assuming enough headroom for the current source (CSO) to
operate, the 10mA wetting current setting produces current ranging between 8.4 mA and 11.4 mA (for 6 V ≤
VS ≤35 V condition). The voltage established on the TIC10024-Q1 input pin (VINX) can be calculated
accordingly.
3. After the VINX voltage is calculated for the 2 switch states, the proper threshold value needs to be chosen
between minimum VINX voltage of state 1 (>10 V) and maximum VINX voltage of state 2 (3.32 V). The
TIC10024-Q1 has 4 thresholds that can be configured for the comparator: 2 V, 2.7 V, 3 V, and 4 V. As a
result, the proper threshold to be used in this design example is 4 V.
4. To properly program the device, follow the below recommend procedure:
• Enable channel IN0 by setting IN_EN_0 bit to 1 in the IN_EN register
Copyright © 2022 Texas Instruments Incorporated
66
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
• Program the wetting current to source by setting CS_IN0 bit to 0 in the CS SELECT register
• Program the wetting current to 10 mA by configuring WC_IN0_IN1 bits to 100 in the WC_CFG0 register
• Disable wetting current auto-scaling by setting AUTO_SCALE_DIS_CSO bit in WC_CFG1 register to 1
• Program the comparator threshold to 4 V by setting the THRES_COMP_IN0_IN3 bits to 11 in the
THRES_COMP register
• Program interrupt generation to both rising and falling transitions by setting the INC_EN_0 bits to 11 in
the INT_EN_COMP1 register
• Enable interrupt generation from switch state change by setting the SSC bit to 1 in the INT_EN_CFG0
register
• Program the CONFIG register: Keep the device in continuous mode by setting the POLL_EN bit to 0.
Start device operation by setting the TRIGGER bit to 1.
• Read the INT_STAT register to clear the baseline SSC interrupt once the interrupt is observed.
• Toggle the external switch open and monitor the INT pin. Read the INT_STAT register and
IN_STATE_COMP register to make sure the correct switch status is reported.
10.2.3 Application Curves
图 10-2 is the scope shot showing the switch getting toggled from close to open at time a). Before toggling, the
voltage at VIN0 stays low at roughly 2.7 V. Once the switch opens, the voltage at VIN0 gets pulled high to the VS
voltage. The INT pin is asserted shortly after the switch toggles at time b) to notify the microcontroller a switch
state change event has occurred.
图10-2. Measured Waveform Showing VIN0 Pin and INT Pin Voltages
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
67
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
10.3 Systems Examples
10.3.1 Using TIC10024-Q1 in a 12 V Automotive System
US
Voltage
Regulator
GND
12-V
Automotive
Battery
VS
VS
VDD
VDD
/INT
/INT
/CS
INx
/CS
SCLK
SI
SCLK
MOSI
MISO
SO
AGND DGND EP
MCU
TIC10024-Q1
Body Control Module
Copyright © 2016, Texas Instruments Incorporated
图10-3. Typical System Diagram of Battery Connections for TIC10024-Q1
The TIC10024-Q1 is designed to operate with a 12 V automotive system. 图 10-3 depicts a typical system
diagram to show how the device is connected to the battery. Please remember to be careful when connecting
the battery directly to the device on the VS supply pin (through a reverse-blocking diode) or the input (INX) pins
since an automotive battery can be subjected to various transient and over-voltage events. Manufacturers have
independently created standards and test procedures in an effort to prevent sensitive electronics from failing due
to these events. Recently, combined efforts are made with ISO to develop the ISO 16750-2 standard (Road
vehicles -- Environmental conditions and testing for electrical and electronic equipment -- Part 2: Electrical
loads), which describe the possible transients that could occur to an automotive battery and specify test methods
to simulate them.
It shall be noted that the TIC10024-Q1 is designed and tested according to the ISO 16750-2 standard. A few
voltage stress tests and their test conditions are listed below. Exposing the device to more severe transient
events than described by the standard can potentially causes performance degradation and long-term damage
to the device.
• Direct current supply voltage: VBAT, min = 6 V; VBAT, max= 16 V
• To emulate a jump start event, voltage profile described in 图10-4 is used.
Copyright © 2022 Texas Instruments Incorporated
68
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
VBAT
VBAT, max
VBAT, min
tr
t1
tf
t
图10-4. Voltage Profile to Test a Jump Start Event
表10-3. Voltage Profile Parameters to Test a Jump Start Event
Parameter
Value
VBAT, min
10.8 V
VBAT, max
24 V
tr
t1
tf
< 10 ms
60 s ± 6 s
< 10 ms
Number of cycles
1
To emulate a load dump event for an alternator with centralized load dump suppression, voltage profile
described in 图10-5 is used. UA and US* are applied directly to VBAT
.
图10-5. Voltage Profile to Test a Load Dump Event With Centralized Load Dump Suppression
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
69
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
表10-4. Voltage Profile to Test a Load Dump Event With Centralized Load Dump Suppression
Parameter
Value
UA
13.5 V
US
79 V ≤US ≤101
35 V
US*
td
40 ms ≤td ≤400 ms
< 10 ms
tr
Number of cycles
5 pulses at intervals of 1 min
To emulate a cranking event, voltage profile describe in 图 10-6 is used. US, US6, and UA are applied directly to
VBAT
.
图10-6. Voltage Profile to Test a Cranking Event
表10-5. Voltage Profile Used to Test a Cranking Event
Parameter
Value - Level I
Value - Level II
Value - Level IV
6 V
US6
US
UB
tf
8 V
4.5 V
9.5 V
6.5 V
6.5 V
14 V ± 0.2 V
5 ms ± 0.5 ms
15 ms ± 1.5 ms
50 ms ± 5 ms
1000 ms ± 100 ms
40 ms ± 4 ms
14 V ± 0.2 V
5 ms ± 0.5 ms
15 ms ± 1.5 ms
50 ms ± 5 ms
10000 ms ± 1000 ms
100 ms ± 10 ms
14 V ± 0.2 V
5 ms ± 0.5 ms
15 ms ± 1.5 ms
50 ms ± 5 ms
10000 ms ± 1000 ms
100 ms ± 10 ms
t6
t7
t8
tr
Copyright © 2022 Texas Instruments Incorporated
70
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
11 Power Supply Recommendations
There are two supply input pins for the TIC10024-Q1: VS and VDD. VS is the main power supply for the entire
chip and is essential for all critical functions of the device. The VS supply is designed to be connected to a 12-V
automotive battery (through a reverse blocking diode) with nominal operating voltage no greater than 16V. The
VDD supply is used to determine the logic level on the SPI communication interface, source the current for the
SO driver, and sets the pull-up voltage for the /CS pin. It can also be used as a possible external pull-up supply
for the /INT pin as an alternative to the VS supply and it shall be connected to a 3 V to 5.5 V logic supply.
Removing VDD from the device disables SPI communications, but does not impact normal operation of the
device.
To improve stability of the supply inputs, some decoupling capacitors are recommended on the PCB. 图 11-1
shows an example on the on-board power supply decoupling scheme. The battery voltage (VBAT) is decoupled
on the Electronic Control Unit (ECU) board using a large decoupling capacitor (CBUFF). The diode is installed to
prevent damage to the internal system under reversed battery condition. CVS shall be installed close to the
TIC10024-Q1 for best decoupling performance. The voltage regulator provides a regulated voltage for the digital
portion of the device and for the local microcontroller and its output is decoupled with CDECOUPLE. 表 11-1 lists
recommended values for each individual decoupling capacitor shown in the system diagram.
表11-1. Decoupling Capacitor Recommendations
CRC RULE
VALUE
CBUFF
100 μF, 50 V rated, ±20%
100 nF, 50V rated, ±10%; X7R
100 nF, 50 V rated
CVBAT
CVS
CDECOUPLE
100 nF~1 μF
ECU
connector
VBAT
Voltage
Regulator
CDECOUPLE
GND
CVBAT CBUFF
CVS
37
38
VS
VS
VDD 19
VDD
TIC10024-Q1
MCU
Electronic Control Unit (ECU)
Copyright © 2016, Texas Instruments Incorporated
图11-1. Recommended Power Supply Decoupling
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
71
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
12 Layout
12.1 Layout Guidelines
1. 图12-1 illustrates an example of a PCB layout with the TIC10024-Q1. Some key considerations are:
2. Decouple the VS and VDD pins with capacitor using recommended values from section Power Supply
Recommendations and place them as close to the pin as possible. Make sure that the capacitor voltage
rating is sufficient for the VS and VDD supplies.
3. Keep the input lines as short as possible.
4. Use a solid ground plane to help distribute heat and reduce electromagnetic interference (EMI) noise pickup.
5. Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if
possible, and only make perpendicular crossings when necessary.
6. To achieve good thermal performance, the exposed thermal pad underneath the device must be soldered to
the board and flooded with vias to ground planes. For simple double-sided PCBs where there are no internal
layers, the surface layers can be used to remove heat. For multilayer PCBs, internal ground planes can be
used for heat removal.
7. Minimize the inductive parasitic between the INx input capacitors and the thermal pad ground return.
Copyright © 2022 Texas Instruments Incorporated
72
Submit Document Feedback
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
12.2 Layout Example
VIA to
ground plane
C
C
IN13
VS
VIAs to ground
plane and heat
sink of the PCB
IN14
IN15
VS
IN12
IN16
IN17
IN11
IN10
IN18
IN19
IN9
IN8
IN20
AGND
IN21
IN7
IN6
IN5
VIA to
ground plane
VIA to
ground plane
IN22
IN23
DGND
IN4
IN0
IN1
IN3
IN2
/CS
/INT
C
C
SCLK
CAP_D
VIA to
ground plane
SI
CAP_PRE
RESET
SO
VDD
CAP_A
Not to Scale
VIA to
ground plane
C
R
R
VIA to ground plane
图12-1. Example Layout
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
73
Product Folder Links: TIC10024-Q1
TIC10024-Q1
ZHCSGQ0A –SEPTEMBER 2017 –REVISED FEBRUARY 2022
www.ti.com.cn
13 Device and Documentation Support
13.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
13.2 Community Resources
13.3 Trademarks
所有商标均为其各自所有者的财产。
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
74
Submit Document Feedback
Product Folder Links: TIC10024-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Jan-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TIC10024QDCPRQ1
ACTIVE
HTSSOP
DCP
38
2000 RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 125
TIC10024Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2022
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TIC10024QDCPRQ1
HTSSOP DCP
38
2000
330.0
16.4
6.9
10.2
1.8
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jan-2022
*All dimensions are nominal
Device
Package Type Package Drawing Pins
HTSSOP DCP 38
SPQ
Length (mm) Width (mm) Height (mm)
350.0 350.0 43.0
TIC10024QDCPRQ1
2000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DCP 38
4.4 x 9.7, 0.5 mm pitch
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224560/B
www.ti.com
PACKAGE OUTLINE
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
0
0
0
SMALL OUTLINE PACKAGE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX
AREA
SEATING
PLANE
36X 0.5
38
1
2X
9
9.8
9.6
NOTE 3
19
20
0.27
0.17
0.08
38X
4.5
4.3
B
C A B
SEE DETAIL A
(0.15) TYP
2X 0.95 MAX
NOTE 5
19
20
2X 0.95 MAX
NOTE 5
0.25
GAGE PLANE
1.2 MAX
39
4.70
3.94
THERMAL
PAD
0.15
0.05
0.75
0.50
0 -8
A
20
DETAIL A
TYPICAL
1
38
2.90
2.43
4218816/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(3.4)
NOTE 9
METAL COVERED
BY SOLDER MASK
(2.9)
SYMM
38X (1.5)
38X (0.3)
SEE DETAILS
38
1
(R0.05) TYP
36X (0.5)
3X (1.2)
SYMM
39
(4.7)
(9.7)
NOTE 9
(0.6) TYP
SOLDER MASK
DEFINED PAD
(
0.2) TYP
VIA
20
19
(1.2)
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 8X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
SOLDER MASK DETAILS
4218816/A 10/2018
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DCP0038A
PowerPADTM TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
(2.9)
BASED ON
0.125 THICK
STENCIL
38X (1.5)
38X (0.3)
METAL COVERED
BY SOLDER MASK
1
38
(R0.05) TYP
36X (0.5)
(4.7)
SYMM
39
BASED ON
0.125 THICK
STENCIL
19
20
SYMM
(5.8)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 8X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
3.24 X 5.25
2.90 X 4.70 (SHOWN)
2.65 X 4.29
0.125
0.15
0.175
2.45 X 3.97
4218816/A 10/2018
NOTES: (continued)
11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
©2020 ICPDF网 联系我们和版权申明