TIOL111DMWT [TI]
具有集成浪涌保护功能的 IO-Link 器件收发器 | DMW | 10 | -40 to 125;
| 型号： | TIOL111DMWT |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有集成浪涌保护功能的 IO-Link 器件收发器 | DMW | 10 | -40 to 125 |
| 文件： | 总33页 (文件大小：1523K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TIOL111, TIOL1113, TIOL1115
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
具有集成浪涌保护功能的 TIOL111、TIOL111x IO-Link 器件收发器
1 特性
2 应用
1
•
7V 至 36V 电源电压
•
•
•
IO-Link 传感器和传动器
•
PNP、NPN 或 IO-Link 可配置输出
工厂自动化
工序自动化
–
IEC 61131-9 COM1、COM2 和 COM3 数据速
率支持
3 说明
•
•
•
•
•
在 250mA 条件下，残余电压低，为 1.75V
50mA 至 350mA 可配置电流限制
TIOL111(x) 系列收发器使用 IO-Link 接口实现工业双
向点到点通信。当此器件通过一个三线制接口连接至一
个 IO-Link 主器件时，主器件能够发起通信并与远程节
点交换数据，而此时 TIOL111(x) 则用作一个用于通信
的完整物理层。
耐受 ±65V 瞬态电压（时间低于 100µs）
L+、CQ 和 L- 上具有高达 60V 的反极性保护
L+ 和 CQ 上有集成式 EMC 保护
–
–
–
±16kV IEC 61000-4-2 ESD 接触放电
±4kV IEC 61000-4-4 电气快速瞬变
±1.2kV/500Ω IEC 61000-4-5 浪涌
这些器件能够承受高达 1.2kV (500Ω) 的 IEC 61000-4-
5 浪涌，并具有集成反向极性保护。
•
•
•
•
•
高达 1.5H 电感负载的快速消磁功能
大电容负载驱动能力
只需通过一个简单的引脚可编程接口，便可轻松连接到
控制器电路。输出电流限制可使用外部电阻器进行配
置。
< 2µA CQ 泄露电流
< 1.5mA 静态电源电流
集成式 LDO 选项可支持高达 20mA 的电流
此外，它们提供了故障报告和内部保护功能，可应对欠
压、过流和过热条件。
–
–
–
TIOL111：无 LDO
TIOL1113：3.3V LDO
TIOL1115：5V LDO
器件信息(1)
器件型号
TIOL111
封装
封装尺寸（标称值）
•
•
•
•
•
过热警告和热保护
远程唤醒指示灯
TIOL1113
TIOL1115
VSON (10)
2.50mm x 3.00mm
故障指示灯
扩展环境温度：-40°C 至 125°C
2.5mm x 3mm 10 引脚 VSON 封装
(1) 如需了解所有可订购器件，请参阅产品说明书末尾的可订购产
品附录。
典型应用图
TIOL111(x)
VCC_OUT
L+
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
10 kΩ
RX
10 kΩ
TX
EN
Sensor
Front-End
Microcontroller
CQ
IO-Link Master
DIAGNOSTICS
and
WAKE
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
RSET
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSEV5
TIOL111, TIOL1113, TIOL1115
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
www.ti.com.cn
目录
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 17
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application ................................................. 19
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 5
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 7
6.7 Typical Characteristics.............................................. 8
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagrams ..................................... 11
9
10 Power Supply Recommendations ..................... 23
11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
11.2 Layout Example .................................................... 24
12 器件和文档支持 ..................................................... 25
12.1 接收文档更新通知 ................................................. 25
12.2 社区资源................................................................ 25
12.3 商标....................................................................... 25
12.4 静电放电警告......................................................... 25
12.5 Glossary................................................................ 25
13 机械、封装和可订购信息....................................... 25
7
8
4 修订历史记录
Changes from Revision C (May 2019) to Revision D
Page
•
•
向数据表添加了器件号 TIOL1113 和 TIOL1115..................................................................................................................... 1
将所有 TIOL111-3 更改为 TIOL1113 并将 TIOL111-5 更改为 TIOL1115 .............................................................................. 1
Changes from Revision B (August 2018) to Revision C
Page
•
•
将特性 从“高达 55V 的反极性保护”更改为“高达 60V 的反极性保护” ...................................................................................... 1
Changed Supply voltage From: MIN = -55 V, MAX = 55 V To: MIN = -60 V, MAX = 60 V in the Absolute Maximum
Ratings.................................................................................................................................................................................... 4
•
•
•
Changed the Voltage difference Max value From: 55 V to 60 V Absolute Maximum Ratings............................................... 4
Changed the IREV test conditions From: up to |55 V| To: up to |60 V| in the Electrical Characteristics.................................. 6
Changed text From: "pins may not exceed 55 V DC at any time." To: "pins may not exceed 60 V DC at any time." in
Reverse Polarity Protection ssection.................................................................................................................................... 14
Changes from Revision A (October 2017) to Revision B
Page
•
Added VIM to the Electrical Characteristics table.................................................................................................................... 5
Changes from Original (July 2017) to Revision A
Page
•
Changed From: 1.25 mW To: 125 mW in 公式 2 ................................................................................................................. 20
2
Copyright © 2017–2019, Texas Instruments Incorporated
TIOL111, TIOL1113, TIOL1115
www.ti.com.cn
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
5 Pin Configuration and Functions
DMW Package
10-Pin (VSON)
Top View
VCC_IN/OUT
1
2
3
4
5
10
WAKE
NFAULT
RX
9
L+
Thermal
Pad
8
CQ
TX
7
L-
EN
6
ILIM_ADJ
Not to scale
Pin Functions
PIN
I/O
DESCRIPTION
NAME
NO.
IO-Link Interface
CQ
L+
L-
8
9
7
I/O
IO-Link data signal (bidirectional)
IO-Link supply voltage (24 V nominal)
IO-Link ground potential
POWER
POWER
Local Controller Interface
Driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak internal pull-
down.
EN
5
I
WAKE
RX
10
3
OPEN-DRAIN Wake up indicator to the local controller. Connect this pin via pull-up resistor to VCC_IN/OUT.
O
I
Receive data output to the local controller
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side switch. Logic low
sets high-side switch. Weak internal pull-up.
TX
4
Thermal Pad
—
—
Connect to L- for optimal thermal and electrical performance
Internal LDO
VCC_IN/OUT
Special Connect Pins
ILIM_ADJ
1
POWER
3.3-V or 5-V linear regulator output; external 3.3-V or 5-V logic supply for option without LDO.
6
2
I
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage supply or an overtemperature condition.
NFAULT
OPEN-DRAIN
Copyright © 2017–2019, Texas Instruments Incorporated
3
TIOL111, TIOL1113, TIOL1115
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–60
–65
MAX
60
65
60
6
UNIT
V
Steady state voltage for L+ and CQ
Supply voltage
Transient pulse width < 100 µs for L+ and CQ
V
Voltage difference
|V(L+) – V(CQ)
|
V
Logic supply voltage (TIOL111)
Input logic voltage
VCC_IN
–0.3
–0.3
–5
V
TX, EN, ILIM_ADJ
6
V
Output current
RX, WAKE, NFAULT
5
mA
°C
Storage temperature, Tstg
-55
170
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages are
with reference to the L- pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
All pins
±4000
Contact discharge, per IEC 61000-4-2(2)(3)
Electrical fast transient, per IEC 61000-4-4(2)
Surge protection with 500 Ω, per IEC 61000-4-5;
±16000
±4000
V(ESD)
Electrostatic discharge
V
Pins L+, CQ and
L-
±1200
(2)
1.2/50 μs
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) Minimum 100-nF capacitor is required between L+ and L-. Minimum 1-µF capacitor is required between VCC_IN/OUT and L-.
(3) Passing level is ±4500 V if the device is powered and EN=TX=HIGH.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
7
NOM
24
MAX
36
UNIT
V
V(L+)
Supply voltage
3.3 V configuration
5 V configuration
3
3.3
5
3.6
V
V(VCC_IN)
Logic level input voltage (TIOL111 only)
4.5
0
5.5
V
RSET
1/tBIT
I(VCC_OUT)
TA
External resistor for CQ current limit
Data rate (Communication mode)
100
250
20
kΩ
kbps
mA
°C
LDO output current (TIOL1113 and TIOL1115 only)
Operating ambient temperature
–40
125
150
TJ
Junction temperature
°C
4
Copyright © 2017–2019, Texas Instruments Incorporated
TIOL111, TIOL1113, TIOL1115
www.ti.com.cn
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
6.4 Thermal Information
TIOL111(x)
UNIT
THERMAL METRIC(1)
DMW (10 Pins)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
68.1
60.1
40.6
13.4
40.7
25.2
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
ψJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (L+)
EN = LOW, no load
1
2
1.5
2.7
mA
mA
I(L+)
Quiescent supply current
EN = HIGH, no load
LOGIC-LEVEL INPUTS (EN, TX)
VIL
Input logic low voltage
Input logic high voltage
Pull-down (EN) resistance
Pull-up (TX) resistance
0.8
V
V
VIH
2
RPD
RPU
100
200
kΩ
kΩ
CONTROL OUTPUTS (WAKE, NFAULT)
VOL
IOZ
Output logic low voltage
IO = 4 mA
0.5
1
V
Output high impedance leakage
Output in Hi-Z, VO = 0 V or VCC_IN/OUT
–1
µA
DRIVER OUTPUT (CQ)
I = 250 mA
1.75
1.5
V
V
V
V
V
V
High-side driver residual voltage I = 200 mA
I = 100 mA
I = 250 mA
I = 200 mA
I = 100 mA
1.1
VDS(ON)
1.75
1.5
Low-side driver residual voltage
1.1
High-side configuration, Rload = 26 Ω between CQ and
L-, 18 V ≤ V(L+) ≤ 30 V
14.5
V
V
V
Voltage between CQ and L-
during IO-Link Master wake-up
pulse
Low-side configuration, Rload = 24 Ω between CQ and
L+, V(L+) = 20 V
VIM
4
4
Low-side configuration, Rload = 44 Ω between CQ and
L+, V(L+) = 30 V
IOZ
CQ leakage
EN = LOW, 0 ≤ V(CQ) ≤ (V(L+) - 0.1 V)
RSET = 100 kΩ
–2
35
2
70
µA
mA
mA
mA
50
350
350
IO(LIM)
Driver output current limit
RSET = 0 kΩ
RSET = OPEN(1)
300
300
400
400
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
Copyright © 2017–2019, Texas Instruments Incorporated
5
TIOL111, TIOL1113, TIOL1115
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
www.ti.com.cn
Electrical Characteristics (continued)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
RECEIVER INPUT (CQ)
V(THH)
V(THL)
Input threshold “H”
Input threshold “L"
Receiver Hysteresis
10.5
8
13
V
V
11.5
V(L+) > 18 V
V(HYS)
0.75
0.75
V
(V(THH) - V(THL)
)
(2)
(3)
V(THH)
V(THL)
Input threshold “H”
Input threshold “L"
Receiver Hysteresis
See Note
See Note
V
V
(4)
(5)
See Note
See Note
V(L+) < 18 V
V(HYS)
VOL
V
V
V
(V(THH) - V(THL)
)
RX output low voltage
RX output high voltage
IOL = 4 mA
0.4
VCC_IN/
OUT–0.5
VOH
IOL = –4 mA
PROTECTION CIRCUITS
L+ falling; NFAULT = Hi-Z
L+ rising; NFAULT = LOW
Rising to falling threshold
6
V
V
V(UVLO)
L+ under voltage lockout
6.5
V(UVLO,HYS)
V(UVLO_IN)
L+ under voltage hysteresis
100
mV
V
VCC_IN falling; NFAULT = Hi-Z
VCC_IN rising; NFAULT = LOW
2.4
2.5
VCC_IN under voltage lockout
(No LDO option)
V
VCC_IN under voltage hysteresis
(No LDO option)
V(UVLO,HYS)
Rising to falling threshold
100
mV
T(WRN)
T(SDN)
T(HYS)
Thermal warning
125
150
°C
°C
°C
Thermal shutdown
Die temperature TJ
160
10
Thermal hysteresis for shutdown
EN = LOW, TX=x; V(CQ) < V(L-) or
V(CQ) > V(L+), up to |36 V|
50
80
µA
µA
EN = LOW, TX=x; V(CQ) < V(L-) or
V(CQ) > V(L+), up to |60 V|
Leakage current in reverse
polarity
IREV
EN = HIGH, TX = LOW; V(CQ to L+) = 3 V
EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V
550
10
µA
µA
LINEAR REGULATOR (LDO)
TIOL1115
TIOL1113
4.75
3.13
5
5.25
3.46
1.9
V
V
V
V(VCC_OUT)
Voltage regulator output
3.3
Voltage regulator drop-out
voltage
TIOL1115
TIOL1113
V(DROP)
REG
ICC = 20 mA load current
I(VCC_OUT) = 1 mA
2.3
1.7
V
(V(L+) – V(VCC_OUT)
)
Line regulation
(dV(VCC_OUT)/dV(L+))
mV/V
Load regulation
(dV(VCC_OUT)/V(VCC_OUT)
LREG
V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
100 kHz, I(VCC_OUT) = 20 mA
1%
)
PSSR
Power Supply Rejection Ratio
40
dB
(2) VTHH (min) = 5 V + (11/18) [V(L+) - 8 V]
(3) VTHH (max) = 6.5 V + (13/18) [V(L+) - 8 V]
(4) VTHL (min) = 4 V + (8/18) [V(L+) -8 V]
(5) VTHL (max) = 6 V + (11/18) [V(L+) -8 V]
6
Copyright © 2017–2019, Texas Instruments Incorporated
TIOL111, TIOL1113, TIOL1115
www.ti.com.cn
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
6.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SECTION NAME
tPLH, tPHL
tP(skew)
Driver propagation delay
600
100
800
ns
ns
Driver propagation delay skew.
See 图 6
See 图 7
See 图 8
RL = 2 kΩ
CL = 5 nF
|tPLH - tPHL
|
tPZH, tPZL
tPHZ, tPLZ
tr, tf
Driver enable delay
4
4
µs
µs
ns
ns
µs
µs
µs
µs
µs
Driver disable delay
R(SET) = 0 Ω
Driver output rise, fall time
Difference in rise and fall time
Wake-up recognition begin
Wake-up recognition end
Wake-up output delay
150
50
|tr – tf|
tWU1
45
85
60
75
tWU2
100
135
140
tpWAKE
tSC
See 图 10
Current fault blanking time
Current fault indication delay
175
200
tpSC
260
50
Current fault driver re-enable
wait time
tSCEN
15
30
ms
ms
CQ re-enable delay after UVLO V(UVLO) rising threshold crossing time to
t(UVLO)
10
(1)
CQ enable time
RECEIVER
tND
(2)
Noise suppression time
250
300
ns
ns
tPLH, tPHL
Receiver propagation delay
See 图 9 15-pF load on RX
150
(1) CQ output remains Hi-Z for this time
(2) Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection
taking place.
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ZHCSGF4D –JULY 2017–REVISED JUNE 2019
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6.7 Typical Characteristics
3
2.5
2
1.8
1.6
1.4
1.2
1
1.5
1
0.8
0.6
0.4
0.2
0
-40èC
25èC
125èC
0.5
0
En=High
En=Low
0
10
20
30
40
0
50
100
150
200
250
L+ Supply Voltage (V)
Load Current (mA)
D001
D002
No Load
TX = Open
25°C
图 1. Supply Current vs Supply Voltage
图 2. Residual Voltage vs Load Current: High Side
1.6
1.4
1.2
1
400
350
300
250
200
150
100
50
Low Side
High Side
0.8
0.6
0.4
0.2
0
-40èC
25èC
125èC
0
0
50
100
150
200
250
0
20
40
60
80
100
Load Current (mA)
RSET (kW)
D003
D004
图 3. Residual Voltage vs Load Current: Low Side
图 4. Current Limit vs RSET
14
13
12
11
10
9
8
7
6
VTHH
VTHL
5
4
7
9
11 13 15 17 19 21 23 25 27 29 31 33 35
L+ Voltage (V)
D005
图 5. Receiver Threshold Boundaries
8
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www.ti.com.cn
ZHCSGF4D –JULY 2017–REVISED JUNE 2019
7 Parameter Measurement Information
L+
RL
TX
EN
CQ
RL
CL
Copyright © 2016, Texas Instruments Incorporated
图 6. Test Circuit for Driver Switching
VOH
VOH
80%
80%
TX
50%
CQ
CQ
tPHL
tPLH
VOH
CQ
50%
20%
20%
VOL
VOL
VOL
tr
tf
图 7. Waveforms for Driver Output Switching Measurements
TX = LOW
50%
TX = HIGH
50%
EN
EN
tPZL
tPLZ
tPZH
tPHZ
V(L+) / 2
CQ
VOH
80%
50%
VOL
CQ
50%
20%
V(L+) / 2
图 8. Waveforms for Driver Enable/Disable Time Measurements
CQ
50%
tPLH
tPHL
RX
50%
图 9. Receiver Switching Measurements
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Parameter Measurement Information (接下页)
CQ
< tWU1
CQ
tWU1 < t < tWU2
CQ
> tSC
RX
WAKE
RX
WAKE
RX
WAKE
high
high
high
tpWAKE
high
NFAULT
NFAULT
NFAULT
tpSC
a) Over-current due to transient
b) Wake-up pulse from master
c) Over-current due to fault condition
图 10. Overcurrent and Wake Conditions for EN = H, TX = H (Full Lines);
and TX = L (Red Dotted Lines)
10
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ZHCSGF4D –JULY 2017–REVISED JUNE 2019
8 Detailed Description
8.1 Overview
图 11 shows that the TIOL111 or TIOL111x driver output (CQ) can be used in either push-pull, high-side, or low-
side configuration using the enable (EN) and transmit data (TX) input pins. The internal receiver converts the 24-
V signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel interface is used
to receive/transmit data and status information between the slave and the local controller.
These devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±65-V
transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels
of protection. These integrated robustness features will simplify the system level design by reducing external
protection circuitry.
TIOL111 or TIOL111x transceivers implement protection features for overcurrent, overvoltage and over-
temperature conditions. The devices also provide a current-limit setting of the driver output current using an
external resistor.
The devices derive the low-voltage supply from the IO-Link L+ voltage (24 V nominal) via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
VCC_ IN
L+
RX
TX
EN
CQ
DIAGNOSTICS
and
WAKE
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
图 11. Block Diagram TIOL111
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Functional Block Diagrams (接下页)
VOLTAGE
REGULATOR
VCC_OUT
L+
RX
TX
EN
CQ
DIAGNOSTICS
and
CONTROL
WAKE
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
Copyright © 2016, Texas Instruments Incorporated
图 12. Block Diagram TIOL111x
8.3 Feature Description
8.3.1 Wake Up Detection
The TIOL111(x) may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the device is in SIO
mode and the master node wants to initiate communication with the device node, the master drives the CQ line
to the opposite of its present state, and will either sink or source the wake up current (≥ 500 mA) for the wake-up
duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The TIOL111(x)
detects this wake-up condition and communicates to the local microcontroller via the WAKE pin. The IO-Link
communication specification requires the device node to switch to receive mode within 500 μs after receiving the
wake-up signal.
For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a high-
impedance (inactive) state. This is illustrated in 图 10.
8.3.2 Current Limit Configuration
The output current can be configured with an external resistor on ILIM_ADJ pin. The maximum settable current
limit is 300 mA. This maximum setting specifies a minimum of 300 mA over temperature and voltage.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitances.
表 1. Current Limit Configuration
NFAULT Indication During
Fault
Output Disable and Auto
Recovery
ILIM_ADJ Pin Condition
CQ Current Limit
RSET resistor to L-
Connected to L-
OPEN
Variable
300 mA
300 mA
Yes
Yes
Yes
Yes
Yes
No
12
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8.3.3 Current Fault Detection, Indication and Auto Recovery
If the output current at CQ exceeds the internally-set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN. See 表 5. Toggling EN will clear NFAULT.
8.3.4 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and TX pins.
8.3.5 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
Receive
Only
CUR_OK = Z
WAKE = Z
Driver = OFF
LDO = ON
Receive and
Transmit
Wake
WAKE = L
CQ at I
O(LIM)
CUR_OK = Z
WAKE = Z
Driver = ON
LDO = ON
CUR_OK = Z
Driver = ON
LDO = ON
for t
WU1
< t < t
WU2
and RX ≠TX
C
Q
at I
O
(LI
M)
Thermal
Warning
Current
Fault
T > T
WRN
CUR_OK = Z
TMP_OK = L
WAKE = Z
WAKE = Z
CUR_OK = L
Driver = OFF
LDO=ON
CQ at I
and T < T
WRN
O(LIM)
Driver = EN/EN*
LDO = ON
Thermal
Shutdown
CUR_OK = Z
TMP_OK = L
WAKE = Z
Current
Fault Recovery
WAKE = Z
CUR_OK = L
Driver = ON for tsc
LDO=ON
Driver = OFF
LDO = ON
NFAULT = [CUR_OK && PWR_OK && TMP_OK]
图 13. Device State Diagram
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8.3.6 Transceiver Function Tables
表 2. Driver Function
EN
TX
CQ
COMMENT
L / Open
X
L
Hi-Z
H
Device is in ready-to-receive state
H
H
CQ is sourcing current (high-side drive)
CQ is sinking current (low-side drive)
H / Open
L
表 3. Receiver Function
CQ VOLTAGE
V(CQ) < V(THL)
V(THL) < V(CQ) < V(THH)
V(THH) < V(CQ)
Open
RX
H
?
COMMENT
Normal receive mode, input low
Indeterminate output, may be either high or low
Normal receive mode, input high
L
?
Indeterminate output, may be either high or low
表 4. Wake-Up Function (tWU1 < t < tWU2
)
EN
TX
CQ CURRENT
WAKE
COMMENT
Device is in ready-to-receive state
L / Open
X
X
Z
Device receives high-level wake-up request from IO-
Link Master
H
H
H / Open
L
| I(CQ) | ≥ 500 mA
L
L
Device receives low-level wake-up request from IO-
Link Master
| I(CQ) | ≥ 500 mA
表 5. Current Limit Indicator Function (t > tSC
)
EN
TX
CQ CURRENT
| I(CQ) | > IO(LIM)
| I(CQ) | < IO(LIM)
| I(CQ) | > IO(LIM)
| I(CQ) | < IO(LIM)
X
NFAULT
COMMENT
L
Z
L
Z
Z
CQ current exceeds the set limit for over tSC
Normal operation
H
H / Open
CQ current exceeds the set limit for over tSC
Normal operation
H
L
L / Open
X
Driver is disabled, Current limit indicator is inactive
8.3.7 The Integrated Voltage Regulator (LDO)
The TIOL1113 and TIOL1115 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for L+ voltages in the range of 7 V to 36 V with respect
to L-. The LDO is capable of delivering up to 20 mA.
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output.
X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over temperature.
Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum capacitance to ensure
stability is 1 μF.
The voltage regulator has an internal 35-mA current limit to protect against initial startup inrush current due to
large decoupling capacitors and accidental short circuit conditions.
8.3.8 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
L+, CQ and L- pins. The maximum voltage between any of the pins may not exceed 60 V DC at any time.
图 14 and 图 15 shows all the possible connection combinations.
14
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L+
CQ
L-
L+
DC
DC
CQ
TIOL111(x)
TIOL111(x)
TIOL111(x)
TIOL111(x)
TIOL111(x)
TIOL111(x)
RL
RL
L-
Correct
Configuration
Reverse Polarity Protected
Fault Conditions
L+
CQ
L-
L+
DC
DC
CQ
RL
RL
L-
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
L+
CQ
L-
L+
DC
RL
DC
CQ
RL
L-
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
图 14. High-Side Driver Configuration
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L+
L+
CQ
L-
DC
DC
CQ
TIOL111(x)
TIOL111(x)
TIOL111(x)
TIOL111(x)
RL
RL
L-
Correct
Reverse Polarity Protected
Fault Conditions
Configuration
L+
L+
CQ
L-
DC
DC
CQ
TIOL111(x)
RL
RL
L-
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
L+
L+
CQ
L-
DC
DC
CQ
TIOL111(x)
RL
RL
L-
Reverse Polarity Protected
Fault Conditions
Reverse Polarity Protected
Fault Conditions
图 15. Low-Side Driver Configuration
16
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8.3.9 Integrated Surge Protection and Transient Waveform Tolerance
The L+ and CQ pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5
surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply
decoupling capacitor between L+ and L-, and 1 µF between VCC_IN/OUT and L-.
External TVS diodes may be required for higher transient protection levels. The system designer should ensure
that the maximum clamping voltage of the external diodes should be < 65 V at the desired current level. The
device is capable of withstanding up to ±65-V transient pulses < 100 µs.
Combination
wave
R
Generator
EUT
L+
CQ
L-
Decoupling
Network
> 100 nF
1.2/50 – 8/20 µs CWG
R = 500 Ω
图 16. Surge Test Setup
8.3.10 Power Up Sequence (TIOL111)
VCC_IN and L+ domains can be powered up in any sequence. In the event of L+ is powered and VCC_IN is not,
the CQ pin will remain in high impedance.
8.3.11 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the L+ voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to L+. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, the LDO is turned off and the CQ output is
disabled (Hi-Z). Receiver performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present) and the
LDO will be enabled immediately. The CQ output is turned on after T(UVLO) delay.
8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch SIO Mode)
Set TX pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on CQ.
8.4.2 PNP Configuration (P-Switch SIO Mode)
Set TX pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on CQ.
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Device Functional Modes (接下页)
8.4.3 Push-Pull, Communication Mode
Set EN pin high and toggle TX as control for realizing the function of a push-pull output on CQ. 表 6, 表 7 and 表
8 summarize the pin configurations to accomplish the functional modes.
表 6. NPN Mode
EN
L / Open
H
TX
CQ
Hi-Z
H / Open
H / Open
N-Switch
表 7. PNP Mode
EN
L / Open
H
TX
L
CQ
Hi-Z
L
P-Switch
表 8. Push-Pull, Communication Mode
EN
TX
X
CQ
L / Open
Hi-Z
H
H
H
N-Switch
P-Switch
L
18
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
When TIOL111(x) is connected to an IO-Link master through a three-wire interface (图 17), the master can
initiate communication and exchange data with a remote node with the TIOL111(x) IO-Link transceiver acting as
a complete physical layer for the communication.
9.2 Typical Application
TIOL111(x)
VCC_OUT
L+
VOLTAGE
REGULATOR
0.1 µF
100 V
1 µF
10 V
10 kΩ
RX
10 kΩ
TX
EN
Sensor
Front-End
Microcontroller
CQ
IO-Link Master
DIAGNOSTICS
and
WAKE
CONTROL
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
RSET
图 17. Typical Application Schematic
9.2.1 Design Requirements
TIOL111 and TIOL111x IO-Link transceivers can be used in slave devices communicating with an IO-Link
master, or as standard digital outputs to either sense or drive a wide range of sensors and loads. 表 9 shows
recommended components for a typical system design.
表 9. Design Parameters
PARAMETERS
Input voltage range (L+)
VALUE
24 V, 30 V (max)
200 mA
Output current (CQ)
Output voltage (VCC_OUT), Pick TIOL1115
5 V
Maximum LDO output current (IVCC(OUT)
)
5 mA
Pull-up resistors for NFAULT and WAKE
L+ decoupling capacitor
10 kΩ
0.1 µF / 100 V
1 µF / 10 V
10 kΩ
LDO output capacitor
ILIM_ADJ resistor (RSET
)
Maximum Ambient Temperature, TA
105 °C
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9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
•
•
The maximum driver output current limit, IO(LIM) = 250 mA (allowed for current limit tolerance).
The maximum voltage drop is given with VDS(ON) = 1.75 V.
This causes a power consumption of:
2&12 = 8&5(10) T +1(.+/) = 1.758 T 250 I# = 437.5 I9
(1)
For a 5 mA LDO current output,
:
;
2&.&1 = k8.+ F 88%%_176 o x +8%%_176 = 30 F 5 V x 5 mA = 125 mW
(2)
(3)
Total power dissipation,
2& = 2&12 + 2&.&1 = 437.5 I9 + 125 I9 = 562.5 I9
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 68.1°C/W (taken from the Thermal
Information table) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
¿6 = 6 F 6 = 2& x E,# = 562.5 I9 T 68.1°%/9 = 38.3°%
,
#
(4)
Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature:
6
,FI=T
= 6
+ ¿6 = 105°% + 38.3°% = 143.3°%
#FI=T
(5)
As long as TJ-max is below the recommended maximum value of 150°C, no thermal shutdown will occur.
However, thermal warning may occur as the junction temperature is greater than TWRN
.
Note that the modeling of the complete system may be necessary to predict junction temperature in smaller
PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the CQ output. Assuming a pure capacitive load without
series/parallel resistance, the maximum capacitance that can be charged without triggering current fault can be
calculated as:
[I
x t
]
SC
O LIM
(
)
C
=
LOAD
V
L+
(
)
(6)
Higher capacitive loads can be driven if a series resistor is connected between the CQ output and the load.
Capacitive loads can be connected to L- or L+.
9.2.2.3 Driving Inductive Loads
The TIOL111(x) family is capable of magnetizing and demagnetizing inductive loads up to 1.5H. These devices
contain internal circuitry that enables fast demagnetization when configured as either P-switch or N-switch mode.
In P-switch configuration, the load inductor L is magnetized when the CQ output is driven high. When the PNP is
turned off, there is a significant amount of negative inductive kick back at the CQ pin. This voltage is clamped
internally at about -75 V.
Similarly in N-switch configuration, the load inductor L is magnetized when the CQ output is driven low. When the
NPN is turned off, there is a significant amount of positive inductive kick back at the CQ pin. This voltage is
clamped internally at about 75 V.
The equivalent protection circuits are shown in 图 18 and 图 19. The minimum value of the resistive load R can
be calculated as:
V
L+
(
)
R =
I
O(LIM)
(7)
20
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L+
L+
R
CQ
CQ
L
L
R
TIOL111(x)
TIOL111(x)
图 18. P-Switch Mode
图 19. N-Switch Mode
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9.2.3 Application Curves
Time 1 ms/div
Time 10 ms/div
125 kHz
图 20. CQ in Communication Mode
图 21. CQ Power Up Delay, Low Side Mode
Time 10 ms/div
Time 50 ms/div
图 22. CQ Power Up Delay, High Side Mode
图 23. CQ in Current Fault, Low Side Mode
Time 10 ms/div
Time 50 ms/div
图 25. CQ in Current Fault Auto Recovery,
图 24. CQ in Current Fault, High Side Mode
Low Side Mode
22
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Time 20 ms/div
Time 10 ms/div
图 26. CQ in Current Fault Auto Recovery,
图 27. IO-Link WAKE, Low Side Mode
High Side Mode
Time 10 ms/div
Time 20 ms/div
1.5-H Inductor
With 100 Ω
RSET = OPEN
图 29. CQ Driving, Low Side Mode
图 28. IO-Link WAKE, High Side Mode
Time 10 ms/div
1.5-H Inductor
With 100 Ω
RSET = OPEN
图 30. CQ Driving, High Side Mode
10 Power Supply Recommendations
The TIOL111 and TIOL111x transceivers are designed to operate from a 24-V nominal supply at L+, which can
vary by +12 V and -17 V from the nominal value to remain within the device's recommended supply voltage
range of 7 V to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor.
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11 Layout
11.1 Layout Guidelines
•
Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as power ground layer for L-, layer 3 for the 24-V supply plane (L+), and layer 4 for the regulated
output supply (VCC_IN/OUT).
•
•
•
Connect the thermal pad to L- with maximum amount of thermal vias for best thermal performance.
Use entire planes for L+, VCC_IN/OUT and L- to assure minimum inductance.
The L+ terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The
recommended minimum capacitor value is 100 nF. The capacitor must have a voltage rating of 50 V minimum
(100 V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
•
•
The optimum placement of the capacitor is closest to the transceiver’s L+ and L- terminals to reduce supply
drops during large supply current loads. See 图 31 for a PCB layout example.
Connect all open-drain control outputs via 10 kΩ pull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
•
•
Connect the RSET resistor between ILIM_ADJ and L-.
Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, ≥ 1-μF, ceramic decoupling
capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R dielectric.
11.2 Layout Example
VIA to Layer 2: Power Ground Plane (L-)
VIA to Layer 3: 24V Supply Plane (L+)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
WAKE
1uF/10V
100nF/
50V
NFAULT
L+
CQ
L-
L+
CQ
L-
RX
TX
EN
Use Multiple Vias
for L+ and L-
Exposed Thermal
Pad Area
RSET
图 31. Layout Example
24
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12 器件和文档支持
12.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 社区资源
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 商标
E2E is a trademark of Texas Instruments.
12.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
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25
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TIOL1113DMWR
TIOL1113DMWT
TIOL1115DMWR
TIOL1115DMWT
TIOL111DMWR
TIOL111DMWT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
VSON
VSON
VSON
VSON
VSON
DMW
DMW
DMW
DMW
DMW
DMW
10
10
10
10
10
10
1500 RoHS & Green
250 RoHS & Green
1500 RoHS & Green
250 RoHS & Green
1500 RoHS & Green
250 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TL1113
NIPDAU
NIPDAU
NIPDAU
NIPDAU
NIPDAU
TL1113
TL1115
TL1115
TL111
TL111
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TIOL1115DMWR
TIOL111DMWR
TIOL111DMWT
VSON
VSON
VSON
DMW
DMW
DMW
10
10
10
1500
1500
250
178.0
178.0
178.0
13.5
13.5
13.5
2.75
2.75
2.75
3.35
3.35
3.35
1.05
1.05
1.05
8.0
8.0
8.0
12.0
12.0
12.0
Q2
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TIOL1115DMWR
TIOL111DMWR
TIOL111DMWT
VSON
VSON
VSON
DMW
DMW
DMW
10
10
10
1500
1500
250
189.0
189.0
189.0
185.0
185.0
185.0
36.0
36.0
36.0
Pack Materials-Page 2
PACKAGE OUTLINE
DMW0010A
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
A
B
PIN 1 INDEX AREA
2.6
2.4
C
1 MAX
SEATING PLANE
0.08 C
1.65 0.1
SYMM
(0.2) TYP
0.05
0.00
EXPOSED
THERMAL PAD
5
6
2X
2
SYMM
11
1.95 0.1
1
10
8X 0.5
0.475
0.275
0.29
0.19
10X
10X
PIN 1 ID
(OPTIONAL)
0.1
C A B
C
0.05
4223225/A 08/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
10X (0.575)
(0.575)
1
10
10X (0.24)
(0.725)
SYMM
11
(1.95)
8X (0.5)
(R0.05) TYP
5
6
(
0.2) VIA
TYP
SYMM
(2.825)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4223225/A 08/2016
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DMW0010A
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
10X (0.575)
METAL
TYP
SYMM
1
11
10
10X (0.24)
(0.535)
SYMM
8X (0.5)
(0.87)
(R0.05) TYP
5
6
2X (1.5)
(2.825)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11
81% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4223225/A 08/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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