TIOL1125 [TI]
具有低残余电压、集成浪涌保护功能和 5V LDO 输出的 IO-Link 器件收发器;
| 型号： | TIOL1125 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有低残余电压、集成浪涌保护功能和 5V LDO 输出的 IO-Link 器件收发器 |
| 文件： | 总39页 (文件大小：2475K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
采用小型封装且具有低残余电压和集成浪涌保护功能的TIOL112 和TIOL112x
IO-Link 器件收发器
1 特性
2 应用
• 7V 至36V 电源电压
• PNP、NPN 或IO-Link 可配置输出
• 现场发送器和执行器
• 工厂自动化
• 过程自动化
– IEC 61131-9 COM1、COM2 和COM3 数据速
率支持
• 功能安全型
• 远程IO 中的IO-Link PHY
3 说明
– 可提供用于功能安全系统设计的文档
• 与TIOL111(x) 引脚兼容，并提升了性能
TIOL112(x) 系列收发器使用 IO-Link 接口实现工业双
向点到点通信。当此器件通过一个三线制接口连接至一
个 IO-Link 主器件时，主器件能够发起通信并与远程节
点交换数据，而此时 TIOL112(x) 则用作一个用于通信
的完整物理层。
– 在200mA 条件下，残余电压低，为0.5V
（典型值）
– 有效驱动器电流限制能力
– 改善了封装的热性能
– 更低的驱动器压摆率，以减少过冲：
最大750ns
• 使系统更加稳健的集成保护特性
这些器件能够承受高达 1.2kV (500Ω) 的 IEC
61000-4-5 浪涌，并集成反向极性保护功能。只需通过
一个简单的引脚可编程接口，便可轻松连接到控制器电
路。可使用外部电阻器配置输出电流限值。TIOL112(x)
可配置为生成唤醒脉冲并用于 IO-link 主应用。针对欠
压、过流和过热情况提供了故障报告和内部保护功能。
– 可配置驱动器过流限制：
50mA 至350mA
– L+、CQ 和L- 上高达65V 的有效反极性保护
– 过流、过热和UVLO 的故障指示灯
– 电感性负载的安全快速消磁功能
– 工作环境温度
器件信息
封装(1)
封装尺寸（标称值）
器件型号
TIOL112
：-40°C 至125°C
• L+ 和CQ 上的集成式EMC 保护
TIOL1123
TIOL1125
TIOL112
VSON (10)
3.00mm x 3.00mm
– ±8 kV IEC 61000-4-2 ESD 接触放电
– ±4kV IEC 61000-4-4 电气快速瞬变
– ±1.2kV/500Ω IEC 61000-4-5 浪涌
• 较大电容性负载驱动能力
DSBGA (12)
2.45mm x 1.70mm
TIOL1123
(1) 如需了解所有可订购器件，请参阅数据表末尾的可订购产品附
录。
• < 2µA CQ 泄露电流
• < 1.5mA 静态电源电流
• 集成式LDO 选项可支持高达20mA 的电流
VCC_OUT
Rev.
Polarity
Protection
VOLTAGE
REGULATOR
L+
0.1 µF
100
1
10
µF
V
V
10
k
ESD and
Surge
Protection
– TIOL1123：3.3V LDO
– TIOL1125：5V LDO
– TIOL1123L (YAH)：可选3.3V/5V 输出
• 远程唤醒指示和唤醒生成
• 节省空间的小型封装选项
– 3mm x 3mm 10 引脚VSON 封装：
与TIOL111 引脚兼容
RX
10
k
TX
EN
Sensor
Front-End
Microcontroller
IO-Link Master
PHY
CQ
Rev. Polarity
Protection
DIAGNOSTICS
& CONTROL
WAKE
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
典型应用图
– 2.45 mm x 1.7 mm DSBGA 封装
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLLSFJ1
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagrams....................................... 13
8.3 Feature Description...................................................14
8.4 Device Functional Modes..........................................21
9 Application and Implementation..................................22
9.1 Application Information............................................. 22
9.2 Typical Application.................................................... 22
9.3 Power Supply Recommendations.............................26
9.4 Layout....................................................................... 26
10 Device and Documentation Support..........................27
10.1 Receiving Notification of Documentation Updates..27
10.2 支持资源..................................................................27
10.3 Trademarks.............................................................27
10.4 静电放电警告.......................................................... 27
10.5 术语表..................................................................... 27
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 ESD Ratings - IEC Specifications...............................5
6.4 Recommended Operating Conditions.........................5
6.5 Thermal Information....................................................6
6.6 Electrical Characteristics.............................................6
6.7 Switching Characteristics............................................8
6.8 Typical Characteristics................................................9
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................13
8.1 Overview...................................................................13
Information.................................................................... 27
4 Revision History
Changes from Revision C (January 2023) to Revision D (March 2023)
Page
• Added the package outline and land pattern images for the YAH (DSBGA) 12-pin package...........................27
Changes from Revision B (December 2022) to Revision C (January 2023)
Page
• 删除了器件信息 表中DSBGA 封装的预告信息 注释..........................................................................................1
Changes from Revision A (April 2022) to Revision B (December 2022)
Page
• Removed the conditional note 2 from the IEC Ratings - ESD Specifications table that specified 4.5kV
when EN=TX=HIGH .......................................................................................................................................... 5
• Changed the description of I(VCC_OUT) from: (TIOL112L only) to: TIOL1123(L), TIOL1125 only in the
Recommended Operating Conditions table........................................................................................................5
• Changed 图6-4 and 图6-6 ................................................................................................................................9
• Added application curves Figure 9-6 and Figure 9-7 showing inductive load demagnetization....................... 25
Changes from Revision * (February 2022) to Revision A (April 2022)
Page
• 删除了器件信息 表中VSON 封装的TIOL112 和TIOL1125 预告信息 注释....................................................... 1
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFJ1
2
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TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
www.ti.com.cn
5 Pin Configuration and Functions
1
2
3
4
5
10
9
1
2
3
4
5
10
9
VCC_IN
NFAULT
RX
WAKE
L+
VCC_OUT
NFAULT
RX
WAKE
L+
8
8
CQ
CQ
Thermal Pad
Thermal Pad
7
7
TX
L–
TX
L–
ILIM_ADJ
ILIM_ADJ
6
6
EN
EN
图5-1. TIOL112
DRC (VSON), 10-Pin
(Top View)
图5-2. TIOL1123, TIOL1125
DRC (VSON), 10-Pin
(Top View)
表5-1. Pin Functions (VSON Package)
PIN NAME
PIN NO
TYPE
DESCRIPTION
TIOL1123
TIOL1125
TIOL112
VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123,
TIOL1125): 3.3-V or 5-V linear regulator output
1
VCC_IN
VCC_OUT
P
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage supply or an overtemperature condition.
2
3
4
NFAULT
RX
NFAULT
RX
O
O
I
Receive data output to the local microcontroller
Transmit data input from the local microcontroller. No effect if EN is low. Logic high sets low-side
switch. Logic low sets high-side switch. Weak internal pull-up.
TX
TX
Driver enable input signal from the local microcontroller. Logic low sets the CQ output at Hi-Z.
Weak internal pull-down.
5
EN
EN
I
6
7
8
9
ILIM_ADJ
ILIM_ADJ
I
GND
I/O
P
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
IO-Link ground potential
L-
CQ
L+
L-
CQ
L+
IO-Link data signal (bidirectional)
IO-Link supply voltage (24 V nominal)
Wake-up indicator to the local microcontroller. Open-drain output, connect this pin via pull-up
resistor to VCC_IN/OUT.
10
WAKE
WAKE
O
Thermal Pad
Thermal Pad
Connect to L- for optimal thermal and electrical performance
—
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Product Folder Links: TIOL112 TIOL1123 TIOL1125
English Data Sheet: SLLSFJ1
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
www.ti.com.cn
1
2
3
1
2
3
L-
CQ
L+
L-
CQ
L+
A
B
C
D
A
B
C
D
VCC_
IN
ILIM
_ADJ
VCC_
OUT
ILIM
_ADJ
L-
L-
NFAU
LT
NFAU
LT
WAKE
VSEL
RX
NC
RX
WAKE
TX
TX
EN
EN
图5-3. TIOL1123L
YAH (DSBGA), 12-Pin
(Top View)
图5-4. TIOL112
YAH (DSBGA), 12-Pin
(Top View)
表5-2. Pin Functions (DSBGA)
PIN NAME
PIN NO
TYPE
DESCRIPTION
TIOL112
TIOL1123L
VCC_IN (TIOL112): External 3.3-V or 5-V logic supply input pin. VCC_OUT (TIOL1123): 3.3-V or
5-V linear regulator output
B3
VCC_IN
VCC_OUT
P
Fault indicator output signal to the microcontroller. A low level indicates either an over- current, an
undervoltage supply or an overtemperature condition.
C3
D1
D2
NFAULT
RX
NFAULT
RX
O
O
I
Receive data output to the local controller
Transmit data input from the local controller. No effect if EN is low. Logic high sets low-side
switch. Logic low sets high-side switch. Weak internal pull-up.
TX
TX
Driver enable input signal from the local controller. Logic low sets the CQ output at Hi-Z. Weak
internal pull-down.
D3
B1
EN
EN
I
ILIM_ADJ
ILIM_ADJ
O
Input for current limit adjustment. Connect resistor RSET between ILIM_ADJ and L-.
A1,
B2
L-
L-
GND
IO-Link ground potential
A2
A3
CQ
L+
CQ
L+
I/O
P
IO-Link data signal (bidirectional)
IO-Link supply voltage (24 V nominal)
TIOL112 (NC): Leave floating. Do not connect.
TIOL1123 (VSEL): Connect to GND for 5V LDO output. Please leave this pin floating for 3.3V
LDO output. VSEL has an internal pull-up of 1 MΩ
C1
C2
NC
VSEL
I
WAKE
WAKE
O
Wake-up indicator to the local controller. Open-drain output, connect this pin via pull-up resistor to
VCC_IN/OUT.
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Product Folder Links: TIOL112 TIOL1123 TIOL1125
English Data Sheet: SLLSFJ1
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–65
–70
MAX
65
70
65
6
UNIT
Steady state voltage for L+ and CQ
Supply voltage
V
V
V
V
Transient pulse width < 100 µs for L+ and CQ
Voltage difference
|V(L+) –V(CQ)
|
Logic supply voltage (TIOL112)
VCC_IN
–0.3
–0.3
min(VCC_IN+
0.3, 6)
Input logic voltage
TX, EN, VSEL
V
Output current
RX, WAKE, NFAULT
5
mA
°C
–5
Storage temperature, Tstg
-55
170
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime. All voltages are with reference to the L- pin, unless otherwise specified.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
V(ESD)
V(ESD)
Electrostatic discharge
Electrostatic discharge
All pins
All pins
±4000
V
Charged Device Model (CDM), per ANSI/ESDA/JEDEC
JS-002 ((2))
±750
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 ESD Ratings - IEC Specifications
VALUE
UNIT
((1))
Electrostatic discharge
Electrostatic discharge
Electrostatic discharge
IEC 61000-4-2 ESD (Contact Discharge), L+, CQ and L-
±8,000
±1,200
±4,000
IEC 61000-4-5, 1.2 µs/50 µs Surge with 500 Ω in series, L+, CQ and L- (1)
IEC 61000-4-4 EFT (Fast transient or burst), L+, CQ and L- (1)
V(ESD)
V
(1) Minimum 100-nF capacitor is required between L+ and L-. Minimum 1-µF capacitor is required between VCC_IN/VCC_OUT and L-.
6.4 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
7
NOM
24
MAX
36
UNIT
V
V(L+)
Supply voltage
3.3 V configuration
5 V configuration
3
3.3
5
3.6
V
V(VCC_IN)
Logic level input voltage (TIOL112 only)
4.5
0
5.5
V
RSET
1/tBIT
I(VCC_OUT)
TA
External resistor for CQ current limit
Data rate (Communication mode)
110
250
20
kΩ
kbps
mA
°C
LDO output current (TIOL1123(L), TIOL1125 only)
Operating ambient temperature
Junction temperature
125
150
–40
TJ
°C
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Product Folder Links: TIOL112 TIOL1123 TIOL1125
English Data Sheet: SLLSFJ1
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
www.ti.com.cn
6.5 Thermal Information
TIOL112,
TIOL1123,
TIOL1125
TIOL112, TIOL1123L
THERMAL METRIC(1)
UNIT
DRC (10 Pins)
YAH (12 Pins)
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
45.9
45.9
17.9
0.7
79.3
0.3
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
19.5
0.1
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
17.8
4.7
19.4
N/A
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.6 Electrical Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (L+)
EN = LOW, no load
EN = HIGH, no load
1
2
1.5
mA
mA
I(L+)
Quiescent supply current
2.95
LOGIC-LEVEL INPUTS (EN, TX, VSEL)
VIL
Input logic low voltage
Input logic high voltage
Pull-down (EN) resistance
Pull-up (TX) resistance
Pull-up (VSEL) resistance
0.8
V
VIH
2
V
RPD
RPU
RPU
100
200
kΩ
kΩ
kΩ
1000
CONTROL OUTPUTS (WAKE, NFAULT)
VOL
IOZ
Output logic low voltage
IO = 4 mA
0.5
1
V
Output high impedance leakage Output in Hi-Z, VO = 0 V or VCC_IN/OUT
µA
–1
DRIVER OUTPUT (CQ)
RDS(ON)
VDS(ON)
RDS(ON)
VDS(ON)
High-side driver on-resistance
2.5
0.5
4.5
0.9
0.5
4.5
0.9
0.5
2
Ω
V
V
I = 200 mA
I = 100 mA
High-side driver residual voltage
Low-side driver on-resistance
Low-side driver residual voltage
0.25
2.5
Ω
V
V
I = 200 mA
0.5
I = 100 mA
0.25
IOZ(CQ)
ILLM
CQ leakage
µA
mA
mA
mA
EN = LOW, 0 ≤V(CQ) ≤(V(L+) - 0.1 V)
EN = LOW, RSET = 0 to 5 kΩ((2)), V(CQ) >= 5 V
RSET = 110 kΩ; V(CQ)= (VL+ - 3) V or 3 V
RSET = 10 kΩ
–2
5
CQ load discharge current
15
35
50
70
300
350
400
((2))
RSET = 0 to 5 kΩ
IO(LIM)
Driver output current limit
500
260
mA
mA
V(CQ)= (VL+ - 3) V or 3 V
TJ < T(SDN) or t < 200 µs ((7))
(Fast-detect mode) RSET = OPEN((1))V(CQ)= (VL+ - 3) V
or 3 V
330
400
RECEIVER INPUT (CQ)
V(THH)
V(THL)
10.5
8
13
V
V
Input threshold “H”
Input threshold “L"
Receiver Hysteresis
11.5
V(L+) > 18 V, EN= LOW
V(HYS)
0.75
V
(V(THH) - V(THL)
)
Copyright © 2023 Texas Instruments Incorporated
English Data Sheet: SLLSFJ1
6
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6.6 Electrical Characteristics (continued)
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
See Note (4)
See Note (6)
TYP
MAX
See Note (5)
See Note (7)
UNIT
V
V(THH)
V(THL)
V(L+) < 18 V, EN= LOW
Input threshold “H”
Input threshold “L"
Receiver Hysteresis
V
V(L+) < 18 V, EN= LOW
V(HYS)
VOL
0.75
V
V
V
(V(THH) - V(THL)
)
RX output low voltage
RX output high voltage
IOL = 4 mA
0.4
6.8
VCC_IN/
OUT–0.5
VOH
IOL = –4 mA
PROTECTION CIRCUITS
L+ falling; NFAULT = Hi-Z
L+ rising; NFAULT = LOW
Rising to falling threshold
6
6.3
6.5
V
V
V(UVLO)
L+ under voltage lockout
V(UVLO,HYS) L+ under voltage hysteresis
200
mV
V
VCC_IN falling; NFAULT = Hi-Z
VCC_IN rising; NFAULT = LOW
2.3
2.5
VCC_IN under voltage lockout
V(UVLO_IN)
(No LDO option)
V
VCC_IN under voltage hysteresis
V(UVLO,HYS)
Rising to falling threshold
190
mV
(No LDO option)
T(WRN)
T(SDN)
T(HYS)
T(WRN)
Thermal warning
125
150
°C
°C
°C
°C
Thermal shutdown
Die temperature TJ
Die temperature TJ
160
14
Thermal hysteresis for shutdown
Thermal hysteresis for warning
14
EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |36
V|
60
µA
µA
EN=LOW, TX=x; V(CQ) < V(L-) or V(CQ) > V(L+), up to |65
V|
Leakage current in reverse
polarity
110
IREV
EN = HIGH, TX = LOW; V(CQ to L+) = 3 V
EN = HIGH, TX = HIGH; V(CQ to L-) = -3 V
640
10
µA
µA
LINEAR REGULATOR (LDO)
TIOL1125, TIOL1123L (5V)
TIOL1123, TIOL1123L (3.3V)
TIOL1125, TIOL1123L (5V)
4.75
3.13
5
3.3
5.25
3.46
1.9
V
V
V
V(VCC_OUT) Voltage regulator output
0.75
Voltage regulator drop-out
voltage
(V(L+) –V(VCC_OUT)
V(DROP)
ICC = 20 mA load current
TIOL1123, TIOL1123L
0.75
2.3
1.7
1%
V
)
(3.3V)
Line regulation (dV(VCC_OUT)
dV(L+))
/
REG
I(VCC_OUT) = 1 mA
mV/V
Load regulation (dV(VCC_OUT)
V(VCC_OUT)
/
LREG
V(L+) = 24 V, I(VCC_OUT) = 100 µA to 20 mA
100 kHz, I(VCC_OUT) = 20 mA
)
PSSR
Power Supply Rejection Ratio
40
dB
(1) Current fault indication will be active. Current fault auto recovery will be de-activated.
(2) Current fault indication and current fault auto recovery will be de-activated.
(3) If operating continuosly with this current limit, ensure that the current through the device does not cause the TJ to be greater than
T(SDN) for a given ambient temperature and thermal porperty of the system. For pulse durations t < 200 µs, the device can source or
sink current of at least 500 mA across the recommended operating conditions. For YAH (DSBGA) package, this parameter is specified
by design and characterization.
(4) VTHH (min) = 5 V + (11/18) [V(L+) - 8 V]
(5) VTHH (max) = 6.5 V + (13/18) [V(L+) - 8 V]
(6) VTHL (min) = 4 V + (8/18) [V(L+) -8 V]
(7) VTHL (max) = 6 V + (11/18) [V(L+) -8 V]
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6.7 Switching Characteristics
Over recommended operating conditions and recommended free-air temperature range (unless otherwise noted). Typical
values are at L+ = 24 V, VVCC_IN = 3.3 V, VVCC_OUT = 3.3 V and TA = 25 ℃unless otherwise specified.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DRIVER
tPLH, tPHL
Driver propagation delay
Driver propagation delay skew. |
600
75
1200
ns
ns
See 图7-1
tP(skew)
tPLH - tPHL
|
See 图7-2
See 图7-3
RL = 2 kΩ
CL = 5 nF
tPZH, tPZL
tPHZ, tPLZ
tr, tf
Driver enable delay
4
4
µs
µs
ns
ns
µs
µs
µs
µs
µs
Driver disable delay
R(SET) = 10 kΩ
Driver output rise, fall time
Difference in rise and fall time
Wake-up recognition begin
Wake-up recognition end
Wake-up output delay
200
700
50
60
|tr –tf|
tWU1
45
85
75
145
150
tWU2
100
tpWAKE
tSC
See 图7-5
See 图7-6
Current fault blanking time
Current fault indication delay
175
175
200
tpSC
280
285
Wake output pulse duration on
wake detection in EN=L mode
tWUL
225
15
µs
ms
ms
Current fault driver re-enable
wait time
tSCEN
t(UVLO)
CQ re-enable delay after UVLO V(UVLO) rising threshold crossing time to
10
30
50
(1)
CQ enable time
RECEIVER
tND
Noise suppression time (2)
250
300
ns
ns
tPLH, tPHL
Receiver propagation delay
150
See 图7-4 15-pF load on RX,
(1) CQ output remains Hi-Z for this time
(2) Noise suppression time is defined as the permissible duration of a receive signal above/below the detection threshold without detection
taking place.
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6.8 Typical Characteristics
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.6
2.4
2.2
2
TA = -40 C
TA = 25 C
TA = 125 C
EN=L
EN=H
1.8
1.6
1.4
1.2
1
0.8
0
25
50
75 100 125 150 175 200 225 250
Load Current (mA)
6
9
12 15 18 21 24 27 30 33 36 39
L+ Supply Voltage (V)
spacer
No Load
TX = Open
TA = 25°C
图6-2. Residual Voltage vs Load Current:
图6-1. Supply Current vs Supply Voltage
High Side
0.9
TA = -40 C
800
700
600
500
400
300
200
100
0
Min
Typ
Max
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
TA = 25 C
TA = 125 C
For RSET below 5 k, TIOL112(x) can
generate wake-up pulse and
enables CQ load discharge current (ILLM
)
0
25
50
75 100 125 150 175 200 225 250
Load Current (mA)
0
10 20 30 40 50 60 70 80 90 100 110
RSET (k)
spacer
For RSET in the 0-5 kΩrange, TIOL112(x) can source/sink 500
mA required for wake-up pulse generation in IO-link
applications. For RSET in the 0-5 kΩrange, TIOL112(x) also
activates a pull-down current source (ILLM) when the driver is
disabled. Min and max curves specified by design and
characterization across temperature and process variation.
TA = 25°C (typ curve)
图6-3. Residual Voltage vs Load Current:
Low Side
图6-4. Current Limit vs RSET
800
14
TIOL111
TIOL112
750
700
650
600
550
500
450
400
350
300
250
200
150
100
50
VTHH
VTHL
13
12
11
10
9
8
7
6
5
0
0
10 20 30 40 50 60 70 80 90 100 110
4
RSET (k)
7
11
15
19
23
27
31
35
L+ (V)
TA = 25°C
TA = 25°C
图6-6. Current limit vs RSET
TIOL112(x) vs TIOL111(x)
:
图6-5. Receiver Threshold Boundaries
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7 Parameter Measurement Information
L+
RL
TX
EN
CQ
RL
CL
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图7-1. Test Circuit for Driver Switching
VOH
VOH
80%
80%
TX
50%
CQ
CQ
tPHL
tPLH
VOH
CQ
50%
20%
20%
VOL
VOL
VOL
tr
tf
图7-2. Waveforms for Driver Output Switching Measurements
TX = LOW
TX = HIGH
EN
50%
EN
50%
tPZL
tPLZ
tPZH
tPHZ
V(L+) / 2
CQ
VOH
80%
50%
VOL
CQ
50%
20%
V(L+) / 2
图7-3. Waveforms for Driver Enable or Disable Time Measurements
CQ
50%
tPLH
tPHL
RX
50%
图7-4. Receiver Switching Measurements
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CQ
< tWU1
CQ
tWU1 < t < tWU2
CQ
> tSC
RX
RX
RX
high
high
WAKE
WAKE
WAKE
tpWAKE
high
high
NFAULT
EN
NFAULT
EN
NFAULT
EN
tpSC
high
high
low
a) Over-current due to transient
b) Valid Wake-up pulse
c) Over-current due to fault condition
图7-5. Overcurrent and Wake Conditions for EN = H and ILIM_ADJ = 10 kΩto 110 kΩ,
TX = H (Full Lines); and TX = L (Red Dotted Lines)
low
EN=L
CQ
75 s < t < 85
s
RX
t
WAKE
WUL
t
pWAKE
high
NFAULT
图7-6. Wake Conditions for EN = L, RX = H (Full Lines); and RX = L (Red Dotted Lines)
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< tWU1
tWU1 < t < tWU2
CQ
CQ
CQ
> tSC
RX
WAKE
RX
WAKE
RX
WAKE
high
high
t
pWAKE
NFAULT
NFAULT
NFAULT
t
t
t
t
t
t
pF2
pF1
pF2
pF1
pF2
pF1
a) Over-current due to transient
b) Valid Wake-up pulse
c) Over-current due to fault condition
图7-7. Overcurrent and Wake Conditions for EN = H and ILIM_ADJ is floating, TX = H (Full Lines); and TX
= L (Red Dotted Lines)
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8 Detailed Description
8.1 Overview
图8-1 shows that the TIOL112 or TIOL112x driver output (CQ) can be used in either push-pull, high-side, or low-
side configuration using the enable (EN) and transmit data (TX) input pins. The internal receiver converts the 24-
V signal on the CQ line to standard logic levels on the receive data (RX) pin. A simple parallel interface is used
to receive/transmit data and status information between the device and the local controller.
These devices have integrated IEC 61000-4-4/5 EFT and surge protection. In addition, tolerance to ±70-V
transients enables flexibility to choose from a wider range of TVS diodes if an application requires higher levels
of protection. These integrated robustness features will simplify the system level design by reducing external
protection circuitry.
TIOL112 or TIOL112x transceivers implement protection features for overcurrent, overvoltage and over-
temperature conditions. The devices also provide a current-limit setting of the driver output current using an
external resistor.
The devices derive the low-voltage supply from the IO-Link L+ voltage (24 V nominal) via an internal linear
regulator to provide power to the local controller and sensor circuitry.
8.2 Functional Block Diagrams
Rev.
Polarity
L+
VCC_IN
Protection
ESD and
Surge
Protection
RX
TX
EN
CQ
Rev. Polarity
Protection
DIAGNOSTICS
& CONTROL
WAKE
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
图8-1. Block Diagram TIOL112
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VSEL (YAH package only)
Rev.
Polarity
Protection
VOLTAGE
REGULATOR
L+
VCC_OUT
ESD and
Surge
Protection
RX
TX
EN
CQ
Rev. Polarity
Protection
DIAGNOSTICS
& CONTROL
WAKE
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
图8-2. Block Diagram TIOL1123(L), TIOL1125
8.3 Feature Description
8.3.1 Wake-Up Detection
The TIOL112(x) may be operated in IO-Link mode or Standard Input / Output (SIO) mode. If the device is in SIO
mode and the IO-link master node wants to initiate communication with the device node, the master drives the
CQ line to the opposite of its present state, and will either sink or source the current (≥500 mA) for the wake-up
duration (typically 80 μs) depending on the CQ logic level as per the IO-Link specification. The TIOL112(x)
detects this as a wake-up condition and communicates to the local microcontroller via the WAKE pin. The IO-
Link communication specification requires the device node to switch to receive mode within 500 μs after
receiving the wake-up signal.
For overcurrent conditions shorter or longer than a valid wake-up pulse, the WAKE pin remains in a high-
impedance (inactive) state. This is illustrated in 图7-5.
If the driver of TIOL112(x) is disabled (EN = L), any change in CQ logic level for duration tWU1 < t < tWU2 is
detected as a wake-up event and WAKE asserts low for the duration of tWUL. This is illustrated in 图 7-6. Please
refer to 表8-4 for the summary of the conditions for Wake-Up detection.
8.3.2 Current Limit Configuration
The output current can be configured with an external resistor on ILIM_ADJ pin. The highest current limit setting
with an external resistor of 10 kΩ provides a minimum of 300 mA over the operating temperature and voltage
range.
Output disable due to current fault and current fault auto recovery features can be disabled by floating ILIM_ADJ
pin. However, the current fault indication is still active in this configuration. This feature is useful when driving
large capacitances.
When ILIM_ADJ pin is shorted to ground, the TIOL112(x) is configured to be in the IO-link master mode. In this
mode, the TIOL112(x) can source or sink minimum of 500 mA to generate a wake-up request. In addition, the
TIOL112(x) enables a small current sink of 5 mA (minimum). The current fault indication, output disable, and
auto recovery features are disabled in this mode.
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表8-1. Current Limit Configuration
CQ Current Limit
(Min.)
NFAULT Indication During
Current Fault
Output Disable and Auto
Recovery
ILIM_ADJ Pin Condition
RSET resistor to L-
Variable
(35 mA to 300 mA)
Yes
Yes
(10 kΩto 110 kΩ)
Connected to L-
500 mA
260 mA
No
No
No
(RSET 0 to 5 kΩ)
OPEN
Yes
8.3.3 Current Fault Detection, Indication and Auto Recovery
If the output current at CQ exceeds the internally-set current limit IO(LIM) for a duration longer than tSC, the
NFAULT pin is driven logic low to indicate a fault condition. The output is turned off, but the LDO continues to
function. The output periodically retries to check if the output is still in the over current condition. In this mode,
the output is switched on for tSC in tSCEN intervals. Current fault auto recovery mode can be disabled by setting
ILIM_ADJ = OPEN. See 表8-5. Toggling EN will clear NFAULT.
8.3.4 Thermal Warning, Thermal Shutdown
If the die temperature exceeds T(WRN), the NFAULT flag is held low indicating a potential over temperature
problem. When the TJ exceeds T(SDN), The output is disabled but the LDO remains operational. As soon as the
temperature drops below the temperature threshold (and after T(HYS)), the internal circuit re-enables the driver,
subject to the state of the EN and TX pins.
8.3.5 Fault Reporting (NFAULT)
NFAULT is driven low if either a current fault condition is detected, die temperature has exceeded T(WRN) or
supply has dropped below the UVLO threshold. NFAULT returns to high-impedance as soon as all three fault
conditions clear.
Receive
Only-Wake
CUR_OK = Z
WAKE = L for tWUL
Driver = OFF
LDO = ON
Receive
Only
CUR_OK = Z
WAKE = Z
Driver = OFF
LDO = ON
Receive and
Transmit
CUR_OK = Z
WAKE = Z
Driver = ON
LDO = ON
Wake
WAKE = L
CUR_OK = Z
Driver = ON
LDO = ON
CQ @ I
LIM
for t
WU1
< t < t
WU2
Thermal
Warning
CUR_OK = Z
TMP_OK = L
WAKE = Z
Current
Fault
WAKE = Z
CUR_OK = L
Driver = OFF
LDO=ON
T > T
WRN
T < TWRN & Current Fault
Driver = EN/EN*
LDO = ON
Thermal
Shutdown
CUR_OK = Z
TMP_OK = L
WAKE = Z
Current
Fault Recovery
WAKE = Z
CUR_OK = L
Driver = ON for tsc
LDO=ON
Driver = OFF
LDO = ON
Note: NFAULT = [CUR_OK && PWR_OK && TMP_OK]
图8-3. Device State Diagram
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8.3.6 Transceiver Function Tables
表8-2. Driver Function
EN
TX
CQ
COMMENT
L / Open
X
L
Hi-Z
H
Device is in ready-to-receive state
H
H
CQ is sourcing current (high-side drive)
CQ is sinking current (low-side drive)
H / Open
L
表8-3. Receiver Function
CQ VOLTAGE
V(CQ) < V(THL)
V(THL) < V(CQ) < V(THH)
V(THH) < V(CQ)
Open
RX
H
?
COMMENT
Normal receive mode, input low
Indeterminate output, may be either high or low
Normal receive mode, input high
L
?
Indeterminate output, may be either high or low
表8-4. Wake-Up Function (tWU1 < t < tWU2
)
EN
TX
CQ CURRENT
WAKE
COMMENT
Asserts low for Device asserts low for tWUL if RX output changes high-
L / Open
X
X
tWUL
L
to-low or low-to-high for tWU1 < t < tWU2
Device receives high-level wake-up request over the
IO-Link bus
H
H
H / Open
L
| I(CQ) | ≥500 mA
| I(CQ) | ≥500 mA
Device receives low-level wake-up request over the
IO-Link bus
L
表8-5. Current Limit Indicator Function (t > tSC
)
EN
TX
CQ CURRENT
| I(CQ) | > IO(LIM)
| I(CQ) | < IO(LIM)
| I(CQ) | > IO(LIM)
| I(CQ) | < IO(LIM)
X
NFAULT
COMMENT
L
Z
L
Z
Z
CQ current exceeds the set limit for over tSC
Normal operation
H
H / Open
CQ current exceeds the set limit for over tSC
Normal operation
H
L
L / Open
X
Driver is disabled, Current limit indicator is inactive
备注
Current limit indicator function is disabled when ILIM_ADJ is connected to GND (or RSET < 5 kΩ
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8.3.7 The Integrated Voltage Regulator (LDO)
The TIOL1123 and TIOL1125 each have an integrated linear voltage regulator (LDO) which can supply power to
external components. The voltage regulator is specified for L+ voltages in the range of 7 V to 36 V with respect
to L-. The LDO is capable of delivering up to 20 mA.
In the DSBGA (YAH) package, TIOL1123L offers pin-configurable LDO output via VSEL pin. When VSEL is
connected to GND, VCC_OUT is configured to provide a 5-V output. When VSEL is left floating, VCC_OUT
provides a 3.3-V output.
表8-6. LDO Output Configuration via VSEL pin (YAH Package)
VSEL pin connection
Connected to L-
Floating
VCC_OUT
5 V
3.3 V
The LDO is designed to be stable with standard ceramic capacitors with values of 1 μF or larger at the output.
X5R- and X7R-type capacitors are best because they have minimal variation in value and ESR over
temperature. Maximum ESR should be less than 1 Ω. With tolerance and dc bias effects, the minimum
capacitance for stability is 1 μF.
The voltage regulator has an internal 35-mA current limit to protect against initial start-up inrush current due to
large decoupling capacitors and accidental short circuit conditions.
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8.3.8 Reverse Polarity Protection
Reverse polarity protection circuitry protects the devices against accidental reverse polarity connections to the
L+, CQ and L- pins. The maximum voltage between any of the pins may not exceed 65 V DC at any time.
图8-4 and 图8-5 shows all the possible connection combinations.
L+
CQ
L-
L+
CQ
L-
DC
DC
TIOL112(x)
TIOL112(x)
TIOL112(x)
TIOL112(x)
RL
RL
Correct
Con gura on
Reverse Polarity Protected
Fault Condi on
L+
CQ
L-
L+
CQ
L-
DC
DC
RL
TIOL112(x)
RL
Reverse Polarity Protected
Fault Condi on
Reverse Polarity Protected
Fault Condi on
L+
CQ
L-
L+
CQ
L-
DC
RL
DC
RL
TIOL112(x)
Reverse Polarity Protected
Fault Condi on
Reverse Polarity Protected
Fault Condi on
图8-4. High-Side Driver Configuration
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L+
CQ
L-
L+
DC
DC
CQ
L-
TIOL112(x)
TIOL112(x)
RL
RL
Correct
Con gura on
Reverse Polarity Protected
Fault Condi on
L+
CQ
L-
L+
CQ
L-
DC
DC
TIOL112(x)
TIOL112(x)
RL
RL
Reverse Polarity Protected
Fault Condi on
Reverse Polarity Protected
Fault Condi on
L+
CQ
L-
L+
CQ
L-
DC
DC
TIOL112(x)
TIOL112(x)
RL
RL
Overcurrent Fault
Protec on Condi on
Reverse Polarity Protected
Fault Condi on
图8-5. Low-Side Driver Configuration
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8.3.9 Integrated Surge Protection and Transient Waveform Tolerance
The L+ and CQ pins of the device are capable of withstanding up to 1.2 kV of 1.2/50 – 8/20 μs IEC 61000-4-5
surge with a source impedance of 500 Ω. The surge testing should be performed with a minimum 100 nF supply
decoupling capacitor between L+ and L-, and 1 µF between VCC_IN/OUT and L-.
External TVS diodes may be required for higher transient protection levels. The system designer should make
sure the maximum clamping voltage of the external diodes is < 65 V at the desired current level. The device is
capable of withstanding up to ±70-V transient pulses < 100 µs.
Combination
wave
R
Generator
EUT
L+
CQ
L-
Decoupling
Network
> 100 nF
1.2/50 –8/20 µs CWG
R = 500 Ω
图8-6. Surge Test Setup
8.3.10 Power Up Sequence (TIOL112)
VCC_IN and L+ domains can be powered up in any sequence. In the event of L+ is powered and VCC_IN is not,
the CQ pin will remain in high impedance.
8.3.11 Undervoltage Lock-Out (UVLO)
The device enters UVLO if the L+ voltage falls below V(UVLO). (For the device without the integrated LDO, the
device monitors VCC_IN in addition to L+. UVLO happens if either supply falls below the threshold.)
As soon as the supply falls below V(UVLO), NFAULT is pulled low, and the driver (CQ) is disabled (Hi-Z). Receiver
performance is not specified in this mode.
When the supply rises above V(UVLO), NFAULT returns to Hi-Z (given no other fault conditions present). The CQ
output is turned on after t(UVLO) delay.
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8.4 Device Functional Modes
These devices can operate in three different modes.
8.4.1 NPN Configuration (N-Switch SIO Mode)
Set TX pin high (or open) and use EN pin as control for realizing the function of an N-switch (low-side
configuration) on CQ.
8.4.2 PNP Configuration (P-Switch SIO Mode)
Set TX pin low and use EN pin as control for realizing the function of a P-switch (high-side configuration) on CQ.
8.4.3 Push-Pull, Communication Mode
Set EN pin high and toggle TX as control for realizing the function of a push-pull output on CQ. 表 8-7, 表 8-8
and 表8-9 summarize the pin configurations to accomplish the functional modes.
表8-7. NPN Mode
EN
L / Open
H
TX
CQ
Hi-Z
H / Open
H / Open
N-Switch
表8-8. PNP Mode
EN
L / Open
H
TX
CQ
Hi-Z
L
L
P-Switch
表8-9. Push-Pull, Communication Mode
EN
TX
CQ
L / Open
X
Hi-Z
H
H
H
N-Switch
P-Switch
L
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
When TIOL112(x) is connected to an IO-Link master through a three-wire interface (图 9-1), the master can
initiate communication and exchange data with a remote node with the TIOL112(x) IO-Link transceiver acting as
a complete physical layer for the communication.
9.2 Typical Application
VCC_OUT
Rev.
Polarity
Protection
VOLTAGE
REGULATOR
L+
0.1 µF
100 V
1 µF
10 V
10 k
ESD and
Surge
RX
Protection
10 k
TX
EN
Sensor
Front-End
Microcontroller
IO-Link Master
PHY
CQ
Rev. Polarity
Protection
DIAGNOSTICS
& CONTROL
WAKE
ESD and
Surge
Protection
NFAULT
CUR_OK
TMP_OK
PWR_OK
L-
ILIM_ADJ
图9-1. Typical Application Schematic
9.2.1 Design Requirements
TIOL112 and TIOL112x IO-Link transceivers can be used to communicate using the IO-Link protocol, or as
standard digital outputs to either sense or drive a wide range of sensors and loads. 表 9-1 shows recommended
components for a typical system design.
表9-1. Design Parameters
PARAMETERS
Design Requirement
TIOL112(x) Specification
Input voltage range (L+)
24 V (typ), 30 V (max)
7 V to 36 V
Choose 250 mA limit with RSET
=
Output current (CQ)
200 mA
5 V
27 kΩ
Choose TIOL1125; VCC_OUT =
5 V
LDO Output voltage
LDO output current
5 mA
I(VCC_OUT): Up to 20 mA
Pull-up resistors for NFAULT and
WAKE
10 kΩ
10 kΩ
L+ decoupling capacitor
LDO output capacitor
0.1 µF / 100 V
1 µF / 10 V
0.1 µF / 100 V
1 µF / 10 V
TIOL112 can support up to TA of
125 °C if TJ < T(SDN)
Maximum Ambient Temperature,
TA
105 °C
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English Data Sheet: SLLSFJ1
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9.2.2 Detailed Design Procedure
9.2.2.1 Maximum Junction Temperature Check
For a 200 mA current limit:
• Choose driver output current limit, IO(LIM) = 250 mA (allowing for current limit tolerance); RSET = 27 kΩ
• The maximum voltage drop across the high-side switch at 250 mA current is VDS(ON) = 1.1 V.
This causes a power consumption of:
PD = V
× I = 1.1 V × 250 mA = 275 mW
O LIM
(1)
(2)
(3)
OP
DS ON
For a 5 mA LDO current output,
PD
= V
− V
× I
= 30 − 5 V × 5 mA = 125 mW
LDO
L +
VCC
OUT
VCC_OUT
Total power dissipation,
PD = PD
+ PD = 275 mW + 125 mW = 400 mW
OP
LDO
Multiply this value with the Junction-to-ambient thermal resistance of θJA = 45.9 °C/W (taken from the Thermal
Information table table) to receive the difference between junction temperature, TJ, and ambient temperature, TA:
℃
∆ T = T − T = PD × θ = 400 mW × 45.9
= 18.36 ℃
(4)
W
J
A
JA
Add this value to the maximum ambient temperature of TA = 105°C to receive the final junction temperature:
℃
T = T + ∆ T = T + PD × θ = 105 ℃ + 400 mW × 45.9
= 105 ℃ + 18.36 ℃ = 123.36 ℃
(5)
W
J
A
A
JA
As long as TJ is below the recommended maximum value of 150°C, no thermal shutdown will occur. However,
the junction temperature is closer to TWRN and thermal warning may be generated if the junction temperature
rises above TWRN.
Note that the modeling of the complete system may be necessary to predict junction temperature in smaller
PCBs and/or enclosures without air flow.
9.2.2.2 Driving Capacitive Loads
These devices are capable of driving capacitive loads on the CQ output. Assuming a pure capacitive load
without series/parallel resistance, the maximum capacitance that can be charged without triggering current fault
can be calculated as:
[I
x t
]
SC
O LIM
(
)
C
=
LOAD
V
L+
(
)
(6)
To drive higher capacitive loads and avoid overcurrent condition disabling the driver, it is recommended leave
ILIM_ADJ pin floating. With ILIM_ADJ floating, TIOL112(x) indicates overcurrent fault without blanking time delay
(tSC) but does not disable the driver. Another approach is to drive high capacitive loads with a series resistor
between the CQ output and the load to avoid overcurrent condition. Capacitive loads can be connected to L- or
L+.
9.2.2.3 Driving Inductive Loads
The TIOL112(x) family is capable of magnetizing and demagnetizing large inductive loads. These devices
contain internal circuitry that enables fast and safe demagnetization when configured as either P-switch or N-
switch mode.
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In P-switch configuration, the load inductor L is magnetized when the CQ output is driven high. When the PNP is
turned off, there is a significant amount of negative inductive kick back at the CQ pin. This voltage is safely
clamped internally at about -15 V.
Similarly, in N-switch configuration, the load inductor L is magnetized when the CQ output is driven low. When
the NPN is turned off, there is a significant amount of positive inductive kick back at the CQ pin. This voltage is
safely clamped internally at about 15 V.
The equivalent protection circuits are shown in 图9-2 and 图9-3. The minimum value of the resistive load R can
be calculated as:
V
L+
(
)
R =
I
O(LIM)
(7)
Rev.
Polarity
Rev.
Polarity
L+
L+
Protection
Protection
ESD and
Surge
ESD and
Surge
R
Protection
Protection
CQ
CQ
Rev. Polarity
Protection
Rev. Polarity
Protection
L
L
ESD and
Surge
ESD and
Surge
R
Protection
Protection
L-
L-
图9-2. P-Switch Mode
图9-3. N-Switch Mode
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9.2.3 Application Curves
Time 10 ms/div
Time 10 ms/div
图9-4. CQ in Current Fault Auto Recovery, Low
图9-5. CQ in Current Fault Auto Recovery, High
Side Mode
Side Mode
L+ = 36 V L = 1.5 H RL =
TA = 25 °C
L+ = 36 V
L=1.5 H RL =
TA = 25 °C
RSET = 10 kΩ
RSET = 10 kΩ
360 Ω
360 Ω
图9-6. CQ Driving Inductive Load, Low Side Mode 图9-7. CQ Driving Inductive Load, High Side Mode
(NPN mode) (PNP mode)
NFAULT is indicated for the duration of charging and discharging of the capacitor but driver is not disabled when ILIM_ADJ is floating
L+ = 24 V TA = 25 °C
CL = 20 µF RL = 100 Ω
RSET = 1 MΩ(ILIM_ADJ Floating)
图9-8. CQ Driving Capacitive Load, Push-Pull Mode
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9.3 Power Supply Recommendations
The TIOL112 and TIOL112x transceivers are designed to operate from a 24-V nominal supply at L+, which can
vary by +12 V and -17 V from the nominal value to remain within the device recommended supply voltage range
of 7 V to 36 V. This supply should be buffered with at least a 100-nF/100-V capacitor.
9.4 Layout
9.4.1 Layout Guidelines
• Use of a 4-layer board is recommended for good heat conduction. Use layer 1 (top layer) for control signals,
layer 2 as power ground layer for L-, layer 3 for the 24-V supply plane (L+), and layer 4 for the regulated
output supply (VCC_IN/OUT).
• Connect the thermal pad to L- with maximum amount of thermal vias for best thermal performance.
• Use entire planes for L+, VCC_IN/OUT and L- to assure minimum inductance.
• The L+ terminal must be decoupled to ground with a low-ESR ceramic decoupling capacitor. The
recommended minimum capacitor value is 100 nF. The capacitor must have a voltage rating of 50 V minimum
(100 V depending on max sensor supply fault rating) and an X5R or X7R dielectric.
• The optimum placement of the capacitor is closest to the transceiver’s L+ and L- terminals to reduce supply
drops during large supply current loads. See 图9-9 for a PCB layout example.
• Connect all open-drain control outputs via 10 kΩpull-up resistors to the VCC_IN/OUT plane to provide a
defined voltage potential to the system controller inputs when the outputs are high-impedance.
• Connect the RSET resistor between ILIM_ADJ and L-.
• Decouple the regulated output voltage at VCC_IN/OUT to ground with a low-ESR, ≥1-μF, ceramic
decoupling capacitor. The capacitor should have a voltage rating of 10 V minimum and an X5R or X7R
dielectric.
9.4.2 Layout Example
VIA to Layer 2: Power Ground Plane (L-)
VIA to Layer 3: 24V Supply Plane (L+)
VIA to Layer 4: Regulated Supply Plane (VCC_IN/OUT)
WAKE
1uF/10V
V
C
C
_
100nF/
50V
I
N
/
O
U
T
NFAULT
L+
CQ
L-
L+
CQ
L-
RX
TX
EN
Use Multiple Vias
for L+ and L-
Exposed Thermal
Pad Area
RSET
图9-9. Layout Example
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10 Device and Documentation Support
10.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.4 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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English Data Sheet: SLLSFJ1
TIOL112, TIOL1123, TIOL1125
ZHCSLJ5D –FEBRUARY 2022 –REVISED MARCH 2023
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PACKAGE OUTLINE
YAH0012-C01
DSBGA - 0.4 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
A
B
E
BALL A1
CORNER
D
C
0.4 MAX
SEATING PLANE
0.05 C
0.17
0.11
1
TYP
SYMM
D
C
SYMM
1.5
TYP
D: Max = 2.47 mm, Min = 2.43 mm
E: Max = 1.72 mm, Min = 1.68 mm
B
A
0.5
TYP
0.25
12X
2
1
3
0.21
0.015
C A B
0.5 TYP
4227086/A 09/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
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Copyright © 2023 Texas Instruments Incorporated
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EXAMPLE BOARD LAYOUT
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
12X ( 0.23)
1
2
3
A
(0.5) TYP
B
C
SYMM
D
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 30X
0.05 MIN
0.05 MAX
METAL UNDER
SOLDER MASK
( 0.23)
METAL
(
0.23)
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4227086/A 09/2021
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
See Texas Instruments Literature No. SNVA009 (www.ti.com/lit/snva009).
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TIOL112, TIOL1123, TIOL1125
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EXAMPLE STENCIL DESIGN
YAH0012-C01
DSBGA - 0.4 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
(R0.05) TYP
12X ( 0.25)
1
2
3
A
(0.5) TYP
B
C
SYMM
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.075 mm THICK STENCIL
SCALE: 30X
4227086/A 09/2021
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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PACKAGE OPTION ADDENDUM
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9-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TIOL1123DRCR
TIOL1123LYAHR
TIOL1125DRCR
TIOL112DRCR
TIOL112YAHR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000 RoHS & Green
1500 RoHS & Green
5000 RoHS & Green
5000 RoHS & Green
1500 RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
1123
Samples
Samples
Samples
Samples
Samples
SNAGCU
NIPDAU
NIPDAU
SNAGCU
T1123L
1125
VSON
112
DSBGA
TL112
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2023
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TIOL1123DRCR
TIOL1123LYAHR
TIOL1125DRCR
TIOL112DRCR
TIOL112YAHR
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000
1500
5000
5000
1500
330.0
180.0
330.0
330.0
180.0
12.4
8.4
3.3
1.88
3.3
3.3
2.63
3.3
1.1
0.53
1.1
8.0
4.0
8.0
8.0
4.0
12.0
8.0
Q2
Q1
Q2
Q2
Q1
12.4
12.4
8.4
12.0
12.0
8.0
VSON
3.3
3.3
1.1
DSBGA
1.88
2.63
0.53
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Jun-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TIOL1123DRCR
TIOL1123LYAHR
TIOL1125DRCR
TIOL112DRCR
TIOL112YAHR
VSON
DSBGA
VSON
DRC
YAH
DRC
DRC
YAH
10
12
10
10
12
5000
1500
5000
5000
1500
367.0
182.0
367.0
367.0
182.0
367.0
182.0
367.0
367.0
182.0
35.0
20.0
35.0
35.0
20.0
VSON
DSBGA
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DRC 10
3 x 3, 0.5 mm pitch
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226193/A
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PACKAGE OUTLINE
DRC0010V
VSON - 1 mm max height
SCALE 4.000
PLASTIC SMALL OUTLINE - NO LEAD
3.1
2.9
B
A
3.1
2.9
PIN 1 INDEX AREA
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.75
1.55
2X (0.5)
(0.2) TYP
EXPOSED
THERMAL PAD
4X (0.25)
5
6
2X
2
11
SYMM
2.4
2.2
10
1
8X 0.5
0.3
0.2
10X
SYMM
10X
PIN 1 ID
0.1
C A B
C
(OPTIONAL)
0.05
0.5
0.3
4226575/A 02/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(1.65)
(0.5)
10X (0.6)
1
10
10X (0.24)
SYMM
11
(3.4)
(2.3)
(0.9)
8X (0.5)
6
5
(R0.05) TYP
(0.2) TYP
VIA
(0.25)
(0.575)
SYMM
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226575/A 02/2021
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
DRC0010V
VSON - 1 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2X (1.51)
(0.5)
SYMM
EXPOSED METAL
TYP
10X (0.6)
1
10
(1.53)
2X
(1.02)
10X (0.24)
11
SYMM
(0.61)
8X (0.5)
6
5
(R0.05) TYP
4X (0.34)
4X (0.25)
(2.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 11:
80% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226575/A 02/2021
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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