TL16C452FNG4_技术文档

TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

Integrates Most Communications Card

Functions From the IBM PC/AT or

Compatibles With Single- or Dual-Channel

Serial Ports

Fully Programmable Serial Interface

Characteristics:

– 5-, 6-, 7-, or 8-Bit Characters

– Even-, Odd-, or No-Parity Bit Generation

and Detection

– 1-, 1 1/2-, or 2 Stop-Bit Generation

– Programmable Baud Rate

(dc to 256 kbit/s)

TL16C451 Consists of One TL16C450 Plus

Centronix Printer Interface

TL16C452 Consists of Two TL16C450s Plus

a Centronix-Type Printer Interface

Fully Double Buffered for Reliable

Asynchronous Operation

description

The TL16C451 and TL16C452 provide single- and dual-channel (respectively) serial interfaces along with a

singleCentronix-typeparallel-portinterface. Theserialinterfacesprovideaserial-to-parallelconversionfordata

received from a peripheral device or modem and a parallel-to-serial conversion for data transmitted by a CPU.

The parallel interface provides a bidirectional parallel data port that fully conforms to the requirements for a

Centronix-type printer interface. A CPU can read the status of the asynchronous communications element

(ACE) interfaces at any point in the operation. The status includes the state of the modem signals (CTS, DSR,

RLSD, and RI) and any changes to these signals that have occurred since the last time they were read, the state

of the transmitter and receiver including errors detected on received data, and printer status. The TL16C451

and TL16C452 provide control for modem signals (RTS and DTR), interrupt enables, baud rate programming,

and parallel-port control signals.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IBM PC/AT is a trademark of International Business Machines Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

1

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

TL16C451 . . . FN PACKAGE

(TOP VIEW)

9

8

7

6

5

4 3 2 1 68 67 66 65 64 63 62 61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

NC 10

NC 11

NC

INT2

SLIN

INIT

AFD

STB

GND

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

INT0

BDO

NC 12

GND 13

DB0 14

DB1 15

DB2 16

DB3 17

DB4 18

DB5 19

DB6 20

DB7 21

GND 22

V

23

CC

RTS0 24

DTR0 25

SOUT0 26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

NC – No internal connection

2

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

TL16C452 . . . FN PACKAGE

(TOP VIEW)

9

8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

SOUT1 10

DTR1 11

RTS1 12

CTS1 13

DB0 14

DB1 15

DB2 16

DB3 17

DB4 18

DB5 19

DB6 20

DB7 21

GND 22

INT1

INT2

SLIN

INIT

AFD

STB

GND

PD0

PD1

PD2

PD3

PD4

PD5

PD6

PD7

INT0

BDO

V

23

CC

RTS0 24

DTR0 25

SOUT0 26

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

3

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

TL16C451 functional block diagram

TL16C451

28

31

29

30

41

32

24

25

26

45

CTS0

DSR0

RLSD0

RI0

RTS0

DTR0

SOUT0

INT0

ACE

1

SIN0

CS0

14 – 21

8

DB0–DB7

8

35 – 33

3

A0–A2

IOW

36

37

39

4

Select

and

Control

Logic

44

IOR

BDO

RESET

CLK

8

63

65

66

67

68

1

53 – 46

8

Parallel

Port

Parallel

Port

PD0–PD7

INIT

ERROR

SLCT

BUSY

PE

57

56

55

58

59

AFD

STB

SLIN

ACK

INT2

LPTOE

CS2

38

TL16C452 functional block diagram

TL16C452

28

24

25

26

45

ACE

1

CTS0

DSR0

RLSD0

RI0

RTS0

DTR0

SOUT0

INT0

31

29

30

41

32

SIN0

CS0

14 – 21

8

DB0–DB7

8

ACE

2

13

12

11

10

60

RTS1

DTR1

SOUT1

INT1

CTS1

DSR1

RLSD1

RI1

5

8

6

62

3

SIN1

CS1

3

35 – 33

A0–A2

IOW

36

37

39

4

Select

and

Control

Logic

8

IOR

44

BDO

RESET

CLK

53 – 46

8

PD0–PD7

INIT

63

65

66

67

68

1

57

56

55

58

59

ERROR

SLCT

BUSY

PE

Parallel

Port

AFD

STB

SLIN

ACK

INT2

LPTOE

CS2

38

4

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

Terminal Functions

TERMINAL

I/O

DESCRIPTION

†

NAME

NO.

A0

A1

A2

35

34

33

Register select. A0, A1, and A2 are used during read and write operations to select the register to read

from or write to. Refer to Table 1 for register addresses, also refer to the chip select signals (CS0, CS1,

CS2).

I

68

56

44

66

4

I

I/O

O

I

ACK

AFD

BDO

BUSY

CLK

Printer acknowledge. ACK goes low to indicate that a successful data transfer has taken place. It

generates a printer port interrupt during its positive transition.

Printer autofeed. AFD is an open-drain line that provides the printer with a low signal when

continuous-form paper is to be autofed to the printer. An internal pullup is provided.

Bus buffer output. BDO is active (high) when the CPU is reading data. When active, this output can

disable an external transceiver.

Printer busy. BUSY is an input line from the printer that goes high when the printer is not ready to accept

data.

I/O

I

External clock. CLK connects the ACE to the main timing reference.

32

3

38

CS0

CS1 [V

CS2

Chip selects. Each chip select enables read and write operations to its respective channel. CS0 and

CS1 select serial channels 0 and 1, respectively, and CS2 selects the parallel port.

]

CC

28

13

I

CTS0

Clear to send. CTSx is an active-low modem status signal. Its state can be checked by reading bit 4

(CTS) of the modem status register. Bit 0 (DCTS) of the modem status register indicates that this signal

has changed states since the last read from the modem status register. If the modem status interrupt

is enabled when CTSx changes state, an interrupt is generated.

CTS1 [GND]

DB0 – DB7

14 – 21

I/O

I

Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information

between the TL16C451/TL16C452 and the CPU. DB0 is the least significant bit (LSB).

31

5

DSR0

DSR1 [GND]

Data set ready. DSRx is an active-low modem status signal. Its state can be checked by reading

bit 5 (DSR) of the modem status register. Bit 1 (DDSR) of the modem status register indicates that this

signal has changed states since the last read from the modem status register. If the modem status

interrupt is enabled when the DSRx changes state, an interrupt is generated.

25

11

O

DTR0

DTR1 [NC]

Data terminal ready. DTRx, when active (low), informs a modem or data set that the ACE is ready to

establishcommunication. DTRx is placed in the active state by setting the DTR bit of the modem control

register. DTRx is placed in the inactive state either as a result of a reset or during loop mode operation

or clearing bit 0 (DTR) of the modem control register.

ERROR

INIT

63

57

I

Printer error. ERROR is an input line from the printer. The printer reports an error by holding this line

low during the error condition.

Printer initialize. INIT is an open-drain line that provides the printer with a signal that allows the printer

initialization routine to be started. An internal pullup is provided.

I/O

O

INT0

INT1 [NC]

45

60

Interrupt. INTx is an active-high 3-state output that is enabled by bit 3 of the MCR. When active, INTx

informs the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt

to be issued are: a receiver error, received data is available, the transmitter holding register is empty,

and an enabled modem status interrupt. The INTx output is reset (low) either when the interrupt is

serviced or as a result of a reset.

INT2

IOR

59

37

36

1

O

I

Printer port interrupt. INT2 is an active-high 3-state output generated by the positive transition of ACK.

It is enabled by bit 4 of the write control register.

Data read strobe. When IOR input is active (low) while the ACE is selected, the CPU is allowed to read

status information or data from a selected ACE register.

I

IOW

Data write strobe. When IOW input is active (low) while the ACE is selected, the CPU is allowed to write

control words or data into a selected ACE register.

I

LPTOE

Parallel data output enable. When low, LPTOE enables the write data register to the PD0–PD7 lines.

A high puts the PD0–PD7 lines in the high-impedance state allowing them to be used as inputs. LPTOE

is usually tied low for printer operation.

†

Names shown in brackets are for the TL16C451.

5

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

Terminal Functions (continued)

TERMINAL

I/O

DESCRIPTION

†

NAME

NO.

PD0–PD7

53–46

I/O

Parallel data bits (0–7). These eight lines provide a byte-wide input or output port to the system. The

eight lines are held in a high-impedance state when LPTOE is high.

PE

67

39

I

Printer paper empty. This is an input line from the printer that goes high when the printer runs out of

paper.

RESET

Reset. When active (low), RESET clears most ACE registers and sets the state of various output

signals. Refer to Table 2.

30

6

RI0

RI1 [GND]

Ring indicator. RIx is an active-low modem status signal. Its state can be checked by reading bit 6 (RI)

of the modem status register. Bit 2 (TERI) of the modem status register indicates that the RIx input has

transitioned from a low to a high state since the last read from the modem status register. If the modem

status interrupt is enabled when this transition occurs, an interrupt is generated.

29

8

I

RLSD0

RLSD1 [GND]

Receive line signal detect. RLSDx is an active-low modem status signal. Its state can be checked by

reading bit 7 of the modem status register. Bit 3 (DRLSD) of the modem status register indicates that

this signal has changed states since the last read from the modem status register. If the modem status

interrupt is enabled when RLSDx changes state, an interrupt is generated. This bit is low when a data

carrier is detected.

24

12

O

I

RTS0

RTS1 [NC]

Request to send. When active (low), RTSx informs the modem or data set that the ACE is ready to

transmit data. RTSx is set to its active state by setting the RTS modem control register bit and is set

to its inactive (high) state either as a result of a reset or during loop mode operations or by clearing bit

1 (RTS) of the modem control register.

SIN0

SIN1 [GND]

41

62

Serial input. SINx is a serial data input from a connected communications device.

SLCT

SLIN

65

58

I

Printerselected.SLCTisaninputlinefromtheprinterthatgoeshighwhentheprinterhasbeenselected.

I/O

Printerselect. SLIN is an open-drain line that selects the printer when it is active (low). An internal pullup

is provided on this line.

SOUT0

SOUT1 [NC]

26

10

I

Serial output. SOUTx is a composite serial data output to a connected communication device. SOUTx

is set during a reset.

55

I/O

STB

Printer strobe. STB is an open-drain line that provides communication synchronization between the

TL16C451/TL16C452and the printer. When it is active (low), it provides the printer with a signal to latch

the data currently on the parallel port. An internal pullup is provided on this line.

V

CC

23,40,

64

5-V supply voltage

GND

2,7,9

Supply common

22,27,42,

43,54,61

†

Names shown in brackets are for the TL16C451.

6

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

(see Note 1 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

CC

Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

I

Output voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V

O

Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1100 mW

Operating free-air temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

A

Storage temperature range, T

Case temperature for 10 seconds, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C

stg

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM

MAX

UNIT

V

Supply voltage, V

CC

High-level Input voltage, V

IH

Low-level Input voltage, V

IL

4.75

2

5

5.25

V

CC

0.8

V

–0.5

0

V

Operating free-air temperature, T

70

°C

A

electrical characteristics over recommended ranges of supply voltage and operating free-air

temperature (unless otherwise noted)

†

TYP

PARAMETER

TEST CONDITIONS

= –0.4 mA on DB0–DB7

MIN

MAX

UNIT

I

OH

OL

= –2 mA to 4 mA on PD0–PD7

V

High-level output voltage

2.4

V

OH

OL

= –0.2 mA on INIT,

AFD, STB, and SLIN

= –0.2 mA on all other outputs

= 4 mA on DB0–DB7

= 12 mA on PD0–PD7

= 10 mA on INIT,

V

Low-level output voltage

0.4

V

AFD, STB, and SLIN (see Note 2)

I

= 2 mA on all other outputs

OL

V

= 5.25 V,

V

= 0,

CC

V = 0 to 5.25 V,

SS

All other terminals floating

I

Input leakage current

±10

±20

µA

Ikg

I

V

= 5.25 V,

V

SS

= 0,

CC

= 0 to 5.25 V,

O

High-impedance output current

oz

Chip selected and in write mode, or chip deselected

V

= 5.25 V, = 0,

V

SS

CC

SIN, DSR, RLSD, CTS, and RI at 2 V,

I

Supply current

10

mA

CC

All other inputs at 0.8 V, XTAL1 at 4 MHz,

No load on outputs,

Baud rate = 50 kbit/s

†

All typical values are at V

= 5 V, T = 25°C.

A

CC

NOTE 2: INIT, AFD, STB, and SLIN are open-collector output terminals that each have an internal pullup to V . This generates a maximum of

CC

per terminal. In addition to this internal current, each terminal sinks at least 10 mA while maintaining the V

2 mA of internal I

OL

specification of 0.4 V maximum.

OL

system timing requirements over recommended ranges of supply voltage and operating free-air

temperature

PARAMETER

FIGURE

MIN

MAX

UNIT

t

Cycle time, read (t

+ t + t

w7 d8 d9

)

175

ns

cR

7

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

t

Cycle time, write (t

+ t + t

)

175

50

ns

cW

w1

w2

w5

w6

wRST

su1

su2

su3

h1

w6 d5 d6

Pulse duration, clock↑

Pulse duration, clock↓

1

2

3

50

Pulse duration, write strobe (IOW)↑

80

Pulse duration, read strobe (IOR)↓

80

Pulse duration, reset

1000

15

Setup time, address (A0 – A2) valid before IOW↓

Setup time, chip select (CSx) valid before IOW↓

Setup time, data (D0 – D7) valid before IOW↑

Hold time, address (A0 – A2) valid after IOW↑

Hold time, chip select (CSx) valid after IOW↑

Hold time, data (D0 – D7) valid before IOW↑

Delay time, write cycle (IOW)↑ to IOW↓

Delay time, read cycle (IOR)↑ to IOR↓

2,3

2

15

2,3

2

20

h2

15

h3

2

80

d3

3

80

d4

system switching characteristics over recommended ranges of supply voltage and operating

free-air temperature

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

60

UNIT

ns

t

Delay time, data (D0 – D7) valid before read (IOR)↑

Delay time, floating data (D0 – D7) valid after read (IOR)↑

Read to driver disable, IOR↓ to BD0↓

3

C

= 100 pF

d5

L

0

60

ns

d6

60

ns

dis(R)

receiver switching characteristics over recommended ranges of supply voltage and operating

free-air temperature

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

t

d7

t

d8

t

d9

Delay time, RCLK↑ to sample clock↑

4

100

ns

RCLK

cycles

4

1

Delay time, stop (sample clock)↑ to set interrupt (INTRPT)↑

Delay time, read RBR/LSR (IOR)↑ to reset interrupt (INTRPT)↓

C

= 100 pF

140

ns

L

transmitter switching characteristics over recommended ranges of supply voltage and operating

free-air temperature

PARAMETER

FIGURE

TEST CONDITIONS

MIN

MAX

UNIT

baudout

cycles

t

5

8

24

Delay time, initial write THR (IOW)↑ to transmit start (SOUT)↓

d10

baudout

cycles

t

5

8

140

32

Delay time, stop (SOUT) low to interrupt (INTRPT)↑

d11

d12

d13

d14

Delay time, write THR (IOW)↓ to reset interrupt (INTRPT) low

C

= 100 pF

ns

L

baudout

cycles

16

Delay time, initial write (IOW)↑ to THRE interrupt (INTRPT)↑

Delay time, read IIR (IOR)↑ to reset THRE interrupt (INTRPT) low

140

ns

modem control switching characteristics over recommended ranges of supply voltage and

operating free-air temperature

PARAMETER

FIGURE

TEST CONDITIONS

= 100 pF

MIN

MAX

UNIT

t

Delay time, write MCR (IOW)↑ to output (RTS, DTS)↓↑

6

C

100

ns

d15

L

8

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

Delay time, modem input (CTS, DSR, RLSD)↑ to set interrupt

(INTRPT) high

t

6

C

= 100 pF

170

140

ns

d16

L

Delay time, read MSR (IOR)↑ to reset interrupt (INTRPT) low

d17

parallel port switching characteristics over recommended ranges of supply voltage and operating

free-air temperature

PARAMETER

FIGURE TEST CONDITIONS

MIN

MAX

UNIT

Delay time, write parallel port control (SLIN, AFD, STB, INIT)↓↑ to

output (IOW) high

t

7

C

= 100 pF

60

ns

d18

L

t

Delay time, write parallel port data (P0 – P7)↓↑ to output (IOW) high

Delay time, output enable to data, PD0 – PD7 valid after LPTOE↓

Delay time, ACK↓↑ to INT2↓↑

7

C

= 100 pF

60

ns

d19

d20

d21

L

100

PARAMETER MEASUREMENT INFORMATION

t

w1

2 V

CLK

(9 MHz Max)

0.8 V

t

w2

N

CLK

BAUDOUT

(1/1)

(see Note A)

BAUDOUT

(1/2)

BAUDOUT

(1/3)

BAUDOUT

(1/N)

(N>3)

2 Clock

Cycles

(N-2) Clock

Cycles

NOTE A: BAUDOUT is an internally generated signal used in the receiver and transmitter circuits to synchronize data.

Figure 1. Baud Generator Timing Waveforms

9

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

90%

10%

Valid

A0–A2

10%

90%

10%

CS0, CS1, CS2

Valid

10%

t

h2

t

w5

t

h1

t

su2

t

su1

t

d3

IOW

90%

10%

t

h3

su3

90%

D0–D7

Valid Data

Figure 2. Write Cycle Timing Waveforms

90%

A0 – A2

Valid

10%

90%

CS0, CS1, CS2

Valid

t

10%

t

10%

h2

t

w6

t

su2

h1

t

d4

su1

IOR

90%

10%

dis(R)

10%

t

dis(R)

BDO

10%

t

d6

t

d5

90%

D0 – D7

Valid Data

Figure 3. Read Cycle Timing Waveforms

10

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

RCLK

(internal signal only

same as BAUDOUT)

t

8 CLKs

d7

Sample Clock

(internal signal only)

SIN

Start

Data Bits 5–8

Parity

Stop

Sample

Clock

t

d8

INTRPT

90%

(RDR/LSI)

10%

t

d9

IOR

(RD RBR/LSR)

10%

Figure 4. Receiver Timing Waveforms

SOUT

Start

Data Bits 5–8

Parity

Stop

Start

90%

50%

10%

t

d10

t

d11

90%

INTRPT

(THRE)

50%

10%

t

d13

t

d12

IOW (WR THR)

10%

t

d14

IOR (RD IIR)

10%

Figure 5. Transmitter Timing Waveforms

11

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

PARAMETER MEASUREMENT INFORMATION

90%

IOW (WR MCR)

RTS, DTR

t

d15

t

d15

90%

CTS, DSR, RLSD

10%

t

d16

90%

INTRPT

(MODEM)

50%

t

d17

IOR (RD MSR)

10%

t

d16

RI

50%

Figure 6. Modem Control Timing Waveforms

IOW

50%

t

d18

90%

10%

SLIN, AFD,

STB, INIT

t

d19

90%

10%

50%

PD0 – PD7

LPTOE

t

d20

10%

90%

ACK

INT2

10%

t

d21

90%

10%

Figure 7. Parallel Port Timing Waveforms

12

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TL16C451, TL16C452

ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

APPLICATION INFORMATION

Data Bus

Address Bus

Control Bus

Serial

Channel 0

Buffers

9-Pin

D

Conn

ACE and

Printer

Port

25-Pin

D

Conn

Parallel

Port

R/C Net

Option

Jumpers

Figure 8. Basic TL16C451 Test Configuration

Serial

9-Pin

D

Conn

Data Bus

Dual

Channel 0

ACE and

Buffers

Printer

Port

Address Bus

Control Bus

Serial

Channel 1

Buffers

9-Pin

D

Conn

25-Pin

D

Conn

Parallel

Port

R/C Net

Option

Jumpers

Figure 9. Basic TL16C452 Test Configuration

13

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ASYNCHRONOUS COMMUNICATIONS ELEMENTS

SLLS053C – MAY 1989 – REVISED AUGUST 1999

PRINCIPLES OF OPERATION

Table 1. Register Selection

†

DLAB

A2

L

A1

L

A0

L

REGISTER

0

Receiver buffer (read), transmitter holding register (write)

Interrupt enable register

Interrupt identification register (read only)

Line control register

L

H

L

X

1

L

H

L

H

L

H

L

Modem control register

L

H

L

Line status register

H

L

Modem status register

H

L

Scratch register

Divisor latch (LSB)

1

L

H

Divisor latch (MSB)

†

The divisor latch access bit (DLAB) is the most significant bit of the line control register. The DLAB

signal is controlled by writing to this bit location (see Table 3).

Table 2. ACE Reset Functions

RESET

CONTROL

REGISTER/SIGNAL

RESET STATE

Interrupt enable register

RESET

All bits cleared (0–3 forced and 4–7 permanent)

Bit 0 is set, bits 1 and 2 are cleared, and bits 3–7

are permanently cleared

Interrupt identification register

RESET

Line control register

Modem control register

Line status register

RESET

All bits cleared

Bits 5 and 6 are set, all other bits are cleared

Bits 0–3 are cleared, bits 4–7 are input signals

High

Modem status register

SOUT

INTRPT (receiver error flag)

INTRPT (received data available)

Read LSR/RESET Low

Read RBR/RESET Low

Read IIR/Write

Low

INTRPT (transmitter holding register empty)

THR/RESET

INTRPT (modem status changes)

OUT2 (interrupt enable)

RTS

Read MSR/RESET Low

RESET

High

DTR

High

OUT1

High

Scratch register

No effect

Divisor latch (LSB and MSB) registers

Receiver buffer registers

Transmitter holding registers

14

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PRINCIPLES OF OPERATION

accessible registers

The system programmer, using the CPU, has access to and control over any of the ACE registers that are

summarized in Table 3. These registers control ACE operations, receive data, and transmit data. Descriptions

of these registers are given in Table 3.

Table 3. Summary of Accessible Registers

REGISTER ADDRESS

O DLAB = 0 O DLAB = 0 1 DLAB = 0

2

3

4

5

6

7

O DLAB = 1 1 DLAB = 1

Receiver

Buffer

Register

(Read

Transmitter

Holding

Register

(Write

Interrupt

Ident.

Register

(Read

Bit

No.

Interrupt

Enable

Register

Line

Control

Register

Modem

Control

Register Register

Line

Status

Modem

Status

Register

Divisor

Latch

Scratch

Register

Latch

(MSB)

(LSB)

Only)

RBR

THR

IER

IIR

LCR

MCR

LSR

MSR

SCR

DLL

DLM

Enable

Received

Data

Available

Interrupt

(ERBF)

Word

Length

Select

Bit 0

Data

Terminal

Ready

(DTR)

Delta

Clear

to Send

(DCTS)

“0” If

Interrupt

Pending

Data

Ready

(DR)

†

0

1

Data Bit 0

Bit 0

Bit 8

Data Bit 0

(WLSO)

Enable

Transmitter

Holding

Register

Empty

Word

Length

Select

Bit 1

Delta

Data

Set

Ready

(DDSR)

Interrupt

ID

Bit (0)

Request

to Send

(RTS)

Overrun

Error

(OE)

Data Bit 1

Bit 1

Bit 9

(WLS1)

Interrupt

(ETBE)

Enable

Receiver

Line Status

Interrupt

(ELSI)

Trailing

EdgeRing

Indicator

(TERI)

Interrupt Number of

Parity

Error

(PE)

2

3

Data Bit 2

Data Bit 3

Data Bit 2

Data Bit 3

Out 1

Bit 2

Bit 3

Bit 2

Bit 3

Bit 10

Bit 11

ID

Bit (1)

Stop Bits

(STB)

Delta

Receive

Line

Signal

Detect

(DRLSD)

Enable

Modem

Status

Interrupt

(EDSSI)

Parity

Enable

(PEN)

Out 2

(Interrupt

Enable)

Framing

Error

(FE)

0

Even

Parity

Select

(EPS)

Clear

to

Send

(CTS)

Break

Interrupt

(BI)

4

5

6

7

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

0

Loop

Bit 4

Bit 5

Bit 6

Bit 7

Bit 4

Bit 5

Bit 6

Bit 7

Bit 12

Bit 13

Bit 14

Bit 15

Transmit-

ter

Holding

Register

(THRE)

Data

Set

Ready

(DSR)

Stick

Parity

0

Transmit-

ter

Empty

Ring

Indicator

(RI)

Set

Break

(TEMT)

Divisor

Latch

Access

Bit

Receive

Line

Signal

Detect

(RLSD)

0

(DLAB)

†

Bit 0 is the least significant bit. It is the first bit serially transmitted or received.

15

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PRINCIPLES OF OPERATION

interrupt control logic

The interrupt control logic is shown in Figure 10.

DR (LSR Bit 0)

ERBFI (IER Bit 0)

THRE (LSR bit 5)

ETBEI (IER Bit 1)

OE (LSR bit 1)

PE (LSR Bit 2)

Interrupt

Output

FE (LSR bit 3)

BI (LSR Bit 4)

ELSI (IER Bit 1)

DCTS (MSR Bit 0)

DDSR (MSR Bit 1)

TERI (MSR Bit 2)

DRLSD (MSR Bit 3)

EDSSI (IER Bit 3)

INTERRUPT ENABLE (MCR Bit 3)

Figure 10. Interrupt Control Logic

interrupt enable register (IER)

The IER enables each of the four types of interrupts (refer to Table 4) and the INTRPT output signal in response

to an interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The

contents of this register are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit, when set, enables the received data available interrupt.

Bit 1: This bit, when set, enables the THRE interrupt.

Bit 2: This bit, when set, enables the receiver line status interrupt.

Bit 3: This bit, when set, enables the modem status interrupt.

Bits 4 thru 7: These bits in the IER are not used and are always cleared.

16

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PRINCIPLES OF OPERATION

interrupt identification register (IIR)

The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with

most microprocessors.

The ACE provides four prioritized levels of interrupts:

Priority 1 – Receiver line status (highest priority)

Priority 2 – Receiver data ready or receiver character time out

Priority 3 –Transmitter holding register empty

Priority 4–Modem status (lowest priority)

When an interrupt is generated, the IIR indicates that an interrupt is pending and indicates the type of interrupt

in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and

described in Table 4.

Bit 0: This bit can be used either in a hardwire prioritized or polled interrupt system. When this bit is cleared,

an interrupt is pending. When bit 0 is set, no interrupt is pending.

Bits 1 and 2: These two bits identify the highest priority interrupt pending as indicated in Table 4.

Bits 3 – 7: These bits in the interrupt identification register are not used and are always clear.

Table 4. Interrupt Control Functions

INTERRUPT

IDENTIFICATION

REGISTER

PRIORITY

LEVEL

INTERRUPT RESET

METHOD

INTERRUPT TYPE

INTERRUPT SOURCE

BIT 2

BIT 1

BIT 0

0

1

None

1

None

–

Overrun error, parity error,

framing error or break

interrupt

Reading the line status

register

1

0

Receiver line status

Reading the receiver buffer

register

1

0

2

3

Received data available

Receiver data available

Reading the interrupt

Identification register (if

source of interrupt) or writing

into the transmitter holding

register

Transmitter holding register

empty

Transmitter holding register

empty

1

0

Clear to send, data set

ready, ring indicator, or data

carrier detect

Reading the modem status

register

0

4

Modem status

17

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PRINCIPLES OF OPERATION

Iine control register (LCR)

The system programmer controls the format of the asynchronous data communication exchange through the

LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates

the need for separate storage of the line characteristics in system memory. The contents of this register are

summarized in Table 3 and are described in the following bulleted list.

Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.

These bits are encoded as shown in Table 5.

Table 5. Serial Character Word Length

Bit 1

Bit 0

Word Length

5 bits

0

1

0

1

0

1

6 bits

7 bits

8 bits

Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When

bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated

is dependent on the word length selected with bits 0 and 1. The number of stop bits generated in relation

to word length and bit 2 is as shown in Table 6.

Table 6. Number of Stop Bits Generated

Word Length Selected

by Bits 1 and 2

Number of Stop

Bits Generated

Bit 2

0

1

Any word length

5 bits

1

1 1/2

2

6 bits

7 bits

2

8 bits

2

Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in transmitted data between

the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit

3 is cleared, no parity is generated or checked.

Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity

(anevennumberoflogicisinthedataandparitybits)isselected. Whenparityisenabledandbit4iscleared,

odd parity (an odd number of logic 1s) is selected.

Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as

cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set.

Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition, i.e, a condition where SOUT

terminal is forced to the spacing (cleared) state. When bit 6 is cleared, the break condition is disabled. The

break condition has no affect on the transmitter logic, it only affects the serial output.

Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the

baud generator during a read or write. Bit 7 must be cleared during a read or write to access the receiver

buffer, the THR, or the IER.

18

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PRINCIPLES OF OPERATION

†

line status register (LSR)

The LSR provides information to the CPU concerning the status of data transfers. The contents of this register

are summarized in Table 3 and are described in the following bulleted list.

Bit 0: This bit is the data ready (DR) indicator for the receiver. Bit 0 is set whenever a complete incoming

character has been received and transferred into the RBR and is cleared by reading the RBR.

‡

Bit 1 : This bit is the overrun error (OE) indicator. When bit 1 is set, it indicates that before the character

in the RBR was read, it was overwritten by the next character transferred into the register. The OE indicator

is cleared every time the CPU reads the contents of the LSR.

‡

Bit 2 : This bit is the parity error (PE) indicator. When bit 2 is set, it indicates that the parity of the received

data character does not match the parity selected in the LCR (bit 4). The PE bit is cleared every time the

CPU reads the contents of the LSR.

‡

Bit 3 : This bit is the framing error (FE) indicator. When bit 3 is set, it indicates that the received character

did not have a valid (set) stop bit. The FE bit is cleared every time the CPU reads the contents of the LSR.

‡

Bit 4 : This bit is the break interrupt (BI) indicator. When bit 4 is set, it indicates that the received data input

was held clear for longer than a full-word transmission time. A full-word transmission time is defined as the

total time of the start, data, parity, and stop bits. The BI bit is cleared every time the CPU reads the contents

of the LSR.

Bit 5: This bit is the THRE indicator. Bit 5 is set when the THR is empty, indicating that the ACE is ready

to accept a new character. If the THRE interrupt is enabled when the THRE bit is set, then an interrupt is

generated. THRE is set when the contents of the THR are transferred to the transmitted shift register. This

bit is cleared concurrent with the loading of the THR by the CPU.

Bit 6: This bit is the transmitter empty (TEMT) indicator, bit 6 is set when the THR and the transmitter shift

register are both empty. When either the THR or the transmitter shift register contains a data character, the

TEMT bit is cleared.

Bit 7: This bit is always clear.

†

‡

The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.

Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.

modem control register (MCR)

The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is

emulating a modem. The contents of this register are summarized in Table 3 and are described in the following

bulleted list.

Bit 0: This bit (DTR) controls the data terminal ready (DTR) output. Setting bit 0 forces the DTR output to

its active state (low). When bit 0 is cleared, DTR goes high.

Bit 1: This bit (RTS) controls the request to send (RTS) output in a manner identical to bit 0’s control over

the DTR output.

Bit 2: This bit (OUT 1) is a reserved location used only in the loopback mode.

Bit 3: This bit (OUT 2) controls the output enable for the interrupt signal. When set, the interrupt is enabled.

When bit 3 is cleared, the interrupt is disabled.

19

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PRINCIPLES OF OPERATION

modem control register (MCR) (continued)

Bit 4: This bit provides a local loopback feature for diagnostic testing of the ACE. When this bit is set, the

following occurs:

1. The SOUT is asserted high.

2. The SIN is disconnected.

3. The output of the transmitter shift register is looped back into the receiver shift register input.

4. The four modem status inputs (CTS, DSR, RLSD, and RI) are disconnected.

5. The MCR bits (DTR, RTS, OUT1, and OUT2) are connected to the modem status register bits (DSR,

CTS, RI, and RLSD), respectively.

6. The four modem control output terminals are forced to their inactive states (high).

In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify

the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.

The modem control interrupts are also operational but the modem control interrupt sources are now the

lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the

IER.

Bits 5 through 7: These bits are always cleared.

modem status register (MSR)

The MSR is an 8-bit register that provides information about the current state of the control lines from the

modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provides change

information; when a control input from the modem changes state the appropriate bit is set. All four bits are

cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are

described in the following bulleted list.

Bit 0. This bit is the delta clear to send (DCTS) indicator. Bit 0 indicates that the CTS input has changed

states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is

enabled, a modem status interrupt is generated.

Bit 1. This bit is the delta data set ready (DDSR) indicator. Bit 1 indicates that the DSR input has changed

states since the last time it was read by the CPU. When this bit is set and the modem status Interrupt is

enabled, a modem status interrupt is generated.

Bit 2. This bit is the trailing edge of ring indicator (TERI) detector. Bit 2 indicates that the RI input to the chip

has changed from a low to a high state. When this bit is set and the modem status Interrupt is enabled, a

modem status interrupt is generated.

Bit 3. This bit is the delta receive line signal detect (DRLSD) indicator. Bit 3 indicates that the RLSD input

to the chip has changed states since the last time it was read by the CPU. When this bit is set and the modem

status interrupt is enabled, a modem status interrupt is generated.

Bit 4. This bit is the complement of the clear to send (CTS) input. When bit 4 (loop) of the MCR is set, bit

4 is equivalent to the MCR bit 1 (RTS).

Bit 5. This bit is the complement of the data set ready (DSR) input. When bit 4 (loop) of the MCR is set, bit

5 is equivalent to the MCR bit 0 (DTR).

Bit 6. This bit is the complement of the ring indicator (RI) input. When bit 4 (loop) of the MCR is set, bit 6

is equivalent to the MCR bit 2 (OUT 1).

Bit 7. This bit is the complement of the receive line signal detect (RLSD) input. When bit 4 (loop) of the MCR

is set, bit 7 is equivalent to the MCR bit 3 (OUT 2).

20

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PRINCIPLES OF OPERATION

parallel port registers

The parallel port registers interface either device to a Centronix-style printer interface. When chip select 2 (CS2)

is low, the parallel port is selected. Tables 7 and 8 show the registers associated with this parallel port. The read

or write function of the register is controlled by the state of the read (IOR) and write (IOW) terminal as shown.

The read data register allows the microprocessor to read the information on the parallel bus.

The read status register allows the microprocessor to read the status of the printer in the five most significant

bits. The status bits are printer busy (BUSY), acknowledge (ACK) which is a handshake function, paper empty

(PE), printer selected (SLCT), and error (ERROR). The read control register allows the state of the control lines

to be read. The write control register sets the state of the control lines, which are interrupt enable (IRQ ENB),

select in (SLIN), initialize the printer (INIT), autofeed the paper (AFD), and strobe (STB), which informs the

printer of the presence of a valid byte on the parallel bus. These signals are cleared when a reset occurs. The

write data register allows the microprocessor to write a byte to the parallel bus. The parallel port is completely

compatible with the parallel port implementation used in the IBM serial/parallel adaptor.

Table 7. Parallel Port Registers

REGISTER BITS

REGISTER

BIT 7

PD7

BUSY

1

BIT 6

PD6

ACK

1

BIT 5

PD5

PE

1

BIT 4

BIT 3

BIT 2

PD2

1

BIT 1

PD1

1

BIT 0

PD0

1

Read data

PD4

PD3

Read status

Read control

Write data

SLCT

ERROR

SLIN

IRQ ENB

PD4

INIT

PD2

INIT

AFD

PD1

AFD

STB

PD0

STB

PD7

1

PD6

1

PD5

1

PD3

Write control

IRQ ENB

SLIN

Table 8. Parallel Port Register Select

CONTROL TERMINALS

REGISTER SELECTED

IOR

L

IOW

H

L

CS2

L

A1

L

A0

L

Read data

Read status

Read control

Invalid

L

H

L

H

L

H

L

H

L

Write data

Invalid

L

H

L

H

Write control

Invalid

L

H

21

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PRINCIPLES OF OPERATION

programmable baud generator

The ACE contains a programmable baud generator that takes a clock input in the range between dc and 9 MHz

16–

and divides it by a divisor in the range between 1 and (2

1). The output frequency of the baud generator is

sixteen times (16×) the baud rate. The formula for the divisor is:

divisor # = CLK frequency input ÷ (desired baud rate × 16)

Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must

beloadedduringinitializationoftheACEinordertoensuredesiredoperationofthebaudgenerator. Wheneither

of the divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load. For

baud rates of 38.4 kilobits per second and below, the error obtained is very small. The accuracy of the selected

baud rate is dependent on the selected crystal frequency.

receiver buffer register (RBR)

The ACE receiver section consists of a receiver shift register and an RBR. Timing is supplied by the 16× receiver

clock (RCLK). Receiver section control is a function of the ACE line control register.

The ACE receiver shift register receives serial data from the serial input (SIN) terminal. The receiver shift

register then converts the data to a parallel form and loads it into the RBR. When a character is placed in the

RBR and the received data available interrupt is enabled, an interrupt is generated. This interrupt is cleared

when the data is read out of the RBR.

scratch register

The scratch register is an 8-bit register that is intended for programmer use as a scratchpad, in the sense that

it temporarily holds programmer data without affecting any other ACE operation.

transmitter holding register (THR)

The ACE transmitter section consists of a THR and a transmitter shift register. Timing is supplied by the baud

out (BAUDOUT) clock signal. Transmitter section control is a function of the ACE line control register.

The ACE THR receives data off of the internal data bus and, when the shift register is idle, moves it into the

transmitter shift register. The transmitter shift register serializes the data and outputs it at the serial output

(SOUT). When the THR is empty and the transmitter holding register empty (THRE) interrupt is enabled, an

interrupt is generated. This interrupt is cleared when a character is loaded into the register.

22

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PACKAGE OPTION ADDENDUM

www.ti.com

20-Mar-2008

PACKAGING INFORMATION

Orderable Device

TL16C451FN

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

PLCC

FN

68

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C451FNG4

TL16C451FNR

TL16C451FNRG4

TL16C452FN

PLCC

FN

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

TL16C452FNG4

TL16C452FNR

TL16C452FNRG4

18 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-3-260C-168 HR

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

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Addendum-Page 1

IMPORTANT NOTICE

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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:

Products

Applications

Audio

Automotive

Broadband

Digital Control

Medical

Amplifiers

Data Converters

DSP

Clocks and Timers

Interface

amplifier.ti.com

dataconverter.ti.com

dsp.ti.com

www.ti.com/clocks

interface.ti.com

logic.ti.com

www.ti.com/audio

www.ti.com/automotive

www.ti.com/broadband

www.ti.com/digitalcontrol

www.ti.com/medical

www.ti.com/military

Logic

Military

Power Mgmt

Microcontrollers

RFID

power.ti.com

microcontroller.ti.com

www.ti-rfid.com

Optical Networking

Security

Telephony

Video & Imaging

Wireless

www.ti.com/opticalnetwork

www.ti.com/security

www.ti.com/telephony

www.ti.com/video

RF/IF and ZigBee® Solutions www.ti.com/lprf

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	TL16C452FNG4
厂家：	TEXAS INSTRUMENTS
描述：	Dual UART with Parallel Port And Without FIFO 68-PLCC 0 to 70 通信数据传输 PC 先进先出芯片外围集成电路
文件：	总24页 (文件大小：337K)
中文：	中文翻译
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