TL16C552FNR [TI]
具有 16 字节 FIFO 并行端口的双路 UART | FN | 68 | 0 to 70;
| 型号： | TL16C552FNR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 16 字节 FIFO 并行端口的双路 UART | FN | 68 | 0 to 70 通信 时钟 数据传输 PC 先进先出芯片 控制器 微控制器 微控制器和处理器 串行IO控制器 |
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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
IBM PC/AT Compatible
Programmable Serial Interface
Characteristics for Each Channel:
– 5-, 6-, 7-, or 8-bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
Two TL16C550 ACEs
Enhanced Bidirectional Printer Port
16-Byte FIFOs Reduce CPU Interrupts
– 1-, 1 1/2-, or 2-Stop Bit Generation
Independent Control of Transmit, Receive,
Line Status, and Data Set Interrupts on
Each Channel
3-State TTL Drive for the Data and Control
Bus on Each Channel
Hardware and Software Compatible With
TL16C452
Individual Modem Control Signals for Each
Channel
description
FN PACKAGE
(TOP VIEW)
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
SOUT1
DTR1
RTS1
CTS1
DB0
INT1
59
INT2
58
SLIN
57
INIT
56
AFD
55
DB1
STB
54
DB2
GND
53
DB3
PD0
52
DB4
PD1
51
DB5
PD2
50
DB6
PD3
49
DB7
PD4
48
TXRDY0
PD5
47
V
PD6
DD
46
RTS0
DTR0
PD7
45
INT0
44
SOUT0
BDO
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
description
The TL16C552 is an enhanced dual channel version of the popular TL16C550 asynchronous communications
element (ACE). The device serves two serial input/output interfaces simultaneously in microcomputer or
microprocessor-based systems. Each channel performs serial-to-parallel conversion on data characters
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
IBM PC/AT is a trademark of International Business Machines Corporation.
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
description (continued)
received from peripheral devices or modems and parallel-to-serial conversion on data characters transmitted
by the CPU. The complete status of each channel of the dual ACE can be read at any time during functional
operation by the CPU. The information obtained includes the type and condition of the transfer operations being
performed and the error conditions.
In addition to its dual communications interface capabilities, the TL16C552 provides the user with a fully
bidirectional parallel data port that fully supports the parallel Centronics-type printer. The parallel port and the
two serial ports provide IBM PC/AT-compatible computers with a single device to serve the three system ports.
A programmable baud rate generator is included that can divide the timing reference clock input by a divisor
16
between 1 and (2 – 1).
The TL16C552 is housed in a 68-pin plastic leaded chip carrier.
functional block diagram
28
31
29
30
41
24
25
26
45
9
CTS0
DSR0
DCD0
RI0
RTS0
DTR0
SOUT0
INT0
ACE
#1
SIN0
RXRDY0
TXRDY0
32
22
CS0
14–21
8
DB–DB7
8
13
5
12
11
10
60
61
42
CTS1
DSR1
DCD1
RI1
RTS1
DTR1
8
SOUT1
INT1
ACE
#2
6
62
3
RXRDY1
TXRDY1
SIN1
CS1
35–33
36
A0–A2
IOW
Select
and
Control
Logic
44
37
BDO
IOR
39
RESET
CLK
8
4
8
53–46
57
PD0–PD7
INIT
63
65
66
67
68
1
ERR
SLCT
BUSY
PE
56
AFD
55
STB
Parallel
Port
58
SLIN
59
INT2
ACK
PEMD
CS2
38
43
ENIRQ
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
68
I
ACK
AFD
Line printer acknowledge. ACK goes low to indicate a successful data transfer has taken place.
It generates a printer port interrupt during its positive transition.
56
I/O
Line printer autofeed. AFD is an open-drain line that provides the printer with an active-low signal
when continuous form paper is to be autofed to the printer. This terminal has an internal pullup
resistor to V
of approximately 10 kΩ.
DD
A0, A1, A2
BDO
35, 34, 33
I
O
I
Address lines A0–A2. A0, A1, and A2 select the internal registers during CPU bus operations. See
Table 2 for the decode of the serial channels and Table 13 for the decode of the parallel printer port.
44
66
Bus buffer output. BDO is an active-high output that is asserted when either serial channel or the
parallel port is read. This output can control the system bus driver (74LS245).
BUSY
Line printer busy. BUSY is an input line from the printer that goes high when the printer is not ready
to accept data.
CLK
4
I
I
Clock input. CLK is an external clock input to the baud rate divisor of each ACE.
32, 3, 38
CS0, CS1, CS2
Chip selects. CS0, CS1, and CS2 act as an enable for the write and read signals for the serial
channels 1 (CS0) and 2 (CS1). CS2 enables the signals to the printer port.
28, 13
14 – 21
29, 8
31, 5
25, 11
43
I
CTS0, CTS1
DB0 – DB7
Clear to send inputs. The logical state of CTS0 or CTS1 is reflected in the CTS bit of the modem
status register (CTS is bit 4 of the modem status register, written MSR4) of each ACE. A change
of state in either CTS terminal, since the previous reading of the associated modem status register,
causes the setting of delta clear to send (∆CTS) bit (MSR0) of each modem status register.
I/O
Data bits DB0 – DB7. The data bus provides eight 3-state I/O lines for the transfer of data, control,
and status information between the TL16C552 and the CPU. These lines are normally in a
high-impedance state except during read operations. D0 is the least significant bit (LSB) and is the
first serial data bit to be received or transmitted.
I
I
DCD0, DCD1
DSR0, DSR1
DTR0, DTR1
ENIRQ
Data carrier detect. DCD is a modem input. Its condition can be tested by the CPU by reading the
MSR7 (DCD) bit of the modem status registers. The MSR3 (delta data carrier detect or ∆DCD) bit
of the modem status register indicates whether the DCD input has changed states since the
previous reading of the modem status register. DCD has no affect on the receiver.
Data set ready inputs. The logical state of DSR0 and DSR1 is reflected in MSR5 of its associated
modem status register. The MSR1 (delta data set ready or ∆DSR) bit indicates whether the
associated DSR terminal has changed states since the previous reading of the modem status
register.
O
I
Data terminal ready lines. DTR0 and DTR1 can be asserted low by setting modem control register
bit 0 (MCR0) of its associated ACE. This signal is asserted high by clearing the DTR bit (MCR0)
or whenever a reset occurs. When active (low), the DTR terminal indicates that its ACE is ready
to receive data.
Parallel port interrupt source mode selection. When ENIRQ is low, the PC/AT mode of interrupts
is enabled. In this mode, the INT2 output is internally connected to the ACK input. When the ENIRQ
input is tied high, the INT2 output is internally tied to the PRINT signal in the line printer status
register. INT2 is latched high on rising edge of ACK.
63
I
ERR
Line printer error. ERR is an input line from the printer. The printer reports an error by holding this
line low during the error condition.
GND
INIT
7, 27, 54
57
Ground (0 V). All terminals must be tied to ground for proper operation.
I/O
I
Line printer initialize. INIT is an open-drain line that provides the printer with an active-low signal,
which allows the printer initialization routine to be started. This terminal has an internal pullup
resistor to V
of approximately 10 kΩ.
DD
37
36
IOR
Input/output read strobe. IOR is an active-low input that enables the selected channel to output
data to the data bus (DB0–DB7). The data output depends upon the register selected by the
address inputs A0, A1, A2, and chip select. Chip select 0 (CS0) selects ACE #1, chip select 1 (CS1)
selects ACE #2, and chip select 2 (CS2) selects the printer port.
I
IOW
Input/output write strobe. IOW is an active-low input causing data from the data bus to be input to
eitherACEortotheparallelport.Thedestinationdependsupontheregisterselectedbytheaddress
inputs A0, A1, A2, and chip selects CS0, CS1, and CS2.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
Terminal Functions (continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
INT0, INT1
45, 60
O
Serial channel interrupts. INT0 and INT1 are 3-state serial channel interrupt outputs (enabled by bit
3 of the MCR) that go active (high) when one of the following interrupts has an active (high) condition
and is enabled by the interrupt enable register of its associated channel: receiver error flag, received
data available, transmitter holding register empty, and modem status. The interrupt is cleared upon
appropriate service. When reset, the interrupt output is in the high-impedance state.
INT2
59
O
Printerportinterrupt. INT2isanactive-high, 3-stateoutputgeneratedbythepositivetransitionofACK.
It is enabled by bit 4 of the write control register. Upon a reset, the interrupt output is in the
high-impedance state. Its mode is also controlled by ENIRQ.
PD0–PD7
PE
53–46
I/O Parallel data bits (0–7). These eight lines (PD0–PD7) provide a byte wide input or output port to the
system.
67
1
I
Printer paper empty. PE is an input line from the printer that goes high when the printer runs out of
paper.
PEMD
I
Printer enhancement mode. When low, PEMD enables the write data register to the PD0–PD7 lines.
A high on this signal allows direction control of the PD0–PD7 port by the DIR bit in the control register.
PEMD is usually tied low for the printer operation.
39
I
RESET
Reset. When low, RESET forces the TL16C552 into an idle mode in which all serial data activities are
suspended. The modem control register along with its associated outputs are cleared. The line status
register is cleared except for the THRE and TEMT bits, which are set. All functions of the device remain
in an idle state until programmed to resume serial data activities. This input has a hysteresis level of
typically 400 mV.
24, 12
9, 61
O
O
RTS0, RTS1
Request to send outputs. RTSx is asserted low by setting MCR1, bit 1 of its UARTs modem control
register. Both RTSx terminals are set by RESET. A low on the RTSx terminal indicates that its ACE has
data ready to transmit. In half-duplex operations, RTSx controls the direction of the line.
RXRDY0,
RXRDY1
Receiver ready. RXRDY0 and RXRDY1 are receiver direct memory access (DMA) signaling
terminals. One of two types of DMA signaling can be selected using FIFO control register bit 3 (FCR3)
when operating in the FIFO mode. Only DMA mode 0 is allowed when operating in the TL16C450
mode. For signal transfer DMA (a transfer is made between CPU bus cycles), mode 0 is used. Multiple
transfers that are made continuously until the receiver FIFO has been emptied are supported by
mode 1.
Mode0. RXRDYxisactive(low)whenintheFIFOmode(FCR0=1, FCR3=0)orwhenintheTL16C450
mode (FCR0=0) and the receiver FIFO or receiver holding register contain at least one character.
When there are no more characters in the receiver FIFO or receiver holding register, the RXRDYx
terminal goes inactive (high).
Mode 1. RXRDYx goes active (low) in the FIFO mode (FCR0=1) when FCR3=1 and the time-out or
trigger levels have been reached. It goes inactive (high) when the FIFO or receiver holding register is
empty.
30, 6
I
I
RI0, RI1
Ring indicator inputs. RI0 and RI1 are modem control inputs. Their condition is tested by reading
MSR6 (RI) of each ACE. The modem status register outputs trailing edge of ring indicator (TERI or
MSR2) that indicates whether either input has changed states from high to low since the previous
reading of the modem status register.
SIN0, SIN1
41, 62
Serialdatainputs. SIN0andSIN1areserialdatainputsthatmoveinformationfromthecommunication
line or modem to the TL16C552 receiver circuits. Mark (set) is a high state and a space (cleared) is
low state. Data on the serial data inputs is disabled when operating in the loop mode.
SLCT
65
58
I
Printer selected. SLCT is an input line from the printer that goes high when the printer has been
selected.
I/O
O
SLIN
Line printer select. SLIN is an open-drain input that selects the printer when it is active (low). This
terminal has an internal pullup resistor to V
of approximately 10 kΩ.
DD
SOUT0, SOUT1
26, 10
Serial data outputs. SOUT0 and SOUT1 are the serial data outputs from the ACE transmitter circuitry.
A mark is a high state and a space is a low state. Each SOUT is held in the mark condition when the
transmitter is disabled, when RESET is true (low), when the transmitter register is empty, or when in
the loop mode.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
Terminal Functions (continued)
TERMINAL
NAME
I/O
DESCRIPTION
NO.
55
I/O
STB
TRI
Printerstrobe. STB isanopen-drainlinethatprovidescommunicationbetweentheTL16C552andthe
printer. When it is active (low), it provides the printer with a signal to latch the data currently on the
parallel port. This terminal has an internal pullup resistor to V
of approximately 10 kΩ.
DD
2
I
3-state control. TRI controls the 3-state control of all I/O and output terminals. When TRI is asserted,
all I/O and outputs become high impedance, allowing board level testers to drive the outputs without
overdriving the internal buffers. This terminal is level sensitive, is a CMOS input, and is pulled down
with an internal resistor that is approximately 5 kΩ.
22, 42
O
TXRDY0,
TXRDY1
Transmitter ready. TXRDY0 and TXRDY1 are transmitter ready signals. Two types of DMA signaling
are available. Either can be selected using FCR3 when operating in the FIFO mode. Only DMA mode
0 is allowed when operating in the TL16C450 mode. Single-transfer DMA (a transfer is made between
CPU bus cycles) is supported by mode 0. Multiple transfers that are made continuously until the
transmitter FIFO has been filled are supported by mode 1.
Mode 0. When in the FIFO mode (FCR0=1, FCR3=0) or in the TL16C450 mode (FCR0=0) and there
are no characters in the transmitter holding register or transmitter FIFO, TXRDY are active (low). Once
TXRDY is activated (low), it goes inactive after the first character is loaded into the holding register of
transmitter FIFO.
Mode 1. TXRDYx goes active (low) if in the FIFO mode (FCR0=1) when FCR3=1 and there are no
charactersinthetransmitterFIFO. WhenthetransmitterFIFOiscompletelyfull, TXRDYxgoesinactive
(high).
V
DD
23, 40, 64
Power supply. V
is the power supply requirement is 5 V ±5%.
DD
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.3 V
DD
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.3 V
O
DD
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage levels are with respect to ground (V ).
SS
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
DD
Clock high-level input voltage, V
V
DD
0.8
V
IH(CLK)
IL(CLK)
Clock low-level input voltage, V
High-level input voltage, V
–0.5
2
V
V
DD
0.8
V
IH
Low-level input voltage, V
–0.5
V
IL
Clock frequency, f
8
MHz
°C
clock
Operating free-air temperature range, T
0
70
A
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
electrical characteristics over recommended ranges of operating free-air temperature and supply
voltage
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
I
I
I
I
= –0.4 mA for DB0–DB7,
= –2 mA for PD0–PD7,
= –0.4 mA for INIT, AFD, STB, and SLIN (see Note 2),
= –0.4 mA for all other outputs
OH
OH
OH
OH
V
V
High-level output voltage
2.4
V
OH
I
I
I
I
= 4 mA for DB0–DB7,
= 12 mA for PD0–PD7,
= 10 mA for INIT, AFD, STB, and SLIN (see Note 2),
= 2 mA for all other outputs
OL
OL
OL
OL
Low-level output voltage
0.4
V
OL
I
I
Input current
V
= 5.25 V,
All other terminals are floating
±10
±10
µA
µA
I
DD
V = 0 to 5.25 V
Clock input current
I(CLK)
OZ
I
V
V
= 5.25 V,
V
O
= 0 with chip deselected, or
DD
O
I
I
High-impedance output current
Supply current
±20
µA
= 5.25 V with chip and write mode selected
V
DD
= 5.25 V,
No loads on outputs,
SIN0, SIN1, DSR0, DSR1, DCD0, DCD1, CTS0, CTS1,
50
mA
DD
RI0 and RI1 at 2 V,
Baud rate generator f
Other inputs at 0.8 V,
= 8 MHz, Baud rate = 56 kbit/s
clock
NOTE 2: These four terminals contain an internal pullup resistor to V
of approximately 10 kΩ.
DD
clocktimingrequirementsoverrecommendedrangesofoperatingfree-airtemperatureandsupply
voltage
MIN
55
MAX
UNIT
ns
t
t
t
Pulse duration, CLK high (external clock, 8 MHz max) (see Figure 1)
Pulse duration, CLK low (external clock, 8 MHz max) (see Figure 1)
Pulse duration, master (RESET) low (see Figure 16)
w1
w2
w3
55
ns
1000
ns
read cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 4)
MIN
80
MAX
UNIT
ns
t
t
t
t
t
t
t
Pulse duration, IOR low
w4
su1
su2
h1
Setup time, chip select valid before IOR low (see Note 3)
Setup time, A2–A0 valid before IOR low (see Note 3)
Hold time, A2–A0 valid after IOR high (see Note 3)
Hold time, chip select valid after IOR high (see Note 3)
15
ns
15
ns
20
ns
20
ns
h2
Delay time, t
+ t
+ t (see Note 4)
175
80
ns
d1
su2 w4 d2
Delay time, IOR high to IOR or IOW low
ns
d2
NOTES: 3. The internal address strobe is always active.
4. In the FIFO mode, t = 425 ns (min) between reads of the receiver FIFO and the status registers (IIR and LSR).
d1
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
write cycle timing requirements over recommended ranges of operating free-air temperature and
supply voltage (see Figure 5)
MIN
80
MAX
UNIT
ns
t
t
t
t
t
t
t
t
t
Pulse duration, IOW low
w5
su4
su5
su6
h3
Setup time, chip select valid before IOW low (see Note 3)
Setup time, A2–A0 valid before IOW low (see Note 3)
Setup time, D0–D7 valid before IOW high
Hold time, A2–A0 valid after IOW high (see Note 3)
Hold time, chip select valid after IOW high (see Note 3)
Hold time, D0–D7 valid after IOW high
15
ns
15
ns
15
ns
20
ns
20
ns
h4
15
ns
h5
Delay time, t
+ t
+ t
175
80
ns
d3
su5 w5 d4
Delay time, IOW high to IOW or IOR low
ns
d4
NOTE 3: The internal address strobe is always active.
read cycle switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figure 4)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
Propagation delay time from IOR high to BDO high or from IOR low to
BDO low
t
C
= 100 pF, See Note 5
60
ns
pd1
L
t
t
Enable time from IOR low to D0–D7 valid
C
C
= 100 pF, See Note 5
= 100 pF, See Note 5
60
60
ns
ns
en
L
L
Disable time from IOR high to D0–D7 released
0
dis
NOTE 5:
V
OL
and V
(and the external loading) determine the charge and discharge time.
OH
transmitter switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 6, 7, and 8)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
RCLK
cycles
t
d5
t
d6
t
d7
t
d8
Delay time, interrupt THRE low to SOUT low at start
8
24
RCLK
cycles
Delay time, SOUT low at start to interrupt THRE high
Delay time, IOW (WR THR) high to interrupt THRE high
Delay time, SOUT low at start to TXRDY low
See Note 6
See Note 6
8
8
32
8
RCLK
cycles
16
RCLK
cycles
C
= 100 pF
L
t
t
t
Propagation delay time from IOW (WR THR) low to interrupt THRE low
Propagation delay time from IOR (RD IIR) high to interrupt THRE low
Propagation delay time from IOW (WR THR) high to TXRDY high
C
C
C
= 100 pF
= 100 pF
= 100 pF
140
140
195
ns
ns
ns
pd2
pd3
pd4
L
L
L
NOTE 6: When the transmitter interrupt delay is active, this delay si lengthened by one character time minus the last stop bit time.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
receiver switching characteristics over recommended ranges of operating free-air temperature
and supply voltage (see Figures 9, 10, 11, 12 and 13)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
RCLK
cycle
t
d9
Delay time from stop to INT high
See Note 7
1
t
t
t
Propagation delay time from RCLK high to sample CLK high
100
150
150
ns
ns
ns
pd5
pd6
pd7
Propagation delay time from IOR (RD RBR/RD LSR) high to reset interrupt low
Propagation delay time from IOR (RD RBR) low to RXRDY high
C = 100 pF
L
NOTE 7: Thereceiverdataavailableindication,theoverrunerrorindication,thetriggerlevelinterruptsandtheactiveRXRDYindicationisdelayed
three RCLK cycles in the FIFO mode (FCR0 = 1). After the first byte has been received, status indicators (PE, FE, BI) is delayed three
RCLK cycles. These indicators are updated immediately for any further bytes received after RD RBR goes active. There are eight RCLK
cycle delays for trigger change level interrupts.
modem control switching characteristics over recommended ranges of operating free-air
temperature and supply voltage (see Figure 14)
PARAMETER
TEST CONDITIONS
MIN
MAX
100
170
140
170
UNIT
ns
t
t
t
t
Propagation delay time from IOW (WR MCR) high to RTS (DTR) low/high
Propagation delay time from modem input (CTS, DSR) low/high to interrupt high
Propagation delay time from IOR (RD MSR) high to interrupt low
Propagation delay time from RI high to interrupt high
C
C
C
C
= 100 pF
= 100 pF
= 100 pF
= 100 pF
pd8
L
L
L
L
ns
pd9
ns
pd10
pd11
ns
parallel port timing requirements over recommended ranges of supply voltage and operating
free-air temperature (see Figure 15)
MIN
1
MAX
UNIT
µs
t
t
t
t
t
t
t
t
Setup time, data valid before STB low
Hold time, data valid after STB high
Pulse duration, STB low
su7
1
µs
h6
1
500
µs
w6
Delay time, BUSY high to ACK low
Delay time, BUSY low to ACK low
Pulse duration, ACK low
Defined by printer
Defined by printer
Defined by printer
Defined by printer
Defined by printer
d10
d11
w6
Pulse duration, BUSY high
w7
Delay time, BUSY high after STB high
d12
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
t
w1
2 V
CLK (XTAL1)
0.8 V
t
w2
f
= 8 MHz MAX
clock
Figure 1. Clock Input (CLK) Voltage Waveform
2.54 V
Device Under Test
680 Ω
TL16C552
†
82 pF
†
Includes scope and jig capacitance
Figure 2. Output Load Circuit
TL16C552
Serial
Channel 1
Buffers
Data Bus
9-Pin D Connector
9-Pin D Connector
Address Bus
Dual
Ace and
Printer
Port
Serial
Channel 2
Buffers
Control Bus
Option
Jumpers
Parallel
Port
25-Pin D Connector
R/C
Network
Figure 3. Basic Test Configuration
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Valid
50%
50%
A2, A1, A0
t
h1
CS0, CS1, CS2
50%
Valid
50%
t
t
h2
su1
t
d1
t
su2
Active
Active
IOR
50%
50%
50%
50%
t
d2
t
w4
OR
Active
IOW
t
pd1
t
t
pd1
BDO
50%
50%
dis
t
en
Data
D0–D7
Valid Data
Figure 4. Read Cycle Timing Waveforms
50%
Valid
50%
A2, A1, A0
t
h3
CS0, CS1, CS2
50%
Valid
50%
t
t
h4
su4
t
d3
t
su5
Active
Active
IOW
IOR
50%
50%
50%
t
d4
t
w5
OR
Active
50%
t
su6
t
h5
Data
D0–D7
Valid Data
Figure 5. Write Cycle Timing Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Start
Start
50%
Serial Out
(SOUT)
Data Bits 5–8
50%
Stop (1–2)
Parity
t
d5
t
d6
Interrupt
(THRE)
50%
50%
50%
50%
50%
t
pd2
t
pd2
t
d7
IOW
(WR THR)
50%
50%
50%
t
pd3
IOR
(RD IIR)
50%
Figure 6. Transmitter Timing Waveforms
Byte #1
IOW
50%
(WR THR)
Start
50%
Data
Parity
Stop
SOUT
t
d8
t
pd4
TXRDY
50%
50%
Figure 7. Transmitter Ready Mode 0 Timing Waveforms
Byte #16
50%
IOW
(WR THR)
Start of
Byte #16
Start
Data
Parity
Stop
SOUT
t
d8
t
pd4
FIFO Full
TXRDY
50%
50%
Figure 8. Transmitter Ready Mode 1 Timing Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
RCLK
t
8 CLK Cycles
pd5
CLK
TL16C450 MODE
SIN
(receiver input
data)
Start
Data Bits 5–8
Parity
Stop
Sample
CLK
t
d9
Interrupt
(data ready or
RCVR ERR)
50%
50%
t
pd6
Active
IOR
50%
Figure 9. Receiver Timing Waveforms
Start
SIN
Data Bits 5–8
Parity
Stop
Sample
CLK
(FIFO at or above
trigger level)
Trigger
Interrupt
(FCR6, 7=0, 0)
50%
50%
(FIFO below
trigger level)
t
d9
t
pd6
IOR
(RD RBR)
Active
50%
50%
50%
Line Status
Interrupt (LSI)
t
pd6
IOR
(RD LSR)
Active
50%
Figure 10. Receiver FIFO First Byte (Sets RDR) Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
SIN
Stop
Sample
CLK
t
d9
(see Note A)
Time Out or
Trigger Level
Interrupt
(FIFO at or above
trigger level)
50%
50%
(FIFO below
trigger level)
t
pd6
LSI
Interrupt
50%
50%
Top Byte of FIFO
t
pd6
t
d9
IOR
(RD LSR)
50%
Active
IOR
(RD RBR)
50%
50%
Active
Active
Previous Byte
Read From FIFO
Figure 11. Receiver FIFO After First Byte (After RDR Set) Waveforms
IOR
(RD RBR)
Active
50%
See Note A
SIN
(first byte)
Stop
Sample
CLK
t
d9
(see Note B )
RXRDY
50%
50%
t
pd7
Figure 12. Receiver Ready Mode 0 Waveforms
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCR0=1, then t = 3 RCLK cycles. For a time-out interrupt, t = 8 RCLK cycles.
d9
d9
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
IOR
(RD RBR)
Active
50%
See Note A
SIN
(first byte that reaches
the trigger level)
Stop
Sample
CLK
t
d9
(see Note B)
RXRDY
50%
50%
t
pd7
NOTES: A. This is the reading of the last byte in the FIFO.
B. When FCR0=1, then t = 3 RCLK cycles. For a trigger change level interrupt, t = 8 RCLK
d9
d9
Figure 13. Receiver Ready Mode 1 Waveforms
IOW
(WR MCR)
50%
50%
t
t
pd8
pd8
50%
RTS, DTR
CTS, DSR, DCD
50%
50%
50%
t
t
pd9
pd9
INT0, INT1,
1 INT, 2 INT
50%
50%
50%
t
t
pd10
pd11
IOR
(RD MSR)
50%
50%
RI
Figure 14. Modem Control Timing Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PARAMETER MEASUREMENT INFORMATION
Valid
50%
su7
50%
DATA
t
t
h6
STB
ACK
50%
50%
t
w6
50%
50%
t
t
w6
d10
t
d11
BUSY
50%
d12
50%
50%
t
t
w7
Figure 15. Parallel Port Timing Waveforms
RESET
50%
50%
t
w3
Figure 16. RESET Voltage Waveform
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
Three types of information are stored in the internal registers used in the ACE: control, status, and data.
Mnemonic abbreviations are shown in the Table 1 for the registers.
Table 1. Internal Register Types With Mnemonics
CONTROL
Line control register
FIFO control register
Modem control register
Divisor latch LSB
MNEMONIC
LCR
STATUS
MNEMONIC
LSR
DATA
MNEMONIC
RBR
Line status register
Modem status register
Receiver buffer register
Transmitter holding register
FCR
MSR
THR
MCR
DLL
Divisor latch MSB
DLM
Interrupt enable register
IER
The address, read, and write inputs are used with the divisor latch access bit (DLAB) in the line control register
(bit 7) to select the register to be written to or read from (see Table 2).
†‡
Table 2. Register Selection
DLAB
A2
L
A1
L
A0
L
MNEMONIC
RBR
THR
IER
REGISTER
Receiver buffer register (read only)
Transmitter holding register (write only)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write only)
Line control register
L
L
L
L
L
L
L
L
H
L
X
X
X
X
X
X
X
H
H
L
H
H
H
L
IIR
L
L
FCR
LCR
L
H
L
H
H
H
H
L
MCR
LSR
Modem control register
L
H
L
Line status register
H
H
L
MSR
SCR
DLL
Modem status register
H
L
Scratch register
Divisor latch (LSB)
L
L
H
DLM
Divisor latch (MSB)
†
‡
X = irrelevant, L = low level, H = high level
The serial channel is accessed when either CS0 or CS1 is low.
Individual bits within the registers are referred to by the register mnemonic and the bit number in parenthesis.
As an example, LCR7 refers to line control register bit 7.
The transmitter buffer register and receiver buffer register are data registers that hold from five to eight bits of
data. If less than eight data bits are transmitted, data is right justified to the LSB. Bit 0 of a data word is always
the first serial data bit received and transmitted. The ACE data registers are double buffered so that read and
write operations may be performed when the ACE is performing the parallel-to-serial or serial-to-parallel
conversion.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
accessible registers
The system programmer, using the CPU, has access to and control over any of the ACE registers that are
summarized in Table 2. These registers control ACE operations, receive data, and transmit data. Descriptions
of these registers follow Table 3.
Table 3. Summary of Accessible Registers
REGISTER BIT NUMBER
REGISTER
MNEMONIC
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
0
RBR
(read only)
Data
Bit 7
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
(MSB)
(LSB)
0
THR
(write only)
Data
Bit 7
Data
Bit 6
Data
Bit 5
Data
Bit 4
Data
Bit 3
Data
Bit 2
Data
Bit 1
Data
Bit 0
†
†
0
DLL
DLM
IER
Bit 7
Bit 15
0
Bit 6
Bit 14
0
Bit 5
Bit 13
0
Bit 4
Bit 12
0
Bit 3
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
1
Bit 11
Bit 10
1
(EDSSI)
Enable
modem
status
(ERLSI)
Enable
receiver
line
(ETBEI)
Enable
transmitter
holding
(ERBFI)
Enable
received
data
interrupt
status
interrupt
register
empty
available
interrupt
interrupt
2
2
3
4
FCR
(write only)
Receiver
Trigger
(MSB)
Receiver
Trigger
(LSB)
Reserved
0
Reserved
0
DMA
mode
select
Tranmitter
FIFO
reset
Receiver
FIFO
reset
FIFO
Enable
IIR
(read only)
FIFOs
Enabled
FIFOs
Enabled
Interrupt ID
‡
Bit (2)
Interrupt ID
Bit (1)
Interrupt ID
Bit (0)
0 If
interrupt
pending
‡
‡
LCR
(DLAB)
Divisor latch
access bit
Set
break
Stick
parity
(EPS)
Even parity
select
(PEN)
Parity
enable
(STB)
Number of
stop bits
(WLSB1)
Word length
select bit 1
(WLSB0)
Word length
select bit 0
MCR
0
0
0
Loop
Enable
external
interrupt
(INT0 or
INT1)
OUT1
(an unused
internal
(RTS)
Request
to send
(DTR)
Data
terminal
ready
signal)
5
6
LSR
Error in
receiver
FIFO
(TEMT)
Transmitter
empty
(THRE)
Transmitter
holding
register
empty
(BI)
Break
interrupt
(FE)
Framing
error
(PE)
Parity
error
(OE)
Overrun
error
(DR)
Data
ready
‡
MSR
SCR
(DCD)
Data carrier
detect
(RI)
Ring
indicator
(DSR)
Data set
ready
(CTS)
Clear
to send
(∆DCD)
Delta
data carrier
detect
(TERI)
Trailing
edge ring
indicator
(∆DSR)
Delta
data set
ready
(∆CTS)
Delta
clear
to send
7
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
†
‡
DLAB = 1
These bits are always 0 when FIFOs are disabled.
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO control register (FCR)
This write-only register is at the same location as the IIR. It enables and clears the FIFOs, sets the trigger level
of the receiver FIFO, and selects the type of DMA signaling. The contents of FCR are described in Table 3 and
the following bulleted list.
Bit 0: FCR0 enables both the transmitter and receiver FIFOs. All bytes in both FIFOs can be reset by
clearing FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the
TL16C450 mode and vice versa. Programming of other FCR bits is enabled by setting FCR0=1.
Bit 1: FCR1=1 clears all bytes in the receiver FIFO and resets the counter. This does not clear the shift
register.
Bit 2: FCR2=1 clears all bytes in the transmitter FIFO and resets the counter. This does not clear the shift
register.
Bit 3: FCR3=1 changes the RXRDY and TXRDY terminals from mode 0 to mode 1 when FCR0=1.
Bits 4 and 5: These two bits are reserved for future use.
Bits 6 and 7: These two bits set the trigger level for the receiver FIFO interrupt as shown in Table 4.
Table 4. Receiver FIFO Trigger Level
BIT
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
7
0
0
1
1
6
0
1
0
1
01
04
08
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and receiver interrupts are enabled:
1. LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is cleared.
2. IIR = 06 receiver line status interrupt has higher priority than the received data available interrupt IIR = 04.
3. Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4. IIR = 04 (receive data available indication) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
The following receiver FIFO character time-out status occurs when receiver FIFO and receiver interrupts are
enabled.
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. A FIFO timeout interrupt occurs when the following conditions exist:
a. Minimum of one character in FIFO
b. Last received serial character was longer than four continuous previous character times ago (if two stop
bits are programmed, the second one is included in the time delay).
c. The last CPU read of the FIFO was more than four continuous character times earlier. At 300 baud and
12-bit characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received
character to interrupt issued.1
2. By using the RCLK input for a clock signal, the character times can be calculated. (The delay is proportional
to the baud rate.)
3. The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received, when
there has been no time-out interrupt.
4. A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmitter interrupts occur as follows when the transmitter and transmitter FIFO interrupts are enabled
(FCRO = 1, IER = 1).
1. When the transmitter FIFO is empty, the THR interrupt (IIR = 02) occurs. The interrupt is cleared as soon
as the THR is written to or the IIR is read. One to sixteen characters can be written to the transmit FIFO when
servicing this interrupt.
2. The transmitter FIFO empty indications are delayed one character time minus the last stop bit time
whenever the following occurs:
THRE = 1 and there has not been a minimum of two bytes at the same time in transmitter FIFO, since the
last THRE = 1. The first transmitter interrupt after changing FCR0 is immediate, however, assuming it is
enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the received data
available interrupt. The THRE interrupt has the same priority as the transmitter FIFO empty interrupt.
FIFO polled mode operation
Clearing IER0, IER1, IER2, IER3, or all, with FCR0 = 1, puts the ACE into the FIFO polled mode. Receiver and
transmitter are controlled separately. Therefore, either or both can be in the polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receiver
and transmitter FIFOs still have the capability of holding characters. The LSR must be read to determine the
ACE status.
interrupt enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INT0 or
INT1) output. All interrupts are disabled by clearing IER0 – IER3. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are described in Table 3 and in the following bulleted list.
Bit 0: IER0, when set, enables the received data available interrupt and the time-out interrupts in the FIFO
mode.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
interrupt enable register (IER) (continued)
Bit 1: IER1, when set, enables the THRE interrupt.
Bit 2: IER2, when set, enables the receiver line status interrupt.
Bit 3: IER3, when set, enables the modem status interrupt.
Bits 4 – 7: IER4 – IER7 are always cleared.
interrupt identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels. The four levels of interrupt conditions are shown in the following bulleted list:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character time out
Priority 3 –Transmitter holding register empty
Priority 4–Modem status (lowest priority)
Information indicating that a prioritized interrupt is pending and the type of interrupt is stored in the IIR. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
FIFO
MODE
ONLY
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
PRIORITY
LEVEL
INTERRUPT RESET
CONTROL
BIT 3
BIT 2 BIT 1 BIT 0
INTERRUPT TYPE
INTERRUPT SOURCE
0
0
0
0
1
1
0
1
0
1
0
0
–
None
None
OE, PE, FE, or BI
–
First
Receiver line status
LSR read
Second
Received data available Receiver data available or trigger level
reached
RBR read until FIFO
drops below the
trigger level
1
1
0
0
Second
Character time-out
indication
No characters have been removed
from or input to the receiver FIFO
during the last four character times and
there is at least one character in it
during this time.
RBR read
0
0
0
0
1
0
0
0
Third
THRE
THRE
IIR read if THRE is
the interrupt source
or THR write
Fourth
Modem status
CTS, DSR, RI, or DCD
MSR read
Bit 0: IIR0 indicates whether an interrupt is pending. When IIR0 is cleared, an interrupt is pending.
Bits 1 and 2: IIR1 and IIR2 identify the highest priority interrupt pending as indicated in Table 5.
Bit 3: IIR3 is always cleared when in the TL16C450 mode. This bit is set along with bit 2 when in the FIFO
mode and a trigger change level interrupt is pending.
Bits 4 and 5: IIR4 and IIR5 are always cleared.
Bits 6 and 7: IIR6 and IIR7 are set when FCR0=1.
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line control register (LCR)
The format of the data character is controlled by the LCR. The LCR may be read. Its contents are described
in the following bulleted list and shown in Figure 17.
Bits 0 and 1: LCR0 and LCR1 are the word length select bits. The number of bits in each serial character
is programmed as shown in Figure 17.
Bit 2: LCR2 is the stop bit select bit. LCR2 specifies the number of stop bits in each transmitted character
as shown in Figure 17. The receiver always checks for one stop bit.
Bit 3: LCR3 is the parity enable bit 3. When LCR3 is high, a parity bit between the last data word bit and
stop bit is generated and checked.
Bit 4: LCR4 is the even parity select bit 4. When enabled, setting this bit selects even parity.
Bit 5: LCR5 is the stick parity bit 5. When parity is enabled (LCR3=1), LCR5=1 causes the transmission
and reception of a parity bit to be in the opposite state from the value of LCR4. This forces parity to a known
state and allows the receiver to check the parity bit in a known state.
Bit 6: LCR6 is the break control bit 6. When LCR6 is set, the serial output (SOUT1 and SOUT0) is forced
to the spacing state (low). The break control bit acts only on the serial output and does not affect the
transmitter logic. When the following sequence is used, no invalid characters are transmitted because of
the break:
Step 1. Load a zero byte in response to the transmitter holding register empty (THRE) status indication.
Step 2. Set the break in response to the next THRE status indication.
Step 3. Wait for the transmitter to be idle when transmitter empty status signal is set high (TEMT=1). Then
clear the break when the normal transmission has to be restored.
Bit 7: LCR7 is the divisor latch access bit (DLAB) bit 7. Bit 7 must be set to access the divisor latches DLL
and DLM of the baud rate generator during a read or write operation. LCR7 must be cleared to access the
receiver buffer register, the transmitter holding register or the interrupt enable register.
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
LINE CONTROL REGISTER
LCR LCR LCR LCR LCR LCR LCR LCR
7
6
5
4
3
2
1
0
0 0 = 5 Data Bits
0 1 = 6 Data Bits
1 0 = 7 Data Bits
1 1 = 8 Data Bits
Word Length
Select
0 = 1 Stop Bits
1 = 1.5 Stop Bits if 5 Data Bits Selected
2 Stop Bits if 6, 7, 8 Data Bits Selected
Stop Bit
Select
0 = Parity Disabled
1 = Parity Enabled
Parity Enable
0 = Odd Parity
1 = Even Parity
Even Parity
Select
0 = Stick Parity Disabled
1 = Stick Parity Enabled
Stick Parity
0 = Break Disabled
1 = Break Enabled
Break Control
Divisor Latch
Access Bit
0 = Access Receiver Buffer
1 = Access Divisor Latches
Figure 17. Line Control Register Contents
line printer port (LPT)
The line printer port contains the functionality of the port included in the TL16C452, but offers a hardware
programmable extended mode controlled by the printer enhancement mode (PEMD) terminal. This
enhancement is the addition of a direction control bit, and an interrupt status bit.
register 0 line printer data register (LPD)
The LPD port is either output only or bidirectional, depending on the state of the extended mode terminal and
data direction control bits.
Compatibility mode (PEMD is low). Reads to the LPD register return the last data that was written to the
port. Write operations immediately output data to the PD0–PD7 terminals.
Extended mode (PEMD is high). Read operations return either the data last written to the LPT data register
when the direction bit is cleared to write, or the data that is present on PD0–PD7 when the direction is set
to read. Writes to the LPD register latch data into the output register, but only drive the LPT port when the
direction bit is cleared to write.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line printer port (LPT) (continued)
Table 6 summarizes the possible combinations of extended mode and the direction control bit. In either
case, the bits of the LPD register are defined as follows:
Table 6. Extended Mode and Direction Control Bit Combinations
PEMD
DIR
X
PD0–PD7 FUNCTION
PC/AT mode – output
PS/2 mode – output
PS/2 mode – input
L
H
H
0
1
register 1 read line printer status register
The line printer status (LPS) register is a read-only register that contains interrupt and printer status of the LPT
connector terminals. In Table 7 (in the default column), are the values of each bit after reset in the case of the
printer being disconnected from the port.
Table 7. LPS Register Bit Description
BIT
0
DESCRIPTION
Reserved
Reserved
PRINT
ERR
DEFAULT
1
1
1
†
†
†
†
†
1
2
3
4
SLCT
5
PE
6
ACK
7
BSY
†
Outputs are dependent upon device inputs.
Bits 0 and 1: These bits are reserved and are always set.
Bit 2: This bit is the printer interrupt (PRINT, active low) status bit. When cleared indicates that the printer
has acknowledged the previous transfer with an ACK handshake (bit 4 of the control register is set). The
bit is cleared on the active to inactive transition of the ACK signal. This bit is set after a read of the status
port.
Bit 3: This bit is the error (ERR, active low) status bit corresponds to ERR input.
Bit 4: This bit is the select (SLCT) status bit corresponds to SLCT input.
Bit 5: This bit is the paper empty (PE) status bit corresponds to PE input.
Bit 6: This bit is the acknowledge (ACK, active low) status bit corresponds to ACK input.
Bit 7: This bit is the busy (BSY, active low) status bit corresponds to BUSY input (active high).
register 2 line printer control (LPC) register
The LPC register is read/write port that controls the PD0–PD7 direction and drive the printer control lines. Write
operations set or clear these bits, while read operations return the state of the last write operation to this register.
The bits in this register are described in Table 8.
PS/2 is a trademark of International Business Machines Corporation.
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line printer port (LPT) (continued)
Table 8. LPC Register Bit Description
BIT
0
DESCRIPTION
STB
1
AFD
2
INIT
3
SLIN
4
INT2 EN
DIR
5
6
Reserved (0)
Reserved (0)
7
Bit 0: This bit is the printer strobe (STB) control bit. When this bit is set, the STB signal is asserted on the
LPT interface. When STB is cleared, the signal is negated.
Bit 1: This bit is the auto feed (AFD) control bit. When this bit is set, the AFD signal is asserted on the LPT
interface. When AFD is cleared, the signal is negated.
Bit 2: This bit is the initialize printer (INIT) control bit. When this bit is set, the INIT signal is negated. When
INIT is cleared, the INIT signal is asserted on the LPT interface.
Bit 3: This bit is the select input (SLIN) control bit. When this bit is set, the SLCT signal is asserted on the
LPT interface. when SLIN is cleared, the signal is negated.
Bit 4: This bit is the interrupt request enable (INT2 EN) control bit. When set, this bit enables interrupts from
the LPT port whenever the ACK signal is released. When cleared, INT2 EN disables interrupts and places
INT2 signal in 3-state.
Bit 5: This bit is the direction (DIR) control bit (only used when PEMD is high). When this bit is set, the output
buffers in the LPD port are disabled allowing data driven from external sources to be read from the LPD port.
When DIR is cleared, the LPD port is in output mode.
line status register (LSR)
The LSR is a single register that provides status indications. The LSR is shown in Table 9 and is described in
the following bulleted list.
Table 9. Line Status Register Bits
LSR BITS
1
Ready
Error
0
LSR0 data ready (DR)
Not ready
No error
LSR1 overrun error (OE)
LSR2 parity error (PE)
LSR3 framing error (FE)
LSR4 break interrupt (BI)
LSR5 THRE
Error
No error
Error
No error
Break
No break
Not empty
Not empty
No error in FIFO
Empty
Empty
Error in FIFO
LSR6 transmitter empty (TEMT)
LSR7 receiver FIFO error
†
LSR is intended only for factory test. It should be considered as read only by applications software.
24
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
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SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
line status register (LSR) (continued)
Bit 0: LSR0 is the data ready (DR) bit. DR is set high when an incoming character has been received and
transferred into the receiver buffer register or the FIFO. LSR0 is cleared by a CPU read of the data in the
receiver buffer register or the FIFO.
Bit 1: SR1 is the overrun error (OE) bit. OE indicates that data in the receiver buffer register was not read
by the CPU before the next character was transferred into the receiver buffer register overwriting the
previous character. The OE indicator is cleared whenever the CPU reads the contents of the LSR. An OE
occurs in the FIFO mode after the FIFO is full and the next character is completely received. The OE is
detected by the CPU on the first LSR read after the overrun happens. The character in the shift register is
not transferred to the FIFO but it is overwritten.
Bit 2: LSR2 is the parity error (PE) bit. PE indicates that the received data character does not have the
correct parity as selected by LCR3 and LCR4. The PE bit is set upon detection of a parity error and is cleared
when the CPU reads the contents of the LSR. In the FIFO mode, the parity error is associated with a
particular character in the FIFO. LSR2 reflects the error when the character is at the top of the FIFO.
Bit 3: LSR3 is the framing error (FE) bit. FE indicates that the received character did not have a valid stop
bit. LSR3 is set when the stop bit following the last data bit or parity bit is detected as a zero bit (spacing
level). The FE indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, the
framing error is associated with a particular character in the FIFO. LSR3 reflects the error when the
character is at the top of the FIFO.
Bit 4: LSR4 is the break interrupt (BI) bit. BI is set when the received data input is held in the spacing
(cleared) state for longer than a full word transmission time (start bit + data bits + parity + stop bits). The
BI indicator is cleared when the CPU reads the contents of the LSR. In the FIFO mode, this is associated
with a particular character in the FIFO. LSR2 reflects the BI when the break character is at the top of the
FIFO. The error is detected by the CPU when its associated character is at the top of the FIFO during the
first LSR read. Only one zero character is loaded into the FIFO when BI occurs.
LSR1 – LSR4 are the error conditions that produce a receiver line status interrupt (priority 1 interrupt in the
interrupt identification register) when any of the conditions are detected. This interrupt is enabled by setting
IER2=1 in the interrupt enable register.
Bit 5: LSR5 is the THRE bit. THRE indicates that the ACE is ready to accept a new character for
transmission. The THRE bit is set when a character is transferred from the transmitter holding register
(THR) into the transmitter shift register (TSR). LSR5 is cleared by the loading of the transmitter holding
register by the CPU. LSR5 is not reset by a CPU read of the LSR. In the FIFO mode when the transmitter
FIFO is empty, this bit is set. It is cleared when one byte is written to the transmitter FIFO. When the THRE
interruptisenabledbyIER1, THREcausesapriority3interruptintheIIR. WhenTHREistheinterruptsource
indicated in IIR, INTRPT is cleared by a read of the IIR.
Bit 6: LSR6 is the transmitter empty (TEMT) bit. TEMT is set when the THR and the TSR are both empty.
LSR6 is cleared when a character is loaded into the THR and remains low until the character is transferred
out of SOUT. TEMT is not cleared by a CPU read of the LSR. In the FIFO mode, when both the transmitter
FIFO and shift register are empty, this bit is set.
Bit 7: LSR7 is the receiver FIFO error bit. The LSR7 bit is always cleared in the TL16C450 mode. In FIFO
mode, it is set when at least one of the following data errors is in the FIFO: PE, FE, or BI indication. It is
cleared when the CPU reads the LSR if there are no subsequent errors in the FIFO.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
master reset
After power up, the ACE RESET input should be held low for one microsecond to reset the ACE circuits to an
idle mode until initialization. A low on RESET causes the following:
1. It initializes the transmitter and receiver clock counters.
2. It clears the LSR, except for TEMT and THRE, which are set. The MCR is also cleared. All of the discrete
lines, memory elements, and miscellaneous logic associated with these register bits are also cleared or
turned off. The LCR, divisor latches, RBR, and transmitter buffer register are not effected.
Following the removal of the reset condition (RESET high), the ACE remains in the idle mode until programmed.
A hardware reset of the ACE sets the THRE and TEMT status bit in the LSR. When interrupts are subsequently
enabled, an interrupt occurs due to THRE. A summary of the affect of a reset on the ACE is given in Table 10.
Table 10. RESET Affects On Registers and Signals
REGISTER/SIGNAL
Interrupt enable register
RESET CONTROL
RESET
All bits cleared (0–3 forced and 4–7
permanent)
Reset
Bit 0 is set, bits 1, 2, 3, 6, and 7 cleared
Bits 4–5 are permanently cleared
Interrupt identification register
Reset
Line control register
Modem control register
FIFO control register
Line status register
Modem status register
SOUT
Reset
Reset
All bits cleared
All bits cleared
Reset
All bits cleared
Reset
All bits cleared, except bits 5 and 6 are set
Reset
Bits 0–3 cleared, bits 4–7 input signal
Reset
High
Interrupt (receiver errs)
Interrupt (receiver data ready)
Interrupt (THRE)
Interrupt (modem status changes)
OUT2
Read LSR/Reset
Read RBR/Reset
Read IIR/Write THR/Reset
Read MSR/Reset
Reset
Cleared
Cleared
Cleared
Cleared
High
Reset
High
RTS
Reset
High
DTR
Reset
High
OUT1
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem control register (MCR)
The MCR controls the interface with the modem or data set as described in Figure 18. The MCR can be written
to and read from. The RTS and DTR outputs are directly controlled by their control bits in this register. A high
input asserts a low (true) at the output terminals. MCR bits 0, 1, 2, 3, and 4 are shown as follows:
MODEM CONTROL REGISTER
MCR MCR MCR MCR MCR MCR MCR MCR
7
6
5
4
3
2
1
0
Data Terminal
Ready
0 = DTR Output High (inactive)
1 = DTR Output Low (active)
Request
to Send
0 = RTS Output High (inactive)
1 = RTS Output Low (active)
0 = OUT1 Output High
1 = OUT1 Output Low
Out 1
0 = OUT2 Output High
1 = OUT2 Output Low
Out 2
0 = Loop Disabled
1 = Loop Enabled
Loop
Bits are Cleared
Figure 18. Modem Control Register Contents
Bit 0: When MCR0 is set, the DTR output is forced low. When MCR0 is cleared, the DTR output is forced
high. The DTR output of the serial channel can be input into an inverting line driver in order to obtain the
proper polarity input at the modem or data set.
Bit 1: When MCR1 is set, the RTS output is forced low. When MCR1 is cleared, the RTS output is forced
high. The RTS output of the serial channel can be input into an inverting line driver to obtain the proper
polarity input at the modem or data set.
Bit 2: When MCR2 is set, OUT1 is forced low.
Bit 3: When MCR3 is set, the OUT2 output is forced low.
Bit 4: MCR4 provides a local loopback feature for diagnostic testing of the channel. When MCR4 is set,
serial output (SOUT) is set to the marking (high) state, and the SIN is disconnected. The output of the TSR
is looped back into the receiver shift register input. The four modem control inputs (CTS, DSR, DCD, and
RI) are disconnected. The modem control outputs (DTR, RTS, OIUT1, and OUT2) are internally connected
tothefourmodemcontrolinputs. Themodemcontroloutputterminalsareforcedtotheirinactivestate(high)
on the TL16C552. In the diagnostic mode, data transmitted is immediately received. This allows the
processor to verify the transmit and receive data paths of the selected serial channel. Interrupt control is
fully operational. However, interrupts are generated by controlling the lower four MCR bits internally.
Interrupts are not generated by activity on the external terminals represented by those four bits.
Bits 5 – 7: These three bits(MCR5 – MCR7) are permanently cleared.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem status register (MSR)
The MSR provides the CPU with status of the modem input lines from the modem or peripheral devices. The
MSR allows the CPU to read the serial channel modem signal inputs by accessing the data bus interface of the
ACE in addition to the current status of four bits of the MSR that indicate whether the modem inputs have
changed since the last reading of the MSR. The delta status bits are set when a control input from the modem
changes state and cleared when the CPU reads the MSR.
The modem input lines are CTS, DSR, RI, and DCD. MSR4 – MSR7 are status indications of these lines. A
status bit = 1 indicates the input is a low. A status bit = 0 indicates the input is high. When the modem status
interrupt in the interrupt enable register is enabled (IER3), an interrupt is generated whenever MSR0 – MSR3
is set. The MSR is a priority 4 interrupt. The contents of the MSR are described in Table 11.
Table 11. Modem Status Register Bits
MSR BIT
MSR0
MSR1
MSR2
MSR3
MSR4
MSR5
MSR6
MSR7
MNEMONIC
∆CTS
∆DSR
TERI
DESCRIPTION
Delta clear to send
Delta data set ready
Trailing edge of ring indicator
Delta data carrier detect
Clear to send
∆DCD
CTS
DSR
Data set ready
RI
Ring indicator
DCD
Data carrier detect
Bit 0: MSR0 is the delta clear to send (∆CTS) bit. ∆CTS displays that the CTS input to the serial channel
has changed state since it was last read by the CPU.
Bit 1: MSR1 is the delta data set ready (∆DSR) bit. ∆DSR indicates that the DSR input to the serial channel
has changed state since the last time it was read by the CPU.
Bit 2: MSR2 is the trailing edge of ring indicator (TERI) bit. TERI indicates that the RI input to the serial
channel has changed states from low to high since the last time it was read by the CPU. High-to-low
transitions on RI do not activate TERI.
Bit 3: MSR3 is the delta data carrier detect (∆DCD) bit. ∆DCD indicates that the DCD input to the serial
channel has changed state since the last time it was read by the CPU.
Bit 4: MSR4 is the clear to send (CTS) bit. CTS is the complement of the CTS input from the modem
indicating to the serial channel that the modem is ready to receive data from SOUT. When the serial channel
is in the loop mode ((MCR4 = 1), MSR4 reflects the value of RTS in the MCR.
Bit 5: MSR5 is the data set ready (DSR) bit. DSR is the complement of the DSR input from the modem to
the serial channel that indicates that the modem is ready to provide received data to the serial channel
receiver circuitry. When the channel is in the loop mode (MCR4=1), MSR5 reflects the value of DTR in the
MCR.
Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RI input. When the channel is in the
loop mode (MCR4=1), MSR6 reflects the value of OUT1 in the MCR.
Bit 7: MSR7 is the data carrier detect (DCD) bit. DCD indicates the status of the data carrier detect (DCD)
input. When the channel is in the loop mode (MCR4=1), MSR7 reflects the value of OUT2 in the MCR.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Reading the MSR register clears the delta modem status indications but has no affect on the other status bits.
For LSR and MSR, the setting of status bits is inhibited during status register read operations. When a status
condition is generated during a read IOR operation, the status bit is not set until the trailing edge of the read.
If a status bit is set during a read operation, and the same status condition occurs, that status bit is cleared at
the trailing edge of the read instead of being set again. In the loop back mode, when modem status interrupts
are enabled, the CTS, DSR, RI and DCD input terminals are ignored. However, a modem status interrupt can
still be generated by writing to MCR3 – MCR0. Applications software should not write to the MSR.
parallel port registers
The TL16C552 parallel port can interface to the device to a Centronics-style printer interface. When chip select
2 (CS2) is low, the parallel port is selected. Table 12 shows the registers associated with this parallel port. The
read or write function of the register is controlled by the state of the read (IOR) and write (IOW) terminal as
shown. The read data register allows the microprocessor to read the information on the parallel bus.
The read status register allows the microprocessor to read the status of the printer in the six most significant
bits. The status bits are printer busy BSY, acknowledge(ACK)whichisahandshakefunction, paperempty(PE),
printer selected (SLCT), error (ERR) and printer interrupt (PRINT). The read control register allows the state
of the control lines to be read. The write control register sets the state of the control lines. They are direction
(DIR), interrupt enable (INT2 EN), select in (SLIN), initialize the printer (INIT), autofeed the paper (AFD), and
strobe (STB), which informs the printer of the presence of a valid byte on the parallel bus. The write data register
allows the microprocessor to write a byte to the parallel bus. The parallel port is completely compatible with the
parallel port implementation used in the IBM serial parallel adaptor.
Table 12. Parallel Port Registers
REGISTER BITS
REGISTER
BIT 7
PD7
BSY
0
BIT 6
PD6
ACK
0
BIT 5
PD5
PE
BIT 4
BIT 3
BIT 2
PD2
BIT 1
PD1
1
BIT 0
PD0
1
Read Data
PD4
PD3
Read Status
Read Control
Write Data
SLCT
ERR
SLIN
PD3
PRINT
INIT
DIR
PD5
DIR
INT2 EN
PD4
AFD
PD1
AFD
STB
PD0
STB
PD7
0
PD6
0
PD2
Write Control
INT2 EN
SLIN
INIT
Table 13. Parallel Port Register Select
CONTROL TERMINALS
REGISTER SELECTED
A1
L
A0
L
IOR
L
IOW
H
H
H
H
L
CS2
L
Read data
Read status
Read control
Invalid
L
L
L
H
L
L
L
H
H
L
L
L
H
L
H
H
H
H
L
Write data
Invalid
L
L
L
H
L
L
L
H
H
Write control
Invalid
L
L
H
29
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TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
programmable baud generator
The ACE serial channel contains a programmable baud rate generator that divides the clock (dc to 8 MHz) by
16
any divisor from 1 to (2 –1). The output frequency of the baud rate generator is 16× the data rate (divisor #
= clock ÷ (baud rate × 16)) referred to in this document as RCLK. Two 8-bit divisor latch registers store the divisor
in a 16-bit binary format. These divisor latch registers must be loaded during initialization. Upon loading either
of the divisor latches, a 16-bit baud counter is immediately loaded. This prevents long counts on initial load. The
baud rate generator can use any of three different popular frequencies to provide standard baud rates. These
frequencies are 1.8432 MHz, 3.072 MHz, and 8 MHz. With these frequencies, standard bit rates from 50- to
512-kbits/s are available. Tables 14, 15, and 16 illustrate the divisors needed to obtain standard rates using
these three frequencies.
Table 14. Baud Rates Using a 1.8432-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
–
–
0.026
0.058
–
–
–
–
–
0.690
–
–
–
–
–
–
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
–
2.860
Table 15. Baud Rates Using a 3.072-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
3840
2560
1745
1428
1280
640
320
160
107
96
80
53
40
27
20
10
5
–
–
0.026
0.034
–
–
–
–
0.312
–
–
0.628
–
1.230
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
–
–
–
30
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C552
DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 16. Baud Rates Using a 8.192-MHz Crystal
BAUD RATE
DESIRED
DIVISOR (N) USED TO
GENERATE 16 X CLOCK
PERCENT ERROR DIFFERENCE
BETWEEN DESIRED AND ACTUAL
50
75
110
134.5
150
300
1000
6667
4545
3717
3333
1667
833
417
277
250
208
139
104
69
52
26
13
9
4
2
1
–
0.005
0.010
0.013
0.010
0.020
0.040
0.080
0.080
–
0.160
0.080
0.160
0.644
0.160
0.160
0.160
0.790
2.344
2.344
2.400
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
128000
256000
512000
programming
The serial channel of the ACE is programmed by the control registers: LCR, IER, DLL, DLM, MCR, and FCR.
These control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
receiver
Serial asynchronous data is input into the SIN terminal. The ACE continually searches for a high-to-low
transition
from the idle state. When the transition is detected, a counter is cleared, and counts the 16× clock to 7 1/2, which
is the center of the start bit. The start bit is valid when the SIN is still low. Verifying the start bits prevents the
receiver from assembling a false data character due to a low-going noise spike on the SIN input.
The LCR determines the number of data bits in a character [LCR0, LCR1]. When parity is used LCR3 and the
polarity of parity LCR4 are needed. Status for the receiver is provided in the LSR. When a full character is
received, including parity and stop bits, the data received indication in LSR0 is set. The CPU reads the RBR,
which clears LSR0. If the character is not read prior to a new character transfer from the RSR to the RBR, the
OE status indication is set in LSR1. When there is a PE, the PE bit is set in LSR2. If a stop bit is not detected,
a FE indication is set in LSR3.
When the data into SIN is a symmetrical square wave, the center of the data cells occurs within ±3.125% of the
actual center, providing an error margin of 46.875%. The start bit can begin as much as one 16× clock cycle
prior to being detected.
31
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DUAL ASYCHRONOUS COMMUNICATIONS ELEMENT
WITH FIFO
SLLS102B – DECEMBER 1990 – REVISED MARCH 1996
PRINCIPLES OF OPERATION
scratchpad register
The scratch register is an 8-bit read/write register that has no affect on either channel in the ACE. It is intended
to be used by the programmer to temporarily hold data.
32
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IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor
product or service without notice, and advises its customers to obtain the latest version of relevant information
to verify, before placing orders, that the information being relied on is current and complete.
TI warrants performance of its semiconductor products and related software to the specifications applicable at
the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
device is not necessarily performed, except those mandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death, personal injury, or
severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED
TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS.
Inclusion of TI products in such applications is understood to be fully at the risk of the customer. Use of TI
products in such applications requires the written approval of an appropriate TI officer. Questions concerning
potential risk applications should be directed to TI through a local SC sales office.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards should be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance, customer product design, software performance, or
infringement of patents or services described herein. Nor does TI warrant or represent that any license, either
express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property
right of TI covering or relating to any combination, machine, or process in which such semiconductor products
or services might be or are used.
Copyright 1998, Texas Instruments Incorporated
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