TL16C750CFN [TI]
1 CHANNEL(S), 1Mbps, SERIAL COMM CONTROLLER, PQCC44;
| 型号： | TL16C750CFN |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 1 CHANNEL(S), 1Mbps, SERIAL COMM CONTROLLER, PQCC44 时钟 数据传输 外围集成电路 |
| 文件： | 总35页 (文件大小：509K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
Pin-to-Pin Compatible With the Existing
TL16C550B/C
Register Selectable Sleep Mode and
Low-Power Mode
Programmable 16- or 64-Byte FIFOs to
Reduce CPU Interrupts
Independent Receiver Clock Input
Independently Controlled Transmit,
Receive, Line Status, and Data Set
Interrupts
Programmable Auto-RTS and Auto-CTS
In Auto-CTS Mode, CTS Controls
Transmitter
Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (DC to 1 Mbits Per
Second)
In Auto-RTS Mode, Receiver FIFO Contents
and Threshold Control RTS
Serial and Modem Control Outputs Drive a
RJ11 Cable Directly When Equipment Is on
the Same Power Drop
Capable of Running With All Existing
TL16C450 Software
False Start Bit Detection
After Reset, All Registers Are Identical to
the TL16C450 Register Set
Complete Status Reporting Capabilities
3-State Output CMOS Drive Capabilities for
Bidirectional Data Bus and Control Bus
Up to 16-MHz Clock Rate for Up to 1-Mbaud
Operation
Line Break Generation and Detection
In the TL16C450 Mode, Hold and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
Serial Data
Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (2 –1) and Generates an Internal 16 ×
16
Fully Prioritized Interrupt System Controls
Clock
Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added or
Deleted to or From the Serial Data Stream
Available in 44-Pin PLCC and 64-Pin SQFP
Industrial Temperature Range Available for
64-Pin SQFP
5-V and 3-V Operation
description
The TL16C750 is a functional upgrade of the TL16C550C asynchronous communications element (ACE),
which in turn is a functional upgrade of the TL16C450. Functionally equivalent to the TL16C450 on power up
(character or TL16C450 mode), the TL16C750, like the TL16C550C, can be placed in an alternate mode (FIFO
mode). This relieves the CPU of excessive software overhead by buffering received and transmitted characters.
The receiver and transmitter FIFOs store up to 64 bytes including three additional bits of error status per byte
for the receiver FIFO. The user can choose between a 16-byte FIFO mode or an extended 64-byte FIFO mode.
In the FIFO mode, there is a selectable autoflow control feature that can significantly reduce software overload
and increase system efficiency by automatically controlling serial data flow through the RTS output and the CTS
input signals (see Figure 1).
The TL16C750 performs serial-to-parallel conversion on data received from a peripheral device or modem and
parallel-to-serial conversion on data received from its CPU. The CPU can read the ACE status at any time. The
ACE includes complete modem control capability and a processor interrupt system that can be tailored to
minimize software management of the communications link.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
description (continued)
The TL16C750 ACE includes a programmable baud rate generator capable of dividing a reference clock by
16
divisors from 1 to (2 – 1) and producing a 16× reference clock for the internal transmitter logic. Provisions are
also included to use this 16× clock for the receiver logic. The ACE accommodates a 1-Mbaud serial rate
(16-MHz input clock) so a bit time is 1 µs and a typical character time is 10 µs (start bit, 8 data bits, stop bit).
Two of the TL16C450 terminal functions have been changed to TXRDY and RXRDY, which provide signaling
to a direct memory access (DMA) controller.
FN PACKAGE
(TOP VIEW)
6
5 4 3 2 1
44 43 42 41 40
39
MR
D5
D6
D7
7
OUT1
DTR
RTS
OUT2
NC
8
38
37
36
35
34
9
RCLK
SIN
NC
SOUT
CS0
CS1
10
11
12
13
14
15
16
17
33 INTRPT
32 RXRDY
31
30
29
A0
A1
A2
CS2
BAUDOUT
18 19 20 21 22 23 24 25 26 2728
PM PACKAGE
(TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
XIN
XOUT
NC
D4
NC
D3
D2
NC
D1
D0
NC
V
1
2
47
46
45
44
43
42
41
40
39
38
37
3
WR1
NC
4
5
WR2
NC
6
7
V
SS
8
RD1
9
CC
RD2
NC
RI
10
11
12
13
NC
DDIS
TXRDY
NC
36 DCD
35 DSR
34 NC
NC 14
ADS 15
NC 16
33 CTS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC–No internal connection
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
functional block diagram
S
e
l
e
c
t
Receiver
FIFO
8
Internal
Data Bus
8
Receiver
11
Shift
SIN
9–2
Data
Bus
Receiver
Buffer
Register
D(7–0)
Buffer
Register
10
RCLK
RTS
Receiver
Timing and
Control
Line
Control
Register
36
31
A0
30
29
Divisor
Latch (LS)
A1
A2
Baud
Generator
17
BAUDOUT
Divisor
Latch (MS)
14
CS0
CS1
Autoflow
Control
Enable
(AFE)
15
16
Transmitter
Timing and
Control
Line
Status
Register
CS2
28
39
24
ADS
Select
and
Control
Logic
MR
Transmitter
FIFO
S
e
l
e
c
t
RD1
25
20
21
26
RD2
Transmitter
Shift
Register
Transmitter
Holding
Register
8
8
13
SOUT
WR1
WR2
DDIS
TXRDY
XIN
Modem
Control
Register
8
8
27
18
19
32
40
37
41
42
43
38
35
CTS
DTR
XOUT
RXRDY
Modem
Control
Logic
Modem
Status
Register
DSR
DCD
RI
44
V
OUT1
OUT2
INTRPT
CC
Power
Supply
22
Interrupt
Enable
Register
Interrupt
Control
Logic
8
V
SS
33
Interrupt
Identification
Register
8
FIFO
Control
Register
NOTE A: Terminal numbers shown are for the FN package.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
Terminal Functions
TERMINAL
NO. NO.
I/O
DESCRIPTION
NAME
FN
PM
A0
A1
A2
31
30
29
20
18
17
I
Register select. A0–A2 are used during read and write operations to select the ACE register to read from
or write to. Refer to Table 1 for register addresses and ADS signal description.
ADS
28
15
I
O
I
Addressstrobe. WhenADSisactive(low), theregisterselectsignals(A0, A1, andA2)andchipselectsignals
(CS0, CS1, CS2) drive the internal select logic directly; when ADS is high, the register select and chip select
signals are held at the logic levels they were in when the low-to-high transition of ADS occurred.
BAUDOUT
17
64
Baudout. BAUDOUTisa16× clocksignalforthetransmittersectionoftheACE. Theclockrateisestablished
by the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches.
BAUDOUT can also be used for the receiver section by tying this output to RCLK.
CS0
CS1
CS2
14
15
16
59
61
62
Chip select. When CS0 and CS1 are high and CS2 is low, the ACE is selected. When any of these inputs
are inactive, the ACE remains inactive. Refer to the ADS signal description.
CTS
40
33
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the
modem status register. Bit 0 (∆CTS) of the modem status register indicates that CTS has changed states
since the last read from the modem status register. When the modem status interrupt is enabled, CTS
changes states, and the auto-CTS mode is not enabled, an interrupt is generated. CTS is also used in the
auto-CTS mode to control the transmitter.
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
42
43
45
46
48
50
51
52
I/O Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the ACE and the CPU. As inputs, they use fail safe CMOS compatible input buffers.
DCD
42
36
I
Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of
themodemstatusregister. Bit 3 (∆DCD)ofthemodemstatusregisterindicatesthatDCDhaschangedstates
since the last read from the modem status register. When the modem status interrupt is enabled and DCD
changes state, an interrupt is generated.
DDIS
DSR
26
41
12
35
O
I
Driver disable. DDIS is active (high) when the CPU is not reading data. When active, DDIS can disable an
external transceiver.
Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the
modem status register. Bit 1 (∆DSR) of the modem status register indicates DSR has changed states since
the last read from the modem status register. When the modem status interrupt is enabled and the DSR
changes states, an interrupt is generated.
DTR
37
33
39
28
23
32
O
O
Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to one.
DTR is placed in the inactive condition either as a result of a master reset, during loop mode operation, or
clearing the DTR bit.
INTRPT
Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data that is available or timed
out (FIFO mode only), an empty transmitter holding register, or an enabled modem status interrupt. INTRPT
is reset (deactivated) either when the interrupt is serviced or as a result of a master reset.
MR
I
Master reset. When active (high), MR clears most ACE registers and sets the levels of various output signals
(refer to Table 2).
OUT1
OUT2
38
35
30
25
O
Outputs 1 and 2. These are user-designated output terminals that are set to their active (low) level by setting
their respective modem control register (MCR) bits (OUT1 and OUT2). OUT1 and OUT2 are set to their
inactive (high) level as a result of master reset, during loop mode operations, or by clearing bit 2 (OUT1) or
bit 3 (OUT2) of the MCR.
RCLK
10
54
I
Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
Terminal Functions (Continued)
TERMINAL
NO. NO.
I/O
DESCRIPTION
NAME
FN
PM
RD1
RD2
24
25
9
10
I
Read inputs. When either RD1 or RD2 is active (low or high respectively) while the ACE is selected, the CPU
is allowed to read status information or data from a selected ACE register. Only one of these inputs is required
for the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied
low or RD1 tied high).
RI
43
36
32
38
26
21
I
Ring indicator. RI is a modem status signal. Its condition can be checked by reading bit 6 (RI) of the modem
status register. Bit 2 (TERI) of the modem status register indicates that RI has transitioned from a low to a high
level since the last read from the modem status register. If the modem status interrupt is enabled when this
transition occurs, an interrupt is generated.
RTS
RXRDY
O
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive data. RTS
is set to its active level by setting the RTS MCR bit and is set to its inactive (high) level either as a result of a
master reset, during loop mode operations, or by clearing bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS
is set to its inactive level by the receiver threshold control logic.
Receiver ready. Receiver direct memory access (DMA) signalling is available with RXRDY. When operating
in the FIFO mode, one of two types of DMA signalling can be selected through the FIFO control register bit
3 (FCR3). When operating in the TL16C450 mode, only DMA mode 0 is allowed. Mode 0 supports
single-transferDMA in which a transfer is made between CPU bus cycles. Mode 1 supports multitransfer DMA
in which multiple transfers are made continuously until the receiver FIFO has been emptied. In DMA mode 0
(FCR0 = 0 or FCR0 = 1, FCR3 = 0), when there is at least one character in the receiver FIFO or receiver holding
register, RXRDY is active (low). When RXRDY has been active but there are no characters in the FIFO or
holding register, RXRDY goes inactive (high). In DMA mode 1 (FCR0 = 1, FCR3 = 1), when the trigger level
or the timeout has been reached, RXRDY goes active (low); when it has been active but there are no more
characters in the FIFO or holding register, it goes inactive (high).
SIN
11
13
55
58
I
Serial data. SIN is the input from a connected communications device.
SOUT
O
Composite serial data output to a connected communication device. SOUT is set to the marking (high) level
as a result of master reset.
TXRDY
27
13
O
Transmitter ready. Transmitter DMA signalling is available with TXRDY. When operating in the FIFO mode,
one of two types of DMA signalling can be selected through FCR3. When operating in the TL16C450 mode,
only DMA mode 0 is allowed. Mode 0 supports single-transfer DMA in which a transfer is made between CPU
bus cycles. Mode 1 supports multitransfer DMA in which multiple transfers are made continuously until the
transmit FIFO has been filled.
V
V
44
22
40
8
5-V supply voltage
Supply common
CC
SS
WR1
WR2
20
21
4
6
I
Write inputs. When either input is active (low or high respectively) and while the ACE is selected, the CPU is
allowed to write control words or data into a selected ACE register. Only one of these inputs is required to
transfer data during a write operation; the other input should be tied in its inactive state (i.e., WR2 tied low or
WR1 tied high).
XIN
XOUT
18
19
1
2
I/O External clock. XIN and XOUT connect the ACE to the main timing reference (clock or crystal).
detailed description
autoflow control
Auto-flow control is composed of auto-CTS and auto-RTS. With auto-CTS, CTS must be active before the
transmit FIFO can emit data (see Figure 1). With auto-RTS, RTS becomes active when the receiver is empty
or the threshold has not been reached. When RTS is connected to CTS, data transmission does not occur
unless the receive FIFO has empty space. Thus, overrun errors are eliminated when ACE1 and ACE2 are
TLC16C750s with enabled autoflow control. If not, overrun errors occur if the transmit data rate exceeds the
receive FIFO read latency.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
autoflow control (continued)
ACE1
ACE2
Parallel
SIN
SOUT
CTS
Serial to
Parallel
to Serial
RCV
FIFO
XMT
FIFO
RTS
Flow
Flow
Control
Control
D7–D0
D7–D0
SOUT
CTS
SIN
Parallel
to Serial
Serial to
Parallel
XMT
FIFO
RCV
FIFO
RTS
Flow
Flow
Control
Control
Figure 1. Autoflow Control (auto-RTS and auto-CTS) Example
auto-RTS (see Figure 1)
Auto-RTS data flow control originates in the receiver timing and control block (see functional block diagram)
andislinkedtotheprogrammedreceiverFIFOtriggerlevel. WhenthereceiverFIFOlevelreachesatriggerlevel
of 1, 4, 8, or 14 in 16-byte mode or 1, 16, 32, or 56 in 64-byte mode, RTS is deasserted. The sending ACE may
send an additional byte after the trigger level is reached (assuming the sending ACE has another byte to send)
because it may not recognize the deassertion of RTS until after it has begun sending the additional byte. RTS
is automatically reasserted once the receiver FIFO is emptied by reading the receiver buffer register. The
reassertion signals the sending ACE to continue transmitting data.
auto-CTS (see Figure 1)
The transmitter circuitry checks CTS before sending the next data byte. When CTS is active, the transmitter
sends the next byte. To stop the transmitter from sending the following byte, CTS must be released before the
middle of the last stop bit that is currently being sent. The auto-CTS function reduces interrupts to the host
system. When flow control is enabled, the CTS state changes and does not trigger host interrupts because the
device automatically controls its own transmitter. Without auto-CTS, the transmitter sends any data present in
the transmit FIFO and a receiver overrun error can result.
enabling auto-RTS and auto-CTS
The auto-RTS and auto-CTS modes of operation are activated by setting bit 5 of the modem control register
(MCR) to 1 (see Figure 2).
Start Bits 0–7
Start Bits 0–7
Start Bits 0–7
Stop
Stop
Stop
SOUT
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. When CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but
it does not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 2. CTS Functional Timing
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
enabling auto-RTS and auto-CTS (continued)
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes for the 16-byte mode and 1, 16, 32, or 56 bytes
for 64-byte mode (see Figure 3).
Start
Byte N
Start Byte N+1
Start
Byte
Stop
Stop
Stop
SIN
RTS
RD
(RD RBR)
1
2
N
N+1
NOTES: A. N = receiver FIFO trigger level
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in auto-RTS.
Figure 3. RTS Functional Timing, Receiver FIFO Trigger Level
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V
CC
Input voltage range, V : Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
I
CC
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Output voltage range, V : Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V + 0.5 V
O
CC
Fail safe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
OK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
O O CC
Operating free-air temperature range, T
Operating free-air temperature range, T (TL16C750I) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This applies for external input and bidirectional buffers. V > V
does not apply to fail safe terminals.
does not apply to fail safe terminals.
CC
I
CC
2. This applies for external output and bidirectional buffers. V > V
O
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
recommended operating conditions
low voltage (3.3 V nominal)
MIN
3
NOM
MAX
UNIT
V
Supply voltage, V
3.3
3.6
CC
Input voltage, V
0
V
CC
V
I
High-level input voltage, V (see Note 3)
IH
0.7 V
V
CC
Low-level input voltage, V (see Note 3)
IL
0.3 V
V
CC
Output voltage, V (see Note 4)
0
V
CC
V
O
High-level output current, I
(all outputs)
1.8
3.2
1
mA
mA
pF
°C
°C
MHz
OH
(all outputs)
Low-level output current, I
OL
Input capacitance, c
I
Operating free-air temperature, T
0
0
25
25
70
A
Junction temperature range, T (see Note 5)
J
115
14
Oscillator/clock speed
NOTES: 3. Meets TTL levels, V
= 2 V and V = 0.8 V on nonhysteresis inputs
ILmax
IHmin
4. Applies for external output buffers
5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
standard voltage (5 V nominal)
MIN
4.75
0
NOM
MAX
UNIT
V
Supply voltage, V
5
5.25
CC
Input voltage, V
V
CC
V
I
High-level input voltage, V
0.7 V
V
IH
CC
Low-level input voltage, V
0.2 V
V
IL
Output voltage, V (see Note 4)
CC
0
V
CC
V
O
High-level output current, I
(all outputs)
4
4
mA
mA
pF
°C
°C
MHz
OH
(all outputs)
Low-level output current, I
OL
Input capacitance, c
1
I
Operating free-air temperature, T
0
0
25
25
70
A
Junction temperature range, T (see Note 5)
J
115
16
Oscillator/clock speed
NOTES: 4. Applies for external output buffers
5. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150°C. The customer is
responsible for verifying junction temperature.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
low voltage (3.3 V nominal)
PARAMETER
TEST CONDITIONS
MIN
V –0.55
CC
MAX
UNIT
V
†
V
V
High-level output voltage
I
I
= –1.8 mA
= 3.2 mA
OH
OH
†
Low-level output voltage
0.5
±10
–1
1
V
OL
OL
I
I
I
High-impedance 3-state output current (see Note 6)
Low-level input current (see Note 7)
V = V
I
or GND
µA
µA
µA
OZ
CC
V = GND
I
IL
High-level input current (see Note 8)
V = V
I CC
IH
†
For all outputs except XOUT
NOTES: 6. The 3-state or open-drain output must be in the high-impedance state.
7. Specifications only apply with pullup termination turned off.
8. Specifications only apply with pulldown termination turned off.
standard voltage (5 V nominal)
PARAMETER
TEST CONDITIONS
MIN
V –0.8
CC
MAX
UNIT
V
†
V
V
High-level output voltage
I
I
= –4 mA
= 4 mA
OH
OH
†
Low-level output voltage
0.5
±10
–1
1
V
OL
OL
I
I
I
High-impedance 3-state output current (see Note 6)
Low-level input current (see Note 7)
V = V
I
or GND
µA
µA
µA
OZ
CC
V = GND
I
IL
High-level input current (see Note 8)
V = V
I CC
IH
†
For all outputs except XOUT
NOTES: 6. The 3-state or open-drain output must be in the high-impedance state.
7. Specifications only apply with pullup termination turned off.
8. Specifications only apply with pulldown termination turned off.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
ALT. SYMBOL FIGURE TEST CONDITIONS
MIN
87
87
25
25
9
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Cycle time, read (t
+ t + t
w7 d8 d9
)
RC
cR
cW
w1
w2
w5
w6
w7
w8
su1
su2
su3
su4
h1
Cycle time, write (t
+ t + t
w6 d5 d6
)
WC
Pulse duration, clock (XIN) high
Pulse duration, clock (XIN) low
Pulse duration, ADS low
Pulse duration, write strobe
Pulse duration, read strobe
Pulse duration, MR
t
4
4
f = 16 MHz maximum
f = 16 MHz maximum
XH
t
XL
t
5, 6
5
ADS
t
40
40
1
WR
t
6
RD
t
MR
Setup time, address valid before ADS↑
Setup time, CS valid before ADS↑
Setup time, data valid before WR1↓
t
5, 6
5, 6
5
8
AS
CS
DS
t
8
↑
t
15
†
Setup time,
↑ before midpoint of stop bit
16
5, 6
5, 6
5
10
Hold time, address low after ADS↑
Hold time, CS valid after ADS↑
Hold time, CS valid after WR1↑
Hold time, address valid after WR1↑
Hold time, data valid after WR1↑
t
0
0
AH
CH
t
h2
↓
t
10
10
5
h3
WCS
†
↓
t
5
h4
h5
h6
h7
d4
d5
d6
d7
d8
d9
WA
↓
t
5
DH
Hold time, CS valid after RD1↑ or RD2↓
t
6
10
20
7
RCS
†
†
Hold time, address valid after RD1↑ or RD2↓
Delay time, CS valid before WR1↓ or WR2↑
Delay time, address valid before WR1↓ or WR2↑
Delay time, write cycle, WR1↑ or WR2↓ to ADS↓
Delay time, CS valid to RD1↓ or RD2↑
t
6
RA
t
5
CSW
t
5
7
AW
†
†
†
t
5
40
7
WC
t
6
CSR
Delay time, address valid to RD1↓ or RD2↑
Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
Delay time, RD1↓ or RD2↑ to data valid
t
6
7
AR
tRC
6
40
45
20
t
6
C
C
= 75 pF
= 75 pF
d10
d11
RVD
L
L
Delay time, RD1↑ or RD2↓ to floating data
t
6
HZ
†
Only applies when ADS is low
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 9)
PARAMETER
Disable time, RD1↓↑
NOTE 9: Charge and discharge times are determined by V , V
ALT. SYMBOL
FIGURE TEST CONDITIONS
= 75 pF
MIN
MAX
UNIT
t
↑↓ to DDIS↑↓
t
6
C
L
20
ns
dis(R)
RDD
, and external loading.
OL OH
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C = 75 pF
L
PARAMETER
ALT. SYMBOL
FIGURE TEST CONDITIONS
MIN
50
MAX
UNIT
ns
t
t
t
t
Pulse duration, BAUDOUT low
Pulse duration, BAUDOUT high
Delay time, XIN↑ to BAUDOUT↑
Delay time, XIN↑↓ to BAUDOUT↓
t
4
4
4
4
f = 16 MHz, CLK ÷ 2
f = 16 MHz, CLK ÷ 2
w3
w4
d1
d2
LW
t
50
ns
HW
t
45
45
ns
BLD
t
ns
BHD
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
commercial maximum switching characteristics, V
= 4.75 V, T = 115°C
J
CC
INTRINSIC
DELAY
(ns)
DELTA
DELAY
(ns/pF)
DELAY (ns)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
= 15 pF
C
= 50 pF = 85 pF
C
C = 100 pF
L
L
L
L
t
t
–0.92
–0.79
0.571
7.65
3.89
27.66
14.83
40.42
20.90
47.66
25.76
69.98
36.34
56.23
30.45
82.65
42.95
PLH
XIN
XO
0.312
PHL
t
r
Output rise time, XO
Output fall time, XO
10.86
5.47
t
f
commercial maximum switching characteristics, V
= 3 V, T = 115°C
J
CC
INTRINSIC
DELAY
(ns)
DELTA
DELAY
(ns/pF)
DELAY (ns)
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
C
= 15 pF
C
= 50 pF = 85 pF
C
C = 100 pF
L
L
L
L
t
t
–4.69
–3.05
1.017
10.57
3.58
46.16
81.75
34.51
97.00
41.13
PLH
XIN
XO
0.442
19.04
64.87
26.53
PHL
t
r
Output rise time, XO
Output fall time, XO
14.39
5.06
115.35
48.01
136.98
57.21
t
f
receiver switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 10)
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN
MAX
UNIT
t
t
Delay time, RCLK to sample clock
t
7
10
ns
d12
SCD
Delay time, stop to set receiver error inter-
rupt or read RBR to LSI interrupt or stop to
RXRDY↓
7, 8, 9,
10, 11
RCLK
cycle
t
2
d13
SINT
Delay time, read RBR/LSR low to reset
interrupt low
7, 8, 9,
10, 11
t
t
C
= 75 pF
L
120
ns
d14
RINT
NOTE 10: In the FIFO mode, the read cycle (RC) = 425 ns (minimum) between reads of the receive FIFO and the status registers (interrupt
identification register or line status register).
transmitter switching characteristics over recommended ranges of supply voltage and operating
free-air temperature
†
PARAMETER
ALT. SYMBOL
FIGURE
TEST CONDITIONS
MIN MAX
UNIT
baudout
cycles
t
Delay time, INTRPT to transmit start
t
12
8
8
24
d15
IRS
baudout
cycles
t
t
t
Delay time, start to interrupt
t
12
12
12
10
50
34
d16
d17
d18
STI
Delay time, WR THR to reset interrupt
Delay time, initial write to interrupt (THRE)
t
C
= 75 pF
ns
HR
L
baudout
cycles
t
SI
16
t
t
Delay time, read IIR to reset interrupt (THRE)
Delay time, write to TXRDY inactive
t
12
C
C
= 75 pF
= 75 pF
70
75
ns
ns
d19
IR
L
L
t
t
13, 14
d20
WXI
baudout
cycles
t
13, 14
C
= 75 pF
9
Delay time, start to TXRDY active
d21
SXA
L
†
THRE = transmitter holding register empty, IIR = interrupt identification register.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
modem control switching characteristics over recommended ranges of supply voltage and
operating free-air temperature, C = 75 pF
L
PARAMETER
ALT. SYMBOL
FIGURE
15
MIN
MAX
60
UNIT
ns
t
t
t
Delay time, WR MCR to output
t
MDO
d22
d23
d24
Delay time, modem interrupt to set interrupt
Delay time, RD MSR to reset interrupt
t
15
35
ns
SIM
t
15
45
ns
RIM
baudout
cycles
t
t
t
Delay time, CTS low to SOUT↓
16
17
17
24
2
d25
d26
d27
baudout
cycles
Delay time, receiver threshold byte to RTS↑
Delay time, read of last byte in receive FIFO to RTS↓
baudout
cycles
3
PARAMETER MEASUREMENT INFORMATION
N
t
t
w2
w1
XIN
t
d2
t
d1
BAUDOUT
(1/1)
t
d1
t
d2
BAUDOUT
(1/2)
t
w3
t
w4
BAUDOUT
(1/3)
BAUDOUT
(1/N)
(N > 3)
2 XIN Cycles
(N–2) XIN Cycles
Figure 4. Baud Generator Timing Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w5
50%
50%
50%
50%
ADS
t
su1
t
h1
†
Valid
A0–A2
50%
Valid
50%
t
su2
t
h2
†
Valid
CS0, CS1, CS2
50%
50%
Valid
t
h3
t
w6
t
d4
†
t
h4
t
d5
t
d6
WR1, WR2
D7–D0
50%
50%
Active
t
su3
t
h5
Valid Data
†
Applicable only when ADS is low
Figure 5. Write Cycle Timing Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
t
w5
50%
50%
50%
ADS
t
su1
t
h1
†
A0–A2
Valid
Valid
50%
su2
50%
50%
t
t
h2
†
50%
50%
Valid
CS0, CS1, CS2
Valid
50%
t
h6
t
w7
†
t
d7
†
t
h7
t †
d8
t
d9
50%
50%
RD1, RD2
DDIS
Active
t
dis(R)
t
dis(R)
50%
50%
t
d10
t
d11
Valid Data
D7–D0
†
Applicable only when ADS is low
Figure 6. Read Cycle Timing Waveforms
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
RCLK
t
d12
8 Clocks
Sample Clock
TL16C450 Mode:
SIN
Start
Data Bits 5–8
Parity
Stop
Sample Clock
INTRPT
(data ready)
50%
50%
t
d13
t
d14
INTRPT
(receiver error)
50%
50%
RD1, RD2
(read RBR)
50%
Active
RD1, RD2
(read LSR)
50%
Active
t
d14
Figure 7. Receiver Timing Waveforms
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
SIN
Data Bits 5–8
Stop
Sample Clock
(FIFO at or above
trigger level)
Trigger Level
INTRPT
(FCR6, 7 = 0, 0)
50%
50%
50%
(FIFO below
trigger level)
t
d13
(see Note A)
t
d14
Line Status
INTRPT
(LSI)
50%
t
d14
RD1
(RD LSR)
Active
50%
Active
RD1
(RD RBR)
50%
NOTE A: For a time-out interrupt, t
= 9 RCLKs.
d13
Figure 8. Receive FIFO First Byte (Sets DR Bit) Waveforms
SIN
Stop
Sample Clock
(FIFO at or above
trigger level)
Time-Out or
Trigger Level
INTRPT
50%
50%
(FIFO below
trigger level)
t
d13
(see Note A
t
)
d14
50%
50%
Line Status
Top Byte of FIFO
INTRPT (LSI)
t
d13
t
d14
RD1, RD2
(RD LSR)
50%
50%
RD1, RD2
(RD RBR)
50%
Active
Active
Previous Byte
Read From FIFO
NOTE A: For a time-out interrupt, t
= 9 RCLKs.
d13
Figure 9. Receive FIFO Bytes Other Than the First Byte (DR Internal Bit Already Set) Waveforms
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
RD
(RD RBR)
50%
Active
See Note A
SIN
Stop
(first byte)
Sample Clock
t
d13
(see Note B)
t
d14
50%
50%
RXRDY
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, t = 9 RCLKs.
d13
Figure 10. Receiver Ready (RXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
RD
(RD RBR)
Active
50%
See Note A
SIN
(first byte that reaches
the trigger level)
Sample Clock
t
d13
(see Note B)
t
d14
50%
50%
RXRDY
NOTES: A. This is the reading of the last byte in the FIFO.
B. For a time-out interrupt, t = 9 RCLKs.
d13
Figure 11. Receiver Ready (RXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Start
50%
Start
50%
Data Bits
50%
Parity
Stop
t
SOUT
t
d15
d16
INTRPT
(THRE)
50%
50%
50%
50%
t
d18
t
d17
t
d17
WR THR
50%
50%
50%
t
d19
RD IIR
50%
Figure 12. Transmitter Timing Waveforms
Byte #1
50%
WR
(WR THR)
Start
50%
SOUT
Data
Parity
Stop
t
t
d21
d20
TXRDY
50%
50%
Figure 13. Transmitter Ready (TXRDY) Waveforms, FCR0 = 0 or FCR0 = 1 and FCR3 = 0 (Mode 0)
Byte #16
WR
50%
(WR THR)
Start
50%
SOUT
Data
Parity
Stop
t
t
d21
d20
TXRDY
50%
50%
FIFO Full
Figure 14. Transmitter Ready (TXRDY) Waveforms, FCR0 = 1 and FCR3 = 1 (Mode 1)
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
WR
(WR MCR)
50%
50%
50%
t
d22
t
d22
RTS, DTR,
OUT1, OUT2
50%
50%
CTS, DSR, DCD
t
d23
INTRPT
(modem)
50%
50%
50%
t
d24
t
d23
RD2
(RD MSR)
50%
RI
50%
Figure 15. Modem Control Timing Waveforms
t
su4
CTS
50%
50%
t
d25
50%
SOUT
Midpoint of Stop Bit
Figure 16. CTS and SOUT Autoflow Control Timing (Start and Stop) Waveforms
Midpoint of Stop Bit
SIN
t
t
d27
d26
50%
50%
RTS
50%
RBRRD
Figure 17. Auto-RTS Timing for Receiver Threshold at All Trigger Levels Waveforms
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PARAMETER MEASUREMENT INFORMATION
SOUT
SIN
D7–D0
D7–D0
MEMR or I/OR
MEMW or I/ON
INTR
RTS
DTR
DSR
DCD
CTS
RI
RD1
EIA
WR1
232-D Drivers
and Receivers
INTRPT
RESET
A0
C
P
U
MR
A0
TL16C750
(ACE)
A1
A2
A1
A2
B
U
S
ADS
WR2
RD2
XIN
3.072 MHz
L
CS
CS2
CS1
CS0
XOUT
BAUDOUT
RCLK
H
Figure 18. Basic TL16C750 Configuration
APPLICATION INFORMATION
Receiver Disable
WR
WR1
TL16C750
(ACE)
Microcomputer
System
Data Bus
Data Bus
D7–D0
8-Bit
Bus Transceiver
DDIS
Driver Disable
Figure 19. Typical Interface for a High-Capacity Data Bus
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
APPLICATION INFORMATION
Alternate
TL16C750
Crystal Control
18
XIN
A16–A23
A16–A23
19
17
10
XOUT
14
15
16
BAUDOUT
RCLK
CS0
CS1
CS2
Address
Decoder
CPU
37
36
38
35
20
1
DTR
RTS
28
ADS
ADS
OUT1
OUT2
39
RSI/ABT
MR
A0–A2
AD0–AD7
Buffer
D0–D2
43
42
41
40
AD0–AD15
PHI1 PHI2
RI
8
6
5
DCD
DSR
CTS
ADS RSTO
RD
PHI1 PHI2
24
20
RD1
13
TCU
SOUT
2
3
WR1
WR
11
33
27
26
32
SIN
INTRPT
AD0–AD15
TXRDY
DDIS
25
21
RD2
7
1
WR2
RXRDY
EIA-232-D
Connector
22
44
GND
(V
SS
)
5 V
(V
CC
)
NOTE A: Terminal numbers shown are for the FN package.
Figure 20. Typical TL16C750 Connection to a CPU
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
Table 1. Register Selection
†
DLAB
A2
L
A1
L
A0
L
REGISTER
0
0
Receiver buffer (read), transmitter holding register (write)
Interrupt enable register
Interrupt identification register (read only)
FIFO control register (write)
Line control register
L
L
H
L
X
X
X
X
X
X
X
1
L
H
H
H
L
L
L
L
H
L
H
H
H
H
L
Modem control register
L
H
L
Line status register
H
H
L
Modem status register
H
L
Scratch register
Divisor latch (LSB)
1
L
L
H
Divisor latch (MSB)
†
Thedivisorlatchaccessbit(DLAB)isthemostsignificantbitofthelinecontrolregister.TheDLABsignal
is controlled by writing to this bit location (see Table 3).
Table 2. ACE Reset Functions
RESET
REGISTER/SIGNAL
Interrupt Enable Register
RESET STATE
CONTROL
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR/MR
Read RBR/MR
All bits cleared (0–5 forced and 6–7 permanent)
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
SOUT
Bit 0 is set, bits 1–4 are cleared, and bits 5–7 are cleared
All bits cleared
All bits cleared
All bits cleared (6–7 permanent)
Bits 5 and 6 are set, all other bits are cleared
Bits 0–3 are cleared, bits 4–7 are input signals
High
Low
Low
INTRPT (receiver error flag)
INTRPT (received data available)
INTRPT (transmitter holding register empty)
INTRPT (modem status changes)
OUT2
Read IR/Write THR/MR Low
Read MSR/MR
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Low
High
RTS
High
DTR
High
OUT1
High
Scratch Register
No effect
No effect
No effect
No effect
Divisor Latch (LSB and MSB) Registers
Receiver Buffer Registers
Transmitter Holding Registers
MR/FCR1–FCR0/
Receiver FIFO
XMIT FIFO
All bits cleared
All bits cleared
∆FCR0
MR/FCR2–FCR0/
∆FCR0
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
accessible registers
The system programmer, through the CPU, has access to and control over any of the ACE registers. These
registers control ACE operations, receive data, and transmit data. Descriptions of these registers follow in
Table 3.
Table 3. Summary of Accessible Registers
REGISTER ADDRESS
0 DLAB = 0
0 DLAB = 0
1 DLAB = 0
2
2
3
4
5
6
7
0 DLAB = 1
1 DLAB = 1
Receiver
Buffer
Register
(Read
Transmitter
Holding
Register
(Write
Interrupt
Ident.
Register
(Read
FIFO
Control
Register
(Write
Bit
No.
Interrupt
Enable
Register
Line
Control
Register
Modem
Control
Register
Line
Status
Register
Modem
Status
Register
Divisor
Latch
(LSB)
Scratch
Register
Latch
(MSB)
Only)
Only)
Only)
Only)
RBR
THR
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
DLL
DLM
Enable
Received
Data
Available
Interrupt
(ERBI)
Word
Length
Select
Bit 0
Delta
Clear
to Send
Data
Terminal
Ready
(DTR)
0 when
interrupt
Pending
Data
Ready
(DR)
FIFO
Enable
†
0
1
Data Bit 0
Data Bit 0
Bit 0
Bit 0
Bit 8
(∆CTS)
(WLS0)
Enable
Transmitter
Holding
Register
Empty
Delta
Data
Set
Word
Length
Select
Bit 1
Interrupt
ID
Bit 1
Receiver
FIFO
Reset
Request
to Send
(RTS)
Overrun
Error
(OE)
Data Bit 1
Data Bit 1
Bit 1
Bit 1
Bit 9
Ready
Interrupt
(ETBEI)
(WLS1)
(∆DSR)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Trailing
Edge Ring
Indicator
(TERI)
Number
of
Stop Bits
(STB)
Interrupt
ID
Bit 2
Transmitter
FIFO
Reset
Parity
Error
(PE)
2
3
Data Bit 2
Data Bit 3
Data Bit 2
Data Bit 3
OUT1
Bit 2
Bit 3
Bit 2
Bit 3
Bit 10
Bit 11
Delta
Data
Carrier
Detect
Enable
Modem
Status
Interrupt
(EDSSI)
Interrupt
ID
Bit 2
(see
Note 4)
DMA
Mode
Select
Parity
Enable
(PEN)
Framing
Error
(FE)
OUT2
Loop
(∆DCD)
Even
Parity
Select
(EPS)
Clear
to
Send
(CTS)
Break
Interrupt
(BI)
Sleep Mode
Enable
4
5
6
Data Bit 4
Data Bit 5
Data Bit 6
Data Bit 4
Data Bit 5
Data Bit 6
0
Reserved
Bit 4
Bit 5
Bit 6
Bit 4
Bit 5
Bit 6
Bit 12
Bit 13
Bit 14
Flow
Transmitter
Holding
Register
(THRE)
Data
Set
Ready
(DSR)
64 Byte
FIFO
Enabled
64 Byte
FIFO
Low Power
Mode Enable
Stick
Parity
Control
Enable
(AFE)
‡
Enable
FIFOs
Enabled
(see
Receiver
Trigger
(LSB)
Transmitter
Empty
(TEMT)
Ring
Indicator
(RI)
Break
Control
0
0
0
Note 11)
Divisor
Latch
Access
Bit
Error in
Receiver
FIFO
(see
Note 12)
FIFOs
Enabled
(see
Data
Receiver
Trigger
(MSB)
Carrier
Detect
(DCD)
7
Data Bit 7
Data Bit 7
0
Bit 7
Bit 7
Bit 15
Note 11)
‡
(DLAB)
†
‡
Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
Access to DLAB LSB, MSB, and FCR bit 5 require LCR bit 7 = 1
NOTE 11: These bits are always 0 in the TL16C450 mode.
23
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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
FIFO control register (FCR)
The FCR is a write-only register at the same location as the IIR, which is a read-only register. The FCR enables
the FIFOs, clears the FIFOs, sets the receiver FIFO trigger level, and selects the type of DMA signaling.
Bit 0: FCR0 when set enables the transmit and receive FIFOs. This bit must be set when other FCR bits
are written to or they are not programmed. Changing this bit clears the FIFOs.
Bit 1: FCR1 when set clears all bytes in the receiver FIFO and resets its counter. The RSR is not cleared.
The logic 1 that is written to this bit position is self clearing.
Bit 2: FCR2 when set clears all bytes in the transmit FIFO and resets its counter to 0. The TSR is not
cleared. The logic 1 that is written to this bit position is self clearing.
Bit 3: When FCR0 is set, setting FCR3 causes the RXRDY and TXRDY to change from mode 0 to
mode 1.
Bit 4: Reserved for future use.
Bit 5: When this bit is set 64-byte mode of operation is selected. When cleared, the 16-byte mode is
selected. A write to FCR bit 5 is protected by setting the line control register (LCR) bit 7 = 1. LCR bit 7 needs
to cleared for normal operation.
Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt (see Table 4).
Table 4. Receiver FIFO Trigger Level
16-BYTE RECEIVER FIFO
TRIGGER LEVEL (BYTES)
64-BYTE RECEIVER FIFO
TRIGGER LEVEL (BYTES)
BIT 7
BIT 6
0
0
1
1
0
1
0
1
01
04
08
14
01
16
32
56
FIFO interrupt mode operation
When the receiver FIFO and receiver interrupts are enabled (FCR0 = 1, IER0 = 1, IER2 = 1), a receiver interrupt
occurs as follows:
1. The received data available interrupt is issued to the microprocessor when the FIFO has reached its
programmed trigger level. It is cleared when the FIFO drops below its programmed trigger level.
2. The IIR receive data available indication also occurs when the FIFO trigger level is reached, and as the
interrupt, is cleared when the FIFO drops below the trigger level.
3. The receiver line status interrupt (IIR = 06 or 0110h) has higher priority than the received data available (IIR
= 04) interrupt.
4. The data ready bit (LSR0) is set when a character is transferred from the shift register to the receiver FIFO.
It is cleared when the FIFO is empty.
When the receiver FIFO and receiver interrupts are enabled:
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
1. FIFO time-out interrupt occurs when the following conditions exist:
a. At least one character is in the FIFO.
b. The most recent serial character was received more than four continuous character times ago (if two
stop bits are programmed, the second one is included in this time delay).
c. The most recent microprocessor read of the FIFO occurred more than four continuous character times
ago. This causes a maximum character received to interrupt an issued delay of 160 ms at
300 baud with a 12-bit character.
2. Character times are calculated by using RCLK for a clock signal (makes the delay proportional to the baud
rate).
3. When a time-out interrupt has occurred, the FIFO interrupt is cleared. The timer is reset when the
microprocessor reads one character from the receiver FIFO. When a time-out interrupt has not occurred,
the time-out timer is reset after a new character is received or after the microprocessor reads the receiver
FIFO.
When the transmitter FIFO and THRE interrupt are enabled (FCR0 = 1, IER1 = 1), transmit interrupts occur as
follows:
1. The transmitter holding register interrupt [IIR (3–0) = 2] occurs when the transmit FIFO is empty. The
transmit FIFO is cleared [IIR (3–0) = 1] when the THR is written to (1 to 16 characters may be written to
the transmit FIFO while servicing this interrupt) or the IIR is read.
2. The transmit FIFO empty indicator (LSR5 (THRE) = 1) is delayed one character time minus the last stop
bit time when there have not been at least two bytes in the transmit FIFO at the same time since the last
time that THRE = 1. The first transmitter interrupt after changing FCR0 is immediate when it is enabled.
Character time-out and receiver FIFO trigger level interrupts have the same priority as the current received data
available interrupt; transmit FIFO empty has the same priority as the current THRE interrupt.
FIFO polled mode operation
With FCR0 = 1 (transmitter and receiver FIFOs enabled), clearing IER0, IER1, IER2, IER3, or all four to 0 puts
the ACE in the FIFO polled mode of operation. Since the receiver and transmitter are controlled separately,
either one or both can be in the polled mode of operation.
In this mode, the user program checks receiver and transmitter status using the LSR. As stated previously:
•
•
LSR0 is set when there is at least one byte in the receiver FIFO.
LSR (1–4) specify which error(s) have occurred. Character error status is handled the same way as
when in the interrupt mode; the IIR is not affected since IER2 = 0.
•
•
•
LSR5 indicates when the THR is empty.
LSR6 indicates that both the THR and TSR are empty.
LSR7 indicates whether there are any errors in the receiver FIFO.
There is no trigger level reached or time-out condition indicated in the FIFO polled mode. However, the receiver
and transmitter FIFOs are still fully capable of holding characters.
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
interrupt enable register (IER)
The IER enables each of the five types of interrupts (refer to Table 5) and the INTRPT signal in response to an
interrupt generation. The IER can also disable the interrupt system by clearing bits 0 through 3. The contents
of this register are summarized in Table3 and are described in the following bulleted list.
Bit 0: When set, this bit enables the received data available interrupt.
Bit 1: When set, this bit enables the THRE interrupt.
Bit 2: When set, this bit enables the receiver line status interrupt.
Bit 3: When set, this bit enables the modem status interrupt.
Bit 4: When set, this bit enables sleep mode. The ACE is always awake when there is a byte in the
transmitter, activity on the SIN, or when the device is in the loopback mode. The ACE is also awake when
either ∆CTS, ∆DSR, ∆DCD, or TERI = 1. Bit 4 must be set to enable sleep mode.
Bit 5: When set, this bit enables low-power mode. Low-power mode functions similar to sleep mode.
However, thisfeaturepowersdowntheclocktotheACEonly, whilekeepingtheoscillatorrunning. Bit5must
be set to enable low-power mode.
Bits 6 and 7: Not used (always cleared)
interrupt identification register (IIR)
The ACE has an on-chip interrupt generation and prioritization capability that permits a flexible interface with
most popular microprocessors.
The ACE provides four prioritized levels of interrupts:
Priority 1 – Receiver line status (highest priority)
Priority 2 – Receiver data ready or receiver character timeout
Priority 3 –Transmitter holding register empty
Priority 4–Modem status (lowest priority)
When an interrupt is generated, the IIR indicates that an interrupt is pending and provides the type of interrupt
in its three least significant bits (bits 0, 1, and 2). The contents of this register are summarized in Table 3 and
described in Table 5. Details on each bit are as follows:
Bit0: Thisbitcanbeusedeitherinahardwireprioritized, orpolledinterruptsystem. Whenthisbitiscleared,
an interrupt is pending. When bit 0 is set, no interrupt is pending.
Bits 1 and 2: Used to identify the highest priority interrupt pending as indicated in Table 3.
Bit 3: This bit is always cleared in the TL16C450 mode. In FIFO mode, this bit is set with bit 2 to indicate
that a time-out interrupt is pending.
Bit 4: Not used (always cleared)
Bits 5, 6, and 7: These bits are to verify the FIFO operation. When all 3 bits are cleared, TL16C450 mode
is chosen. When bits 6 and 7 are set and bit 5 is cleared, 16-byte mode is chosen. When bits 5, 6, and 7
are set, 64-byte mode is chosen.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
interrupt identification register (IIR) (continued)
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
PRIORITY
LEVEL
INTERRUPT RESET
METHOD
INTERRUPT TYPE
INTERRUPT SOURCE
BIT 3 BIT 2 BIT 1 BIT 0
0
0
0
1
None
1
None
None
None
Overrun error, parity error,
framing error or break interrupt
0
1
1
0
Receiver line status
Reading the line status register
Receiver data available in the
Received data available TL16C450 mode or trigger level
reached in the FIFO mode.
Reading the receiver buffer
register
0
1
1
1
0
0
0
0
2
2
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time
Character time-out
indication
Reading the receiver buffer
register
Reading the interrupt
Transmitter holding
register empty
Transmitter holding register
empty
identification register (if source
of interrupt) or writing into the
transmitter holding register
0
0
0
0
1
0
0
0
3
4
Clear to send, data set ready,
ring indicator, or data carrier
detect
Reading the modem status
register
Modem status
line control register (LCR)
The system programmer controls the format of the asynchronous data communication exchange through the
LCR. In addition, the programmer is able to retrieve, inspect, and modify the contents of the LCR; this eliminates
the need for separate storage of the line characteristics in system memory. The contents of this register are
summarized in Table 3 and described in the following bulleted list.
Bits 0 and 1: These two bits specify the number of bits in each transmitted or received serial character.
These bits are encoded as shown in Table 6.
Table 6. Serial Character Word Length
BIT 1
BIT 0
WORD LENGTH
5 bits
0
0
1
1
0
1
0
1
6 bits
7 bits
8 bits
Bit 2: This bit specifies either one, one and one-half, or two stop bits in each transmitted character. When
bit 2 is cleared, one stop bit is generated in the data. When bit 2 is set, the number of stop bits generated
is dependent on the word length selected with bits 0 and 1. The receiver clocks only the first stop bit,
regardless of the number of stop bits selected. The number of stop bits generated, in relation to word length
and bit 2, is shown in Table 7.
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
line control register (LCR) (continued)
Table 7. Number of Stop Bits Generated
WORD LENGTH SELECTED
BY BITS 1 AND 2
NUMBER OF STOP
BITS GENERATED
BIT 2
0
1
1
1
1
Any word length
5 bits
1
1 1/2
2
6 bits
7 bits
2
8 bits
2
Bit 3: This bit is the parity enable bit. When bit 3 is set, a parity bit is generated in data transmitted between
the last data word bit and the first stop bit. In received data, when bit 3 is set, parity is checked. When bit
3 is cleared, no parity is generated or checked.
Bit 4: This bit is the even parity select bit. When parity is enabled (bit 3 is set) and bit 4 is set, even parity
(an even number of logic 1s in the data and parity bits) is selected. When parity is enabled and bit 4 is
cleared, odd parity (an odd number of logic 1s) is selected.
Bit 5: This is the stick parity bit. When bits 3, 4, and 5 are set, the parity bit is transmitted and checked as
cleared. When bits 3 and 5 are set and bit 4 is cleared, the parity bit is transmitted and checked as set. When
bit 5 is cleared, stick parity is disabled.
Bit 6: This bit is the break control bit. Bit 6 is set to force a break condition; i.e., a condition where SOUT
is forced to the spacing (low) state. When bit 6 is cleared, the break condition is disabled and has no affect
on the transmitter logic; it only affects the serial output.
Bit 7: This bit is the divisor latch access bit (DLAB). Bit 7 must be set to access the divisor latches of the
baud generator during a read or write or access bit 5 of the FCR. Bit 7 must be cleared during a read or write
to access the receiver buffer, the THR, or the IER.
†
line status register (LSR)
The LSR provides information to the CPU concerning the status of data transfers. The contents of this register
are described in the following bulleted list and summarized in Table 3.
Bit0: Thisbitisthedataready(DR)indicatorforthereceiver. DRissetwhenacompleteincomingcharacter
is received and transferred into the RBR or the FIFO. DR is cleared by reading all of the data in the RBR
or the FIFO.
‡
Bit 1 : This bit is the overrun error (OE) indicator. When OE is set, it indicates that before the character in
the RBR was read, it was overwritten by the next character transferred into the register. OE is cleared every
time the CPU reads the contents of the LSR. When the FIFO mode data continues to fill the FIFO beyond
the trigger level, an OE occurs only after the FIFO is full and the next character has been completely
received in the shift register. An OE is indicated to the CPU as soon as it happens. The character in the shift
register is overwritten, but it is not transferred to the FIFO.
‡
Bit 2 : This bit is the parity error (PE) indicator. When PE is set, it indicates that the parity of the received
data character does not match the parity selected in the LCR (bit 4). PE is cleared every time the CPU reads
the contents of the LSR. In the FIFO mode, PE is associated with the particular character in the FIFO to
which it applies. PE is revealed to the CPU when its associated character is at the top of the FIFO.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
†
line status register (LSR) (continued)
‡
Bit 3 : This bit is the framing error (FE) indicator. When FE is set, it indicates that the received character
does not have a valid (set) stop bit. FE is cleared every time the CPU reads the contents of the LSR. In the
FIFO mode, this error is associated with the particular character in the FIFO to which it applies. FE is
revealed to the CPU when its associated character is at the top of the FIFO. The ACE tries to resynchronize
after a FE. To accomplish this, it is assumed that the FE is due to the next start bit. The ACE samples this
start bit twice and then accepts the input data.
Bit 4: This bit is the break interrupt (BI) indicator. When BI is set, it indicates that the received data input
was held in the low state for longer than a full-word transmission time. A full-word transmission time is
defined as the total time to transmit the start, data, parity, and stop bits. BI is cleared every time the CPU
reads the contents of the LSR. In the FIFO mode, BI is associated with the particular character in the FIFO
to which it applies. BI is revealed to the CPU when its associated character is at the top of the FIFO. When
a break occurs, only one 0 character is loaded into the FIFO. The next character transfer is enabled after
SIN goes to the marking state for at least two RCLK samples and then receives the next valid start bit.
Bit 5: This bit is the transmitter holding register empty (THRE) indicator. THRE is set when the THR is
empty, indicating that the ACE is ready to accept a new character. If the THRE interrupt is enabled when
THRE is set, an interrupt is generated. THRE is set when the contents of the THR are transferred to the
TSR. THRE is cleared concurrent with the loading of the THR by the CPU. In the FIFO mode, THRE is set
when the transmit FIFO is empty; it is cleared when at least one byte is written to the transmit FIFO.
Bit 6: This bit is the transmitter empty (TEMT) indicator. TEMT bit is set when the THR and the TSR are
both empty. When either the THR or the TSR contains a data character, TEMT is cleared. In the FIFO mode,
TEMT is set when the transmitter FIFO and TSR are both empty.
Bit 7: In TL16C750 mode and in TL16C450 mode, this bit is always cleared. In the FIFO mode, LSR7 is
set when there is at least one parity, framing, or break error in the FIFO. It is cleared when the
microprocessor reads the LSR and there are no subsequent errors in the FIFO.
modem control register (MCR)
The MCR is an 8-bit register that controls an interface with a modem, data set, or peripheral device that is
emulating a modem. The contents of this register are summarized in Table 3 and are described in the following
bulleted list.
Bit 0: This bit (DTR) controls the DTR output.
Bit 1: This bit (RTS) controls RTS output.
Bit 2: This bit (OUT1) controls OUT1 signal.
Bit 3: This bit (OUT2) controls the OUT2 signal.
When any of bits 0 through 3 is set, the associated output is forced low; a cleared bit forces the associated output
high.
†
‡
The line status register is intended for read operations only; writing to this register is not recommended outside of a factory testing environment.
Bits 1 through 4 are the error conditions that produce a receiver line status interrupt.
29
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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
modem control register (MCR) (continued)
Bit 4: This bit (LOOP) provides a local loop back feature for diagnostic testing of the ACE. When LOOP
is set, the following occurs:
–
–
–
–
–
SOUT is asserted high.
SIN is disconnected.
The output of the TSR is looped back into the RSR input.
The four modem control inputs (CTS, DSR, DCD, and RI) are disconnected.
The four modem control outputs (DTR, RTS, OUT1, and OUT2) are internally connected to the four
modem control inputs.
–
The four modem control outputs are forced to their inactive (high) states.
Bit 5: This bit (AFE) is the autoflow control enable. When bit 5 is set, the autoflow control, as described in
the detailed description, is enabled.
In the diagnostic mode, data that is transmitted is immediately received. This allows the processor to verify
the transmit and receive data paths to the ACE. The receiver and transmitter interrupts are fully operational.
The modem control interrupts are also operational, but the modem control interrupt sources are now the
lower four bits of the MCR instead of the four modem control inputs. All interrupts are still controlled by the
IER.
The ACE flow can be configured by programming bits 1 and 5 of the MCR as shown in Table 8.
Table 8. ACE Flow Configuration
MCR BIT 5
(AFE)
MCR BIT 1
(RTS)
ACE FLOW CONFIGURATION
1
1
0
1
0
Auto-RTS and auto-CTS enabled (autoflow control enabled)
Auto-CTS only enabled
X
Auto-RTS and auto-CTS disabled
Whenbit5oftheFCRiscleared, thereisa16-byteAFC. Whenbit5oftheFCRisset, thereisa64-byteAFC.
modem status register (MSR)
The MSR is an 8-bit register that provides information about the current state of the control lines from the
modem, data set, or peripheral device to the CPU. Additionally, four bits of this register provide change
information. When a control input from the modem changes state, the appropriate bit is set. All four bits are
cleared when the CPU reads the MSR. The contents of this register are summarized in Table 3 and are
described in the following bulleted list.
Bit 0: This bit is the change in clear-to-send (∆CTS)indicator. ∆CTSindicatesthatCTShaschangedstates
since the last time it was read by the CPU. When ∆CTS is set (autoflow control is not enabled and the
modem status interrupt is enabled), a modem status interrupt is generated. When autoflow control is
enabled, no interrupt is generated. When ∆CTS is set, sleep or low-power modes are avoided.
Bit 1: This bit is the change in data set ready (∆DSR) indicator. ∆DSR indicates that DSR has changed
states since the last time it was read by the CPU. When ∆DSR is set and the modem status interrupt is
enabled, a modem status interrupt is generated. When ∆DSR is set, the sleep or low-power modes are
avoided.
30
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TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
modem status register (MSR) (continued)
Bit 2: This bit is the trailing edge of the ring indicator (TERI) detector. TERI indicates that RI to the chip has
changed from a low to a high level. When TERI is set and the modem status interrupt is enabled, a modem
status interrupt is generated. When TERI is set, sleep or low-power modes are avoided.
Bit 3: This bit is the change in data carrier detect (∆DCD) indicator. ∆DCD indicates that DCD to the chip
has changed states since the last time it was read by the CPU. When ∆DCD is set and the modem status
interrupt is enabled, a modem status interrupt is generated. When ∆DCD is set, sleep or low-power modes
are avoided.
Bit 4: This bit is the complement of CTS. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 1 (RTS).
Bit 5: This bit is the complement of DSR input. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 0 (DTR).
Bit 6: This bit is the complement of RI. When the ACE is in the diagnostic test mode (LOOP [MCR4] = 1),
this bit is equal to the MCR bit 2 (OUT1).
Bit 7: This bit is the complement of DCD. When the ACE is in the diagnostic test mode (LOOP
[MCR4] = 1), this bit is equal to the MCR bit 3 (OUT2).
programmable baud generator
The ACE contains a programmable baud generator that takes a clock input in the range between dc and 16 MHz
16
and divides it by a divisor in the range between 1 and (2 –1). The output frequency of the baud generator is
16× the baud rate. The formula for the divisor is:
divisor = XIN frequency input ÷ (desired baud rate × 16)
Two 8-bit registers, called divisor latches, store the divisor in a 16-bit binary format. These divisor latches must
be loaded during initialization of the ACE to ensure desired operation of the baud generator. When either of the
divisor latches is loaded, a 16-bit baud counter is also loaded to prevent long counts on initial load.
Tables 9 and 10 illustrate the use of the baud generator with crystal frequencies of 1.8432 MHz and 3.072 MHz
respectively. For baud rates of 38.4 kbits/s and below, the error obtained is very small. The accuracy of the
selected baud rate is dependent on the selected crystal frequency (see Figure 21).
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
programmable baud generator (continued)
Table 9. Baud Rates Using a 1.8432-MHz Crystal
DIVISOR USED
TO GENERATE
16× CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
2304
1536
1047
857
768
384
192
96
110
0.026
0.058
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
56000
64
58
0.69
48
32
24
16
12
6
3
2
2.86
Table 10. Baud Rates Using a 3.072-MHz Crystal
DIVISOR USED
TO GENERATE
16× CLOCK
PERCENT ERROR
DIFFERENCE BETWEEN
DESIRED AND ACTUAL
DESIRED
BAUD RATE
50
75
3840
2560
1745
1428
1280
640
320
160
107
96
110
0.026
0.034
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
0.312
80
53
0.628
1.23
40
27
20
10
5
32
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16C750
ASYNCHRONOUS COMMUNICATIONS ELEMENT
WITH 64-BYTE FIFOs AND AUTOFLOW CONTROL
SLLS191C – JANUARY 1995 – REVISED DECEMBER 1997
PRINCIPLES OF OPERATION
programmable baud generator (continued)
V
CC
V
CC
Driver
XIN
XIN
External
Clock
C1
Crystal
R
P
Optional
Driver
RX2
XOUT
Optional
Clock
Output
Oscillator Clock
to Baud Generator
Logic
Oscillator Clock
to Baud Generator
Logic
XOUT
C2
TYPICAL CRYSTAL/OSCILLATOR NETWORK
CRYSTAL
3.072 MHz
1.8432 MHz
R
RX2
C1
C2
P
1 MΩ
1 MΩ
1.5 kΩ
1.5 kΩ
10–30 pF
10–30 pF
40–60 pF
40–60 pF
Figure 21. Typical Clock Circuits
receiver buffer register (RBR)
The ACE receiver section consists of a RSR and a RBR. The RBR is actually a 64-byte FIFO. Timing is supplied
by the 16× receiver clock (RCLK). Receiver section control is a function of the ACE line control register.
The ACE RSR receives serial data from the SIN terminal. The RSR then deserializes the data and moves it into
the RBR FIFO. In the TL16C450 mode, when a character is placed in the RBR and the received data available
interrupt is enabled, an interrupt is generated. This interrupt is cleared when the data is read out of the RBR.
In the FIFO mode, the interrupts are generated based on the control setup in the FIFO control register.
scratch register
The scratch register is an 8-bit register used by the programmer as a scratchpad that temporarily holds the
programmer data without affecting any other ACE operation.
transmitter holding register (THR)
The ACE transmitter section consists of a THR and a transmitter shift register (TSR). The THR is actually a
64-byte FIFO. Timing is supplied by the baud out (BAUDOUT) clock signal. Transmitter section control is a
function of the ACE line control register.
The ACE THR receives data off the internal data bus and when the shift register is idle, moves it into the TSR.
TheTSRserializesthedataandoutputsitattheSOUTterminal. IntheTL16C450mode, whentheTHRisempty
and the transmitter holding register empty (THRE) interrupt is enabled (IER1 = 1), an interrupt is generated. This
interrupt is cleared when a character is loaded into the register. In the FIFO mode, the interrupts are generated
based on the control setup in the FIFO control register.
33
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
20-Mar-2008
PACKAGING INFORMATION
Orderable Device
TL16C750FN
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
PLCC
FN
44
44
44
44
64
64
64
64
0
26 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TL16C750FNG4
TL16C750FNR
TL16C750FNRG4
TL16C750IPM
TL16C750IPMG4
TL16C750PM
PLCC
PLCC
PLCC
LQFP
LQFP
LQFP
LQFP
FN
FN
FN
PM
PM
PM
PM
Y
26 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
500 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
TL16C750PMG4
TL16C750Y
160 Green (RoHS & CU NIPDAU Level-3-260C-168 HR
no Sb/Br)
OBSOLETE DIESALE
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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