TL16PNP100A [TI]
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER; STANDALONE PLUG -AND- PLAY （即插即用）控制器
| 型号： | TL16PNP100A |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER |
| 文件： | 总20页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
FN PACKAGE
(TOP VIEW)
PnP Card Autoconfiguration Sequence
Compliant
Supports Two Logical Devices
Decodes 10-Bit I/O Address Location With
Programmable 1-, 2-, 4-, 8-, 16-Byte Block
Size
6
5
4
3
2
1 44 43 42 41 40
39
D0
D1
D2
D3
A6
7
Maps Interrupts to Six Interrupt Outputs
IRQ3–IRQ7 and IRQ9
A7
8
38
37
36
35
34
A8
9
Provides Simple 3-Terminal Interface to
SGS-Thomson EEPROM 2K/4K ST93C56/66
or Equivalent
A9
10
GND 11
D4 12
A10
A11
13
14
15
16
17
3-State Output EEPROM Interface Allows
the EEPROM to be Accessed by Another
Controller
D5
D6
33 GND
32 CLK
31
30
29
D7
INTR0
CS0
GND
IRQ3
Provides Direct Connection to ISA/AT Bus
EEPROM
Data and Interrupt Signals Require No
Buffer
18 19 20 21 22 23 24 25 26 27 28
Available in 44-Pin Plastic Leaded Chip
Carrier (PLCC) and 48-Pin TQFP Package
description
PT PACKAGE
(TOP VIEW)
The TL16PNP100A responds to the plug-and-
play (PnP) autoconfiguration process. The
process puts all PnP cards in a configuration
mode, isolates one PnP card at a time, assigns a
card-select number (CSN), and reads the card
resource-data structure from the ST93C56/66
EEPROM. After the resource requirements and
capabilities are determined for all cards, the
process uses the CSN to configure the card by
writing to the configuration registers. The
TL16PNP100A implements configuration regis-
ters only for I/O applications with two logical
devices, and DMA application support is not
provided. Finally, the process activates the
TL16PNP100A card and removes it from
configuration mode. After the configuration
process, the logic function can then start
responding to industry standard architecture
(ISA) bus cycles. The controller disables the
EEPROM interface after the configuration is
complete to allow another on-board controller to
access the EEPROM.
48 47 46 45 44 43 42 41 40 39 38 37
36
35
34
33
32
31
30
29
28
27
26
25
A6
A7
A8
A9
NC
A10
A11
GND
CLK
INTR0
CS0
EEPROM
D0
D1
D2
D3
GND
D4
NC
D5
D6
1
2
3
4
5
6
7
8
9
D7 10
GND
IRQ3
11
12
13 14 15 16 17 18 19 20 21 22 23 24
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
functional block diagram
8
15–12, 10–7
D (7–0)
Output
Enable
27
26
SCS
8
SCLK
EEPROM
28
29
Controller
SIO
EEPROM
8
INTR0
INTR1
8
Card
Control
8
24
31
30
23
CS0
CS1
8
8
Logical Device
Control
Logical
Devices
Decoder
17–21, 22
8
IRQ3–IRQ7,
IRQ9
Logical Device
Configuration
8
8
Select
Address
Register
8
34–44, 1
6
8
A11–A0
Read-Data Port
Write-Data Port
Address Port
AEN
IOR
5
Decoder
LFSR
Key
4
3
IOW
RESET
Enable
NOTE A: Terminal numbers shown are for the FN package.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
Terminal Functions
TERMINAL
I/O
DESCRIPTION
FN
NO.
PT
NO.
NAME
A0
A11–A1
1
42
41–33,
31, 30
I
12-bit ISA address terminals. A0 and A1–A11 are used during the PnP autoconfiguration
sequence.
44–34
AEN
6
48
I
ISA address enable. AEN is active during DMA operation and causes the controller to ignore the
ISA transaction.
CLK
CS0
32
30
28
26
I
22-MHz external clock input. CLK synchronizes PnP logic and generates a 0.68-MHz SCLK.
O
Chip select. CS0 is used for logical device number 0. The address decoder only decodes a 10-bit
address for one I/O location with programmable block size.
CS1
23
18
O
Chip select. CS1 is used for logical device number 1 . The address decoder only decodes a 10-bit
address for one I/O location with programmable block size.
D0–D3
D4–D7
7–10
12–15
1–4
6,8 – 10
I/O Data bus. D0–D3 and D4–D7 with 3-state outputs provide a bidirectional path for data, control,
and status information between the TL16PNP100A and the CPU. Output drive sinks 24 mA at
0.4 V and sources 12 mA at 2.4 V.
EEPROM
GND
29
25
I/O EEPROM interface access enable. A 3-state bidirectional signal. When EEPROM is pulled low,
the EEPROM interface is being accessed. A release state indicates the EEPROM interface is
idle. A 100 µA pullup transistor is connected internally to this terminal.
11, 16,
33
5, 11,
29
Ground (0 V). All terminals must be tied to GND for proper operation.
INTR0
INTR1
IOR
31
24
5
27
19
47
46
I
I
Interrupt request from logical device number 0. INTR0 is an active-high signal.
Interrupt request from logical device number 1. INTR1 is an active-high signal.
I
ISA read input
ISA write input
IOW
4
I
IRQ3–IRQ7
IRQ9
17–21
22
12–16
17
O
Interrupt request. INTRn request is mapped to one of the IRQs based on the value of the content
of the interrupt request level (0×70) register. Output drive sinks 24 mA at 0.4 V and sources
12 mA at 2.4 V. These terminals are 3-state outputs.
RESET
3
45
I
Reset. When active (high), RESET clears most logical device registers and puts the
TL16PNP100A in the wait-for-key state. The CSN is reset to 0×0. All configuration registers are
set to their power-up values.
SCLK
SCS
SIO
26
27
22
23
I/O Serial clock (3-state output path). SCLK controls the serial bus timing for address data. A 100-µA
pulldown transistor is connected internally to this terminal.
I/O EEPROM chip select (3-state output). SCS controls the activity of the EEPROM. A 100-µA
pulldown transistor is connected internally to this terminal.
28
24
I/O Serial input/output. A 3-state bidirectional EEPROM I/O data path. A 100 µA pulldown transistor
is connected internally to this terminal.
V
CC
2, 25
21, 43
5-V supply voltage
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
detailed description
block size
This device generates read instructions for the EEPROM. Read transactions consist of read opcode, address
and data cycles. Data cycles are comprised of 2-byte DATA. After power up resets, this device reads the
programmable block size value from address zero in the EEPROM. Data [15:13] carries the block size
information for logical device 0. Data [11–9] carries the block size information for the logical device 1 (see Table
1).
Table 1. Block Size
BLOCK SIZE
DATA [15:13]/[11:9]
ADDRESS BITS DECODED
(Bytes)
000
001
010
100
111
1
A9–A0
A9–A1
A9–A2
A9–A3
A9–A4
2
4
8
16 (default)
EEPROM signal description
This device interfaces to SGS-Thomson’s compatible EEPROM 2-Kbit ST93C56 or 4-Kbit ST93C66. After
completion of the configuration sequence, it allows an optional on-board controller to access the EEPROM.
During and after reset, TL16PNP100A gains access to the EEPROM by asserting EEPROM low, informing the
optional on-board controller that it is accessing the EEPROM. After the configuration is complete, the device
leaves the configuration mode, is activated, and is in the wait-for-key state. The EEPROM signal is then
released and pulled high, SIO is released and pulled down, and SCS and SCLK are placed in the
high-impedance state and pulled down.
NOTE
When the device enters the configuration mode again and leaves the wait-for-key state, it gains
directaccesstotheEEPROMaftertheEEPROMsignalisreleased. Thewakecommandgenerates
a read transaction from address 0×1, which is the beginning of the resource data of the card.
When the EEPROM signal is released, the interface of the EEPROM is idle. The TL16PNP100A
drives the EEPROM signal low when the device enters the configuration mode again.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range at any input, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
Operating free-air temperature range, T
Storage temperature range, T
Case temperature for 10 seconds: FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
recommended operating conditions
MIN NOM
MAX
UNIT
V
Supply voltage, V
4.75
2
5
5.25
CC
High-level input voltage, V
V
CC
0.8
V
IH
Low-level input voltage, V
–0.5
0
V
IL
Operating free-air temperature, T
70
°C
A
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
= –4 mA (see Note 1)
MIN
MAX
UNIT
I
I
I
I
V
V
–0.8
OH
OH
OL
OL
CC
V
V
High-level output voltage
V
OH
= –12 mA (see Note 2)
= 4 mA (see Note 1)
= 24 mA (see Note 2)
–0.8
CC
0.5
0.5
Low-level output voltage
Input current
V
OL
V
= 0,
SS
V
= 5.25 V,
CC
V = 0 to 5.25 V,
I
l
±1
±10
0.7
µA
All other terminals
floating
I
V
V
= 5.25 V,
CC
= 0 to 5.25 V,
V
SS
= 0,
High-impedance-state output cur-
rent
I
µA
OZ
O
Pullup transistors and pulldown transistors are off
V
= 5.25 V, = 25°C,
T
A
CC
All inputs at 0.8 V,
No load on outputs
CLK at 4 MHz,
I
Supply current
mA
CC
C
Clock input capacitance
Clock frequency
15
20
22
pF
i(CLK)
f
10
MHz
CLK
†
All typical values are at V
= 5 V and T = 25°C.
A
CC
NOTES: 1. These parameters apply for all outputs except D7–D0, IRQ3–IRQ7 and IRQ9.
2. These parameters only apply for D7–D0 and IRQ3–IRQ7 and IRQ9 outputs.
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
t
f
Pulse duration, SCLK high to low (see Note 3)
Pulse duration, SCLK low to high (see Note 3)
SCLK clock frequency (see Note 4)
t
t
250
250
0.3
ns
ns
w(SCLKH)
w(SCLKL)
CLK
CHCL
See Figure 8
CLCH
0.68
MHz
NOTES: 3. TheST93C56chipselect, S, mustbebroughtlowforaminimumof250ns(t
to the ST93C56 specification.
betweenconsecutiveinstructioncyclesaccording
SLSH)
4. The SCLK signal is attained by internally dividing the frequency of the XIN signal by 32.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
switching characteristics
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
t
t
Delay time, CS high to SCLK high
t
t
See Figure 8
50
ns
ns
d1
SHCH
Delay time, SIO input valid to SCLK high
100
d2
DVCH
See Figure 8 and Fig-
ure 9
Propagation delay time, SCLK high to SIO level transi-
tion
t
t
t
t
t
t
t
t
100
ns
pd1
pd2
pd3
d3
CHDX
CHQV
CLSL
SLQZ
Propagation delay time, SCLK high to output valid
Propagation delay time, SCLK low to CS transition
Delay time, CS low to D/Q output Hi-Z
500
2
ns
clock
period
See Figure 9
100
ns
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
ALTERNATE
SYMBOL
PARAMETER
TEST CONDITIONS
See Figure 5
MIN
2
MAX
UNIT
clock
periods
t
t
Pulse duration, write strobe, IOW low
Pulse duration, read strobe, IOR low
t
t
w1
WR
clock
periods
See Figure 6
3
w2
RD
t
t
Pulse duration, master reset
t
t
1
µs
w3
MR
Setup time, data D7–D0 valid before
↑
See Figure 5
15
ns
su1
DS
From the first rising edge of XIN
after address becomes invalid,
See Figure 5 and Figure 6
Hold time, chip select CSx valid after address
A0–A11 becomes invalid
t
t
t
t
t
t
20
30
ns
ns
ns
h1
h2
d4
CH
Hold time, data valid D7–D0 after IOW↑
See Figure 5
5
5
DH
From the first rising edge of XIN
after address valid,
See Figure 5 and Figure 6
Delay time, CSx valid after address A0–A11 valid
CSRW
t
t
Hold time, address A0–A11 valid after
↑
t
t
See Figure 5
ns
ns
h3
AW
C
= 45 pF after 2 clock periods,
L
Delay time, IOR valid to data D0–D7 valid
30
20
15
d5
CSVD
See Figure 6
C
= 45 pF,
L
t
t
Delay time,
↑ to floating data D0–D7
t
ns
ns
d6
HZ
See Figure 6
Delay time, INTR0↑, INTR1↑, INTR0↓,
to IRQ↑
↓
See Figure 7
d7
↓
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
IOWR
IOR
D7–D0
8
Logical
Device #0
A3–A0
4
RESETDRV
IOWR
IOR
D7–D0
8
Logical
Device #1
ISA Bus
A3–A0
4
RESETDRV
23
24
30
31
A11–A0
12
8
1, 34–44
26
27
28
SCLK
SCS
SIO
C
S
D
D7–D0
RESETDRV
IOW
7–10, 12–15
3
4
5
EEPROM
TL16PNP100A
IOR
Q
IRQ3-7, IRQ9
17–22
6
AEN
EEPROM
29
To Optional
On-Board
Controller
32
CLK
NOTE A: A 2-kΩ resistor should be inserted between D and Q. See the SGS-Thomson EEPROM 2K/4K ST93C56/66 application
report.
Figure 1. Basic TL16PNP100A Configuration
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
on-board EEPROM programming
This section describes a simple approach to programming the resource EEPROM in an expansion board that
uses the TL16PNP100A. This approach involves utilizing a readily available standard EEPROM programmer
and a ribbon cable in addition to minor additions to the expansion board.
hardware required for programming an expansion board EEPROM
The hardware required for programming an expansion board EEPROM is listed in the following bulleted list and
shown in Figure 2.
Ribbon cable with DB25 connector
On-board ribbon connector and two jumper wires
8
7
6
5
2
1
C
V
CC
SCLK
SCS
SI0
V
CC
DU
J2
S
D
Q
3
4
Ca
ORG
V
SS
TL16PNP100A
R1
J1
ST93C56166
Expansion
Board
Connector
14
DB25 Connector
Parallel PC
Printer Port
21
11
7
(see Page 2 For pinout)
8
9
Figure 2. Programming an Expansion Board EEPROM
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
32-byte I/O block size
The TL16PNP100A supports I/O block sizes ranging from 1 to 16 bytes. The following is one method to enable
this device to support 32-byte I/O block size.
Use only one logical device, and consequently one CS, either CS0 or CS1.
In the first 2 bytes of the EEPROM select an I/O block size of 16 bytes for the selected logical device.
In the EEPROM I/O descriptor resources, set the number of ports to 32 and the base address increment
to 32.
Use a NOR gate and an inverter to qualify address line A4 with the signal EEPROM as shown in
Figure 3:
A4 (from ISA Bus)
to A4 of TL16PNP100A
EEPROM (from TL16PNP100A)
Figure 3. 32-Byte I/O Support
This operation forces A4 to 0 after completing the confirguration process (EEPROM signal is pulled up internally
and goes high after the configuration process is complete.) When the address on the ISA bus is in the next 16
I/O addresses, only A4 changes from 0 to 1. Since A4 is being forced to 0, the TL16PNP100A thinks that the
address is still in the 16-byte range and it asserts CS.
Example:
Using logical device 0:
Connect CS0 directly to the CS input of the device.
Insert the NOR gate as described above.
In the EEPROM, set the I/O block size to 0x00E0 (Blk_size = 16 bytes)
The I/O descriptor in the EEPROM resources should be as follows:
I/O Port Descriptor 1
db
db
db
db
db
db
db
db
047h
000h
020h
002h
0e0h
003h
020h
020h
; Small item, type I/O port descriptor
; Information, [0] = 0, 10 bit decode
; Minimum base address [7:0]
; Minimum base address [15:8]
; Maximum base address [7:0]
; Maximum base address [15:8]
; Base address increment = 32
; Number of ports required = 32
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
During configuration, assuming the system assigned the device address range 0x220 to 0x23F, EEPROM is
low and A4 from the ISA bus passes to A4 on the TL16PNP100A. When configuration is complete EEPROM
goes high, and A4 at the input of TL16PNP100A is reset to 0. Since the block size is 16, the TL16PNP100A looks
at address bits A9 to A4. When the address on the A9 to A0 is in the range of 0x220 to 0x22F, A9 to A4 is as
follows:
A9
1
A8
0
A7
0
A6
0
A5
1
A4
0
A3
X
A1
X
A1
X
A0
X
and CS0 is asserted low.
When the address is in the range of 0x230 to 0x23F, A9 to A4 is as follows:
A9
1
A8
0
A7
0
A6
0
A5
1
A4
1
A3
X
A1
X
A1
X
A0
X
However, since A4 at the input of PNP100A is forced to 0, A9 to A4 is the same as in the range of 0x220 to 0x22F
and TL16PNP100A asserts CS0 low.
obtaining Windows 95 logo
ToobtaintheWindows95 logo, thecardshouldbeabletodecode16-bitI/Oaddress. SincetheTL15PNP100A
uses10-bitaddressdecoding, anORgateisneededon-boardtodecodetheupper6addressbits(SA15-SA10).
The customer can use this gate by changing the I/O port descriptors in the EEPROM to reflect the 16-BIT ISA
address. However, the customer must make sure that the upper 6 BITS in the I/O port descriptors have thesame
minimum and maximum base in the address registers.
For example, a logical device requires a base address between 0200h and 0300h with an 8-byte as a base
alignment and one I/O port requested. (Notice that the requested base address is such that the upper six bits
in the minimum and maximum base address ranges are the same as in this example all are considered to be
zeros). To meet the requested resources, the following steps must be done:
1. Modify the gate logic on the board as shown in Figure 4.
SA15
SA14
SA13
SA12
SA11
SA10
OR GATE
LOGIC
CS to Logical Device
CS I/O (From TL16PNP100A)
Figure 4. Gate Logic Modification
All the signals on the left side of the OR gate are ISA signals.
Window 95 is a trademark of Microsoft Corporation.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
APPLICATION INFORMATION
2. Program the I/O ports descriptors in the EEPROM as follows:
47h
01h
00h
02h
00h
03h
08h
01h
I/O port descriptors with 7 bytes
Information, bit 0 is set. The logical device is decoding full 16-bit ISA addresses
Address bits 7–0 for minimum configuration base I/O address
Address bits 15–8 for minimum configuration base I/O address
Address bits 7–0 for maximum configuration base I/O address
Address bits 15–8 for maximum configuration base I/O address
Base alignment, which has a block size of 8 bytes
One I/O port is needed
Using the above setup, the PnP BIOS maps the logical device to an address so that the upper six bits are always
zeros. The 0 output from the OR gate occurs when SA15-SA10 and SAEN are low. This forces the logical device
to check SA09-SA0 for a possible valid address.
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PARAMETER MEASUREMENT INFORMATION
CLK
A0–A11
Valid Address
50%
50%
t
d4
t
h1
CS0/CS1
IOW
50%
50%
Valid
t
t
h3
w1
50%
Active
50%
t
t
h2
su1
Valid Data
D7–D0
Figure 5. Write-Cycle Timing
CLK
A0–A11
Valid Address
50%
50%
t
d4
t
h1
CS0/CS1
IOR
50%
50%
Valid
t
w2
50%
Active
50%
t
d5
t
d6
Valid Data
D7–D0
Figure 6. Read-Cycle Timing
INTR0/INTR1
IRQx
t
d7
t
d7
Figure 7. External Interrupt (EXINTR) Timing
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
PnP card configuration sequence
The PnP logic is quiescent on power up and must be enabled by software.
1. The initiation key places the PnP logic into configuration mode through a series of predefined writes to
the ADDRESS port (see PnP Autoconfiguration Ports section).
2. A serial identifier is accessed in bit-sequence and used to isolate the ISA cards. Seventy-two
READ_DATA port reads are required to isolate each card.
3. Once isolated, a card is assigned a CSN that is later used to select the card. This assignment is
accomplished by programming the CSN.
4. The PnP software then reads the resource-data structure on each card. When all resource capabilities
and demands are known, a process of resource arbitration is invoked to determine resource allocation
for each card.
5. All PnP cards are then activated and removed from the configuration mode. This activation is
accomplished by programming the ACTIVE register.
PnP autoconfiguration ports
Three 8-bit ports (see Table 2) are used by the software to access the configuration space on each ISA PnP
card. These registers are used by the PnP software to issue commands, check status, access the resource data
information, and configure the PnP hardware.
The ports have been chosen so as to avoid conflicts in the installed base of ISA functions, while at the same
time minimizing the number of ports needed in the ISA I/O space.
Table 2. Autoconfiguration Ports
PORT NAME
ADDRESS
LOCATION
TYPE
0×0279 (printer status port)
Write only
Write only
Read only
WRITE_DATA
READ_DATA
0×0A79 (printer status port + 0×0800)
Relocatable in range 0×0203 to 0×03FF
The PnP registers are accessed by first writing the address of the desired register to the ADDRESS port,
followed by a read of data from the READ_DATA port or a write of data to the WRITE_DATA port. Once
addressed, the desired register may be accessed through the WRITE_DATA or READ_DATA ports.
The ADDRESS port is also the destination of the initiation key writes (see PnP ISA specification).
The address of the READ_DATA port is set by programming the SET RD_DATA PORT register. When a card
cannot be isolated for a given READ_DATA port address, the READ_DATA port address is in conflict. The
READ_DATA port address must then be relocated and the isolation process begun again. The entire range
between 0×0203 and 0×3FF is available; however, in practice it is expected that only a few address locations
are necessary before the software determines that PnP cards are not present.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
PnP registers
PnP card standard registers are divided into three parts: card control, logical device control, and logical device
configuration. There is exactly one of each card control register on each ISA card. Card control registers are
used for global functions that control the entire card. Logical device control registers and logical device
configuration registers are repeated for each logical device. Since the TL16PNP100A has two logical devices
and they are intended only for I/O applications, not all the configuration registers are implemented.
PnP card control registers
The PnP card device control registers are listed in Table 3.
Table 3. PnP Card Control Registers
ADDRESS PORT
VALUE
READ/WRITE
CAPABILITY
REGISTER NAME VALUE
SET RD_DATA PORT
POWER UP
0×00
Write only
00 00 00 00
Writing to this register modifies the address port used for reading from the PnP ISA card. Writing to this register is only
allowed when the card is in the isolation state.
Bits 7–0
SERIAL ISOLATION
Reading from this register causes a card in the isolation state to compare one bit of the board ID.
CONFIGURATION CONTROL Write only
These bits become I/O port address bits 9–2.
0×01
0×02
Read only
00 00 00 00
0 00
This 3-bit register consists of three independent commands, which are activated by writing a 1 to their corresponding
register bits. These bits are automatically reset to 0 by the hardware after the commands execute.
Bit 2
Bit 1
Writing a 1 to bit 1 causes the card to reset its CSN and RD-DATA port to zero.
Writing a 1 to bit 2 causes the card to enter the wait-for-key state, but the card CSN is
preserved and the logical device is unaffected.
Bit 0
Writing a 1 to bit 0 resets the configuration registers of the logical device to their default state, and the
CSN is preserved.
0×03
WAKE[CSN]
Write only
00 00 00 00
Writingto this register, when the write data bits 7–0 matches the card CSN, causes the card to go from the sleep state either
to the isolation state when the write data for this command is zero, or to the configuration state when the write data is not
zero. The pointer to the SERIAL IDENTIFIER is reset. This register is write only.
0×04
0×05
0×06
0×07
RESOURCE DATA
Read only
00 00 00 00
Reading from this register reads the next byte of resource information from the EEPROM. The STATUS register must be
polled until its bit 0 is reset before this register may be read.
STATUS
Bit 0
Read only
0
A one-bit register that, when set, indicates it is okay to read the next data byte from the
RESOURCE DATA register.
CARD-SELECT NUMBER
Read/write
00 00 00 00
Writing to this register sets a card CSN, which is uniquely assigned after the serial identification process. This allows each
card to be individually selected during a Wake[CSN] command.
LOGICAL DEVICE NUMBER
Read/write
00 00 00 00
This register specifies which logical device is being configured.
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
PnP logical device control registers
The registers in Table 4 are repeated for each logical device. These registers control device functions, such as
enabling the device onto the ISA bus.
Table 4. PnP Logical Device Control Registers
ADDRESS PORT
READ/WRITE
CAPABILITY
REGISTER NAME VALUE
POWER UP
VALUE
0×30
ACTIVE
This register controls whether the logical device is active on the bus.
Read/write
00 00 00 00
Bits 7–1
Bit 0
These bits are reserved and must be set to zero.
If set, bit 0 activates the logical device.
An inactive device does not respond to nor drive any ISA bus signals. Before a logical device is activated, I/O range check
must be disabled.
0×31
I/O RANGE CHECK
Read/write
00 00 00 00
This register is used to perform a conflict check on the I/O port range programmed for use by the logical device.
Bits 7–2
Bit 1
These bits are reserved and must be set to zero.
If set to 1, bit 1 I/O range check is enabled. I/O range check is only valid when the logical device is
inactive.
Bit 0
If set to 1, the logical device responds to I/O read operations to its assigned I/O range with a 0×55 when
I/O range check is in operation. If clear, the logical device responds with a 0×AA.
PnP logical device configuration registers
The registers in Table 5 are repeated for each logical device and are used to program the ISA bus resource use
of the device.
Table 5. PnP Logical Device Configuration Registers
ADDRESS PORT
VALUE
READ/WRITE
CAPABILITY
REGISTER NAME VALUE
I/O PORT BASE ADDRESS [15–8]
POWER UP
0×60
0×61
Read/write
00
This register indicates the selected I/O lower limit address bits [15–8] for I/O descriptor 0. When the device is activated,
if there is an address match to register 0×61 and an address match to this register, a chip select is generated to the logical
device.
Bits 7–2
Bits 1–0
Bits 15–10 are not supported, since the logical device uses 10-bit address decoding.
Bits 1–0 have address bits 9 and 8 are indicated here.
I/O PORT BASE ADDRESS [7–0]
Read/write
00 00 00 00
This register indicates the selected I/O lower limit address bits [7–0] for I/O descriptor 0. When the device is activated, if
there is an address match to register 0×60 and an address match to this register, a chip select is generated to the logical
device.
Bits 7–0
Address bits 7–0 are indicated here.
0×70
0×71
INTERRUPT REQUEST LEVEL SELECT
Read/write
00 00
This register indicates the selected interrupt level.
Bits 3–0
INTERRUPT REQUEST TYPE
This register indicates which type of interrupt is used for the selected interrupt level.
These bits select the interrupt level. This device uses 6 interrupts from IRQ3 to IRQ7 and IRQ9.
Read/write 00 00
Bit 7–2
Bit 1
Bit 0
These bits are reserved.
This bit is level, where 1 = high, 0 = low
This bit is type, where 1 = level, 0 = edge
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
Table 6. PnP Logical Device Configuration Registers (continued)
ADDRESS PORT
VALUE
READ/WRITE
CAPABILITY
REGISTER NAME VALUE
DMA CHANNEL SELECT 0
POWER UP
0×74
Read only
00 00 01 00
This register has a value of 4 to indicate that DMA is not supported.
DMA CHANNEL SELECT 1
0×75
Read only
00 00 01 00
This register has a value of 4 to indicate that DMA is not supported.
EEPROM
The TL16PNP100A has been designed to interface with the ST93C56/66 EEPROM (SGS-Thomson) or an
equivalent. The EEPROM provides the block size for each device and the PnP resource data.
memory organization
The EEPROM should be organized as 128/255 words times 16 bits, so its ORG terminal should be connected
to V
or left unconnected. The EEPROM memory organization is shown in Table 7.
CC
Table 7. EEPROM Memory Organization
EEPROM
BIT LOCATION
LOCATION
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
X 0 0 0
PnP Resource Data
X 128/255
EEPROM READ (see Figure 8 and Figure 9)
This device only supports read transactions. The READ op code instruction (10) must be sent to the EEPROM.
Theopcodeisthenfollowedbyan8-bit-longaddressforthe16-bitword. TheREADopcodewithaccompanying
address directs the EEPROM to output serial data on the EEPROM data terminals D and Q, which is connected
to the TL16PNP100A bidirectional serial data bus (SIO). Specifically, when a READ op code and address are
received, the instruction and address are decoded and the addressed EEPROM data is transferred into an
output shift register in the EEPROM. Each read transaction consists of a start bit, 2-bit op code (10), 8-bit
address, and 16-bit data. The TL16PNP100A does not accommodate the EEPROM autoaddress next-word
feature.
READ op code transfer (see Figure 8)
Initially, the EEPROM chip select signal (S) which connects to the TL16PNP100A EEPROM chip select (CS),
is raised. The EEPROM data, D and Q, then sample the TL16PNP100A SIO line on the following rising edges
of the TL16PNP100A serial clock, SCLK, until a 1 is sampled and decoded by the EEPROM as a start bit. The
TL16PNP100A SCLK signal connects to the EEPROM clock C. The READ op code (10) is then sampled on
the next two rising edges of SCLK. TL16PNP100A sources the op code at the falling edges of SCLK.
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
PRINCIPLES OF OPERATION
READ op code transfer (continued)
t
w(SCLKH)
C
(SCLK)
t
w(SCLKL)
t
d1
S
(CS)
t
pd1
t
d2
D/Q
(SIO)
Start
Start
Op Code Input = 1
Op Code Input = 0
Op Code Input
NOTE A: The corresponding TL16PNP100A terminal names are provided in parentheses. D/Q indicates that D and Q terminals in the EEPROMs
are tied together through 2-kΩ resistor.
Figure 8. READ Op Code Transfer
READ address and data transfer (see Figure 9)
After receiving the READ op code, the EEPROM samples the READ address on the next eight rising edges of
SCLK. The device sources the address at the falling edge of SCLK. The EEPROM then sends out a dummy
0 bit on the D/Q line, which is followed by the 16-bit data word with the MSB first. Output data changes are
triggered by the rising edges of SCLK. The data is also read by the TL16PNP100A on the rising edges of SCLK.
C
(SCLK)
t
pd3
S
(CS)
t
d2
t
t
pd2
pd1
t
d3
D/Q
(SIO)
Address Input
Data Output
NOTE A: Thecorrespondingterminalnamesareprovidedinparentheses. D/QindicatesthatDandQterminalsintheEEPROMsaretiedtogether
through 2-kΩ resistor.
Figure 9. READ Address and Data Transfer
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57) MAX
0.120 (3,05)
D
0.090 (2,29)
D1
0.020 (0,51) MIN
3
1
19
0.032 (0,81)
0.026 (0,66)
4
18
D2/E2
D2/E2
E
E1
8
14
0.021 (0,53)
0.013 (0,33)
0.050 (1,27)
9
13
0.007 (0,18)
M
0.008 (0,20) NOM
D/E
D1/E1
D2/E2
NO. OF
PINS
**
MIN
0.385 (9,78)
MAX
MIN
MAX
MIN
MAX
0.395 (10,03)
0.350 (8,89)
0.356 (9,04)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TL16PNP100A
STANDALONE PLUG-AND-PLAY (PnP) CONTROLLER
SLLS200C – MARCH 1995 – REVISED SEPTEMBER 1997
MECHANICAL DATA
PT (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
M
0,08
0,50
0,17
36
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
Gage Plane
9,20
SQ
8,80
0,25
0,05 MIN
0°–7°
1,45
1,35
0,75
0,45
Seating Plane
0,10
1,60 MAX
4040052/B 03/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-136
D. This may also be a thermally-enhanced plastic package with leads connected to the die pads.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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