TLA2518IRTET [TI]
具有 SPI 接口和 GPIO 的小型 8 通道、12 位模数转换器 (ADC) | RTE | 16 | -40 to 85;
| 型号： | TLA2518IRTET |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有 SPI 接口和 GPIO 的小型 8 通道、12 位模数转换器 (ADC) | RTE | 16 | -40 to 85 转换器 模数转换器 |
| 文件： | 总43页 (文件大小：2117K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
具有 SPI 接口和 GPIO 的 TLA2518 小型 8 通道 12 位 ADC
1 特性
2 应用
1
•
•
•
•
小封装尺寸：
WQFN 3mm × 3mm
8 通道，可配置为以下任意组合：
最多 8 个模拟输入、数字输入或数字输出
用于 I/O 扩展的 GPIO：
开漏、推挽数字输出
宽工作范围：
•
•
•
•
宏远程无线电单元 (RRU)
电池管理系统 (BMS)
串式逆变器
–
中央逆变器
–
3 说明
–
TLA2518 是一款易于使用的 8 通道多路复用 12 位
1MSPS 逐次逼近寄存器模数转换器 (SAR ADC)。8 个
通道可独立配置为模拟输入、数字输入或数字输出。
该器件具有一个用于执行 ADC 转换过程的内部振荡
器。
–
–
–
AVDD：2.35V 至 5.5V
DVDD：1.65V 至 5.5V
温度范围：-40°C 至 +85°C
•
•
增强型 SPI 数字接口：
–
–
高速 60MHz 接口
TLA2518 通过兼容 SPI 的接口进行通信，并支持通过
单次转换启动对多个数据样本求平均值。内置的可编程
平均滤波器有助于降低来自模拟输入的噪声，并减少主
机需要读取的数据样本数量。
使用 >13.5MHz SPI 实现最大吞吐量
可编程均值滤波器:
–
–
–
用于求平均值的可编程样本大小
利用内部转换求平均值
16 位分辨率
器件信息(1)
器件型号
TLA2518
封装
封装尺寸（标称值）
WQFN (16)
3.00mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
TLA2518 方框图和 应用
Device Block Diagram
Example Applications
AVDD (VREF
)
AIN / GPIO
AIN / GPIO
DECAP
AVDD
AIN / GPIO
AIN / GPIO
AIN / GPIO
AIN / GPIO
SPI
Controller
DVDD
TLA2518
AIN0 / GPIO0
AIN1 / GPIO1
AIN2 / GPIO2
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
CS
Programmable
Averaging Filters
ADC
AIN / GPIO
AIN / GPIO
SCLK
SDO
SDI
SPI Interface
MUX
VSIGNAL + noise
Sequencer
Pin CFG
Reduced
noise
R1
R2
GND
TLA2518
+
Averaging
Filters
GPO Write
GPI Read
Controller
TLA2518
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SBAS980
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
目录
7.4 Device Functional Modes........................................ 19
7.5 TLA2518 Registers ................................................. 22
Application and Implementation ........................ 29
8.1 Application Information............................................ 29
8.2 Typical Applications ................................................ 29
Power Supply Recommendations...................... 32
9.1 AVDD and DVDD Supply Recommendations......... 32
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Timing Requirements................................................ 5
6.7 Switching Characteristics.......................................... 6
6.8 Typical Characteristics.............................................. 8
Detailed Description ............................................ 12
7.1 Overview ................................................................. 12
7.2 Functional Block Diagram ....................................... 12
7.3 Feature Description................................................. 13
8
9
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 33
11 器件和文档支持 ..................................................... 34
11.1 接收文档更新通知 ................................................. 34
11.2 社区资源................................................................ 34
11.3 商标....................................................................... 34
11.4 静电放电警告......................................................... 34
11.5 Glossary................................................................ 34
12 机械、封装和可订购信息....................................... 34
7
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
Changes from Original (June 2019) to Revision A
Page
•
已更改 将器件状态从“预告信息”更改为“生产数据”.................................................................................................................. 1
2
Copyright © 2019, Texas Instruments Incorporated
TLA2518
www.ti.com.cn
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
5 Pin Configuration and Functions
RTE Package
16-Pin WQFN
Top View
AIN2/GPIO2
AIN3/GPIO3
AIN4/GPIO4
AIN5/GPIO5
1
2
3
4
12
11
10
9
SDO
CS
Thermal
Pad
DVDD
GND
Not to scale
Pin Functions
PIN
FUNCTION(1)
DESCRIPTION
NAME
NO.
15
16
1
AIN0/GPIO0
AIN1/GPIO1
AIN2/GPIO2
AIN3/GPIO3
AIN4/GPIO4
AIN5/GPIO5
AIN6/GPIO6
AIN7/GPIO7
AI, DI, DO
AI, DI, DO
AI, DI, DO
AI, DI, DO
AI, DI, DO
AI, DI, DO
AI, DI, DO
AI, DI, DO
Channel 0; can be configured as either an analog input (default), digital input, or digital output.
Channel 1; can be configured as either an analog input (default), digital input, or digital output.
Channel 2; can be configured as either an analog input (default), digital input, or digital output.
Channel 3; can be configured as either an analog input (default), digital input, or digital output.
Channel 4; can be configured as either an analog input (default), digital input, or digital output.
Channel 5; can be configured as either an analog input (default), digital input, or digital output.
Channel 6; can be configured as either an analog input (default), digital input, or digital output.
Channel 7; can be configured as either an analog input (default), digital input, or digital output.
2
3
4
5
6
Analog supply input, also used as the reference voltage to the ADC; connect a 1-µF
decoupling capacitor to GND.
AVDD
7
Supply
Chip-select input pin; active low. The device takes control of the data bus when CS is low.
The device starts converting the active input channel on the rising edge of CS. SDO goes hi-Z
when CS is high.
CS
11
DI
DECAP
DVDD
GND
8
Supply
Supply
Supply
DI
Connect a decoupling capacitor to this pin for the internal power supply.
Digital I/O supply voltage; connect a 1-µF decoupling capacitor to GND.
Ground for the power supply; all analog and digital signals are referred to this pin voltage.
Serial clock for the SPI interface.
10
9
SCLK
13
14
12
—
SDI
DI
Serial data in for the device.
SDO
DO
Serial data out for the device.
Thermal pad
Supply
Exposed thermal pad; connect to GND.
(1) AI = analog input, DI = digital input, and DO = digital output.
Copyright © 2019, Texas Instruments Incorporated
3
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
MAX
5.5
UNIT
V
DVDD to GND
AVDD to GND
5.5
V
AINx / GPOx(2) to GND
GND – 0.3 AVDD + 0.3
V
Digital input to GND
GND – 0.3
–10
5.5
10
V
Current through any pin except supply pins(3)
Junction temperature, TJ
Storage temperature, Tstg
mA
°C
°C
–40
125
150
–60
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) AINx / GPIOx refers to pins 1, 2, 3, 4, 5, 6, 15, and 16.
(3) Pin current must be limited to 10mA or less.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per
±2000
ANSI/ESDA/JEDEC JS-001, all pins(1)
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLY
AVDD
DVDD
Analog supply voltage
Digital supply voltage
2.35
1.65
3.3
3.3
5.5
5.5
V
V
ANALOG INPUTS
FSR
VIN
Full-scale input range
Absolute input voltage
AINX - GND
AINX - GND
0
AVDD
V
V
–0.1
AVDD + 0.1
TEMPERATURE RANGE
TA Ambient temperature
–40
25
85
℃
(1) AINx refers to AIN0, AIN1, AIN2, AIN3, AIN4, AIN5, AIN6, and AIN7.
6.4 Thermal Information
TLA2518
THERMAL METRIC(1)
RTE (WQFN)
16 PINS
49.7
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
53.4
24.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.3
ΨJB
24.7
RθJC(bot)
9.3
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
4
Copyright © 2019, Texas Instruments Incorporated
TLA2518
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
6.5 Electrical Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
PARAMETER
ANALOG INPUTS
CSH Sampling capacitance
TEST CONDITIONS
MIN
TYP
MAX UNIT
12
pF
DC PERFORMANCE
Resolution
No missing codes
12
±0.3
±0.5
±0.5
±5
bits
LSB
DNL
INL
Differential nonlinearity
Integral nonlinearity
Input offset error
LSB
V(OS)
Post offset calibration
Post offset calibration
LSB
Input offset thermal drift
Gain error
ppm/°C
%FSR
ppm/°C
GE
±0.05
±5
Gain error thermal drift
AC PERFORMANCE
AVDD = 5 V, fIN = 2 kHz
AVDD = 3 V, fIN = 2 kHz
71.5
70.5
dB
dB
SINAD Signal-to-noise + distortion ratio
DECAP Pin
Decoupling capacitor on DECAP
pin
0.1
1
µF
SPI INTERFACE (CS, SCLK, SDI, SDO)
VIH
VIL
Input high logic level
Input low logic level
0.7 x DVDD
–0.3
5.5
V
V
0.3 x DVDD
Source current = 2 mA,
DVDD > 2 V
0.8 x DVDD
0.7 x DVDD
DVDD
DVDD
VOH
Output high logic level
Output low logic level
V
V
Source current = 2 mA,
DVDD ≤ 2 V
Sink current = 2 mA, DVDD > 2 V
0
0
0.4
VOL
Sink current = 2 mA, DVDD ≤ 2 V
0.2 x DVDD
GPIOs
VIH
Input high logic level
Input low logic level
0.7 x AVDD
–0.3
AVDD + 0.3
0.3 x AVDD
V
V
VIL
GPO_DRIVE_CFG = push-pull,
ISOURCE = 2 mA
VOH
Output high logic level
0.8 x AVDD
0
AVDD
V
VOL
IOH
IOL
Output low logic level
ISINK = 2 mA
0.2 x AVDD
V
Output high source current
Output low sink current
VOH > 0.7 x AVDD
VOL < 0.3 x AVDD
5
5
mA
mA
POWER-SUPPLY CURRENTS
Full throughput, AVDD = 5 V
Full throughput, AVDD = 3 V
No conversion, AVDD = 5 V
470
440
10
600
550
25
IAVDD
Analog supply current
µA
6.6 Timing Requirements
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
MIN
MAX
UNIT
CONVERSION CYCLE
fCYCLE
tCYCLE
tACQ
Sampling frequency
1000
kSPS
s
ADC cycle-time period
Acquisition time
1 / fCYCLE
300
ns
tQT_ACQ
Quiet acquisition time
10
ns
Copyright © 2019, Texas Instruments Incorporated
5
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
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Timing Requirements (continued)
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
MIN
10
MAX
UNIT
ns
tD_CNVCAP
tWH_CSZ
tWL_CSZ
Quiet conversion time
Pulse duration: CS high
Pulse duration: CS low
10
ns
10
ns
SPI INTERFACE TIMINGS
fCLK
Maximum SCLK frequency
60
MHz
ns
tCLK
Minimum SCLK time period
16.67
0.45
0.45
3.5
1.5
2
tPH_CK
tPL_CK
tSU_CSCK
tSU_CKDI
tHT_CKDI
tD_CKCS
SCLK high time
0.55
0.55
tCLK
tCLK
ns
SCLK low time
Setup time: CS falling to the first SCLK capture edge
Setup time: SDI data valid to the SCLK capture edge
Hold time: SCLK capture edge to data valid on SDI
Delay time: last SCLK falling to CS rising
ns
ns
6
ns
6.7 Switching Characteristics
at AVDD = 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum values
at TA = –40°C to +85°C; typical values at TA = 25°C
PARAMETER
CONVERSION CYCLE
Test Conditions
MIN
MAX
UNIT
tCONV
tACQ
ADC conversion time
Acquisition time
600
ns
ns
400
RESET
AVDD ≥ 2.35 V,
CDECAP = 1 µF
tPU
Power-up time for device
5
5
ms
ms
Delay time; RST bit = 1b to device reset
complete(1)
tRST
SPI INTERFACE TIMINGS
tDEN_CSDO Delay time: CS falling to data enable
tDZ_CSDO
15
15
ns
ns
Delay time: CS rising to SDO going Hi-Z
Delay time: SCLK launch edge to (next)
data valid on SDO
tD_CKDO
16
ns
(1) RST bit is automatically reset to 0b after tRST
.
6
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TLA2518
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
Sample
S
Sample
S + 1
CS
tcycle
tconv_max
tconv
tconv_min
tacq
ADCST (Internal)
CNV (S)
ACQ (S + 1)
图 1. Conversion Cycle Timing
tCLK
tPH_CK
tPL_CK
SCLK(1)
CS
tSU_CKDI
tHT_CKDI
tSU_CSCK
tD_CKCS
SCLK(1)
SDI
tDEN_CSDO
tDZ_CSDO
tD_CKDO
SDO
SDO
(1) The SCLK polarity, launch edge, and capture edge depend on the SPI protocol selected.
图 2. SPI-Compatible Serial Interface Timing
版权 © 2019, Texas Instruments Incorporated
7
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
6.8 Typical Characteristics
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
0
45000
39581
-30
30000
-60
-90
25955
15000
-120
-150
0
0
100
200 300
Frequency (kHz)
400
500
2048
2049
C008
C001
Output Code
fIN = 2 kHz, SNR = 73.2 dB, THD = –92.1 dB
Standard deviation = 0.49 LSB
图 4. Typical FFT
图 3. DC Input Histogram
0.8
0.4
0
0.8
0.4
0
-0.4
-0.8
-0.4
-0.8
0
1024
2048
Output Code
3072
4095
0
1024
2048
Output Code
3072
4095
C002
C004
Typical DNL = ±0.5 LSB
Typical INL = ±0.5 LSB
图 5. Typical DNL
图 6. Typical INL
0.5
0.3
0.75
0.45
Maximum
Minimum
Maximum
Minimum
0.1
0.15
-0.1
-0.3
-0.5
-0.15
-0.45
-0.75
-40
-15
10
35
60
85
-40
-15
10
35
60
85
Temperature (èC)
Temperature (èC)
C003
C005
图 7. DNL vs Temperature
图 8. INL vs Temperature
8
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TLA2518
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
0.5
0.75
Maximum
Minimum
Maximum
Minimum
0.3
0.45
0.1
0.15
-0.1
-0.3
-0.5
-0.15
-0.45
-0.75
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
C018
C019
图 9. DNL vs AVDD
图 10. INL vs AVDD
2
1.2
0.4
-0.4
-1.2
-2
0.05
0.03
0.01
-0.01
-0.03
-0.05
-40
-15
10 35
Temperature (°C)
60
85
-40
-15
10 35
Temperature (°C)
60
85
C006
C007
图 11. Offset Error vs Temperature
图 12. Gain Error vs Temperature
2
1.2
0.4
-0.4
-1.2
-2
0.05
0.03
0.01
-0.01
-0.03
-0.05
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
C016
C017
图 13. Offset Error vs AVDD
图 14. Gain Error vs AVDD
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Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
73.2
73.1
73
11.8
73.5
12
SINAD
SNR
ENOB
SINAD
SNR
ENOB
11.775
11.75
11.725
11.7
73
11.85
11.7
11.55
72.5
72
72.9
72.8
71.5
11.4
5.5
-40
-15
10 35
Temperature (°C)
60
85
2.5
3
3.5
4
AVDD (V)
4.5
5
C009
C010
图 15. Noise Performance vs Temperature
图 16. Noise Performance vs AVDD
-90.3
-90.5
-90.7
-90.9
-91.1
94.8
94.4
94
-82
-84
-86
-88
-90
-92
96
94
92
90
88
86
THD
SFDR(dBFS)
THD
SFDR
93.6
93.2
85
-40
-15
10 35
Temperature (°C)
60
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
C011
C012
图 17. Distortion Performance vs Temperature
图 18. Distortion Performance vs AVDD
485
479
473
467
461
455
500
480
460
440
420
-40
-15
10 35
Temperature (°C)
60
85
2.5
3
3.5
4
AVDD (V)
4.5
5
5.5
C013
C014
图 19. Analog Supply Current vs Temperature
图 20. Analog Supply Current vs AVDD
10
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
Typical Characteristics (接下页)
at TA = 25°C, AVDD = 5 V, DVDD = 1.8 V, and fSAMPLE = 1 MSPS (unless otherwise noted)
500
400
300
200
100
0
0
200
400 600
Throughput (kSPS)
800
1000
C015
图 21. Analog Supply Current vs Throughput
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7 Detailed Description
7.1 Overview
The TLA2518 is a small, eight-channel, multiplexed, 12-bit, 1-MSPS, analog-to-digital converter (ADC) with an
enhanced-SPI serial interface. The eight channels of the TLA2518 can be individually configured as either analog
inputs, digital inputs, or digital outputs. The device uses an internal oscillator for conversion. The analog input
channel selection can be auto-sequenced to simplify the digital interface with the host.
The device features a programmable averaging filter that outputs a 16-bit result for enhanced resolution.
7.2 Functional Block Diagram
DECAP
AVDD
DVDD
AIN0 / GPIO0
AIN1 / GPIO1
AIN2 / GPIO2
AIN3 / GPIO3
AIN4 / GPIO4
AIN5 / GPIO5
AIN6 / GPIO6
AIN7 / GPIO7
CS
Averager
1 to 128
ADC
SCLK
SPI Interface
SDO
SDI
MUX
Sequencer
Pin CFG
GND
GPO Write
GPI Read
12
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7.3 Feature Description
7.3.1 Multiplexer and ADC
The eight channels of the multiplexer can be independently configured as ADC inputs or general-purpose
inputs/outputs (GPIOs). 图 22 shows that each input pin has ESD protection diodes to AVDD and GND. On
power-up or after device reset, all eight multiplexer channels are configured as analog inputs.
图 22 shows an equivalent circuit for pins configured as analog inputs. The ADC sampling switch is represented
by ideal switch (SW) in series with the resistor RSW (typically 150 Ω) and the sampling capacitor, CSH (typically 12
pF).
GPO_VALUE[0]
GPIO_CFG[0]
AVDD
GPI_VALUE[0]
PIN_CFG[0]
AIN0 / GPIO0
RSW
SW
MUX
CSH
Multiplexer
AVDD
ADC
AIN7 / GPIO7
PIN_CFG[7]
GPI_VALUE[7]
GPIO_CFG[7]
GPO_VALUE[7]
图 22. Analog Inputs, GPIOs, and ADC Connections
During acquisition, the SW switch is closed to allow the signal on the selected analog input channel to charge the
internal sampling capacitor. During conversion, the SW switch is opened to disconnect the analog input channel
from the sampling capacitor.
The multiplexer channels can be configured as GPIOs in the PIN_CFG register. The direction of a GPIO (either
as an input or an output) can be set in the GPIO_CFG register. The logic level on the channels configured as
digital inputs can be read from the GPI_VALUE register. The digital outputs can be accessed by writing to the
GPO_VALUE register. The digital outputs can be configured as either open-drain or push-pull in the
GPO_DRIVE_CFG register.
7.3.2 Reference
The device uses the analog supply voltage (AVDD) as a reference for the analog-to-digital conversion process.
TI recommends connecting a 1-µF, low-equivalent series resistance (ESR) ceramic decoupling capacitor
between the AVDD and GND pins.
7.3.3 ADC Transfer Function
The ADC output is in straight binary format. 公式 1 computes the ADC resolution:
1 LSB = VREF / 2N
where:
•
•
VREF = AVDD
N = 12
(1)
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Feature Description (接下页)
图 23 and 表 1 detail the transfer characteristics for the device.
PFSC
MC + 1
MC
NFSC+1
NFSC
VIN
1 LSB
AVDD/2 (AVDD/2 + 1 LSB)
(AVDD œ 1 LSB)
图 23. Ideal Transfer Characteristics
表 1. Transfer Characteristics
IDEAL OUTPUT
CODE
INPUT VOLTAGE FOR SINGLE-ENDED INPUT
CODE
DESCRIPTION
≤1 LSB
1 LSB to 2 LSBs
NFSC
NFSC + 1
MC
Negative full-scale code
000
001
800
801
FFF
—
Mid code
(AVDD / 2) to (AVDD / 2) + 1 LSB
(AVDD / 2) + 1 LSB to (AVDD / 2) + 2 LSB
≥ AVDD – 1 LSB
MC + 1
PFSC
—
Positive full-scale code
7.3.4 ADC Offset Calibration
The variation in ADC offset error resulting from changes in temperature or AVDD can be calibrated by setting the
CAL bit in the GENERAL_CFG register. The CAL bit is reset to 0 after calibration. The host can poll the CAL bit
to check the ADC offset calibration completion status.
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7.3.5 Programmable Averaging Filter
The TLA2518 features a built-in oversampling (OSR) function that can be used to average several samples. The
averaging filter can be enabled by programming the OSR[2:0] bits in the OSR_CFG register. The averaging filter
configuration is common to all analog input channels. 图 24 shows that the averaging filter module output is 16
bits long. In manual conversion mode and auto-sequence mode, only the first conversion for the selected analog
input channel must be initiated by the host; see the Manual Mode and Auto-Sequence Mode sections. As shown
in 图 24, any remaining conversions for the selected averaging factor are generated internally. The time required
to complete the averaging operation is determined by the sampling speed and number of samples to be
averaged. As shown in 图 24, the 16-bit result can be read out after the averaging operation completes.
Sample
AINx
(start of averaging)
Sample
AINx
Sample
AINx
CS
N œ 1 conversions triggered
internally
tAVG = N samples x tCYCLE
SCLK
SDO
[15:0] Data
16 clocks
图 24. Averaging Example
公式 2 provides the LSB value of the 16-bit average result.
AVDD
1 LSB =
216
(2)
7.3.6 General-Purpose I/Os
The eight channels of the TLA2518 can be independently configured as analog inputs, digital inputs, or digital
outputs. 表 2 shows how the PIN_CFG and GPIO_CFG registers can be used to configure the device channels.
表 2. Configuring Channels as Analog Inputs or GPIOs
PIN_CFG[7:0]
GPIO_CFG[7:0]
GPO_DRIVE_CFG[7:0]
CHANNEL CONFIGURATION
Analog input (default)
0
1
1
1
x
0
1
1
x
x
0
1
Digital input
Digital output; open-drain driver
Digital output; push-pull driver
Digital outputs can be configured to logic 1 or 0 by writing to the GPO_VALUE register. Reading the GPI_VALUE
register returns the logic level for all channels configured as digital inputs or digital outputs. The GPI_VALUE
register can be read to detect a failure in external components, such as a floating pullup resistor or a low-
impedance pulldown resistor, that prevents digital outputs being set to the desired logic level.
7.3.7 Oscillator and Timing Control
The device uses an internal oscillator for conversion. When using the averaging module, the host initiates the
first conversion and subsequent conversions are generated internally by the device. Also, in autonomous mode
of operation, the start of the conversion signal is generated by the device. 表 3 describes how the sampling rate
can be controlled by the OSC_SEL and CLK_DIV[3:0] register fields when the device generates the start of the
conversion.
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表 3. Configuring Sampling Rate for Internal Conversion Start Control
OSC_SEL = 0
OSC_SEL = 1
CLK_DIV[3:0]
SAMPLING FREQUENCY, fCYCLE
(kSPS)
CYCLE TIME,
tCYCLE (µs)
SAMPLING FREQUENCY,
CYCLE TIME, tCYCLE
(µs)
fCYCLE (kSPS)
31.25
20.83
15.63
10.42
7.81
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
1000
666.7
500
1
1.5
2
32
48
64
333.3
250
3
96
4
128
192
256
384
512
768
1024
1536
2048
3072
4096
6144
166.7
125
6
5.21
8
3.91
83
12
16
24
32
48
64
96
128
192
2.60
62.5
41.7
31.3
20.8
15.6
10.4
7.8
1.95
1.3
0.98
0.65
0.49
0.33
0.24
5.2
0.16
The conversion time of the device, given by tCONV in the Switching Characteristics table, is independent of the
OSC_SEL and CLK_DIV[3:0] configuration.
7.3.8 Output Data Format
图 25 shows various SPI frames for reading data. The data output is MSB aligned. If averaging is enabled the
output data from the ADC are 16 bits long, otherwise the output data are 12 bits long. Optionally, a 4-bit channel
ID can be appended at the end of the output data by configuring the APPEND_STATUS[1:0] field.
CS
SCLK
12
13
14
15
16
18
19
20
17
1
2
Data output when averaging is disabled
OSR[2:0] = 00b
12 SCLKs minimum. Remaining clocks optional.
SDO
LSB
Channel ID
MSB
12 bit ADC data
4 bits optional
Data output when averaging is enabled
OSR[2:0] > 00b
16 SCLKs minimum. Remaining clocks optional.
SDO
LSB
Channel ID
MSB
16 bit averaged ADC data
4 bits optional
图 25. SPI Frames for Reading Data
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7.3.9 Device Programming
7.3.9.1 Enhanced-SPI Interface
The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds
and still achieve full throughput. As described in 表 4, the host controller can use any of the four SPI-compatible
protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device.
表 4. SPI Protocols for Configuring the Device
SCLK POLARITY
(At the CS Falling Edge)
SCLK PHASE
(Capture Edge)
PROTOCOL
CPOL_CPHA[1:0]
DIAGRAM
SPI-00
SPI-01
SPI-10
SPI-11
Low
Low
High
High
Rising
Falling
Falling
Rising
00b
01b
10b
11b
图 26
图 27
图 26
图 27
On power-up or after coming out of any asynchronous reset, the device supports the SPI-00 protocol for data
read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0]
field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must
adhere to the newly-selected protocol.
CS
CS
CPOL = 0
CPOL = 0
SCLK
SCLK
CPOL = 1
CPOL = 1
SDO
0
MSB
MSB-1
LSB+1
LSB
MSB
MSB-1
LSB+1
LSB
SDO
MSB-2
图 27. Standard SPI Timing Protocol
图 26. Standard SPI Timing Protocol
(CPHA = 1)
(CPHA = 0)
7.3.9.2 Register Read/Write Operation
The device supports the commands listed in 表 5 to access the internal configuration registers.
表 5. Opcodes for Commands
OPCODE
0000 0000b
0001 0000b
0000 1000b
0001 1000b
0010 0000b
COMMAND DESCRIPTION
No operation
Single register read
Single register write
Set bit
Clear bit
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7.3.9.2.1 Register Write
A 24-bit SPI frame is required for writing data to configuration registers. The 24-bit data on SDI, as shown in 图
28. consists of an 8-bit write command (0000 1000b), an 8-bit register address, and 8-bit data. The write
command is decoded on the CS rising edge and the specified register is updated with the 8-bit data specified
during the register write operation.
CS
SCLK
18
1
2
8
9
10
16
17
24
0000 1000b
(WR_REG)
SDI
8-bit Address
8-bit Data
图 28. Register Write Operation
7.3.9.2.2 Register Read
Register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second
SPI frame reads data from the register address provided in the first frame. As shown in 图 29, the 8-bit register
address and the 8-bit dummy data are sent over the SDI pin during the first 24-bit frame with the read command
(0001 0000b). On the rising edge of CS, the read command is decoded and the requested register data are
available for reading during the next frame. During the second frame, the first eight bits on SDO correspond to
the requested register read. During the second frame, SDI can be used to initiate another operation or can be set
to 0.
CS
SCLK
18
1
2
8
9
10
16
17
24
18
1
2
8
9
10
16
17
24
0001 0000b
(RD_REG)
SDI
8-bit Address
0000 0000b
Command
8-bit Address
8-bit Data
Optional; can set SDI = 0
SDO
8-bit Register Data
图 29. Register Read Operation
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7.4 Device Functional Modes
表 6 lists the functional modes supported by the TLA2518.
表 6. Functional Modes
FUNCTIONAL
MODE
CONVERSION CONTROL
MUX CONTROL
SEQ_MODE[1:0]
Manual
On-the-fly
CS rising edge
CS rising edge
CS rising edge
Register write to MANUAL_CHID
First 5 bits after the CS falling edge
Channel sequencer
00b
10b
01b
Auto-sequence
The device powers up in manual mode and can be configured into either of these modes by writing the
configuration registers for the desired mode.
7.4.1 Device Power-Up and Reset
On power-up, the BOR bit is set indicating a power-cycle or reset event. The device can be reset by setting the
RST bit or by recycling the power on the AVDD pin.
7.4.2 Manual Mode
Manual mode allows the external host processor to directly select the analog input channel. 图 30 shows the
steps for operating the device in manual mode.
Idle
SEQ_MODE = 0
Configure channels as AIN/GPIO using PIN_CFG
Select Manual mode
(SEQ_MODE = 00b)
Configure desired Channel ID in MANUAL_CHID field
Host starts conversion and reads conversion result
No
Yes
Same
Channel ID?
图 30. Device Operation in Manual Mode
In manual mode, the command to switch to a new channel (indicated by cycle N in 图 31) is decoded by the
device on the CS rising edge. The CS rising edge is also the start of the conversion signal, and therefore the
device samples the previously selected MUX channel in cycle N+1. The newly selected analog input channel
data are available in cycle N+2. For switching the analog input channel, a register write to the MANUAL_CHID
field requires 24 clocks; see the Register Write section for more details. After a channel is selected, the number
of clocks required for reading the output data depends on the device output data frame size; see the Output Data
Format section for more details.
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Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
Switch to AINy
Switch to AINz
Switch to AINx
Data AINy
SDO
Data AINx
24 clocks
Data AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX OUT = AINz
MUX
Cycle N
Cycle (N + 1)
Cycle (N + 2)
图 31. Starting Conversions and Reading Data in Manual Mode
7.4.3 On-the-Fly Mode
In the on-the-fly mode of operation, the analog input channel is selected, as shown in 图 32, using the first five
bits on SDI without waiting for the CS rising edge. Thus, the ADC samples the newly selected channel on the CS
edge and there is no latency between the channel selection and the ADC output data.
Sample
AINx
Sample
AINx
Sample
AINy
Sample
AINz
tCONV
tCYCLE
CS
SCLK
SDI
2
2
1
24
1
3
4
5
12
1
3
4
5
12
5 clocks
SEQ_MODE =
10b
4-bit AINy ID
1
4-bit AINz ID
1
12 clocks
Data AINx
12 clocks
SDO
Data AINx
24 clocks
Data AINy
MUX OUT = AINz
MUX OUT = AINx
100-ns
MUX OUT = AINx
MUX OUT = AINy
MUX
No Cycle Latency
图 32. Starting Conversions and Reading Data in On-the-Fly Mode
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The number of clocks required for reading the output data depends on the device output data frame size; see the
Output Data Format section for more details.
7.4.4 Auto-Sequence Mode
In auto-sequence mode, the internal channel sequencer switches the multiplexer to the next analog input
channel after every conversion. The desired analog input channels can be configured for sequencing in the
AUTO_SEQ_CHSEL register. To enable the channel sequencer, set SEQ_START = 1b. After every conversion,
the channel sequencer switches the multiplexer to the next analog input in ascending order. To stop the channel
sequencer from selecting channels, set SEQ_START = 0b.
In the example shown in 图 33, AIN2 and AIN6 are enabled for sequencing in AUTO_SEQ_CHSEL. The channel
sequencer loops through AIN2 and AIN6 and repeats until SEQ_START is set to 0b. The number of clocks
required for reading the output data depends on the device output data frame size; see the Output Data Format
section for more details.
Sample
AINx
Sample
AIN2
Sample
AIN6
Sample
AIN2
Sample
AIN6
tCYCLE
CS
SCLK
SDI
SEQ_START
SDO
Data AIN6
Data AIN2
Data AINx
24 clocks
Data AINx
Data AIN2
12 clocks
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AIN2
MUX OUT = AIN6
MUX OUT = AINx
MUX
Scan channels AIN2 and AIN6 and repeat
图 33. Starting Conversions and Reading Data in Auto-Sequence Mode
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7.5 TLA2518 Registers
Table 7 lists the TLA2518 registers. All register offset addresses not listed in Table 7 should be considered as
reserved locations and the register contents should not be modified.
Table 7. TLA2518 Registers
Address
Acronym
Register
Name
Section
0x0
0x1
SYSTEM_STATUS
GENERAL_CFG
DATA_CFG
SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
DATA_CFG Register (Address = 0x2) [reset = 0x0]
OSR_CFG Register (Address = 0x3) [reset = 0x0]
OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
PIN_CFG Register (Address = 0x5) [reset = 0x0]
0x2
0x3
OSR_CFG
0x4
OPMODE_CFG
PIN_CFG
0x5
0x7
GPIO_CFG
GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_VALUE Register (Address = 0xB) [reset = 0x0]
GPI_VALUE Register (Address = 0xD) [reset = 0x0]
SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
0x9
GPO_DRIVE_CFG
GPO_VALUE
0xB
0xD
0x10
0x11
0x12
GPI_VALUE
SEQUENCE_CFG
CHANNEL_SEL
AUTO_SEQ_CH_SEL
Complex bit access types are encoded to fit into small table cells. Table 8 shows the codes that are used for
access types in this section.
Table 8. TLA2518 Access Type Codes
Access Type
Read Type
R
Code
Description
R
Read
Write Type
W
W
Write
Reset or Default Value
-n
Value after reset or the default
value
Register Array Variables
i,j,k,l,m,n
When these variables are used in
a register name, an offset, or an
address, they refer to the value of
a register array where the register
is part of a group of repeating
registers. The register groups form
a hierarchical structure and the
array is represented with a
formula.
y
When this variable is used in a
register name, an offset, or an
address it refers to the value of a
register array.
7.5.1 SYSTEM_STATUS Register (Address = 0x0) [reset = 0x81]
SYSTEM_STATUS is shown in Figure 34 and described in Table 9.
Return to the Summary Table.
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Figure 34. SYSTEM_STATUS Register
7
6
5
4
3
2
1
0
RSVD
SEQ_STATUS
RESERVED
R-0b
OSR_DONE
CRCERR_FUS
E
RESERVED
BOR
R-1b
R-0b
R/W-0b
R-0b
R-0b
R/W-1b
Table 9. SYSTEM_STATUS Register Field Descriptions
Bit
7
Field
Type
R
Reset
1b
Description
RSVD
Reads return 1b.
6
SEQ_STATUS
R
0b
Status of the channel sequencer.
0b = Sequence stopped
1b = Sequence in progress
Reserved. Reads return 0b.
5-4
3
RESERVED
OSR_DONE
R
0b
0b
R/W
Averaging status. Clear this bit by writing 1b to this bit.
0b = Averaging in progress or not started; average result is not
ready.
1b = Averaging complete; average result is ready.
2
CRCERR_FUSE
R
0b
Device power-up configuration CRC check status. To re-evaluate
this bit, software reset the device or power cycle AVDD.
0b = No problems detected in power-up configuration.
1b = Device configuration not loaded correctly.
Reserved. Reads return 0b.
1
0
RESERVED
BOR
R
0b
1b
R/W
Brown out reset indicator. This bit is set if brown out condition occurs
or device is power cycled. Write 1b to this bit to clear the flag.
0b = No brown out from the last time this bit was cleared.
1b = Brown out condition detected or device power cycled.
7.5.2 GENERAL_CFG Register (Address = 0x1) [reset = 0x0]
GENERAL_CFG is shown in Figure 35 and described in Table 10.
Return to the Summary Table.
Figure 35. GENERAL_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
CH_RST
R/W-0b
CAL
RST
W-0b
R/W-0b
Table 10. GENERAL_CFG Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-3
2
RESERVED
CH_RST
Reserved. Reads return 0b.
Force all channels to be analog inputs.
0b = Normal operation.
R/W
0b
1b
= All channels are set as analog inputs irrespective of
configuration in other registers.
1
0
CAL
RST
R/W
W
0b
0b
Calibrate ADC offset.
0b = Normal operation.
1b = ADC offset is calibrated. After calibration is complete, this bit is
set to 0b.
Software reset all registers to default values.
0b = Normal operation.
1b = Device is reset. After reset is complete, this bit is set to 0b and
BOR bit is set to 1b.
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7.5.3 DATA_CFG Register (Address = 0x2) [reset = 0x0]
DATA_CFG is shown in Figure 36 and described in Table 11.
Return to the Summary Table.
Figure 36. DATA_CFG Register
7
6
5
4
3
2
1
0
FIX_PAT
R/W-0b
RESERVED
R-0b
APPEND_STATUS[1:0]
R/W-0b
RESERVED
R-0b
CPOL_CPHA[1:0]
R/W-0b
Table 11. DATA_CFG Register Field Descriptions
Bit
Field
Type
Reset
Description
7
FIX_PAT
R/W
0b
Device outputs fixed data bits which can be helpful for debugging
communication with the device.
0b = Normal operation.
1b = Device outputs fixed code 0xA5A repeatitively when reading
ADC data.
6
RESERVED
R
0b
0b
Reserved. Reads return 0b.
5-4
APPEND_STATUS[1:0]
R/W
Append 4-bit channel ID or status flags to output data.
0b = Channel ID is not appended to ADC data.
1b = 4-bit channel ID is appended to ADC data.
10b = Reserved.
11b = Reserved.
3-2
1-0
RESERVED
R
0b
0b
Reserved. Reads return 0b.
CPOL_CPHA[1:0]
R/W
This field sets the polarity and phase of SPI communication.
0b = CPOL = 0, CPHA = 0.
1b = CPOL = 0, CPHA = 1.
10b = CPOL = 1, CPHA = 0.
11b = CPOL = 1, CPHA = 1.
7.5.4 OSR_CFG Register (Address = 0x3) [reset = 0x0]
OSR_CFG is shown in Figure 37 and described in Table 12.
Return to the Summary Table.
Figure 37. OSR_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
OSR[2:0]
R/W-0b
Table 12. OSR_CFG Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-3
2-0
RESERVED
OSR[2:0]
Reserved. Reads return 0b.
R/W
0b
Selects the oversampling ratio for ADC conversion result.
0b = No averaging
1b = 2 samples
10b = 4 samples
11b = 8 samples
100b = 16 samples
101b = 32 samples
110b = 64 samples
111b = 128 samples
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7.5.5 OPMODE_CFG Register (Address = 0x4) [reset = 0x0]
OPMODE_CFG is shown in Figure 38 and described in Table 13.
Return to the Summary Table.
Figure 38. OPMODE_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
OSC_SEL
R/W-0b
CLK_DIV[3:0]
R/W-0b
Table 13. OPMODE_CFG Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-5
4
RESERVED
OSC_SEL
Reserved. Reads return 0b.
R/W
0b
Selects the oscillator for internal timing generation.
0b = High-speed oscillator.
1b = Low-power oscillator.
3-0
CLK_DIV[3:0]
R/W
0b
Refer to section on oscillator and timing control for details.
7.5.6 PIN_CFG Register (Address = 0x5) [reset = 0x0]
PIN_CFG is shown in Figure 39 and described in Table 14.
Return to the Summary Table.
Figure 39. PIN_CFG Register
7
6
5
4
3
2
1
0
PIN_CFG[7:0]
R/W-0b
Table 14. PIN_CFG Register Field Descriptions
Bit
7-0
Field
PIN_CFG[7:0]
Type
Reset
Description
R/W
0b
Configure device channels AIN / GPIO [7:0] as analog inputs or
GPIOs.
0b = Channel is configured as analog input.
1b = Channel is configured as GPIO.
7.5.7 GPIO_CFG Register (Address = 0x7) [reset = 0x0]
GPIO_CFG is shown in Figure 40 and described in Table 15.
Return to the Summary Table.
Figure 40. GPIO_CFG Register
7
6
5
4
3
2
1
0
GPIO_CFG[7:0]
R/W-0b
Table 15. GPIO_CFG Register Field Descriptions
Bit
7-0
Field
GPIO_CFG[7:0]
Type
Reset
Description
R/W
0b
Configure GPIO[7:0] as either digital inputs or digital outputs.
0b = GPIO is configured as digital input.
1b = GPIO is configured as digital output.
Copyright © 2019, Texas Instruments Incorporated
25
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
7.5.8 GPO_DRIVE_CFG Register (Address = 0x9) [reset = 0x0]
GPO_DRIVE_CFG is shown in Figure 41 and described in Table 16.
Return to the Summary Table.
Figure 41. GPO_DRIVE_CFG Register
7
6
5
4
3
2
1
0
GPO_DRIVE_CFG[7:0]
R/W-0b
Table 16. GPO_DRIVE_CFG Register Field Descriptions
Bit
7-0
Field
GPO_DRIVE_CFG[7:0]
Type
Reset
Description
R/W
0b
Configure digital outputs GPO[7:0] as open-drain or push-pull
outputs.
0b = Digital output is open-drain; connect external pullup resistor.
1b = Push-pull driver is used for digital output.
7.5.9 GPO_VALUE Register (Address = 0xB) [reset = 0x0]
GPO_VALUE is shown in Figure 42 and described in Table 17.
Return to the Summary Table.
Figure 42. GPO_VALUE Register
7
6
5
4
3
2
1
0
GPO_VALUE[7:0]
R/W-0b
Table 17. GPO_VALUE Register Field Descriptions
Bit
7-0
Field
GPO_VALUE[7:0]
Type
Reset
Description
R/W
0b
Logic level to be set on digital outputs GPO[7:0].
0b = Digital output set to logic 0.
1b = Digital output set to logic 1.
7.5.10 GPI_VALUE Register (Address = 0xD) [reset = 0x0]
GPI_VALUE is shown in Figure 43 and described in Table 18.
Return to the Summary Table.
Figure 43. GPI_VALUE Register
7
6
5
4
3
2
1
0
GPI_VALUE[7:0]
R-0b
Table 18. GPI_VALUE Register Field Descriptions
Bit
7-0
Field
GPI_VALUE[7:0]
Type
Reset
Description
R
0b
Readback the logic level on channels configured digital inputs.
0b = Digital input is at logic 0.
1b = Digital input is at logic 1.
7.5.11 SEQUENCE_CFG Register (Address = 0x10) [reset = 0x0]
SEQUENCE_CFG is shown in Figure 44 and described in Table 19.
Return to the Summary Table.
26
Copyright © 2019, Texas Instruments Incorporated
TLA2518
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ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
Figure 44. SEQUENCE_CFG Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
SEQ_START
R/W-0b
RESERVED
R-0b
SEQ_MODE[1:0]
R/W-0b
Table 19. SEQUENCE_CFG Register Field Descriptions
Bit
7-5
4
Field
Type
R
Reset
0b
Description
RESERVED
SEQ_START
Reserved. Reads return 0b.
R/W
0b
Control for start of channel sequence when using auto sequence
mode (SEQ_MODE = 01b).
0b = Stop channel sequencing.
1b = Start channel sequencing in ascending order for channels
enabled in AUTO_SEQ_CH_SEL register.
3-2
1-0
RESERVED
R
0b
0b
Reserved. Reads return 0b.
SEQ_MODE[1:0]
R/W
Selects the mode of scanning of analog input channels.
0b = Manual sequence mode; channel selected by MANUAL_CHID
field.
1b
=
Auto
sequence
mode;
channel
selected
by
AUTO_SEQ_CH_SEL.
10b = On-the-fly sequence mode.
11b = Reserved.
7.5.12 CHANNEL_SEL Register (Address = 0x11) [reset = 0x0]
CHANNEL_SEL is shown in Figure 45 and described in Table 20.
Return to the Summary Table.
Figure 45. CHANNEL_SEL Register
7
6
5
4
3
2
1
0
RESERVED
R-0b
MANUAL_CHID[3:0]
R/W-0b
Table 20. CHANNEL_SEL Register Field Descriptions
Bit
Field
Type
R
Reset
0b
Description
7-4
3-0
RESERVED
Reserved. Reads return 0b.
MANUAL_CHID[3:0]
R/W
0b
In manual mode (SEQ_MODE = 00b), this field contains the 4-bit
channel ID of the analog input channel for next ADC conversion. For
valid ADC data, the selected channel must not be configured as
GPIO in PIN_CFG register. 1xxx = Reserved.
0b = AIN0
1b = AIN1
10b = AIN2
11b = AIN3
100b = AIN4
101b = AIN5
110b = AIN6
111b = AIN7
7.5.13 AUTO_SEQ_CH_SEL Register (Address = 0x12) [reset = 0x0]
AUTO_SEQ_CH_SEL is shown in Figure 46 and described in Table 21.
Return to the Summary Table.
Copyright © 2019, Texas Instruments Incorporated
27
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
Figure 46. AUTO_SEQ_CH_SEL Register
7
6
5
4
3
2
1
0
AUTO_SEQ_CH_SEL[7:0]
R/W-0b
Table 21. AUTO_SEQ_CH_SEL Register Field Descriptions
Bit
7-0
Field
Type
Reset
Description
AUTO_SEQ_CH_SEL[7:0] R/W
0b
Select analog input channels AIN[7:0] in for auto sequencing mode.
0b = Analog input channel is not enabled in scanning sequence.
1b = Analog input channel is enabled in scanning sequence.
28
版权 © 2019, Texas Instruments Incorporated
TLA2518
www.ti.com.cn
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
8 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The two primary circuits required to maximize the performance of a high-precision, successive approximation
register analog-to-digital converter (SAR ADC) are the input driver and the reference driver circuits. This section
details some general principles for designing the input driver circuit, reference driver circuit, and provides some
application circuits designed for the TLA2518.
8.2 Typical Applications
8.2.1 Mixed-Channel Configuration
AVDD (VREF
)
Digital Output (open-drain)
Digital Output (push-pull)
Analog Input
Analog Input
Analog Input
Analog Input
SPI
Controller
Device
Digital Input
Digital Input
图 47. DAQ Circuit: Single-Supply DAQ
8.2.1.1 Design Requirements
The goal of this application is to configure some channels of the TLA2518 as digital inputs, open-drain digital
outputs, and push-pull digital outputs.
8.2.1.2 Detailed Design Procedure
The TLA2518 can support GPIO functionality at each input pin. Any analog input pin can be independently
configured as a digital input, a digital open-drain output, or a digital push-pull output though the PIN_CFG and
GPIO_CFG registers; see 表 2.
8.2.1.2.1 Digital Input
The digital input functionality can be used to monitor a signal within the system. 图 48 illustrates that the state of
the digital input can be read from the GPI_VALUE register.
版权 © 2019, Texas Instruments Incorporated
29
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
Typical Applications (接下页)
ADC
From input device
GPIx
GPIx
SW
AVDD
图 48. Digital Input
8.2.1.2.2 Digital Open-Drain Output
The channels of the TLA2518 can be configured as digital open-drain outputs supporting an output voltage up to
5.5 V. An open-drain output, as shown in 图 49, consists of an internal FET (Q) connected to ground. The output
is idle when not driven by the device, which means Q is off and the pullup resistor, RPULL_UP, connects the GPOx
node to the desired output voltage. The output voltage can range anywhere up to 5.5 V, depending on the
external voltage that the GPIOx is pulled up to. When the device is driving the output, Q turns on, thus
connecting the pullup resistor to ground and bringing the node voltage at GPOx low.
VPULL_UP
Receiving Device
ADC
RPULL_UP
GPOx
ILOAD
Q
图 49. Digital Open-Drain Output
The minimum value of the pullup resistor, as calculated in 公式 3, is given by the ratio of VPULL_UP and the
maximum current supported by the device digital output (5 mA).
RMIN = (VPULL_UP / 5 mA)
(3)
The maximum value of the pullup resistor, as calculated in 公式 4, depends on the minimum input current
requirement, ILOAD, of the receiving device driven by this GPIO.
RMAX = (VPULL_UP / ILOAD
)
(4)
Select RPULL_UP such that RMIN < RPULL_UP < RMAX
.
30
版权 © 2019, Texas Instruments Incorporated
TLA2518
www.ti.com.cn
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
Typical Applications (接下页)
8.2.1.2.3 Application Curve
45000
30000
15000
0
39581
25955
2048
2049
C001
Output Code
Standard deviation = 0.49 LSB
图 50. DC Input Histogram
8.2.2 Digital Push-Pull Output Configuration
The channels of the TLA2518 can be configured as digital push-pull outputs supporting an output voltage up to
AVDD. As shown in 图 51, a push-pull output consists of two mirrored opposite bipolar transistors, Q1 and Q2.
The device can both source and sink current because only one transistor is on at a time (either Q2 is on and
pulls the output low, or Q1 is on and sets the output high). A push-pull configuration always drives the line
opposed to an open-drain output where the line is left floating.
ADC
AVDD
Q1
GPOx
Digital
output
Q2
图 51. Digital Push-Pull Output
版权 © 2019, Texas Instruments Incorporated
31
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
9 Power Supply Recommendations
9.1 AVDD and DVDD Supply Recommendations
The TLA2518 has two separate power supplies: AVDD and DVDD. The device operates on AVDD; DVDD is
used for the interface circuits. For supplies greater than 2.35 V, AVDD and DVDD can be shorted externally if
single-supply operation is desired. The AVDD supply also defines the full-scale input range of the device.
Decouple the AVDD and DVDD pins individually, as illustrated in 图 52, with 1-µF ceramic decoupling capacitors.
The minimum capacitor value required for AVDD and DVDD is 200 nF and 20 nF, respectively. If both supplies
are powered from the same source, a minimum capacitor value of 220 nF is required for decoupling.
AVDD
AVDD
GND
1 mF
1 mF
DVDD
DVDD
图 52. Power-Supply Decoupling
32
版权 © 2019, Texas Instruments Incorporated
TLA2518
www.ti.com.cn
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
10 Layout
10.1 Layout Guidelines
图 53 shows a board layout example for the TLA2518. Avoid crossing digital lines with the analog signal path and
keep the analog input signals and the AVDD supply away from noise sources.
Use 1-µF ceramic bypass capacitors in close proximity to the analog (AVDD) and digital (DVDD) power-supply
pins. Avoid placing vias between the AVDD and DVDD pins and the bypass capacitors. Connect the GND pin to
the ground plane using short, low-impedance paths. The AVDD supply voltage also functions as the reference
voltage for the TLA2518. Place the decoupling capacitor (CREF) for AVDD close to the device AVDD and GND
pins and connect CREF to the device pins with thick copper tracks.
10.2 Layout Example
SCLK
SDI
DECAP
AVDD
AIN/GPIO
图 53. Example Layout
版权 © 2019, Texas Instruments Incorporated
33
TLA2518
ZHCSJX7A –JUNE 2019–REVISED DECEMBER 2019
www.ti.com.cn
11 器件和文档支持
11.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
11.2 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.3 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。
11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
34
版权 © 2019, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TLA2518IRTER
TLA2518IRTET
ACTIVE
ACTIVE
WQFN
WQFN
RTE
RTE
16
16
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
2518
2518
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Sep-2021
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLA2518IRTER
TLA2518IRTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
330.0
180.0
12.4
12.4
3.3
3.3
3.3
3.3
1.1
1.1
8.0
8.0
12.0
12.0
Q2
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Dec-2019
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLA2518IRTER
TLA2518IRTET
WQFN
WQFN
RTE
RTE
16
16
3000
250
367.0
210.0
367.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RTE 16
3 x 3, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225944/A
www.ti.com
PACKAGE OUTLINE
RTE0016C
WQFN - 0.8 mm max height
S
C
A
L
E
3
.
6
0
0
PLASTIC QUAD FLATPACK - NO LEAD
3.1
2.9
B
A
PIN 1 INDEX AREA
3.1
2.9
SIDE WALL
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
C
0.8 MAX
SEATING PLANE
0.08
0.05
0.00
1.68 0.07
(DIM A) TYP
5
8
EXPOSED
THERMAL PAD
12X 0.5
4
9
4X
SYMM
17
1.5
1
12
0.30
16X
0.18
PIN 1 ID
(OPTIONAL)
13
16
0.1
C A B
SYMM
0.05
0.5
0.3
16X
4219117/B 04/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.68)
SYMM
13
16
16X (0.6)
1
12
16X (0.24)
SYMM
(2.8)
17
(0.58)
TYP
12X (0.5)
9
4
(
0.2) TYP
VIA
5
8
(R0.05)
ALL PAD CORNERS
(0.58) TYP
(2.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219117/B 04/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RTE0016C
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(
1.55)
16
13
16X (0.6)
1
12
16X (0.24)
17
SYMM
(2.8)
12X (0.5)
9
4
METAL
ALL AROUND
5
8
SYMM
(2.8)
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 17:
85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4219117/B 04/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
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您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
TLA2528
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具有 I2C 接口和 GPIO 的小型 8 通道 12 位模数转换器 (ADC) | RTE | 16 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLA2528IRTET
具有 I2C 接口和 GPIO 的小型 8 通道 12 位模数转换器 (ADC) | RTE | 16 | -40 to 85Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLA25GMA
Uplink Far Field Noise Suppression & Downlink SNR Enhancing Microphone Amplifier with Earpiece DriverWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TI
TLA290LP
Telecom Filter, 8 Function(s), DIP-16Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TDK
TLA290LS
Telecom Filter, 8 Function(s)Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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TDK
TLA3700
Audio Line Matching TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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FILTRAN
TLA3700-1
Audio Line Matching TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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FILTRAN
TLA3700-2
Audio Line Matching TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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FILTRAN
TLA3700-2
General Purpose Audio TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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APITECH
TLA3853
Audio Line Matching TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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FILTRAN
TLA3853-1
Audio Line Matching TransformerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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FILTRAN
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