TLC1543QDWRG4 [TI]

10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS; 10位模拟数字转换器带串行控制和11个模拟输入


型号：	TLC1543QDWRG4
厂家：	TEXAS INSTRUMENTS
描述：	10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS 10位模拟数字转换器带串行控制和11个模拟输入转换器模数转换器光电二极管输入元件
文件：	总33页 (文件大小：1154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TLC1542I, TLC1542M, TLC1542Q

TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 11 ANALOG INPUTS

FEATURES

DB, DW, J, OR N PACKAGE

•

10-Bit Resolution A/D Converter

(TOP VIEW)

11 Analog Input Channels

Three Built-In Self-Test Modes

Inherent Sample-and-Hold Function

Total Unadjusted Error: ±1LSB Max

On-Chip System Clock

EOC

I/O CLOCK

ADDRESS

DATA OUT

End-of-Conversion (EOC) Output

Terminal Compatible With TLC542

CMOS Technology

15 CS

REF+

REF−

A10

GND

DESCRIPTION

The TLC1542C, TLC1542I, TLC1542M, TLC1542Q,

TLC1543C, TLC1543I, and TLC1543Q are CMOS

10-bit switched-capacitor successive-approximation

analog-to-digital converters. These devices have

three inputs and a 3-state output [chip select (CS),

input-output clock (I/O CLOCK), address input

(ADDRESS), and data output (DATA OUT)] that

provide a direct 4-wire interface to the serial port of a

host processor. These devices allow high-speed data

transfers from the host.

FK OR FN PACKAGE

(TOP VIEW)

20 19

I/O CLOCK

ADDRESS

DATA OUT

In addition to a high-speed A/D converter and

versatile control capability, these devices have an

on-chip 14-channel multiplexer that can select any

one of 11 analog inputs or any one of three internal

self-test voltages. The sample-and-hold function is

automatic. At the end of A/D conversion, the

end-of-conversion (EOC) output goes high to

indicate that conversion is complete. The converter

incorporated in the devices features differential

high-impedance reference inputs that facilitate

ratiometric conversion, scaling, and isolation of

analog circuitry from logic and supply noise. A

REF+

9 10 11 12 13

switched-capacitor

design

allows

low-error

conversion over the full operating free-air

temperature range.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TLC1542I, TLC1542M, TLC1542Q

TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

AVAILABLE OPTIONS

PACKAGE

SMALL

OUTLINE

(DB)

T_A

SMALL OUTLINE

(DW)

CHIP CARRIER

(FN)

PLASTIC DIP

(N)

CHIP CARRIER

(FK)

CERAMIC DIP

(J)

TLC1542CDW

TLC1543CDW

TLC1542IDW

TLC1543IDW

TLC1542CFN

TLC1543CFN

TLC1542IFN

TLC1543IFN

TLC1542QFN

TLC1543QFN

TLC1542CN

TLC1543CN

TLC1542IN

TLC1543IN

0°C to 70°C

TLC1543CDB

TLC1543IDB

TLC1543QDB

-40°C to 85°C

-40°C to 125°C

-55°C to 125°C

TLC1543QDW

TLC1542MFK

TLC1542MJ

FUNCTIONAL BLOCK DIAGRAM

REF+

REF−

10-Bit

Analog-to-Digital

Converter

Sample and

Hold

(switched capacitors)

14-Channel

Analog

Multiplexer

Output

Data

10-to-1 Data

Selector and

Driver

DATA

OUT

Input Address

A10

System Clock,

Control Logic,

and I/O

Self-Test

Reference

Counters

EOC

ADDRESS

I/O CLOCK

TYPICAL EQUIVALENT INPUTS

INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE

INPUT CIRCUIT IMPEDANCE DURING HOLD MODE

1 kΩ TYP

A0−A10

C = 60 pF TYP

(equivalent input

capacitance)

5 MΩ TYP

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

TERMINAL FUNCTIONS

TERMINAL

I/O

DESCRIPTION

NAME

NO.

ADDRESS

Serial address input. A 4-bit serial address selects the desired analog input or test voltage that is to be

converted next. The address data is presented with the MSB first and shifts in on the first four rising

edges of I/O CLOCK. After the four address bits have been read into the address register, this input is

ignored for the remainder of the current conversion period.

A0-A10

1-9, 11, 12

Analog signal inputs. The 11 analog inputs are applied to these terminals and are internally

multiplexed. The driving source impedance should be less than or equal to 1 kΩ.

Chip select. A high-to-low transition on this input resets the internal counters and controls and enables

DATA OUT, ADDRESS, and I/O CLOCK within a maximum of a setup time plus two falling edges of

the internal system clock. A low-to-high transition disables ADDRESS and I/O CLOCK within a setup

time plus two falling edges of the internal system clock.

DATA OUT

The 3-state serial output for the A/D conversion result. This output is in the high-impedance state

when CS is high and active when CS is low. With a valid chip select, DATA OUT is removed from the

high-impedance state and is driven to the logic level corresponding to the MSB value of the previous

conversion result. The next falling edge of I/O CLOCK drives this output to the logic level

corresponding to the next most significant bit, and the remaining bits shift out in order with the LSB

appearing on the ninth falling edge of I/O CLOCK. On the tenth falling edge of I/O CLOCK, DATA

OUT is driven to a low logic level so that serial interface data transfers of more than ten clocks

produce zeroes as the unused LSBs.

EOC

End of conversion. This output goes from a high to a low logic level on the trailing edge of the tenth

I/O CLOCK and remains low until the conversion is complete and data are ready for transfer.

GND

The ground return terminal for the internal circuitry. Unless otherwise noted, all voltage measurements

are with respect to this terminal.

I/O CLOCK

Input/output clock. This terminal receives the serial I/O CLOCK input and performs the following four

functions: 1) It clocks the four input address bits into the address register on the first four rising edges

of the I/O CLOCK with the multiplex address available after the fourth rising edge. 2) On the fourth

falling edge of I/O CLOCK, the analog input voltage on the selected multiplex input begins charging

the capacitor array and continues to do so until the tenth falling edge of I/O CLOCK. 3) It shifts the

nine remaining bits of the previous conversion data out on DATA OUT. 4) It transfers control of the

conversion to the internal state controller on the falling edge of the tenth clock.

REF+

The upper reference voltage value (nominally V_CC) is applied to this terminal. The maximum input

voltage range is determined by the difference between the voltage applied to this terminal and the

voltage applied to the REF- terminal.

REF-

V_CC

The lower reference voltage value (nominally ground) is applied to this terminal.

Positive supply voltage

DETAILED DESCRIPTION

With chip select (CS) inactive (high), the ADDRESS and I/O CLOCK inputs are initially disabled and DATA OUT

is in the high-impedance state. When the serial interface takes CS active (low), the conversion sequence begins

with the enabling of I/O CLOCK and ADDRESS and the removal of DATA OUT from the high-impedance state.

The serial interface then provides the 4-bit channel address to ADDRESS and the I/O CLOCK sequence to I/O

CLOCK. During this transfer, the serial interface also receives the previous conversion result from DATA OUT.

I/O CLOCK receives an input sequence that is between 10 and 16 clocks long from the host serial interface. The

first four I/O clocks load the address register with the 4-bit address on ADDRESS, selecting the desired analog

channel, and the next six clocks providing the control timing for sampling the analog input.

There are six basic serial-interface timing modes that can be used with the device. These modes are determined

by the speed of I/O CLOCK and the operation of CS as shown in Table 1. These modes are (1) a fast mode with

a 10-clock transfer and CS inactive (high) between conversion cycles, (2) a fast mode with a 10-clock transfer

and CS active (low) continuously, (3) a fast mode with an 11- to 16-clock transfer and CS inactive (high)

between conversion cycles, (4) a fast mode with a 16-clock transfer and CS active (low) continuously, (5) a slow

mode with an 11- to 16-clock transfer and CS inactive (high) between conversion cycles, and (6) a slow mode

with a 16-clock transfer and CS active (low) continuously.

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

The MSB of the previous conversion appears at DATA OUT on the falling edge of CS in mode 1, mode 3, and

mode 5, on the rising edge of EOC in mode 2 and mode 4, and following the sixteenth clock falling edge in

mode 6. The remaining nine bits are shifted out on the next nine falling edges of I/O CLOCK. Ten bits of data

are transmitted to the host-serial interface through DATA OUT. The number of serial clock pulses used also

depends on the mode of operation, but a minimum of ten clock pulses is required for conversion to begin. On

the tenth clock falling edge, the EOC output goes low and returns to the high logic level when conversion is

complete and the result can be read by the host. Also, on the tenth clock falling edge, the internal logic takes

DATA OUT low to ensure that the remaining bit values are zero when the I/O CLOCK transfer is more than ten

clocks long.

Table 1 lists the operational modes with respect to the state of CS, the number of I/O serial transfer clocks that

can be used, and the timing edge on which the MSB of the previous conversion appears at the output.

Table 1. MODE OPERATION

TIMING

DIAGRAM

MODES

NO. OF 1/O CLOCK

MSB AT DATA OUT⁽¹⁾

Mode 1 High between conversion cycles

Mode 2 Low continuously

CS falling edge

Figure 9

EOC rising edge

CS falling edge

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Fast Modes

Mode 3 High between conversion cycles

Mode 4 Low continuously

11 TO 16⁽²⁾

16⁽²⁾

11 to 16⁽³⁾

16⁽³⁾

EOC rising edge

CS falling edge

Mode 5 High between conversion cycles

Mode 6 Low continuously

Slow Modes

16th clock falling edge

(1) These edges also initiate serial-interface communication.

(2) No more than 16 clocks should be used.

(3) No more than 16 clocks should be used.

FAST MODES

The device is in a fast mode when the serial I/O CLOCK data transfer is completed before the conversion is

completed. With a 10-clock serial transfer, the device can only run in a fast mode since a conversion does not

begin until the falling edge of the tenth I/O CLOCK.

MODE 1: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 10-CLOCK TRANSFER

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer is ten clocks long. The

falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The rising edge

of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified delay time.

Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time plus two falling

edges of the internal system clock.

MODE 2: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 10-CLOCK TRANSFER

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer is ten clocks long. After

the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of EOC then

begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the previous

conversion to appear immediately on this output.

MODE 3: FAST MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK

TRANSFER

In this mode, CS is inactive (high) between serial I/O CLOCK transfers, and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

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MODE 4: FAST MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions; the rising edge of

EOC then begins each sequence by removing DATA OUT from the low logic level, allowing the MSB of the

previous conversion to appear immediately on this output.

SLOW MODES

In a slow mode, the conversion is completed before the serial I/O CLOCK data transfer is completed. A slow

mode requires a minimum 11-clock transfer into I/O CLOCK, and the rising edge of the eleventh clock must

occur before the conversion period is complete; otherwise, the device loses synchronization with the host-serial

interface and CS has to be toggled to initialize the system. The eleventh rising edge of the I/O CLOCK must

occur within 9.5 µs after the tenth I/O clock falling edge.

MODE 5: SLOW MODE, CS INACTIVE (HIGH) BETWEEN CONVERSION CYCLES, 11- to 16-CLOCK

TRANSFER

In this mode, CS is inactive (high) between serial I/O CLOCK transfers and each transfer can be 11 to 16 clocks

long. The falling edge of CS begins the sequence by removing DATA OUT from the high-impedance state. The

rising edge of CS ends the sequence by returning DATA OUT to the high-impedance state within the specified

delay time. Also, the rising edge of CS disables the I/O CLOCK and ADDRESS terminals within a setup time

plus two falling edges of the internal system clock.

MODE 6: SLOW MODE, CS ACTIVE (LOW) CONTINUOUSLY, 16-CLOCK TRANSFER

In this mode, CS is active (low) between serial I/O CLOCK transfers and each transfer must be exactly 16 clocks

long. After the initial conversion cycle, CS is held active (low) for subsequent conversions. The falling edge of

the sixteenth I/O CLOCK then begins each sequence by removing DATA OUT from the low state, allowing the

MSB of the previous conversion to appear immediately at DATA OUT. The device is then ready for the next

16-clock transfer initiated by the serial interface.

ADDRESS BITS

The 4-bit analog channel-select address for the next conversion cycle is presented to the ADDRESS terminal

(MSB first) and is clocked into the address register on the first four leading edges of I/O CLOCK. This address

selects one of 14 inputs (11 analog inputs or three internal test inputs).

ANALOG INPUTS AND TEST MODES

The 11 analog inputs and the three internal test inputs are selected by the 14-channel multiplexer according to

the input address as shown in Tables 2 and 3. The input multiplexer is a break-before-make type to reduce

input-to-input noise injection resulting from channel switching.

Sampling of the analog input starts on the falling edge of the fourth I/O CLOCK, and sampling continues for six

I/O CLOCK periods. The sample is held on the falling edge of the tenth I/O CLOCK. The three test inputs are

applied to the multiplexer, sampled, and converted in the same manner as the external analog inputs.

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Table 2. ANALOG-CHANNEL-SELECT ADDRESS

VALUE SHIFTED INTO ADDRESS

INPUT

ANALOG INPUT SELECTED

BINARY

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

HEX

A10

Table 3. TEST-MODE-SELECT ADDRESS

VALUE SHIFTED INTO

ADDRESS INPUT

INTERNAL SELF-TEST

VOLTAGE SELECTED⁽¹⁾

OUTPUT RESULT (HEX)⁽²⁾

BINARY

HEX

ref+

− V

ref−

1011

200

V_ref-

V_ref+

1100

1101

000

3FF

(1) V_ref+is the voltage applied to the REF+ input, and V_ref-is the voltage applied to the REF- input.

(2) The output results shown are the ideal values and vary with the reference stability and with internal

offsets.

CONVERTER AND ANALOG INPUT

The CMOS threshold detector in the successive-approximation conversion system determines each bit by

examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the

conversion process, the analog input is sampled by closing the S_Cswitch and all S_Tswitches simultaneously.

This action charges all the capacitors to the input voltage.

In the next phase of the conversion process, all S_Tand S_Cswitches are opened and the threshold detector

begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF-)

voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and

then the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector

looks at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the

equivalent nodes of all the other capacitors on the ladder are switched to REF-. If the voltage at the summing

node is greater than the trip point of the threshold detector (approximately one-half V_CC), a 0 bit is placed in the

output register and the 512-weight capacitor is switched to REF-. If the voltage at the summing node is less than

the trip point of the threshold detector, a 1 bit is placed in the register and the 512-weight capacitor remains

connected to REF+ through the remainder of the successive-approximation process. The process is repeated for

the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all bits are counted.

With each step of the successive-approximation process, the initial charge is redistributed among the capacitors.

The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

Threshold

Detector

To Output

Latches

512

256

128

Node 512

REF+

REF−

Figure 1. Simplified Model of the Successive-Approximation System

CHIP-SELECT OPERATION

The trailing edge of CS starts all modes of operation, and CS can abort a conversion sequence in any mode. A

high-to-low transition on CS within the specified time during an ongoing cycle aborts the cycle, and the device

returns to the initial state (the contents of the output data register remain at the previous conversion result).

Exercise care to prevent CS from being taken low close to completion of conversion because the output data

can be corrupted.

REFERENCE VOLTAGE INPUTS

There are two reference inputs used with the device: REF+ and REF-. These voltage values establish the upper

and lower limits of the analog input to produce a full-scale and zero reading respectively. The values of REF+,

REF-, and the analog input should not exceed the positive supply or be lower than GND consistent with the

specified absolute maximum ratings. The digital output is at full scale when the input signal is equal to or higher

than REF+ and at zero when the input signal is equal to or lower than REF-.

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

(1)

UNIT

(2)

V_CC, see

V_I

Supply voltage range

-0.5 V to 6.5 V

-0.3 V to V_CC+ 0.3 V

V_CC+ 0.1 V

Input voltage range

V_O

Output voltage range

V_ref+

V_ref-

Positive reference voltage

Negative reference voltage

Peak input current (any input)

Peak total input current (all inputs)

-0.1 V

±20 mA

±30 mA

TLC1542C, TLC1543C

TLC1542I, TLC1543I

TLC1542Q, TLC1543Q

TLC1542M

0°C to 70°C

-40°C to 85°C

-40°C to 125°C

-55°C to 125°C

-65°C to 150°C

260°C

T_A

Operating free-air temperature range

Storage temperature range,

T_stg

Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to digital ground with REF- and GND wired together (unless otherwise noted).

RECOMMENDED OPERATING CONDITIONS

MIN

NOM

MAX

UNIT

V_CC

Supply voltage

4.5

5.5

V_ref+, see⁽¹⁾

Positive reference voltage

Negative reference voltage

V_CC

(1)

V_ref-, see

V_CC+0.

(1)

V_ref+-V_ref-, see

Differential reference voltage

2.5

V_CC

(1)

Analog input voltage ,see

V_CC

V_IH

V_IL

High-level control input voltage

Low-level control input voltage

V_CC= 4.5 V to 5.5 V

0.8

Setup time, address bits at data input before I/O

CLOCK↑

t_su(A), see Figure 4

100

t_h(A), see Figure 4

t_h(CS), see Figure 5

Hold time, address bits after I/O CLOCK↑

Hold time, CS low after last I/O CLOCK↓

t_su(CS), see ⁽²⁾and

Figure 5

Setup time, CS low before clocking in first

address bit

1.425

µs

(3)

Clock frequency at I/O CLOCK, see

190

2.1

MHz

t_wH(I/O)

t_wL(I/O)

Pulse duration, I/O CLOCK high,

Pulse duration, I/O CLOCK low,

t_t(I/O), see ⁽⁴⁾and

Figure 6

Transition time, I/O CLOCK,

µs

t_t(CS)

Transition time, ADDRESS and CS,

(1) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to

REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V_ref+- V_ref-); however, the

electrical specifications are no longer applicable.

(2) To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the internal system clock

after CS↓ before responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum CS

setup time has elapsed.

(3) For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V) at least 1 I/O CLOCK rising edge (≥ 2 V) must occur within 9.5

µs.

(4) This is the time required for the clock input signal to fall from V_IHmin to V_ILmax or to rise from V_ILmax to V_IHmin. In the vicinity of normal

room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition applications where

the sensor and the A/D converter are placed several feet away from the controlling microprocessor.

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RECOMMENDED OPERATING CONDITIONS (continued)

MIN

NOM

MAX

UNIT

TLC1542C, TLC1543C

TLC1542I, TLC1543I

TLC1542Q, TLC1543Q

TLC1542M

-40

-55

T_A

Operating free-air temperature,

°C

125

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range, V_CC= V_ref+= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz

(unless otherwise noted)

PARAMETER

TEST CONDITIONS

I_OH= -1.6 mA

MIN TYP⁽¹⁾

MAX

UNIT

V_CC= 4.5 V,

2.4

V_OHHigh-level output voltage

V_CC= 4.5 V to 5.5 V,

V_CC= 4.5 V,

I_OH= -20 µA

I_OL= 1.6 mA

I_OL= 20 µA

CS at V_CC

V_CC-0.1

0.4

0.1

V_OLLow-level output voltage

Off-state

V_CC= 4.5 V to 5.5 V,

V_O= V_CC

I_OZ

(high-impedance-state)

output current

µA

V_O= 0,

CS at V_CC

-10

I_IH

I_IL

High-level input current

Low-level input current

Operating supply current

V_I= V_CC

V_I= 0

0.005

0.8

2.5

-2.5

2.5

µA

I_CC

CS at 0 V

Selected channel leakage

current TLC1542/TLC1543

C, I, or Q

Selected channel at V_CC

Unselected channel at 0 V

Unselected channel at V_CC

µA

Selected channel at 0 V,

-1

Selected channel at V_CC

T_A= 25°C

Unselected channel at 0 V,

Selected channel at 0 V,

T_A= 25°C

Selected channel leakage

current TLC1542M

Unselected channel at V_CC

-1

µA

Selected channel at V_CC

Unselected channel at 0 V

Unselected channel at V_CC

2.5

Selected channel at 0 V,

-2.5

Maximum static analog

reference current into REF+

V_ref+= V_CC

V_ref-= GND

µA

Analog

inputs

Input

capacitance

C_i

Control

inputs

(1) All typical values are at V_CC= 5 V, T_A= 25°C.

OPERATING CHARACTERISTICS

over recommended operating free-air temperature range, V_CC= V_ref+= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz

(unless otherwise noted)

TEST

CONDITIONS

(1)

MIN TYP

MAX

UNIT

TLC1542C, I, or Q

TLC1543C, I, or Q

TLC1542M

±0.5

±1

LSB

(2)

E_L

Linearity error, see

)

±1

(1) All typical values are at T_A= 25°C.

(2) Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

OPERATING CHARACTERISTICS (continued)

over recommended operating free-air temperature range, V_CC= V_ref+= 4.5 V to 5.5 V, I/O CLOCK frequency = 2.1 MHz

(unless otherwise noted)

TEST

CONDITIONS

(1)

MIN TYP

MAX

UNIT

(4)

TLC1542C, I, or Q

TLC1543C, I, or Q

TLC1542M

See

±1

LSB

(3)

(4)

E_ZS

Zero-scale error, see

See

TLC1542C, I, or Q

TLC1543C, I, or Q

TLC1542M

(3)

E_FS

Full-scale error, see

TLC1542C, I, or Q

TLC1543C, I, or Q

TLC1542M

(5)

Total unadjusted error, see

ADDRESS = 1011

ADDRESS = 1100

ADDRESS = 1101

512

(6)

Self-test output code, see Table 3 and

Conversion time

1023

See timing

diagrams

t_conv

µs

See timing

diagrams and

+10 I/O

CLOCK

periods

t_c

Total cycle time (access, sample, and conversion)

Channel acquisition time (sample)

(7)

See timing

diagrams and

I/O CLOCK

periods

t_acq

(7)

t_v

Valid time, DATA OUT remains valid after I/O CLOCK↓ See Figure 6

µs

t_d(I/O-DATA)

t_d(I/O-EOC)

t_d(EOC-DATA)

t_PZH, t_PZL

t_PHZ, t_PLZ

t_r(EOC)

Delay time, I/O CLOCK↓ to DATA OUT valid

Delay time, tenth I/O CLOCK↓ to EOC↓

Delay time, EOC↑ to DATA OUT (MSB)

Enable time, CS↓ to DATA OUT (MSB driven)

Disable time, CS↑ to DATA OUT (high impedance)

Rise time, EOC

See Figure 6

See Figure 7

See Figure 8

See Figure 3

See Figure 8

See Figure 7

See Figure 6

240

100

1.3

150

300

t_f(EOC)

Fall time, EOC

t_r(DATA)

Rise time, data bus

t_f(DATA)

Fall time, data bus

Delay time, tenth I/O CLOCK↓ to CS↓ to abort

t_d(I/O-CS)

µs

(8)

conversion (see Note

)

(3) Zero-scale error is the difference between 0000000000 and the converted output for zero input voltage; full-scale error is the difference

between 1111111111 and the converted output for full-scale input voltage.

(4) Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied to

REF- convert as all zeros (0000000000). The device is functional with reference voltages down to 1 V (V_ref+-V_ref-); however, the

electrical specifications are no longer applicable.

(5) Total unadjusted error comprises linearity, zero-scale, and full-scale errors.

(6) Both the input address and the output codes are expressed in positive logic.

(7) I/O CLOCK period = 1/(I/O CLOCK frequency) (see Figure 6)

(8) Any transitions of CS are recognized as valid only if the level is maintained for a setup time plus two falling edges of the internal clock

(1.425 µs) after the transition.

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION

Test Point

= 2.18 kΩ

DATA OUT

EOC

12 kΩ

= 50 pF

C = 100 pF

Figure 2. Load Circuits

2 V

0.8 V

, t

PZH PZL

, t

PHZ PLZ

2.4 V

0.4 V

90%

10%

DATA

OUT

Figure 3. DATA OUT Enable and Disable Voltage Waveforms

Address

Valid

2 V

ADDRESS

0.8 V

h(A)

su(A)

I/O CLOCK

0.8 V

Figure 4. ADDRESS Setup and Hold Time Voltage Waveforms

2 V

0.8 V

su(CS)

h(CS)

I/O CLOCK

First

Clock

Last

Clock

0.8 V

Figure 5. I/O CLOCK Setup and Hold Time Voltage Waveforms

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

t(I/O)

2 V

0.8 V

I/O CLOCK

0.8 V

I/O CLOCK Period

d(I/O-DATA)

2.4 V

0.4 V

2.4 V

0.4 V

DATA OUT

, t

r(DATA) f(DATA)

Figure 6. I/O CLOCK and DATA OUT Voltage Waveforms

I/O CLOCK

10th

0.8 V

Clock

d(I/O-EOC)

2.4 V

0.4 V

EOC

f(EOC)

Figure 7. I/O CLOCK and EOC Voltage Waveforms

r(EOC)

2.4 V

EOC

0.4 V

d(EOC-DATA)

2.4 V

0.4 V

DATA OUT

Valid MSB

Figure 8. EOC and DATA OUT Voltage Waveforms

Submit Documentation Feedback

TLC1542I, TLC1542M, TLC1542Q

TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

TIMING DIAGRAMS

(see Note A)

I/O

CLOCK

Access Cycle B

Sample Cycle B

Hi-Z State

DATA

OUT

Previous Conversion Data

MSB

LSB

ADDRESS

MSB

LSB

EOC

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

Figure 9. Timing for 10-Clock Transfer Using CS

Must be High on Power Up

(see Note A)

I/O

CLOCK

Access Cycle B

Sample Cycle B

DATA

OUT

Low Level

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

MSB

LSB

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

Figure 10. Timing for 10-Clock Transfer Not Using CS

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

See Note B

(see Note A)

I/O

CLOCK

Access Cycle B

Sample Cycle B

Low

Level

Hi-Z

DATA

OUT

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

MSB

LSB

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

B. A low-to-high transition of CS disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two

falling edges of the internal system clock.

Figure 11. Timing for 11- to 16-Clock Transfer Using

CS (Serial Transfer Interval Shorter Than Conversion)

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Must Be High on Power Up

(see Note A)

I/O

CLOCK

Access Cycle B

Sample Cycle B

See Note B

DATA

OUT

Low Level

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

MSB

LSB

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

B. The first I/O CLOCK must occur after the rising edge of EOC.

Figure 12. Timing for 16-Clock Transfer Not Using

CS (Serial Transfer Interval Shorter Than Conversion)

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

(see Note A)

I/O

CLOCK

See Note B

Access Cycle B

Sample Cycle B

Hi-Z State

Low

Level

DATA

OUT

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

MSB

LSB

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing

serial interface synchronization.

Figure 13. Timing for 11- to 16-Clock Transfer Using

CS (Serial Transfer Interval Longer Than Conversion)

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

PARAMETER MEASUREMENT INFORMATION (continued)

Must be High on Power Up

(see Note A)

I/O

CLOCK

Access Cycle B

Sample Cycle B

See Note B

Low Level

See Note C

DATA

OUT

Previous Conversion Data

MSB

LSB

ADDRESS

EOC

MSB

LSB

Shift in New Multiplexer Address;

Simultaneously Shift Out Previous

Conversion Value

A/D Conversion

Interval

Initialize

A. A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time plus two falling edges of the

internal system clock after CS↓ before responding to control input signals. Therefore, no attempt should be made to

clock in an address until the minimum CS setup time has elapsed.

B. The 11th rising edge of the I/O CLOCK sequence must occur before the conversion is complete to prevent losing

serial interface synchronization.

C. C. The I/O CLOCK sequence is exactly 16 clock pulses long.

Figure 14. Timing for 16-Clock Transfer Not Using

CS (Serial Transfer Interval Longer Than Conversion)

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

APPLICATION INFORMATION

1023

1022

1021

1111111111

1111111110

1111111101

See Notes A and B

= V − 1/2 LSB

513

512

1000000001

1000000000

=V + 1/2 LSB

511

0111111111

0000000010

0000000001

0000000000

0.0048 0.0096

2.4528 2.4576 2.4624

V − Analog Input Voltage − V

4.9056

4.9104 4.9152

A. This curve is based on the assumption that V_ref+and V_ref-have been adjusted so that the voltage at the transition

from digital 0 to 1 (V_ZT) is 0.0024 V and the transition to full scale (V_FT) is 4.908 V. 1 LSB = 4.8 mV.

B. The full-scale value (V_FS) is the step whose nominal midstep value has the highest absolute value. The zero-scale

value (V_ZS) is the step whose nominal midstep value equals zero.

Figure 15. Ideal Conversion Characteristics

TLC1542/43

A10

I/O CLOCK

ADDRESS

Control

Circuit

Processor

DATA OUT

EOC

Analog

Inputs

5-V DC Regulator

REF+

REF−

GND

To Source

Ground

Figure 16. Serial Interface

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TLC1542C, TLC1543C, TLC1543I, TLC1543Q

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SLAS052G–MARCH 1992–REVISED JANUARY 2006

APPLICATION INFORMATION (continued)

SIMPLIFIED ANALOG INPUT ANALYSIS

Using the equivalent circuit in Figure 17Figure 17, the time required to charge the analog input capacitance from

0 to V_Swithin 1/2 LSB can be derived as follows:

The capacitance charging voltage is given by

−t /R C

t i

V = V

(1−e

)

where

R = R + r

(1)

(2)

The final voltage to 1/2 LSB is given by

V (1/2 LSB) = V − (V /2048)

Equating equation 1 to equation 2 and solving for time t_cgives

−t /R C

t i

V −(V /2048) = V 1−e

(

)

and

t (1/2 LSB) = R × C × ln(2048)

(3)

(4)

Therefore, with the values given the time for the analog input signal to settle is

t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(2048)

This time must be less than the converter sample time shown in the timing diagrams.

†

Driving Source

TLC1542/3

1 kΩ MAX

50 pF MAX

= Input Voltage at A0−A10

= External Driving Source Voltage

= Source Resistance

= Input Resistance

= Equivalent Input Capacitance

†

Driving source requirements:

•

Noise and distortion for the source must be equivalent to the

resolution of the converter.

•

R must be real at the input frequency.

Figure 17. Equivalent Input Circuit Including the Driving Source

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PACKAGE OPTION ADDENDUM

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3-Feb-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

5962-9064202Q2A

5962-9064202QRA

TLC1542CDW

OBSOLETE

ACTIVE

LCCC

CDIP

SOIC

TBD

Call TI

-55 to 125

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

TLC1542C

TLC1542CN

TLC1542I

TLC1542CDWG4

TLC1542CDWR

TLC1542CDWRG4

TLC1542CFN

ACTIVE

SOIC

PLCC

PDIP

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

Level-1-260C-UNLIM

N / A for Pkg Type

2000

Green (RoHS

& no Sb/Br)

0 to 70

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLC1542CFNG3

TLC1542CN

Green (RoHS

& no Sb/Br)

CU SN

Pb-Free

(RoHS)

CU NIPDAU

TLC1542CNE4

TLC1542IDW

Pb-Free

(RoHS)

N / A for Pkg Type

Green (RoHS

& no Sb/Br)

Level-1-260C-UNLIM

TLC1542IDWG4

TLC1542IDWR

TLC1542IDWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLC1542IFN

TLC1542IN

OBSOLETE

ACTIVE

PLCC

PDIP

TBD

Call TI

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

TLC1542IN

TLC1542INE4

ACTIVE

PDIP

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

TLC1542MFKB

TLC1542MJB

OBSOLETE

LCCC

CDIP

TBD

Call TI

-55 to 125

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

3-Feb-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TLC1542QFN

TLC1543CDB

ACTIVE

PLCC

SSOP

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125 TLC1542Q

Green (RoHS

& no Sb/Br)

CU NIPDAU

P1543

TLC1543CDBG4

Green (RoHS

& no Sb/Br)

TLC1543CDBLE

TLC1543CDBR

OBSOLETE

ACTIVE

SSOP

TBD

Call TI

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

P1543

TLC1543CDBRG4

TLC1543CDW

TLC1543CDWG4

TLC1543CDWR

TLC1543CDWRG4

TLC1543CFN

ACTIVE

OBSOLETE

SSOP

SOIC

PLCC

PDIP

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

Level-1-260C-UNLIM

N / A for Pkg Type

Level-1-260C-UNLIM

Call TI

P1543

Green (RoHS

& no Sb/Br)

TLC1543C

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLC1543CFNG3

TLC1543CFNR

TLC1543CFNRG3

TLC1543CN

Green (RoHS

& no Sb/Br)

CU SN

1000

Green (RoHS

& no Sb/Br)

CU SN

0 to 70

TLC1543C

TLC1543CN

Y1543

Green (RoHS

& no Sb/Br)

CU SN

Pb-Free

(RoHS)

CU NIPDAU

Call TI

TLC1543CNE4

TLC1543IDB

PDIP

Pb-Free

(RoHS)

SSOP

Green (RoHS

& no Sb/Br)

TLC1543IDBG4

TLC1543IDBLE

Green (RoHS

& no Sb/Br)

Y1543

TBD

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

3-Feb-2013

Orderable Device

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

TLC1543IDBR

TLC1543IDBRG4

TLC1543IDW

ACTIVE

SSOP

SOIC

PLCC

PDIP

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

CU SN

Level-1-260C-UNLIM

N / A for Pkg Type

Y1543

Green (RoHS

& no Sb/Br)

Y1543

Green (RoHS

& no Sb/Br)

TLC1543I

TLC1543IN

TLC1543IDWG4

TLC1543IDWR

TLC1543IDWRG4

TLC1543IFN

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

TLC1543IFNG3

TLC1543IN

Green (RoHS

& no Sb/Br)

CU SN

Pb-Free

(RoHS)

CU NIPDAU

TLC1543INE4

Pb-Free

(RoHS)

N / A for Pkg Type

TLC1543QDB

ACTIVE

SSOP

TBD

CU NIPDAU

Level-1-220C-UNLIM

Level-1-260C-UNLIM

-40 to 125 1543Q

TLC1543QDBG4

Green (RoHS

& no Sb/Br)

TLC1543QDBR

TLC1543QDBRG4

TLC1543QDW

ACTIVE

SSOP

SOIC

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

-40 to 125 1543Q

Green (RoHS

& no Sb/Br)

-40 to 125 1543Q

Green (RoHS

& no Sb/Br)

-40 to 125 TLC1543Q

TLC1543QDWG4

TLC1543QDWR

TLC1543QDWRG4

Green (RoHS

& no Sb/Br)

2000

Green (RoHS

& no Sb/Br)

Green (RoHS

& no Sb/Br)

Addendum-Page 3

PACKAGE OPTION ADDENDUM

www.ti.com

3-Feb-2013

Orderable Device

TLC1543QFN

Status Package Type Package Pins Package Qty

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Top-Side Markings

Samples

Drawing

(1)

(2)

(3)

(4)

ACTIVE

PLCC

Green (RoHS

& no Sb/Br)

CU SN

Level-1-260C-UNLIM

-40 to 125 TLC1543Q

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC1543 :

Enhanced Product: TLC1543-EP

•

NOTE: Qualified Version Definitions:

Enhanced Product - Supports Defense, Aerospace and Medical Applications

•

Addendum-Page 4

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

TLC1542CDWR

TLC1542IDWR

TLC1543CDBR

TLC1543IDBR

SOIC

SSOP

SOIC

2000

330.0

24.4

16.4

24.4

10.8

8.2

13.3

7.5

2.7

2.5

2.7

12.0

24.0

16.0

24.0

8.2

7.5

TLC1543QDBR

TLC1543QDBRG4

TLC1543QDWR

8.2

7.5

8.2

7.5

10.8

13.3

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

26-Mar-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

TLC1542CDWR

TLC1542IDWR

TLC1543CDBR

TLC1543IDBR

SOIC

SSOP

SOIC

2000

367.0

45.0

38.0

45.0

TLC1543QDBR

TLC1543QDBRG4

TLC1543QDWR

Pack Materials-Page 2

MECHANICAL DATA

MPLC004A – OCTOBER 1994

FN (S-PQCC-J**)

PLASTIC J-LEADED CHIP CARRIER

20 PIN SHOWN

Seating Plane

0.004 (0,10)

0.180 (4,57) MAX

0.120 (3,05)

0.090 (2,29)

0.020 (0,51) MIN

0.032 (0,81)

0.026 (0,66)

D2/E2

0.021 (0,53)

0.013 (0,33)

0.050 (1,27)

0.007 (0,18)

0.008 (0,20) NOM

D/E

D1/E1

D2/E2

NO. OF

PINS

MIN

0.385 (9,78)

MAX

MIN

MAX

MIN

MAX

0.395 (10,03)

0.350 (8,89)

0.356 (9,04)

0.141 (3,58)

0.191 (4,85)

0.291 (7,39)

0.341 (8,66)

0.169 (4,29)

0.219 (5,56)

0.319 (8,10)

0.369 (9,37)

0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)

0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)

0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)

0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.958 (24,33) 0.441 (11,20) 0.469 (11,91)

1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)

4040005/B 03/95

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-018

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

0,15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

0,25

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

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TLC1543QDWRG4 [TI]

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