TLC1551IJ [TI]
10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS; 10位模拟数字转换器具有并行输出型号: | TLC1551IJ |
厂家: | TEXAS INSTRUMENTS |
描述: | 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH PARALLEL OUTPUTS |
文件: | 总9页 (文件大小:141K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
†
Power Dissipation . . . 40 mW Max
J
OR NW PACKAGE
(TOP VIEW)
Advanced LinEPIC Single-Poly Process
Provides Close Capacitor Matching for
Better Accuracy
REF+
REF–
ANLG GND
AIN
RD
WR
CLKIN
CS
D9
1
24
23
22
21
20
19
18
17
16
15
14
13
2
Fast Parallel Processing for DSP and µP
Interface
3
4
Either External or Internal Clock Can Be
Used
ANLG V
5
DD
DGTL GND1
DGTL GND2
D8
6
D7
7
Conversion Time . . . 6 µs
Total Unadjusted Error . . . ±1 LSB Max
CMOS Technology
DGTL V
D6
8
DD1
DGTL V
DD2
D5
9
EOC
D0
D1
D4
D3
D2
10
11
12
description
The TLC1550x and TLC1551 are data acquisition
analog-to-digital converters (ADCs) using a 10-bit,
†
Refer to the mechanical data for the JW
package.
switched-capacitor,
successive-approximation
FK OR FN PACKAGE
(TOP VIEW)
network. A high-speed, 3-state parallel port directly
interfaces to a digital signal processor (DSP) or
microprocessor (µP) system data bus. D0 through
D9 are the digital output terminals with D0 being the
least significant bit (LSB). Separate power
terminals for the analog and digital portions
minimize noise pickup in the supply leads.
Additionally, the digital power is divided into two
parts to separate the lower current logic from the
higher current bus drivers. An external clock can be
applied to CLKIN to override the internal system
clock if desired.
4
3
2 1 28 27 26
5
AIN
ANLG V
DGTL GND1
NC
DGTL GND2
25 CS
24 D9
6
DD
7
D8
NC
D7
D6
D5
23
22
21
20
19
8
9
DGTL V
10
11
DD1
DGTL V
DD2
The TLC1550I and TLC1551I are characterized for
operation from –40°C to 85°C. The TLC1550M is
characterized over the full military range of –55°C
to 125°C.
12 13 14 15 16 17 18
NC – No internal connection
AVAILABLE OPTIONS
PACKAGE
T
A
CERAMIC CHIP CARRIER PLASTIC CHIP CARRIER
CERAMIC DIP
(J)
PLASTIC DIP
(NW)
(FK)
(FN)
TLC1550IFN
TLC1551IFN
TLC1550INW
–40°C to 85°C
–55°C to 125°C
–
–
–
TLC1550MFK
–
TLC1550MJ
–
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic fields. These
circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to MIL-STD-883C,
Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than maximum-rated
voltages to these high-impedance circuits. During storage or handling, the device leads should be shorted together or the device
should be placed in conductive foam. In a circuit, unused inputs should always be connected to an appropriated logic voltage level,
preferably either V
or ground.
CC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Advanced LinEPIC is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
functional block diagram
EOC
10
CS
Successive-
Approximation
Register
D0–D9
Control
Logic
WR
RD
10
Frequency
Divided by 2
Internal
Clock
DGTL
Comp
V
DD1
10-Bit
100 kΩ
Capacitor
NOM
DAC and S/H
Clock Detector
CLKIN
REF+
REF–
AIN
typical equivalent inputs
INPUT CIRCUIT IMPEDANCE DURING SAMPLING MODE
INPUT CIRCUIT IMPEDANCE DURING HOLD MODE
1 kΩ TYP
AIN
AIN
C = 60 pF TYP
i
(equivalent input
capacitance)
5 MΩ TYP
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
Terminal Functions
TERMINAL
DESCRIPTION
†
‡
NAME
ANLG GND
AIN
NO.
4
NO.
3
Analog ground. The reference point for the voltage applied on terminals ANLG V , AIN, REF+, and REF–.
DD
5
4
Analog voltage input. The voltage applied to AIN is converted to the equivalent digital output.
ANLG V
CLKIN
6
5
Analog positive power supply voltage. The voltage applied to this terminal is designated V .
DD3
DD
26
22
Clock input. CLKIN is used for external clocking instead of using the internal system clock. It usually takes a
few microseconds before the internal clock is disabled. To use the internal clock, CLKIN should be tied high
or left unconnected.
CS
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
25
13
14
16
17
18
19
20
21
23
24
7
21
11
12
13
14
15
16
17
18
19
20
6
Chip-select. CS must be low for RD or WR to be recognized by the A/D converter.
Data bus output. D0 is bit 1 (LSB).
Data bus output. D1 is bit 2.
Data bus output. D2 is bit 3.
Data bus output. D3 is bit 4.
Data bus output. D4 is bit 5.
Data bus output. D5 is bit 6.
Data bus output. D6 is bit 7.
Data bus output. D7 is bit 8.
Data bus output. D8 is bit 9.
Data bus output. D9 is bit 10 (MSB).
DGTL GND1
DGTL GND2
Digital ground 1. The ground for power supply DGTL V
Digital ground 2. The ground for power supply DGTL V
and is the substrate connection.
DD1
DD2
9
7
.
DGTL V
DGTL V
EOC
10
8
Digital positive power-supply voltage 1. DGTL V
supplies the logic. The voltage applied to DGTL V is
DD1
DD1
DD1
designated V
.
DD1
11
12
28
9
10
24
Digitalpositivepower-supplyvoltage2.DGTLV
suppliesonlythehigher-currentoutputbuffers.Thevoltage
DD2
DD2
applied to DGTL V
DD2
is designated V .
DD2
End-of-conversion. EOC goes low indicating that conversion is complete and the results have been transferred
to the output latch. EOC can be connected to the µP- or DSP-interrupt terminal or can be continuously polled.
RD
Read input. When CS is low and RD is taken low, the data is placed on the data bus from the output latch. The
output latch stores the conversion results at the most recent negative edge of EOC. The falling edge of RD
resets EOC to a high within the t
specifications.
d(EOC)
REF+
2
1
Positive voltage-reference input. Any analog input that is greater than or equal to the voltage on REF+ converts
to 1111111111. AnaloginputvoltagesbetweenREF+andREF–converttotheappropriateresultinaratiometric
manner.
REF–
WR
3
2
Negative voltage reference input. Any analog input that is less than or equal to the voltage on REF– converts
to 0000000000.
27
23
Write input. When CS is low, conversion is started on the rising edge of WR. On this rising edge, the ADC holds
the analog input until conversion is completed. Before and after the conversion period, which is given by t
the ADC remains in the sampling mode.
,
conv
†
‡
Terminal numbers for FK and FN packages.
Terminal numbers for J and NW packages.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
, V
, and V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5 V
DD3
DD1 DD2
Input voltage range, V (any input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
Output voltage range, V
+ 0.3 V
+ 0.3 V
I
DD
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
O
Peak input current (any digital input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10 mA
Peak total input current (all inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±30 mA
Operating free-air temperature range, T : TLC1550I, TLC1551I . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
TLC1550M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Case temperature for 10 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: J or NW package . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1:
V
isthevoltagemeasuredatDGTLV
with respect to DGND1. V
isthevoltagemeasuredatDGTLV
withrespecttothe
with respect to AGND. For these specifications, all ground terminals are tied
DD1
DGND2. V
DD1
DD2
DD2
is the voltage measured at ANLG V
DD3
DD
, and V
together (and represent 0 V). When V
, V
are equal, they are referred to simply as V
.
DD1 DD2
DD3
DD
recommended operating conditions
MIN
NOM MAX
UNIT
V
Supply voltage, V
, V
, V
4.75
5
5.5
DD1 DD2 DD3
Positive reference voltage, V (see Note 2)
V
DD3
0
V
ref+
Negative reference voltage, V
(see Note 2)
V
ref–
Differential reference voltage, V
– V
ref–
(see Note 2)
0.3
0.3
V
ref+
Analog input voltage range
0
2
V
DD3
V
High-level control input voltage, V
V
IH
Low-level control input voltage, V
0.8
7.8
V
IL
Input clock frequency, f
(CLKIN)
Setup time, CS low before WR or RD goes low, t
0.5
0
MHz
ns
ns
ns
su(CS)
Hold time, CS low after WR or RD goes high, t
0
h(CS)
WR or RD pulse duration, t
w(WR)
50
40% of
period
80% of
period
Input clock low pulse duration, t
wL(CLKIN)
TLC155xI
–40
–55
85
Operating free-air temperature, T
°C
A
TLC1550M
125
NOTE 2: Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied to
REF– convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
electrical characteristics over recommended operating free-air temperature range,
V
= V
= 4.75 to 5.5 V and V
= 0 (unless otherwise noted)
DD
ref+
ref–
†
TYP
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
V
High-level output voltage
V
= 4.75 V,
I
= –360 µA
= 25°C
A
2.4
V
OH
DD
OH
T
0.4
0.5
10
V
I
= 4.75 V,
= 2.4 mA
DD
OL
V
OL
Low-level output voltage
V
T
= –55°C to 125°C
A
V
= V
DD
= 0,
,
CS and RD at V
CS and RD at V
O
O
DD
DD
I
Off-state (high-impedance-state) output current
µA
OZ
V
–10
2.5
I
IH
I
IL
I
IL
High-level input current
V = V
I DD
0.005
–2.5 –0.005
µA
µA
µA
Low-level input current (except CLKIN)
Low-level input current (CLKIN)
V = 0
I
–150
7
–50
14
–12
2
V
V
= 5 V,
= 0,
T
= 25°C
= 25°C
O
A
I
I
Short-circuit output current
mA
mA
pF
OS
DD
T
–6
8
O
A
Operating supply current
CS low and RD high
Analog inputs
Input capacitance
60
5
90*
15*
C
See typical equivalent inputs TLC1550/1I
i
Digital inputs
* On products compliant to MIL-STD-883, Class B, this parameter is not production tested.
†
All typical values are at V
= 5 V, T = 25°C.
A
DD
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
operating characteristics over recommended operating free-air temperature range with internal
clock and minimum sampling time of 4 µs, V
= V
= 5 V and V
= 0 (unless otherwise noted)
DD
ref+
ref–
†
‡
PARAMETER
TLC1550I
TEST CONDITIONS
T
A
MIN TYP
MAX
±0.5
±1
UNIT
Full range
Full range
25°C
TLC1551I
E
E
E
Linearity error
Zero-scale error
Full-scale error
See Note 3
LSB
L
±0.5
±1
TLC1550M
Full range
Full range
Full range
25°C
TLC1550I
TLC1551I
±0.5
±1
See Notes 2 and 4
LSB
LSB
ZS
FS
±0.5
±1
TLC1550M
Full range
Full range
Full range
25°C
TLC1550I
TLC1551I
±0.5
±1
See Notes 2 and 4
See Note 5
±0.5
±1
TLC1550M
Full range
Full range
Full range
25°C
TLC1550I
TLC1551I
TLC1550M
±0.5
±1
Total unadjusted error
Conversion time
LSB
±1
f
= 4.2 MHz or
clock(external)
internal clock
t
6
µs
conv
t
t
Data access time after RD goes low
Data valid time after RD goes high
35
ns
ns
a(D)
5
v(D)
See Figure 3
Disable time, delay time from RD high to high
impedance
t
t
30
ns
ns
dis(D)
Delay time, RD low to EOC high
0
15
d(EOC)
†
‡
Full range is –40°C to 85°C for the TL155xI devices and –55°C to 125°C for the TLC1550M.
All typical values are at V
= 5 V, T = 25°C.
A
DD
NOTES: 2. Analog input voltages greater than that applied to REF+ convert to all 1s (1111111111), while input voltages less than that applied
to REF– convert to all 0s (0000000000). The total unadjusted error may increase as this differential voltage falls below 4.75 V.
3. Linearity error is the difference between the actual analog value at the transition between any two adjacent steps and its ideal value
after zero-scale error and full-scale error have been removed.
4. Zero-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified zero scale.
Full-scale error is the difference between the actual mid-step value and the nominal mid-step value at specified full scale.
5. Total unadjusted error is the difference between the actual analog value at the transition between any two adjacent steps and its
ideal value. It includes contributions from zero-scale error, full-scale error, and linearity error.
PARAMETER MEASUREMENT INFORMATION
Source Current = 6 mA
Test Point
See Note A
Output
Under Test
V
cp
= 1 V
C
= 62 pF
L
Sink Current = 6 mA
V
cp
= voltage commutation point for switching between source and sink currents
NOTE A: Equivalent load circuit of the Teradyne A500 tester for timing parameter measurement
Figure 1. Test Load Circuit
2–6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
APPLICATION INFORMATION
simplified analog input analysis
Using the circuit in Figure 2, the time required to charge the analog input capacitance from 0 to V within 1/2
S
LSB can be derived as follows:
The capacitance charging voltage is given by
–t R C
c
t
i
(1)
(2)
V
V
1–e
C
S
where
R = R + r
t
s
i
The final voltage to 1/2 LSB is given by
V (1/2 LSB) = V – (V /1024)
C
S
S
Equating equation 1 to equation 2 and solving for time t gives
c
–t R C
c
t
i
(3)
(4)
V
V
512
V
1–e
S
S
S
and
t (1/2 LSB) = R × C × ln(1024)
c
t
i
Therefore, with the values given, the time for the analog input signal to settle is
t (1/2 LSB) = (R + 1 kΩ) × 60 pF × ln(1024)
(5)
c
s
This time must be less than the converter sample time shown in the timing diagrams.
†
Driving Source
TLC1550/1
R
r
i
s
V
I
V
S
V
C
1 kΩ MAX
C
i
50 pF MAX
V
V
= Input voltage at AIN
= External driving source voltage
I
S
s
R = Source resistance
r
= Input resistance
i
C = Input capacitance
i
†
Driving source requirements:
•
Noise and distortion for the source must be equivalent to the
resolution of the converter.
•
R must be real at the input frequency.
s
Figure 2. Input Circuit Including the Driving Source
2–7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC1550I, TLC1550M, TLC1551I
10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH PARALLEL OUTPUTS
SLAS043C – MAY 1991 – REVISED MARCH 1995
PRINCIPLES OF OPERATION
The operating sequence for complete data acquisition is shown in Figure 3. Processors can address the TLC1550
and TLC1551 as an external memory device by simply connecting the address lines to a decoder and the decoder
output to CS. Like other peripheral devices, the write (WR) and read (RD) input signals are valid only when CS is low.
Once CS is low, the on-board system clock permits the conversion to begin with a simple write command and the
converted data to be presented to the data bus with a simple read command. The device remains in a sampling (track)
mode from the rising edge of EOC until conversion begins with the rising edge of WR, which initiates the hold mode.
After the hold mode begins, the clock controls the conversion automatically. When the conversion is complete, the
end-of-conversion (EOC) signal goes low indicating that the digital data has been transferred to the output latch.
Lowering CS and RD then resets EOC and transfers the data to the data bus for the processor read cycle.
t
t
h(CS)
su(CS)
CS
0.8 V
0.8 V
0.8 V
0.8 V
t
conv
t
w(WR)
2 V
1.4 V
1.4 V
0.8 V
WR
RD
t
h(CS)
t
su(CS)
2 V
0.8 V
t
v(D)
t
t
a(D)
dis(D)
2 V
0.8 V
2 V
0.8 V
D0–D9
EOC
Data Valid
t
d(EOC)
2 V
0.8 V
Figure 3. TLC1550 or TLC1551 Operating Sequence
2–8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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