TLC2932AIPWRG4 [TI]
HIGH PERFORMANCE PAHSE LOCKED LOOP; ？高性能PAHSE锁相环
| 型号： | TLC2932AIPWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH PERFORMANCE PAHSE LOCKED LOOP |
| 文件： | 总23页 (文件大小：675K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇ ꢆꢑꢋ ꢁ ꢎꢂ ꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
D
VCO (Voltage-Controlled Oscillator):
D
Independent VCO, PFD Power-Down Mode
Thin Small-Outline Package (14 Terminal)
CMOS Technology
D
D
D
− Complete Oscillator Using Only One
External Bias Resistor (RBIAS)
Pin Compatible TLC2932IPW
− Lock Frequency:
13 MHz to 32 MHz (VDD = 3 V +5%,
T = –205C to 755C, x1 Output)
A
14-PIN TSOP (PW PACKAGE)
(TOP VIEW)
13 MHz to 35 MHz (VDD = 3.3 V +5%,
T = –205C to 755C, x1 Output)
A
LOGIC V
1
2
3
4
5
6
7
VCO V
RBIAS
VCO IN
VCO GND
VCO INHIBIT
PFD INHIBIT
TEST
14
13
12
11
10
9
15 MHz to 55 MHz (VDD = 5 V +5%,
DD
DD
SELECT
VCO OUT
FIN−A
T = –205C to 755C, x1 Output)
A
− Selectable Output Frequency
D
PFD (Phase Frequency Detector):
High Speed, Edge-Triggered Detector
with Internal Charge Pump
FIN−B
PFD OUT
LOGIC GND
8
description
The TLC2932A is designed for phase-locked loop (PLL) systems and is composed of a voltage-controlled
oscillator (VCO) and an edge-triggered type phase frequency detector (PFD). The oscillation frequency range
of the VCO is set by an external bias resistor (R
). The VCO has a 1/2 frequency divider at the output stage.
BIAS
The high speed PFD with internal charge pump detects the phase difference between the reference frequency
input and signal frequency input from the external counter. Both the VCO and the PFD have inhibit functions,
which can be used as power-down mode. Due to the TLC2932A high speed and stable oscillation capability,
the TLC2932A is suitable for use as a high-performance PLL.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE (PW)
–20°C to 75°C
TLC2932AIPW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢊ
ꢌ
ꢎ
ꢓ
ꢔ
ꢂ
ꢀ
ꢊ
ꢌ
ꢋ
ꢕ
ꢈ
ꢋ
ꢖ
ꢗ
ꢘ
ꢙ
ꢚ
ꢛ
ꢜ
ꢝ
ꢞ
ꢗ
ꢚ
ꢘ
ꢟ
ꢚ
ꢘ
ꢟ
ꢠ
ꢛ
ꢘ
ꢡ
ꢢ
ꢛ
ꢚ
ꢣ
ꢤ
ꢣꢠ ꢡ ꢗ ꢧꢘ ꢢꢥ ꢝ ꢡ ꢠ ꢚꢙ ꢣꢠ ꢦ ꢠ ꢨꢚ ꢢꢜꢠ ꢘꢞꢩ ꢂ ꢥꢝ ꢛꢝ ꢟꢞ ꢠꢛ ꢗꢡ ꢞꢗ ꢟ ꢣꢝ ꢞꢝ ꢝꢘ ꢣ ꢚꢞ ꢥꢠꢛ
ꢟ
ꢞ
ꢡ
ꢗ
ꢘ
ꢞ
ꢥ
ꢠ
ꢙ
ꢚ
ꢛ
ꢜ
ꢝ
ꢞ
ꢗ
ꢦ
ꢠ
ꢚ
ꢛ
Copyright 2005, Texas Instruments Incorporated
ꢡ
ꢢ
ꢠ
ꢟ
ꢗ
ꢙ
ꢗ
ꢟ
ꢝ
ꢞ
ꢗ
ꢚ
ꢘ
ꢡ
ꢝ
ꢛ
ꢠ
ꢣ
ꢠ
ꢡ
ꢗ
ꢧ
ꢘ
ꢧ
ꢚ
ꢝ
ꢨ
ꢡ
ꢩ
ꢀ
ꢠ
ꢪ
ꢝ
ꢡ
ꢈ
ꢘ
ꢡ
ꢞ
ꢛ
ꢤ
ꢜ
ꢠ
ꢘ
ꢟ ꢥꢝ ꢘ ꢧꢠ ꢚꢛ ꢣꢗ ꢡ ꢟ ꢚꢘ ꢞꢗ ꢘꢤꢠ ꢞ ꢥꢠ ꢡ ꢠ ꢢꢛ ꢚꢣ ꢤꢟꢞ ꢡ ꢫ ꢗꢞꢥ ꢚꢤꢞ ꢘꢚꢞ ꢗꢟꢠ ꢩ
ꢞ
ꢡ
ꢛ
ꢠ
ꢡ
ꢠ
ꢛ
ꢦ
ꢠ
ꢡ
ꢞ
ꢥ
ꢠ
ꢛ
ꢗ
ꢧ
ꢥ
ꢞ
ꢞ
ꢚ
1
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
functional block diagram
12
VCO IN
BIAS
4
FIN−A
13
10
Phase
Frequency
Detector
Voltage
Controlled
Oscillator
3
6
5
9
FIN−B
PFD OUT
VCO OUT
VCO INHIBIT
SELECT
PFD INHIBIT
2
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
LOGIC VDD
1
Power supply for the internal logic. This power supply should be separated from VCO V
cross-coupling between supplies.
to reduce
DD
SELECT
2
I
VCO output frequency select. When SELECT is high, the VCO output frequency is ×1/2 and when
low. The output frequency is ×1.
VCO OUT
FIN−A
3
4
5
O
I
VCO output. When the VCO INHIBIT is high, VCO output is low.
Input reference frequency f
(REF IN)
is applied to FIN−A.
FIN−B
I
Input for VCO external counter output frequency f
external counter.
. FIN−B is nominally provided from the
(FIN−B)
PFD OUT
LOGIC GND
TEST
6
7
O
PFD output. When the PFD INHIBIT is high, PFD output is in the high-impedance state.
GND for the internal logic.
8
Connect to GND.
PFD INHIBIT
VCO INHIBIT
VCO GND
VCO IN
9
I
I
PFD inhibit control. When PFD INHIBIT is high, PFD output is in the high-impedance state.
VCO inhibit control. When VCO INHIBIT is high, VCO output is low.
GND for VCO.
10
11
12
I
I
VCO control voltage input. Nominally the external loop filter output connects to VCO IN to control
VCO oscillation frequency.
RBIAS
13
14
Bias supply. An external resistor (R
oscillation frequency range.
) between VCO V
BIAS DD
and R
BIAS
supplies bias for adjusting the
VCO V
DD
Power supply for VCO. This power supply should be separated from LOGIC V
cross-coupling between supplies.
to reduce
DD
2
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
detailed description
VCO oscillation frequency
The VCO oscillation frequency is determined by an external register (R
) connected between the VCO V
DD
BIAS
and the BIAS terminals. The oscillation frequency and range depends on this resister value. For the lock
frequency range refer to the recommended operating conditions. Figure 1 shows the typical frequency variation
and VCO control voltage.
VCO Oscillation Frequency Range
Bias Resistor (R
)
BIAS
1/2 VDD
VCO Control Voltage (VCO IN)
Figure 1. Oscillation Frequency
VCO output frequency 1/2 divider
The TLC2932A SELECT terminal sets the f
VCO output frequency as shown in Table 1. The 1/2 f
output
OSC
OSC
should be used for minimum VCO output jitter.
Table 1. VCO Output 1/2 Divider Function
SELLECT
Low
VCO OUTPUT
f
OSC
1/2 f
High
OSC
VCO inhibit function
The VCO has an externally controlled inhibit function which inhibit the VCO output. A high level on the VCO
INHIBIT terminal stops the VCO oscillation and powers down the VCO. The output maintains a low level during
the power−down mode as shown in Table 2.
Table 2. VCO Inhibit Function
VCO INHIBIT
Low
VCO OSCILLATOR
Active
VCO OUT
Active
I
DD(VCO)
Normal
High
Stopped
Low level
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to FIN−A and FIN−B as shown in Figure 2. Normally the
reference is supplied to FIN−A and the frequency from the external counter output is fed to FIN−B. For clock
recovery PLL system, other types of phase detectors should be used.
3
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
FIN−A
FIN−B
V
OH
PFD OUT
HI-Z
V
OL
Figure 2. PFD Function Timing Chart
PFD inhibit control
A high level on the PFD INHIBIT terminal places PFD OUT in the high-impedance state and the PFD stops
phase detection as shown in Table 3. A high level on the PFD INHIBIT terminal can also be used as the
power-down mode for the PFD.
Table 3. VCO Output Control Function
PFD INHIBIT
Low
DETECTION
Active
PFD OUT
Active
I
DD(PFD)
Normal
High
Stopped
Hi−Z
Power Down
VCO block schematic
PFD block schematic
Charge Pump
V
DD
FIN−A
FIN−B
PFD OUT
Detector
PFD INHIBIT
4
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (each supply), V
Input voltage range (each input), V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
+ 0.5 V
IN
DD
Input current (each input), I
Output current (each output), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IN
O
Operating free-air temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to GND.
2. For operation above 25_C free-air temperature, derate linearly at the rate of 5.6 mW/°C.
recommended operating conditions
PARAMETERS
MIN
TYP
MAX
UNIT
V
DD
V
DD
V
DD
= 3 V
2.85
3.135
4.75
3
3.15
= 3.3 V
= 5 V
3.3
5
3.465
5.25
Supply voltage (each supply, see Note 3)
V
Input voltage, (inputs except VCO IN)
Output current, (each output)
0
0
V
V
mA
V
DD
2
VCO control voltage at VCO IN
0.9
13
V
DD
32
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3 V
= 3.3 V
= 5 V
13
15
35
55
Lock frequency
Bias Resisitor
MHz
= 3 V
2.2
2.2
2.2
5.1
5.1
5.1
= 3.3 V
= 5 V
kΩ
NOTE 3: It is recommended that the logic supply terminal (LOGIC V ) and the VCO supply terminal (VCO V ) should be at the same voltage
DD DD
and separated from each other.
electrical characteristics, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
VCO section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN
TYP
MAX
UNIT
V
V
OH
V
OL
V
TH
High level output voltage
Low level output voltage
I
I
2.4
OH
= 2 mA
0.3
2.1
1
V
OL
Input threshold voltage at select, VCO inhibit
Input current at Select, VCO inhibit
VCO IN input impedance
0.9
1.5
V
I
I
V = V
DD
or GND
µA
MΩ
µA
mA
I
Z
VCO IN = 1/2 V
See Note 4
10
0.35
8.4
I(VCOIN)
DD(INH)
DD
I
VCO supply current (inhibit)
VCO supply current
1
I
See Note 5
17
DD(VCO)
NOTES: 4. Current into VCO V , when VCO INHIBIT = high, PFD is inhibited.
DD
5. Current into VCO V , when VCO IN = 1/2 V , R
= 3.3 kΩ, VCOOUT = 15−pF Load, VCO INHIBIT = GND, and PFD INHIBIT
DD DD BIAS
= GND.
5
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢊ
ꢇ
ꢈ
ꢉ
ꢇ
ꢋ
ꢌ
ꢍ
ꢎ
ꢌꢏ
ꢆ
ꢐ
ꢂ
ꢋ
ꢊ
ꢇ
ꢆ
ꢑ
ꢋ
ꢁ
ꢎ
ꢂ
ꢒ
ꢋꢓ
ꢁ
ꢎ
ꢎꢊ
SLES150 − OCTOBER 2005
electrical characteristics, V
= 3 V, T = 25°C (unless otherwise noted) (continued)
A
DD
PFD section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN
TYP
MAX
UNIT
V
V
V
High level output voltage
Low level output voltage
I
I
2.4
OH
OH
= 2 mA
0.3
1
V
OL
OL
I
High impedance state output current
High level input voltage at Fin−A, Fin−B
Low level input voltage at Fin−A, Fin−B
Input threshold voltage at PFD inhibit
Input capacitance at Fin−A, Fin−B
Input impedance at Fin−A, Fin−B
PFD inhibit = high, V = V
DD
or GND
µA
V
OZ
O
V
V
V
2.1
0.9
IH
0.5
2.1
V
IL
1.5
5.6
10
TH
C
pF
MΩ
µA
IN
Z
IN
I
I
High impedance state PFD supply current See Note 6
PFD supply current See Note 7
1
3
DD(Z)
mA
DD(PFD)
NOTES: 6. The current into LOGIC V
when FIN−A and FIN−B = ground, PFD INHIBIT = V , PFD OUT open, and VCO OUT is inhibited.
DD
DD
DD
7. The current into LOGIC V
when FIN−A = 1 MHz and FIN−B = 1 MHz (V = 3 V, rectangular wave), PFD INHIBIT = GND, PFD
I(PP)
OUT open, and VCO OUT is inhibited.
operation characteristics, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
VCO section
Parameter
TEST CONDITIONS
MIN
TYP
MAX
33
UNIT
MHz
µs
f
f
t
t
Operation oscillation frequency
R
= 3.3 kΩ, VCO IN = 1/2 V
17
25
OSC
BIAS
DD
Time to stable oscillation (see Note 8)
Rise time
10
STB
C
C
R
= 15 pF
9
7.6
14
ns
r
f
L
Fall time
= 15 pF
12
ns
L
Duty cycle at VCO OUT
= 3.3 kΩ, VCO IN = 1/2 V
45%
50%
55%
BIAS
DD
α (f
OSC
)
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 V , T = –20°C to
DD
75°C
–0.264
%/°C
%/mV
ps
A
k
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 V , V = 4.75 V to
DD DD
5.25 V
0.004
SVS
(fosc)
Jitter absolute (see Note 9)
PLL jitter, N = 128
325
NOTES: 8. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
9. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MH
ns
f
t
t
t
t
t
t
Maximum operation frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
17
max
PLZ
PHZ
PZL
PZH
r
22
21
6.5
7
50
50
30
30
10
10
ns
ns
ns
C
C
= 15 pF
3.4
1.9
ns
L
L
Fall time
= 15 pF
ns
f
6
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
electrical characteristics, V
= 3.3 V, T = 25°C (unless otherwise noted)
A
DD
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
OH
V
OL
V
TH
High level output voltage
Low level output voltage
I
I
= –2 mA
= 2 mA
2.64
OH
0.33
2.25
1
V
OL
Input threshold voltage at select, VCO inhibit
Input current at Select, VCO inhibit
VCO IN input impedance
1.05
1.65
V
I
I
V = V
DD
or GND
µA
MΩ
µA
mA
I
Z
VCO IN = 1/2 V
See Note 10
See Note 11
10
0.38
10.8
I(VCOIN)
DD(INH)
DD
I
VCO supply current (inhibit)
VCO supply current
1
I
22
DD(VCO)
NOTES: 10. Current into VCO V , when VCO INHIBIT = high, PFD is inhibited.
DD
11. Current into VCO V , when VCO IN = 1/2 V , R
= 3.3 kΩ, VCOOUT = 15−pF Load, VCO INHIBIT = GND, and PFD INHIBIT
DD DD BIAS
= GND.
PFD section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN
TYP
MAX UNIT
V
V
High level output voltage
I
I
2.97
V
OH
OH
Low level output voltage
= 2 mA
0.2
1
V
µA
V
OL
OL
I
High impedance state output current
High level input voltage at Fin−A, Fin−B
Low level input voltage at Fin−A, Fin−B
Input threshold voltage at PFD inhibit
Input capacitance at Fin−A, Fin−B
Input impedance at Fin−A, Fin−B
PFD inhibit = high, V = V or GND
DD
OZ
O
V
V
V
2.1
IH
0.5
V
IL
1.05
1.65
5.6
10
2.25
TH
C
pF
MΩ
µA
IN
Z
IN
I
I
High impedance state PFD supply current See Note 12
PFD supply current See Note 13
1
3
DD(Z)
mA
DD(PFD)
NOTES: 12. The current into LOGIC V
when FIN−A and FIN−B = ground, PFD INHIBIT = V , PFD OUT open, and VCO OUT is inhibited.
DD
DD
DD
13. The current into LOGIC V
when FIN−A = 1 MHz and FIN−B = 1 MHz (V = 3.3 V, rectangular wave), PFD INHIBIT = GND,
I(PP)
PFD OUT open, and VCO OUT is inhibited.
operation characteristics, V
= 3.3 V, T = 25°C (unless otherwise noted)
DD
A
VCO section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX UNIT
f
Operation oscillation frequency
R
= 3.3 kΩ, VCO IN = 1/2 VDD
BIAS
18
30
43
10
14
12
55
MHz
µs
OSC
fstb
tr
Time to stable oscillation (see Note 14)
Rise time
C
C
R
= 15 pF
8.5
7.3
50
ns
L
t
f
Fall time
= 15 pF
ns
f
L
Duty cycle at VCO OUT
=3.3 kΩ, VCO IN = 1/2 VDD
BIAS
45
%
DUTY
α (f
OSC
)
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 VDD, T = –20°C to 75°C
–0.28
7
%/°C
A
k
(f
)
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 V , V
DD DD
= 4.75 V to 5.25 V
0.004
%/m
V
SVS OSC
Jitter absolute (see Note 15)
PLL jitter, N = 128
245
ps
NOTES: 14. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
15. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
7
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢊ
ꢇ
ꢈ
ꢉ
ꢇ
ꢋ
ꢌ
ꢍ
ꢎ
ꢌꢏ
ꢆ
ꢐ
ꢂ
ꢋ
ꢊ
ꢇ
ꢆ
ꢑ
ꢋ
ꢁ
ꢎ
ꢂ
ꢒ
ꢋꢓ
ꢁ
ꢎ
ꢎꢊ
SLES150 − OCTOBER 2005
operation characteristics, V
= 3.3 V, T = 25°C (unless otherwise noted) (continued)
A
DD
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
f
t
t
t
t
t
t
Maximum operation frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
22
max
PLZ
PHZ
PZL
PZH
r
21
21
5.8
6.2
3
50
50
30
30
10
10
ns
ns
ns
C
C
= 15 pF
ns
L
L
Fall time
= 15 pF
1.7
ns
f
electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
VCO section
PARAMETER
TEST CONDITIONS
= –2 mA
MIN
TYP
MAX
UNIT
V
OH
V
OL
V
TH
High level output voltage
Low level output voltage
I
I
4
V
V
V
OH
= 2 mA
0.5
3.5
OL
Input threshold voltage at select, VCO
inhibit
1.5
2.5
I
Input current at Select, VCO inhibit
VCO IN input impedance
VCO supply current (inhibit)
VCO supply current
V = V
DD
or GND
1
µA
M(
I
I
Z
VCO IN = 1/2 V
See Note 16
See Note 17
10
0.56
28
I(VCOIN)
DD
IDD(inh)
IDD(vco)
1
µA
mA
50
NOTES: 16. Current into VCO V , when VCO INHIBIT = high, PFD is inhibited.
DD
17. Current into VCO V , when VCO IN = 1/2 V , R
DD DD BIAS
= 3.3 kΩ, VCOOUT = 15−pF Load, VCO INHIBIT = GND, and PFD INHIBIT
= GND.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High level output voltage
I
I
= –2 mA
= 2 mA
4.5
OH
OH
Low level output voltage
0.2
1
V
OL
OL
I
High impedance state output current
PFD inhibit = high, V = V
or
DD
µA
OZ
o
GND
V
V
V
High level input voltage at Fin−A, Fin−B
Low level input voltage at Fin−A, Fin−B
Input threshold voltage at PFD inhibit
Input capacitance at Fin−A, Fin−B
Input impedance at Fin−A, Fin−B
4.5
1.5
V
V
IH
1
IL
2.5
5.6
10
3.5
TH
C
pF
MΩ
µA
IN
Z
IN
I
I
High impedance state PFD supply current See Note 18
PFD supply current See Note 19
1
3
DD(Z)
0.5
mA
DD(PFD)
NOTES: 18. The current into LOGIC V
when FIN−A and FIN−B = ground, PFD INHIBIT = V , PFD OUT open, and VCO OUT is inhibited.
DD
DD
DD
19. The current into LOGIC V
when FIN−A = 1 MHz and FIN−B = 1 MHz (V = 5 V, rectangular wave), PFD INHIBIT = GND, PFD
I(PP)
OUT open, and VCO OUT is inhibited
8
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
operation characteristics, V
VCO section
= 5 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
75
UNIT
MHz
us
f
f
t
t
f
Operation oscillation frequency
R
= 3.3 kΩ, VCO IN = 1/2 V
37
57
OSC
BIAS
DD
Time to stable oscillation (see Note 20)
Rise time
10
STB
C
C
R
= 15 pF
7.5
6.4
10
ns
r
L
Fall time
= 15 pF
10
ns
f
L
Duty cycle at VCO OUT
= 3.3 kΩ, VCO IN = 1/2 V
45%
50%
55%
DUTY
BIAS
DD
α (f
OSC
)
Temperature coefficient of oscillation
frequency
VCO IN = 1/2 V , T = –20°C to
DD
75°C
–0.346
0.002
145
%/°C
%/mV
ps
A
k
(f
Supply voltage coefficient of oscillation
frequency
VCO IN = 1/2 V , V = 4.75 V
DD DD
to 5.25 V
SVS OS
)
C
Jitter absolute (see Note 21)
PLL jitter, N = 128
NOTES: 20. The time period to the stable VCO oscillation frequency after the VCO INHIBIT terminal is changed to a low level.
21. Jitter performance is highly dependent on circuit layout and external device characteristics. The jitter specification was made with
a carefully deigned PCB with no device socket.
PFD section
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
ns
f
t
t
t
t
t
t
Maximum operation frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
38
max
PLZ
PHZ
PZL
PZH
r
20
20
4
40
40
20
20
10
10
ns
ns
4.3
2.1
1.3
ns
C
C
= 15 pF
ns
L
L
Fall time
= 15 pF
ns
f
9
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
90%
90%
10%
10%
VCO OUT
t
r
t
f
Figure 3. VCO Output Voltage Waveform
VDD
F
F
−A
−B
IN
50%
GND
VDD
IN
50%
GND
VDD
PFD INHIBIT
PFD OUT
50%
50%
GND
VDD
90%
90%
50%
10%
50%
50%
10%
50%
GND
tPZH
tPHZ
tPZL
tPLZ
tr
tf
Figure 4. PFD Output Voltage Waveform
Table 4. PFD Output Test Conditions
PARAMETER
R
C
S1
S2
L
L
t
PZH
PHZ
t
OPEN
CLOSE
OPEN
t
r
1 kΩ
15 pF
t
PZL
PLZ
t
CLOSE
t
f
10
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
Measurement
Point
S1
R
L
S2
C
L
Figure 5. PFD Output Test Conditions
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=3.3kohm
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=2.2kohm
100
100
90
80
70
60
50
40
30
20
10
0
90
−25°C
80
−25°C
25°C
25°C
70
85°C
60
85°C
50
40
30
20
10
0
0
1
2
3
4
0
1
2
3
4
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 6.
Figure 7.
11
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=2.2kohm
VCO CONTROL VOLTAGE
Vdd=3.0V Rbias=5.1kohm
100
100
90
80
70
60
50
40
30
20
10
0
−25°C
25°C
90
80
70
60
50
40
30
20
10
0
85°C
−25°C
25°C
85°C
0
1
2
3
4
0
1
2
3
4
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 8.
Figure 9.
VCO OSCILATION FREQUENCY
VS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=5.1kohm
VCO CONTROL VOLTAGE
Vdd=3.3V Rbias=3.3kohm
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
−25°C
25°C
−25°C
25°C
85°C
85°C
0
1
2
3
4
0
1
2
3
4
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 10.
Figure 11.
12
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO OSCILATION FREQUENCY
VS
VCO OSCILATION FREQUENCY
VS
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=3.3kohm
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=2.2kohm
140
140
120
100
80
−25°C
120
25°C
−25°C
100
85°C
25°C
85°C
80
60
40
20
0
60
40
20
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCOIN − VCO Control Voltage − V
VCOIN − VCO Control Voltage − V
Figure 12.
Figure 13.
VCO OSCILATION FREQUENCY
VS
VCO Oscilation frequency
Vs
VCO CONTROL VOLTAGE
Vdd=5.0V Rbias=5.1kohm
Bias resister
Vdd=3V, VCOIN=1.5V, Ta=25’C
140
120
100
80
35
33
31
29
27
25
23
21
19
17
15
−25°C
25°C
85°C
60
40
20
0
1
2
3
4
5
6
0
1
2
3
4
5
6
VCOIN − VCO Control Voltage − V
Rbias(kohm)
Figure 14.
Figure 15.
13
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO Oscilation frequency
Vs
VCO Oscilation frequency
Vs
Bias resister
Bias resister
Vdd=5V, VCOIN=2.5V, Ta=25’C
Vdd=3.3V, VCOIN=1.6V, Ta=25’C
65
63
61
59
57
55
53
51
49
47
45
40
38
36
34
32
30
28
26
24
22
20
1
2
3
4
5
6
1
2
3
4
5
6
Rbias(kohm)
Rbias(kohm)
Figure 16.
Figure 17.
Temperature Coefficient Oscilation frequency
Temperature Coefficient Oscilation frequency
Vs
Bias resister
Vs
Bias resister
Vdd=3.3V, VCOIN=1.6V, Ta=−20’C to 75’C
Vdd=3V, VCOIN=1.5V, Ta=−20’C to 75’C
0.000
−0.050
−0.100
−0.150
−0.200
−0.250
−0.300
−0.350
−0.400
−0.450
−0.500
0.000
−0.050
−0.100
−0.150
−0.200
−0.250
−0.300
−0.350
−0.400
−0.450
−0.500
1
2
3
4
5
6
1
2
3
4
5
6
Rbias(kohm)
Rbias(kohm)
Figure 18.
Figure 19.
14
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
VCO Oscilation frequency
Vs
VCO Supply Voltage
VCOIN=1.5V, Ta=25’C
Temperature Coefficient Oscilation frequency
Vs
Bias resister
Vdd=5.0V, VCOIN=2.5V, Ta=−20’C to 75’C
35
33
31
29
27
25
23
21
19
17
0.000
−0.050
−0.100
−0.150
−0.200
−0.250
−0.300
−0.350
−0.400
−0.450
−0.500
15
2.5
2.7
2.9
3.1
3.3
3.5
1
2
3
4
5
6
VCO Supply Voltage (V)
Rbias(kohm)
Figure 20.
Figure 21.
VCO Oscilation frequency
Vs
VCO Oscilation frequency
Vs
VCO Supply Voltage
VCOIN=2.5V, Ta=25’C
VCO Supply Voltage
VCOIN=1.6V, Ta=25’C
65
63
61
59
57
55
53
51
49
47
45
40
38
36
34
32
30
28
26
24
22
20
4.5
5.5
4
5
6
2.8
3.2
3.4
3.6
3.8
3
VCO Supply Voltage (V)
VCO Supply Voltage (V)
Figure 22.
Figure 23.
15
TI.COM
ꢀ ꢁ ꢂ ꢃꢄ ꢅ ꢃ ꢆ
ꢇ ꢈꢉ ꢇ ꢊꢋ ꢌꢍ ꢎꢌꢏꢆ ꢐꢂꢋ ꢊ ꢇꢆꢑ ꢋ ꢁꢎ ꢂꢒ ꢋꢓ ꢁ ꢎ ꢎꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
Supply Voltage Coefficient of Oscilation frequency
Supply Voltage Coefficient of Oscilation frequency
Vs
Bias resister
Vs
Bias resister
Vdd=3.0V to 3.6V,VCOIN=1.6V, Ta=25’C
Vdd=2.7V to 3.3V,VCOIN=1.5V, Ta=25’C
0.100
0.080
0.100
0.080
0.060
0.060
0.040
0.040
0.020
0.020
0.000
0.000
−0.020
−0.040
−0.060
−0.080
−0.100
−0.020
−0.040
−0.060
−0.080
−0.100
1
2
3
4
5
6
1
2
3
4
5
6
Rbias (kohm)
Rbias (kohm)
Figure 24.
Figure 25.
Recommended Lock frequency
Supply Voltage Coefficient of Oscilation frequency
Vs
Bias resister
Vs
Bias resister
Vdd=2.85V to 3.15V, Ta=−20’C to 75’C
Vdd=4.5V to 5.5V,VCOIN=2.5V, Ta=25’C
50
45
40
35
30
25
20
15
10
0.100
0.080
0.060
0.040
0.020
0.000
−0.020
−0.040
−0.060
−0.080
−0.100
5
0
1
2
3
4
5
6
1
2
3
4
5
6
Rbias (kohm)
Rbias (kohm)
Figure 26.
Figure 27.
16
TI.COM
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅ ꢃꢆ
ꢇꢈ ꢉꢇ ꢊꢋ ꢌꢍ ꢎꢌ ꢏꢆꢐ ꢂꢋ ꢊꢇꢆ ꢑꢋ ꢁ ꢎ ꢂꢒꢋ ꢓ ꢁꢎ ꢎ ꢊ
SLES150 − OCTOBER 2005
TYPICAL CHARACTERISTICS
Recommended Lock frequency
Recommended Lock frequency
Vs
Vs
Bias resister
Bias resister
Vdd=4.75V to 5.25V, Ta=−20’C to 75’C
Vdd=3.135V to 3.465V, Ta=−20’C to 75’C
80
70
60
50
40
30
20
10
0
50
45
40
35
30
25
20
15
10
5
0
1
2
3
4
5
6
1
2
3
4
5
6
Rbias (kohm)
Rbias (kohm)
Figure 28.
Figure 29.
17
TI.COM
PACKAGE OPTION ADDENDUM
www.ti.com
30-Jul-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
TLC2932AIPW
TLC2932AIPWG4
TLC2932AIPWR
TLC2932AIPWRG4
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
14
14
14
14
90
90
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC2932AIPWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 35.0
TLC2932AIPWR
2000
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All
semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time
of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components which meet ISO/TS16949 requirements, mainly for automotive use. Components which
have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2012, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明