TLC2942IDBLE [TI]
High-Performance Dual Phase-Locked Loop Building Block 38-SSOP;
| 型号： | TLC2942IDBLE |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | High-Performance Dual Phase-Locked Loop Building Block 38-SSOP |
| 文件： | 总28页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
DB PACKAGE
Dual TLC2932 by Multichip Module (MCM)
Technology
(TOP VIEW)
Voltage-Controlled Oscillator (VCO)
Section:
– Complete Oscillator Using Only One
LOGIC V
VCO V
BIAS1
1
DD1
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
DD1
SELECT1
2
VCO OUT1
VCOIN1
VCO GND1
VCOINHIBIT1
PFD INHIBIT1
NC
3
External Bias Resistor (R
)
BIAS
F
F
–A1
–B1
4
IN
– Recommended Lock Frequency Range:
22 MHz to 50 MHz (V = 5 V ±5%,
5
IN
DD
PFD OUT1
6
T = –20°C to 75°C, ×1 Output)
A
LOGIC GND1
7
11 MHz to 25 MHz (V
= 5 V ±5%,
DD
GND
NC
GND
8
T = –20°C to 75°C, ×1/2 Output)
A
NC
9
– Output Frequency . . . ×1 and ×1/2
NC
NC
10
11
12
13
14
15
16
Selectable
NC
NC
Includes a High-Speed Edge-Triggered
Phase Frequency Detector (PFD) With
Internal Charge Pump
GND
GND
LOGIC V
VCO V
DD2
DD2
SELECT2
BIAS2
Independent VCO, PFD Power-Down Mode
VCO OUT2
VCOIN2
F
F
–A2
VCO GND2
VCOINHIBIT2
PFD INHIBIT2
NC
IN
description
–B2 17
IN
PFD OUT2 18
The TLC2942 is a multichip module product that
uses two TLC2932 chips. The TLC2932 chip is
composed of a voltage-controlled oscillator and
an edge-triggered phase frequency detector. The
oscillation frequency range of each VCO is set by
LOGIC GND2 19
NC – No internal connection
an external bias resistor (R
) and each VCO output can be a ×1 or ×1/2 output frequency. Each high speed
BIAS
PFD with internal charge pump detects the phase difference between the reference frequency input and signal
frequency input from the external counter. The VCO and the PFD have inhibit functions that can be used as a
power-down mode. The high-speed and stable oscillation capability of the TLC2932 makes the TLC2942
suitable for use in dual high-performance phase-locked loop (PLL) systems.
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(DB)
–20°C to 75°C
TLC2942IDB
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
functional block diagram
VCO
INHIBIT1
VCO
INHIBIT2
VCO OUT1 VCO OUT2
SELECT1
SELECT2
14 22
34
2
3
15
24
36
VCO_1
VCO_2
VCOIN1
VCOIN2
16
17
4
5
F
F
–A2
–B2
F
F
–A1
–B1
IN
IN
PFD_1
33
PFD_2
21
IN
IN
6
18
PFD OUT1 PFD OUT2
PFD INHIBIT1 PFD INHIBIT2
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
Terminal Functions
TERMINAL
NAME
BIAS1
I/
O
DESCRIPTION
NO.
37
I
VCO1 bias supply. An external resistor (R
the oscillation frequency range.
1) between VCO V
BIAS
and BIAS1 supplies bias for adjusting
and BIAS2 supplies bias for adjusting
DD1
BIAS2
25
I
VCO2 bias supply. An external resistor (R
the oscillation frequency range.
) between VCO V
BIAS2
DD2
F
IN
F
IN
F
IN
–A1
–A2
–B1
4
16
5
I
I
I
Input reference frequency 1. The frequency f(REF IN)1 is applied to F -A1.
IN
Input reference frequency 2. The frequency f(REF IN)2 is applied to F -A2.
IN
Input for VCO1 external counter output frequency f(F -B)1. F -B1 is nominally provided from the external
IN IN
counter (see Figure 28).
F
IN
–B2
17
I
Input for VCO2 external counter output frequency f(F -B)2. F -B2 is nominally provided from the external
IN IN
counter (see Figure 28).
GND
8, 12,
27,31
Ground
LOGIC V
LOGIC V
1
Logic1 supply voltage. LOGIC V
from the other supply lines to reduce cross-coupling between power supplies.
supplies voltage to internal logic 1. LOGIC V
should be separate
should be separate
DD1
DD2
DD1
DD1
13
Logic2 supply voltage. LOGIC V supplies voltage to internal logic 2. LOGIC V
from the other supply lines to reduce cross-coupling between power supplies.
DD2
DD2
LOGIC GND1
LOGIC GND2
NC
7
Ground for the internal logic 1
19
Ground for the internal logic 2
9, 10, 11,
20, 28,
29, 30,
32
No internal connection
PFD INHIBIT1
PFD INHIBIT2
33
I
I
PFD inhibit 1 control. When PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state (see
Table 4).
21
PFD inhibit 2 control. When PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state (see
Table 5).
PFD OUT1
PFD OUT2
SELECT1
6
18
2
O
O
I
PFD1 output. When the PFD INHIBIT1 is high, PFD OUT1 is in the high-impedance state.
PFD2 output. When the PFD INHIBIT2 is high, PFD OUT2 is in the high-impedance state.
VCO1 output frequency select. When SELECT1 is high, the VCO1 output frequency is 1/2 and when
SELECT1 is low, the output frequency is 1 (see Table 1).
SELECT2
14
I
VCO2 output frequency select. When SELECT2 is high, the VCO2 output frequency is 1/2 and when
SELECT2 is low, the output frequency is 1 (see Table 1).
VCO GND1
VCO GND2
VCOINHIBIT1
VCOINHIBIT2
VCO OUT1
VCO OUT2
35
23
34
22
3
Ground for VCO1
Ground for VCO2
I
VCO1 inhibit control. When VCOINHIBIT1 is high, VCO OUT1 is low (see Table 2).
VCO2 inhibit control. When VCOINHIBIT2 is high, VCO OUT2 is low (see Table 3).
VCO1 output. When VCOINHIBIT1 is high, VCO OUT1 is low.
VCO2 output. When VCOINHIBIT2 is high, VCO OUT2 is low.
O
O
15
38
VCO V
VCO1 supply voltage. VCO V
DD1
supplies voltage for VCO1. VCO V
should be separated from LOGIC
DD1
DD1
V
DD1
and LOGIC V
and VCO V 2 to reduce cross-coupling between power supplies.
DD2
DD
VCO V
26
36
24
VCO2 supply voltage. VCO V
supplies voltage for VCO2. VCO V
should be separated from LOGIC
DD2
DD2
DD2
V
DD1
and LOGIC V
DD2
and VCO V 1 to reduce cross-coupling between power supplies.
DD
VCOIN1
VCOIN2
I
I
VCO1 control voltage input. Nominally the external loop filter output1 connects to VCOIN1 to control VCO1
oscillation frequency.
VCO2 control voltage input. Nominally the external loop filter output2 connects to VCOIN2 to control VCO2
oscillation frequency.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
detailed description
multichip module
TheTLC2942isamultichipmodule(MCM)productthatusestwoTLC2932chips. Anewlydevelopedleadframe
for TLC2942IBD is specially shaped and cut in the package to electrically isolate one chip from another. The
two chips are completely independent from each other to perform the best stable oscillation and locking. If
asynchronouslockingoperationisrequiredforthesetwoPLLblocks, eachTLC2942VCOandPFDcanachieve
the same stability as the single chip TLC2932IPW.
Three NC terminals are on both sides of the package between chip1 and chip2 due to the lead frame shape.
To avoid performance degradation, special attention is needed for each PLL block PCB layout especially for
supply voltage lines and GND patterns.
voltage-controlled oscillator (VCO)
VCO1 and VCO2 have the same typical characteristics. Each VCO oscillation frequency is determined by an
external resistor (R
)connectedbetweeneachVCOV and BIAS terminals. The oscillation frequency and
BIAS
DD
range depends on this register value. The bias resistor value for the minimum temperature coefficient is
nominally 3.3 kΩ with V = 3 V and nominally 2.2 kΩ with V = 5 V. For the lock frequency range refer to
DD
DD
the recommended operating conditions. Figure 1 shows the typical frequency variation and VCO control
voltage.
VCO Oscillation Frequency Range
Bias Resistor (R
)
BIAS
1/2 V
DD
VCO Control Voltage (VCOIN)
Figure 1. VCO1 and VCO2 Oscillation Frequency
VCO output frequency 1/2 divider
SELECT1 and SELECT2 select between f
and 1/2 f
for the VCO output frequencies as shown in Table 1.
osc
osc
Table 1. SELECT1 and SELECT2 Function Table
VCO1 OUTPUT
FREQUENCY
VCO2 OUTPUT
FREQUENCY
SELECT1
SELECT2
f
Low
Low
f
osc1
osc2
1/2 f
osc1
High
High
1/2 f
osc2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO inhibit function
Each VCO has an externally controlled inhibit function that inhibits the VCO output. The VCO oscillation is
stopped during a high level on VCOINHIBIT, so the high level can also be used as the power-down mode. The
VCO output maintains a low level during the power-down mode (see Table 2 and Table 3).
Table 2. VCO1 Inhibit Function
VCOINHIBIT1
Low
VCO1 OSCILLATOR
VCO OUT1
Active
VCO1 I
DD
Active
Stop
Normal
High
Low
Power Down
Table 3. VCO2 Inhibit Function
VCOINHIBIT2
Low
VCO2 OSCILLATOR
VCO OUT2
Active
VCO2 I
DD
Active
Stop
Normal
High
Low
Power Down
PFD operation
The PFD is a high-speed, edge-triggered detector with an internal charge pump. The PFD detects the phase
difference between two frequency inputs supplied to F –A and F –B as shown in Figure 2. Nominally the
IN
IN
reference is supplied to F –A, and the frequency from the external counter output is fed to F –B.
IN
IN
F
F
–A1,
IN
–A2
IN
F
F
–B1,
–B2
IN
IN
V
OH
PFD OUT1,
PFD OUT2
Hi-Z
V
OL
Figure 2. PFD Function Timing Chart
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
PFD output control
A high level on PFD INHIBIT places the PFD OUT in the high-impedance state and the PFD stops phase
detection as shown in Table 4 and Table 5. A high level on PFD INHIBIT also can be used as the power-down
mode for the PFD.
Table 4. PFD1 Inhibit Function
PFD INHIBIT1
Low
DETECTION
Active
PFD OUT1
Active
PFD1 I
DD
Normal
High
Stop
Hi-Z
Power Down
Table 5. PFD2 Inhibit Function Table
PFD INHIBIT2
Low
DETECTION
Active
PFD OUT2
Active
PFD2 I
DD
Normal
High
Stop
Hi-Z
Power Down
schematics
VCO block schematic (VCO1, VCO2)
R
BIAS
Ring Oscillator
1/2
M
U
X
VCO
Output
Bias
Circuit
VCO OUT1,
VCO OUT2
VCOIN1,
VCOIN2
(VCO control)
SELECT1,2
VCOINHIBIT
PFD block schematic (PFD1, PFD2)
Charge Pump
V
DD
F
F
–A
–B
IN
PFD OUT
Detector
IN
PFD INHIBIT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage (each supply), V
Input voltage range (each input), V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
+ 0.5 V
I
DD
Input current (each input), I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
I
Output current (each output), I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
O
Continuous total power dissipation, at (or below) T = 25°C (see Note 2) . . . . . . . . . . . . . . . . . . . . . . 1160 mW
Operating free-air temperature range, T
A
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20°C to 75°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to network GND.
2. For operation above 25°C free-air temperature, derate linearly at the rate of 9.3 mW/°C.
recommended operating conditions
MIN NOM
MAX
3.15
5.25
UNIT
V
V
= 3 V
= 5 V
2.85
4.75
0
3
5
DD
Supply voltage, V
(each supply, see Note 3)
V
DD
DD
Input voltage, V , (all inputs except VCOIN1, VCOIN2)
V
DD
V
mA
V
I
Output current, I (each output)
O
0
±2
VCO control voltage at each VCOIN1, VCOIN2
0.9
14
22
7
V
DD
21
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3 V
= 5 V
= 3 V
= 5 V
= 3 V
= 5 V
Lock frequency, (each VCO) (×1 output)
MHz
MHz
50
10.5
25
Lock frequency, (each VCO) (×1/2 output)
11
2.2
1.5
3.3
2.2
4.3
3.3
Bias resistor, (each BIAS), R
R
kΩ
°C
BIAS1, BIAS2
Operating temperature, T
–20
75
A
NOTE 3: ItisrecommendedthatLOGICV
each other.
andVCOV
DD1
orLOGICV
andVCOV shouldbeatthesamevoltageandseparatedfrom
DD2
DD1
DD2
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 electrical characteristics, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
= –2 mA
= 2 mA
2.4
OH
OH
OL
I
0.3
2.1
V
OL
SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1
V
IT
Input threshold voltage
0.9
1.5
V
SELECT1, SELECT2,
VCOINHIBIT2, VCOINHIBIT1
I
I
Input current
V = V or GND
I DD
±1
µA
Z
Input impedance
VCOIN2, VCOIN1
VCOIN = 1/2 V
See Note 4
10
0.01
5
MΩ
µA
i(VCOIN)
DD(INH)
DD(VCO)
DD
I
I
VCO supply current (inhibit) (each chip)
VCO supply current (each chip)
1
See Note 5
15
mA
NOTES: 4. The current into VCO V
and LOGIC V
when VCOINHIBIT = V , and the PFD is inhibited.
whenVCOIN=1/2V , R =3.3kΩ, VCOINHIBIT=GND, andthePFDisinhibited.
DD BIAS
DD
andLOGICV
DD DD
5. ThecurrentintoVCOV
DD
DD
PFD1, PFD2 electrical characteristic, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
= –2 mA
= 2 mA
2.7
OH
OH
0.2
V
OL
OL
PFD INHIBIT = high,
= V or GND
I
High-impedance output current
High-level input voltage
±1
µA
OZ
V
O
DD
F
F
–A1, F –B1,
IN
IN
IN
V
2.7
0.9
V
IH
–A2, F –B2
IN
F
IN
–A1, F –B1,
IN
V
V
Low-level input voltage
Input threshold voltage
Input capacitance
0.5
2.1
V
V
IL
FIN–A2, F –B2
IN
PFD INHIBIT2, PFD INHIBIT1
1.5
5
IT
F
IN
F
IN
–A1, F –B1,
IN
C
pF
i
–A2, F –B2
IN
F
IN
F
IN
–A1, F –B1,
IN
Z
i
Input impedance
10
MΩ
–A2, F –B2
IN
I
I
High-impedance state PFD supply current
PFD supply current
See Note 6
See Note 7
0.1
0.1
1
µA
DD(Z)
1.5
mA
DD(PFD)
NOTES: 6. The current into LOGIC V , when F –A and F –B = GND, PFD INHIBIT= V , no load, and VCO OUT is inhibited.
DD
DD
IN
IN
DD
= 3 V rectangular wave, PFD INHIBIT = GND, no load,
7. The current into LOGIC V
when F –A and F –B = 1 MHz with V
IN IN I(PP)
and VCO OUT is inhibited.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 operating characteristics, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
µs
R
R
= 3.3 kΩ,
BIAS1, BIAS2
f
t
Operating oscillation frequency
Time to stable oscillation
15
19
23
osc
VCOIN1, VCOIN2 = 1/2 V
DD
See Note 8
10
14
s(fosc)
C
C
C
C
R
= 15 pF,
= 50 pF,
= 15 pF,
= 50 pF,
See Figure 3
7
14
6
L
L
L
L
t
Rise time
ns
ns
r
f
See Figure 3
See Figure 3
See Figure 3
12
t
Fall time
10
, R
BIAS1 BIAS2
= 3.3 kΩ,
Duty cycle at VCO OUT
45%
50%
55%
VCOIN1, VCOIN2 = 1/2 V
DD
R
R
= 3.3 kΩ,
BIAS1, BIAS2
VCOIN1, VCOIN2 = 1/2 V
= –20°C to 75°C
α
Temperature coefficient of oscillation frequency
,
0.04
%/°C
(fosc)
DD
T
A
R
R
= 3.3 kΩ,
BIAS1, BIAS2
VCOIN1, VCOIN2 = 1.5 V,
= 2.85 V to 3.15 V
k
Supply voltage coefficient of oscillation frequency
Jitter absolute (see Note 9)
0.02
100
%/mV
ps
SVS(fosc)
V
DD
R
= 3.3 kΩ
BIAS1
NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, V
= 3 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
20
MHz
max
PLZ
PHZ
PZL
PZH
r
21
23
50
50
30
30
10
10
ns
ns
See Figures 4 and 5 and Table 4
11
10
2.3
2.1
ns
ns
C
= 15 pF,
See Figure 4
L
Fall time
f
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
OH
V
OL
V
IT
High-level output voltage
Low-level output voltage
Input threshold voltage
I
= –2 mA
= 2 mA
4
V
V
V
OH
OL
I
0.5
3.5
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
1.5
2.5
I
I
Input current
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
V = V or GND
I DD
±1
µA
Z
Input impedance
VCOIN1, VCOIN2
VCOIN = 1/2 V
See Note 4
10
0.01
15
MΩ
µA
i(VCOIN)
DD(INH)
DD(VCO)
DD
I
I
VCO supply current (inhibit) (each chip)
VCO supply current (each chip)
1
See Note 10
35
mA
NOTES: 4. The current into VCO V
DD
and LOGIC V when VCOINHIBIT = V , and the PFD is inhibited.
DD DD
10. ThecurrentintoVCOV
andLOGICV
whenVCOIN=1/2V , R =2.2kΩ, VCOINHIBIT=GND, andthePFDisinhibited.
DD
DD
DD BIAS
PFD1, PFD2 electrical characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
High-level output voltage
Low-level output voltage
I
I
= 2 mA
4.5
OH
OH
= 2 mA
0.2
V
OL
OL
PFD INHIBIT1, PFD INHIBIT2 = high,
= V or GND
I
High-impedance output current
±1
µA
V
OZ
V
O
DD
F
F
–A1, F –B1,
IN
IN
IN
V
V
V
High-level input voltage
Low-level input voltage
Input threshold voltage
Input capacitance
4.5
1.5
IH
IL
IT
–A2, F –B2
IN
F
IN
–A1, F –B1,
IN
1
V
FIN–A2, F –B2
IN
PFD INHIBIT2,
PFD INHIBIT1
2.5
5
3.5
V
F
IN
F
IN
–A1, F –B1,
IN
C
pF
MΩ
i
–A2, F –B2
IN
F
IN
F
IN
–A1, F –B1,
IN
Z
Input impedance
10
i
–A2, F –B2
IN
I
I
High-impedance state PFD supply current
PFD supply current (each chip)
See Note 6
See Note 11
0.1
1
3
µA
DD(Z)
0.15
mA
DD(PFD)
NOTES: 6. The current into LOGIC V , when F –A and F –B = GND, PFD INHIBIT= V , no load, and VCO OUT is inhibited.
DD
DD
IN
IN
DD
= 5-V rectangular wave, PFD INHIBIT = GND, no load,
11. The current into LOGIC V
and
when F –A and F –B = 1 MHz with V
IN IN I(PP)
VCO OUT is inhibited.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
VCO1, VCO2 operating characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MHz
µs
R
R = 2.2 kΩ,
BIAS1, BIAS2
f
t
Operating oscillation frequency
Time to stable oscillation
32
41
50
osc
VCOIN1, VCOIN2 = 1/2 V
DD
See Note 8
10
10
s(fosc)
C
C
C
C
R
= 15 pF,
= 50 pF,
= 15 pF,
= 50 pF,
See Figure 3
5.5
8
L
L
L
L
t
Rise time
ns
ns
r
f
See Figure 3
See Figure 3
See Figure 3
5
10
t
Fall time
6
R
= 2.2 kΩ,
BIAS1, BIAS2
Duty cycle at VCO OUT
45%
50%
55%
VCOIN1, VCOIN2 = 1/2 V
DD
R
R
= 2.2 kΩ,
BIAS1, BIAS2
Temperature coefficient of oscillation frequency VCOIN1, VCOIN2 = 1/2 V
= –20°C to 75°C
α
,
0.06
%/°C
(fosc)
DD
T
ope
R
R
= 2.2 kΩ,
BIAS1, BIAS2
VCOIN1, VCOIN2 = 2.5 V,
= 4.75 V to 5.25 V
Supply voltage coefficient of oscillation fre-
quency
k
0.006
100
%/mV
ps
SVS(fosc)
V
DD
Jitter absolute (see Note 9)
R
= 3.3 kΩ
BIAS1
NOTES: 8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, V
= 5 V, T = 25°C (unless otherwise noted)
A
DD
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
f
t
t
t
t
t
t
Maximum operating frequency
PFD output disable time from low level
PFD output disable time from high level
PFD output enable time to low level
PFD output enable time to high level
Rise time
40
MHz
max
PLZ
PHZ
PZL
PZH
r
21
20
40
40
20
20
10
10
ns
ns
See Figures 4 and 5 and Table 4
7.3
6.5
2.3
1.7
ns
ns
C
= 15 pF,
See Figure 4
L
Fall time
f
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
PARAMETER MEASUREMENT INFORMATION
90%
10%
90%
10%
VCO OUT1,
VCO OUT2
t
r
t
f
Figure 3. VCO Output Voltage Waveform
V
V
DD
GND
DD
F
F
–A1,
–A2
IN
IN
GND
V
DD
V
DD
F
F
–B1,
–B2
IN
IN
GND
GND
V
V
DD
DD
PFD INHIBIT1,
PFD INHIBIT2
50%
50%
GND
GND
t
t
PHZ
PLZ
t
r
t
f
V
V
OH
DD
90%
50%
90%
PFD OUT1,
PFD OUT2
50%
10%
50%
50%
10%
V
OL
GND
t
PZL
t
PZH
(a) OUTPUT PULLDOWN
(see Figure 5 and Table 6)
(b) OUTPUT PULLUP
(see Figure 5 and Table 6)
†
F
IN
–A and F –B are for reference phase only, not for timing.
IN
Figure 4. PFD Output Voltage Waveform
Table 6. PFD1 and PDF2 Output Test Conditions
V
DD
PARAMETER
R
C
S
1
S
2
L
L
Test Point
t
t
t
t
t
t
PZH
PHZ
r
S1
Open
Close
Close
Open
R
L
PFD OUT
1 kΩ
15 pF
DUT
PZL
PLZ
f
S2
C
L
Figure 5. PFD1 and PFD2 Output Test Conditions
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
40
30
20
100
80
V
R
= 3 V
DD
V
R
= 5 V
DD
–20°C
75°C
= 2.2 kΩ
BIAS
= 1.5 kΩ
25°C
BIAS
–20°C
25°C
60
75°C
40
10
0
20
0
1
2
3
0
1
2
3
4
5
V
– VCO Control Voltage – V
I (VCOIN)
V
– VCO Control Voltage – V
I (VCOIN)
Figure 6
Figure 7
VCO OSCILLATION FREQUENCY
vs
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
80
60
40
20
0
40
V
R
= 5 V
DD
V
R
= 3 V
DD
= 2.2 kΩ
BIAS
= 3.3 kΩ
BIAS
–20°C
–20°C
30
20
75°C
75°C
25°C
25°C
10
0
0
1
2
3
4
5
0
1
2
3
V
I (VCOIN)
– VCO Control Voltage – V
V
I (VCOIN)
– VCO Control Voltage – V
Figure 8
Figure 9
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
VCO OSCILLATION FREQUENCY
vs
VCO OSCILLATION FREQUENCY
vs
VCO CONTROL VOLTAGE
VCO CONTROL VOLTAGE
40
30
20
80
60
40
20
0
V
R
= 3 V
V
R
= 5 V
DD
DD
= 4.3 kΩ
= 3.3 kΩ
BIAS
BIAS
75°C
25°C
–20°C
25°C
10
0
75°C
–20°C
0
1
2
3
0
1
2
3
4
5
V
I (VCOIN)
– VCO Control Voltage – V
V
– VCO Control Voltage – V
I (VCOIN)
Figure 10
Figure 11
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
BIAS RESISTOR
BIAS RESISTOR
60
30
V
= 5 V
V
= 3 V
DD
DD
VCOIN = 1/2 V
T
A
VCOIN = 1/2 V
T
A
DD
DD
= 25°C
= 25°C
50
25
40
30
20
20
15
10
1.5
2
2.5
3
3.5
2
2.5
3
3.5
4
4.5
R
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 12
Figure 13
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
TEMPERATURE COEFFICIENT OF
TEMPERATURE COEFFICIENT OF
OSCILLATION FREQUENCY
vs
OSCILLATION FREQUENCY
vs
BIAS RESISTOR
BIAS RESISTOR
0.4
0.3
0.2
0.1
0
0.4
V
= 3 V
DD
V
= 5 V
DD
VCOIN = 1/2 V
T
A
DD
= –20°C to 75°C
VCOIN = 1/2 V
DD
T
A
= –20°C to 75°C
0.3
0.2
0.1
0
2
2.5
3
3.5
4
4.5
3.3
– Bias Resistor – kΩ
1.5
2
2.5
3
3.5
2.2
BIAS
R
BIAS
R
– Bias Resistor – kΩ
Figure 14
Figure 15
VCO OSCILLATION FREQUENCY
VCO OSCILLATION FREQUENCY
vs
vs
VCO SUPPLY VOLTAGE
VCO SUPPLY VOLTAGE
48
44
24
R
= 2.2 kΩ
R
= 3.3 kΩ
BIAS
BIAS
VCOIN = 1/2 V
DD
T
A
VCOIN = 1.5 V
= 25°C
= 25°C
T
A
22
40
36
32
20
18
16
4.75
5
5.25
2.85
3
3.15
V – VCO Supply Voltage – V
DD
V
DD
– VCO Supply Voltage – V
Figure 16
Figure 17
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
SUPPLY VOLTAGE COEFFICIENT OF VCO
SUPPLY VOLTAGE COEFFICIENT OF VCO
OSCILLATION FREQUENCY
OSCILLATION FREQUENCY
vs
vs
BIAS RESISTOR
BIAS RESISTOR
0.05
0.04
0.03
V
= 2.85 V to 3.15 V
V
= 4.75 V to 5.25 V
DD
VCOIN = 1/2 V
DD
VCOIN = 1/2 V
DD
T
A
DD
T
A
= 25°C
= 25°C
0.01
0.02
0.01
0
0.005
0
1.5
2
2.5
3
3.5
2
2.5
3
3.5
4
4.5
R
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 18
Figure 19
RECOMMENDED LOCK FREQUENCY
RECOMMENDED LOCK FREQUENCY
(×1 OUTPUT)
vs
(×1 OUTPUT)
vs
BIAS RESISTOR
BIAS RESISTOR
60
50
40
V
T
= 4.75 V to 5.25 V
= –20°C to 75°C
30
V
T
A
= 2.85 V to 3.15 V
= –20°C to 75°C
DD
A
DD
25
20
15
30
20
10
10
2
2.5
3
3.5
4
4.5
1.5
2
2.5
3
3.5
R
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 20
Figure 21
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
TYPICAL CHARACTERISTICS
RECOMMENDED LOCK FREQUENCY
RECOMMENDED LOCK FREQUENCY
(×1/2 OUTPUT)
vs
(×1/2 OUTPUT)
vs
BIAS RESISTOR
BIAS RESISTOR
30
25
20
V
= 4.75 V to 5.25 V
DD
15
V
T
= 2.85 V to 3.15 V
DD
= –20°C to 75°C
T
= –20°C to 75°C
A
A
SELECT = V
SELECT = V
DD
DD
12.5
10
15
10
5
7.5
5
2
2.5
R
3
3.5
4
4.5
1.5
2
2.5
3
3.5
– Bias Resistor – kΩ
R
– Bias Resistor – kΩ
BIAS
BIAS
Figure 22
Figure 23
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
gain of VCO and PFD
Figure 24 is a block diagram of the PLL. The
Divider
divider N value depends on the input frequency
and the desired VCO output frequency according
(K = 1/N)
N
to the system application requirements. The K
p
and K values are obtained from the operating
V
PFD
(K )
VCO
(K )
characteristics of the device as shown in Figure
p
V
f
REF
24. K is defined from the phase detector V and
p
OL
TLC2942
LPF
V
specifications and the equation shown in
OH
Figure 24(b). K is defined from Figures 8, 9, 10,
and 11 as shown in Figure 24(c).
V
(K )
f
V
OH
The parameters for the block diagram with the
units are as follows:
(a)
K : VCO gain (rad/s/V)
V
–2π –π
0
π
2π
f
MAX
K : PFD gain (V/rad)
p
V
OH
K : LPF gain (V/V)
f
K : countdown divider gain (1/N)
N
f
MIN
V
OL
external counter
Range of
Comparison
When a large N counter is required by the
application, there is a possibility that the PLL
response becomes slow due to the counter
response delay time. In the case of a high
frequency application, the counter delay time
should be accounted for in the overall PLL design.
V
V
IN MIN
IN MAX
V – V
OH OL
4π
2π(f
– f )
MAX MIN
K
=
K
=
p
V
V
– V
IN MAX
(c)
IN MIN
(b)
Figure 24. Example of a PLL Block Diagram
R
BIAS
The external bias resistor sets the VCO center frequency with 1/2 V applied to the VCOIN terminal. However,
DD
for optimum temperature performance, a resistor value of 3.3 kΩ with a 3-V supply, or a resistor value of
2.5 kΩ for a 5-V supply is recommended. For the most accurate results, a metal-film resistor is the better choice,
but a carbon-compositiion resistor can be used with excellent results also. A 0.22-µF capacitor should be
connected from the BIAS terminal to ground as close to the device terminals as possible.
hold-in range
From the technical literature, the maximum hold-in range for an input frequency step for the three types of filter
configurations shown in Figure 25 is as follows:
0.8 K
K
K ( )
(1)
p
H
V
f
Where
K (∞) = the filter transfer function value at ω = ∞
f
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
low-pass-filter (LPF) configurations
Many excellent references are available that include detailed design information about LPFs and they should
be consulted for additional information. Lag-lead filters or active filters are often used. Examples of LPFs are
shown in Figure 25. When the active filter of Figure 25(c) is used, the reference should be applied to F -B
IN
because of the amplifier inversion. Also, in practical filter implementations, C2 is used as additional filtering at
the VCO input. The value of C2 should be equal to or less than one-tenth the value of C1.
C2
R1
V
I
V
O
R1
C1
R2
–
V
I
V
O
C2
R2
C1
T1 = C1R1
T2 = C1R2
C1
T1 = C1R1
V
I
A
V
O
R1
T1 = C1R1
T2 = C1R2
(a) LAG FILTER
(b) LAG-LEAD FILTER
(c) ACTIVE FILTER
Figure 25. LPF Examples for PLL
the passive filter
The transfer function for the low-pass filter shown in Figure 25(b) is:
V
O
1
s
s
T2
(2)
V
(
)
T1 T2
1
IN
Where
T1
R1 C1 and T2
R2 C1
Using this filter makes the closed loop PLL system a type 1 second-order system. The response curves of this
system to a unit step are shown in Figure 26.
the active filter
When using the active filter shown in Figure 25(c), the phase detector inputs must be reversed since the filter
adds an additional inversion. Therefore, the input reference frequency should be applied to the F -B terminal
IN
and the output of the VCO divider should be applied to the input reference terminal, F -A.
IN
The transfer function for the active filter shown in Figure 25(c) is:
1
s
R2 C1
R1 C1
(3)
F(s)
s
Using this filter makes the closed loop PLL system a type 2 second-order system. The response curves of this
system to a unit step are shown in Figure 27.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
1.9
1.8
= 0.1
1.7
= 0.2
1.6
= 0.3
1.5
= 0.4
1.4
= 0.6
= 0.5
1.3
= 0.7
1.2
= 0.8
1.1
1
0.9
= 1.0
0.8
= 1.5
0.7
0.6
= 2.0
0.5
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
ω t = 4.5
n s
nt
Figure 26. Type 1 Second-Order Step Response
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
1.9
1.8
1.7
1.6
ζ = 0.1
ζ = 0.2
ζ = 0.3
1.5
1.4
1.3
ζ = 0.4
ζ = 0.5
ζ = 0.6
ζ = 0.7
1.2
1.1
1
0.9
0.8
ζ = 0.8
ζ = 1.0
0.7
0.6
0.5
ζ = 2.0
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
ω
nt
Figure 27. Type 2 Second-Order Step Response
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
Assume the loop has to have a 100-µs settling time (t ) with a countdown divider N value = 8. Using the Type
s
1, second-order response curves of Figure 26, a value of 4.5 radians is selected for ω t with a damping factor
n s
of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial
parameters are summarized in Table 7. The loop constants, K and K , are calculated from the data sheet
V
p
specifications and Table 8 shows these values.
The natural loop frequency is calculated as follows:
Since
t
4.5
(4)
n s
Then
4.5
100
45 k-radians sec
Table 7. Design Parameters
n
s
PARAMETER
SYMBOL
VALUE
8
UNITS
Divider value
N
t
Lockup time
100
4.5
µs
Radian value to selected lockup time
Damping factor
ω t
n
rad
ζ
0.7
Table 8. Device Specifications
PARAMETER
VCO gain
SYMBOL
VALUE
UNITS
76.6
Mrad/V/s
MHz
MHz
V
f
f
70
MAX
K
V
20
5
MIN
V
V
IN MAX
0.9
V
IN MIN
PFD gain
K
p
0.342357
V/rad
Using the low-pass filter in Figure 25(b) and divider N value, the transfer function for phase and frequency are
shown in equations 5 and 6. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is:
K
K
2(s)
1(s)
p
(
V
1
s
T2
T2
(5)
)
N
T1 T2
K
K
K
K
p
p
V
V
2
s
s
1
N (T1 T2)
N (T1 T2)
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
and the transfer function for frequency is:
F
F
K
K
OUT(s)
REF(s)
p
V
)
1
s
T2
T2
(6)
(
T1 T2
K
K
K
K
p
p
V
V
2
s
s
1
N (T1 T2)
N (T1 T2)
2
2
The standard two-pole denominator is D = s + 2 ζ ω s + ω and comparing the coefficients of the denominator
n
n
of equation 5 and 6 with the standard two-pole denominator gives the following results:
K
K
p
V
(7)
n
N
(T1 T2)
Solving for T1 + T2
K
K
p
V
2
T1 T2
N
n
and by using this value for T1 + T2 in equation 7 the damping factor is:
n
N
(8)
T2
2
K
V
K
p
V
solving for T2:
T2
2
N
–
(9)
K
K
p
then by substituting for T2 in equation 7 and solving for T1 as given in equation 10:
K
K
p
2
2
V
N
(10)
T1
–
K
K
n
N
p
V
n
From the circuit constants and the initial design parameters then:
K
K
v
p
2
N
1
C1
R1
R2
(11)
(12)
2
K
K
n
p
N
V
n
2
N
1
C1
K
K
n
p
V
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
The capacitor, C1, is usually chosen between 1 µF and 0.1 µF to allow for reasonable resistor values and
physical capacitor size. In this example, C1 is chosen to be 0.1 µF and the corresponding R1 and R2 calculated
values are listed in Table 9.
Table 9. Calculated Values
PARAMETER
SYMBOL
VALUE
45000
3.277
UNITS
rad/sec
Natural angular frequency
ω
n
K = (K • K )/N
Mrad/sec
V
p
Lag-lead filter
15870
16000
Calculated value
Nearest standard value
R1
Ω
Calculated value
Nearest standard value
308
300
R2
C1
Ω
Selected value
0.1
µF
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
The evaluation and operation schematic for the TLC2942I is shown in Figure 28.
AV
DD
V
DD
PLL1
(digital)
VCO
1
2
3
4
5
6
7
38
37
36
35
34
33
8
LOGIC V
SELECT
VCO V
DD
DD
†
R1
1/2 f
BIAS
osc
0.22 µF
R3
C1
VCO OUT
VCOIN
REF IN
DGND
F
–A
–B
IN
IN
C2
R2
VCO GND
F
VCOINHIBIT
AGND
PFD OUT
PFD INHIBIT
GND
Phase
Comparator
LOGIC GND (Digital)
DGND
Divide
By
N
S1
S2
S3
PLL2
DGND
R4 R5
R6
DV
DD
†
R
resistor
BIAS
Figure 28. Evaluation and Operation Schematic
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
APPLICATION INFORMATION
PCB layout considerations
The TLC2942I contains high frequency analog oscillators; therefore, very careful breadboarding and
printed-circuit-board (PCB) layout is required for evaluation.
The following design recommendations benefit the TLC2942I user:
External analog and digital circuitry should be physically separated and shielded as much as possible to
reduce system noise.
RF breadboarding or RF PCB techniques should be used throughout the evaluation and production
process.
Wide ground leads or a ground plane should be used on the PCB layouts to minimize parasitic inductance
and resistance. The ground plane is the better choice for noise reduction.
LOGIC V
and VCO V
should be separate PCB traces and connected to the best filtered supply point
DD
DD
available in the system to minimize supply cross-coupling.
VCO V to GND and LOGIC V to GND should be decoupled with a 0.1-µF capacitor placed as close
DD
DD
as possible to the appropriate device terminals.
The no-connection (NC) terminal on the package should be connected to GND.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
MECHANICAL DATA
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
28 PIN SHOWN
0,38
0,65
28
M
0,15
0,22
15
0,15 NOM
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–8°
1,03
0,63
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
8
14
16
20
24
28
30
38
DIM
3,30
2,70
6,50
5,90
6,50
5,90
7,50
6,90
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
9,90
12,30
4040065 /C 10/95
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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